programmable configurations

KU College of EngineeringElec 204: Digital Systems DesignLecture 9 1

Programmable Configurations

• Read Only Memory (ROM) – – a fixed array of AND gates and a programmable array of OR gates

• Programmable Array Logic (PAL) – – a programmable array of AND gates feeding a fixed array of OR

gates.

• Programmable Logic Array (PLA) –– a programmable array of AND gates feeding a programmable array

of OR gates.

• Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) – – complex enough to be called “architectures”


ROM, PAL and PLA Configurations

(a) Programmable read-only memory (PROM)

InputsFixed

AND array(decoder)

ProgrammableOR array

OutputsProgrammableConnections

(b) Programmable array logic (PAL) device

Inputs ProgrammableAND array

FixedOR array


(c) Programmable logic array (PLA) device

Inputs ProgrammableOR array


ProgrammableConnections

ProgrammableAND array


Read Only Memory

• Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have:– N input lines, – M output lines, and

– 2N decoded minterms. • Fixed AND array with 2N outputs implementing all N-literal

minterms. • Programmable OR Array with M outputs lines to form up to

M sum of minterm expressions. • A program for a ROM or PROM is simply a multiple-output

truth table– If a 1 entry, a connection is made to the corresponding minterm for the

corresponding output– If a 0, no connection is made


• Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)

• The fixed "AND" array is a“decoder” with 3 inputs and 8outputs implementing minterms.

• The programmable "OR“array uses a single line torepresent all inputs to anOR gate. An “X” in thearray corresponds to attaching theminterm to the OR

• Read Example: For input (A2,A1,A0)= 011, output is (F3,F2,F1,F0 ) = 0011.

• What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?

Read Only Memory Example

D7D6D5D4D3D2D1D0

A2

A1A0

A

B

C

F0F1F2F3

X XX

XX

X

XX

XX


Programmable Array Logic (PAL)

• The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs.

• Disadvantage– ROM guaranteed to implement any M functions of N

inputs. PAL may have too few inputs to the OR gates.

• Advantages– For given internal complexity, a PAL can have larger N and M– Some PALs have outputs that can be complemented, adding POS

functions– No multilevel circuit implementations in ROM (without external

connections from output to input). PAL hasoutputs from OR terms as internal inputs to all ANDterms, making implementation of multi-level circuits easier.


Programmable Array Logic Example

• 4-input, 3-output PAL with fixed, 3-input OR terms

• What are the equations for F1 through F4?F1 = C’ + A’B’

F2 = A’BC’ + AC + AB’

F3 = AD + BD + F1

F4 = AB + CD + F1’

0 91 2 3 4 5 6 7 8

AND gates inputs

0 9

Productterm

1

2

3

4

5

6

7

8

9

10

11

12

F1

F2

F3

F4

I3= C

I2= B

I 1= A

1 2 3 4 5 6 7 8

I4 = D

X X

X X

X X X

X X

X

X

X

XX

X

X X

X

X X


Programmable Logic Array (PLA)

• Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs.

• Advantages– A PLA can have large N and M permitting implementation of equations

that are impractical for a ROM (because of the number of inputs, N, required

– A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL ORs

– Some PLAs have outputs that can be complemented, adding POS functions

• Disadvantage– Often, the product term count limits the application of a PLA. Two-level

multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA.


Programmable Logic Array Example

• 3-input, 3-output PLA with 4 product terms

What are the equations for F1 and F2?

Could the PLA implement the functions without the XOR gates?

Fuse intact

Fuse blown

1

F1

F2

X

A

B

C

C C B B A A 0

1

2

3

4X

XX

X X

X

X

X

X

X

X

X

X

X A B

A C

B C

A B

X


Combinational Functions and Circuits

• Rudimentary logic functions • Decoding• Encoding• Selecting


Rudimentary Logic Functions

• Functions of a single variable X

• Can be used on theinputs to functionalblocks to implementother than the block’sintended function

TABLE 4-1Functions of One Variable

X F = 0 F = X F = F = 1

01

00

01

10

11

X

0

1

F= 0

F= 1

(a)

F= 0

F= 1

VCC or VDD

(b)

X F= X

(c)

X F= X

(d)


Multiple-bit Rudimentary Functions

• Multi-bit Examples:

• A wide line is used to represent a bus which is a vector signal

• In (b) of the example, F = (F3, F2, F1, F0) is a bus.

• The bus can be split into individual bits as shown in (b)

• Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.

• The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F.

F(d)

0

F3

1 F2

F1A F0

(a)

01

A1

2 34

F0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

A A


Enabling Function

• Enabling permits an input signal to pass through to an output

• Disabling blocks an input signal from passing through to an output, replacing it with a fixed value

• The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1

• When disabled, 0 output• When disabled, 1 output

XF

EN

(a)

ENX

F

(b)


Decoders

• Multiple-input multiple-output logic circuit which maps coded inputs to coded outputs

• n input bits can code upto 2n different output bits• n-to-m decoder: maps n-bit input to m-bit output

where m < 2n


Decoders• General decoder structure

• Typically n inputs, 2n outputs– 2-to-4, 3-to-8, 4-to-16, etc.


Binary 2-to-4 decoder

Note “x” (don’t care) notation.


2-to-4-decoder logic diagram

m0=I1’I0’

m1=I1’I0

m2=I1I0’

m3=I1I0


Decoder Expansion3-to-8 decoder out of 2 2-to-4 decoders with enable


Decoder and OR Gate Implementation of a Binary Adder

• Arithmetic sum of three bits X,Y,Z• Output pair (C,S)

S(X,Y,Z) = )7,4,2,1(m

C(X,Y,Z) = )7,6,5,3(m


S(X,Y,Z) = )7,4,2,1(m

C(X,Y,Z) = )7,6,5,3(m


Decoder Applications

• Microprocessor memory systems– Selecting different banks of memory

• Microprocessor input/output systems– Selecting different devices

• Microprocessor instruction decoding– Enabling different functional units

• Memory chips– Enabling different rows of memory depending on address

• Lots of other applications– Seven segment decoder, 4-to-7 decoder


Encoders vs. Decoders

Decoder Encoder


Binary encoders


Need priority in most applications


Priority Encoder


A0 = D3 + D1D2’A1 = D2 + D3

V = D0 + D1 + D2 + D3


Another approach to the design of 8-input priority encoder


Priority-encoder logic equations


• Selecting of data or information is a critical function in digital systems and computers

• Circuits that perform selecting have:– A set of information inputs from which the selection is

made– A single output– A set of control lines for making the selection

• Logic circuits that perform selecting are called multiplexers

• Selecting can also be done by three-state logic or transmission gates

Selecting


Multiplexers

• MUX: – Selects binary information from one of many input

lines and directs the information to a single output line.

– Selection of a particular input is controlled by a set of input variables.

– # of selection control bits: n

– # of possible input lines: 2n

– # of output: 1

2n-to-1 MUX


Multiplexers


4-to-1-Line MUX


Quadruple 2-to-1-Line MUX


Combinational Circuit ImplementationUsing MUX

F(X,Y,Z)=m(1,2,6,7) using a 4-to-1 MUX


F(A,B,C,D)=m(1,3,4,11,12,13,14,15)


Demultiplexer

• Inverse of the MUX

• Receives information from a single line and transmits it to one of the 2n possible output lines

• 1-to-4-Line DMUX / 2-to-4-Line Decoder


Binary Adders

• Arithmetic circuits: – combinational circuits with add, subt, mult & div.

• Present a hierarchical design– Simple addition of two bits

• 0+0 = 02, 0+1 = 12, 1+0 = 12 and 1+1 = 102

– Half Adder: • Combinational circuit that adds two bits

– Full Adder:• Combinational circuit that adds three bits (two input, one

carry)


Half Adder

• Sum of two binary digits

S=X’Y+XY’C=XY


Full Adder

• Sum of three binary digits


Logic Diagram for Full Adder

XY Z(XY)

XY + Z(XY)

XY Z


Binary Ripple Carry Adder

• The parallel adder of n binary full adders

• Carry out Carry in of next full adder


Carry Lookahead Adder

• Ripple carry adder– Simple but has a long

circuit delay

• Define a partial full adder

• Try to lower gate delays for ripple carry adder


Binary Adder/Subtractor


Overflow

• When does it occur?

• How do we detect it? 01110 10000+ 5 0101 -4 1100 + 7 0111 -6 1010+12 ? 01100 -10 ? 10110


Binary Multipliers


4-bit by 3-bit multiplier

programmable configurations

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