programmable logic programmable logic arrays (plas)
TRANSCRIPT
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 1
Programmable Logic
Regular logic Programmable Logic Arrays Multiplexers/Decoders ROMs
Field Programmable Gate Arrays Xilinx Vertex
“Random Logic”Full Custom Design
“Regular Logic”Structured Design
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 2
• • •
inputs
ANDarray
• • •
outputs
ORarrayproduct
terms
Programmable Logic Arrays (PLAs)
Pre-fabricated building block of many AND/OR gates Actually NOR or NAND ”Personalized" by making or breaking connections among gates Programmable array block diagram for sum of products form
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example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A
personality matrix 1 = uncomplemented in term0 = complemented in term– = does not participate
1 = term connected to output0 = no connection to output
input side:
output side:
product inputs outputsterm A B C F0 F1 F2 F3
AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1
reuse of terms
Enabling Concept
Shared product terms among outputs
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Before Programming
All possible connections available before "programming" In reality, all AND and OR gates are NANDs
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A B C
F1 F2 F3F0
AB
B'C
AC'
B'C'
A
After Programming Unwanted connections are "blown"
Fuse (normally connected, break unwanted ones) Anti-fuse (normally disconnected, make wanted connections)
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notation for implementingF0 = A B + A' B'F1 = C D' + C' D
AB+A'B'CD'+C'D
AB
A'B'
CD'
C'D
A B C D
Alternate Representation for High Fan-inStructures Short-hand notation--don't have to draw all the wires
Signifies a connection is present and perpendicular signal isan input to gate
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A B C F1 F2 F3 F4 F5 F60 0 0 0 0 1 1 0 00 0 1 0 1 0 1 1 10 1 0 0 1 0 1 1 10 1 1 0 1 0 1 0 01 0 0 0 1 0 1 1 11 0 1 0 1 0 1 0 01 1 0 0 1 0 1 0 01 1 1 1 1 0 0 1 1
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC
A B C
F1 F2 F3 F4 F5F6
full decoder as for memory address
bits stored in memory
Programmable Logic Array Example
Multiple functions of A, B, C F1 = A B C F2 = A + B + C F3 = A' B' C' F4 = A' + B' + C' F5 = A xor B xor C F6 = (A xnor B xnor C)’
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0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
D
A
B
C
minimized functions:
W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
D
A
B
C
K-map for W K-map for X
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
D
A
B
C
K-map for Y
PLA Design Example
BCD to Gray code converter
K-map for Z
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
D
A
B
C
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not a particularly goodcandidate for PLA
implementation since no terms are shared among outputs
however, much more compact and regular implementation
when compared with discrete AND and OR gates
A B C D
W X Y Z
A
BD
BC
BC'
B
C
A'B'C'D
BCD
AD'
BCD'
minimized functions:
W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
PLA Design Example (cont’d)
Code converter: programmed PLA
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0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
D
A
B
C
minimized functions:
W =X = Y = Z =
A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
D
A
B
C
K-map for W K-map for X
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
D
A
B
C
K-map for Y
PLA Design Example
BCD to Gray code converter
K-map for Z
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
D
A
B
C
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0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
D
A
B
C
minimized functions:
W =X = Y = Z =
A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
D
A
B
C
K-map for W K-map for X
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
D
A
B
C
K-map for Y
PLA Design Example #1
BCD to Gray code converter
K-map for Z
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
D
A
B
C
BC’
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 12 EQ NE LT GT
A'B'C'D'
A'BC'D
ABCD
AB'CD'
AC'
A'C
B'D
BD'
A'B'D
B'CD
ABC
BC'D'
A B C D
PLA Design Example #2
Magnitude comparator
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
D
A
B
C
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0
D
A
B
C
0 0 0 0
1 0 0 0
1 1 0 1
1 1 0 0
D
A
B
C
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
D
A
B
C
K-map for EQ K-map for NE
K-map for GTK-map for LT
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multiplexer demultiplexer 4x4 switch
control control
Multiplexer/Demultiplexer: MakingConnections Direct point-to-point connections between gates
Multiplexer: route one of many inputs to a single output
Demultiplexer: route single input to one of many outputs
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two alternative formsfor a 2:1 Mux truth table
functional form
logical form
A Z0 I0
1 I1
I1 I0 A Z0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1
Z = A' I0 + A I1
Multiplexers/Selectors
Multiplexers/Selectors: general concept 2n data inputs, n control inputs (called "selects"), 1 output Used to connect 2n points to a single point Control signal pattern forms binary index of input connected
to output
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2:1 mux: Z = A' I0 + A I1
4:1 mux: Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
In general, Z = Σ (mkIk)
in minterm shorthand form for a 2n:1 Mux
2 -1
I0I1I2I3I4I5I6I7
A B C
8:1mux
ZI0I1I2I3
A B
4:1mux
ZI0I1
A
2:1mux Z
k=0
n
Multiplexers/Selectors (cont'd)
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control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7
control signal A chooses which of theupper or lower mux's output to gate to Z
alternativeimplementation
C
Z
A B
4:1mux
2:1mux
2:1mux
2:1mux
2:1mux
I4I5
I2I3
I0I1
I6I7
8:1mux
Cascading Multiplexers
Large multiplexers implemented by cascading smaller ones
Z
I0I1I2I3
A
I4I5I6I7
B C
4:1mux
4:1mux
2:1mux
8:1mux
CS 150 - Fall 2005 – Lec. #3: Programmable Logic - 17CA B
01234567
10100011
S2
8:1 MUX
S1 S0
F
Multiplexers as Lookup Tables (LUTs)
2n:1 multiplexer implements any function of n variables With the variables used as control inputs and Data inputs tied to 0 or 1 In essence, a lookup table
Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)
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A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
C'
C'
0
1 A B
S1 S0
F0123
4:1 MUX
C'C'01
F
CA B
01234567
10100011
S2
8:1 MUX
S1 S0
Multiplexers as LUTs (cont’d)
2n-1:1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement
Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)
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Generalization
Example: F(A,B,C,D) implemented by an 8:1 MUX
n-1 mux control variables
single mux data variable
four possibleconfigurationsof truth table rowscan be expressedas a function of In
choose A,B,C as control variables
multiplexer implementation
I0 I1 . . . In-1 In F
. . . . 0 0 0 1 1
. . . . 1 0 1 0 1
0 In In' 1
CA B
01234567
1D01D’DD’D’
S2
8:1 MUX
S1 S0
1 0
1 0
1 1
0 0D
A
1 1
0 1
0 1
1 0
B
C
Multiplexers as LUTs (cont’d)
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Announcements
We took everyone on the wait list into the class Result is that Tu labs are very crowded! Th night lab is very light -- think of switching to get more TA face
time! Send email to [email protected] to request a lab change
First HW due Friday at 2 PM … just before Lab Lecture CS 150 hand-in box outside and just to the right of 125 Cory doors
Second HW on class web site
Use ucb.class.cs150 newsgroup for lab, hw, course questions!
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1:2 Decoder:O0 = G • S’O1 = G • S
2:4 Decoder: O0 = G • S1’ • S0’O1 = G • S1’ • S0O2 = G • S1 • S0’O3 = G • S1 • S0
3:8 Decoder: O0 = G • S2’ • S1’ • S0’O1 = G • S2’ • S1’ • S0O2 = G • S2’ • S1 • S0’O3 = G • S2’ • S1 • S0O4 = G • S2 • S1’ • S0’O5 = G • S2 • S1’ • S0O6 = G • S2 • S1 • S0’O7 = G • S2 • S1 • S0
Demultiplexers/Decoders
Decoders/demultiplexers: general concept Single data input, n control inputs, 2n outputs Control inputs (called “selects” (S)) represent binary index of
output to which the input is connected Data input usually called “enable” (G)
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demultiplexer generates appropriateminterm based on control signals
(it "decodes" control signals)
Demultiplexers as General-Purpose Logic
n:2n decoder implements any function of n variables With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function
A'B'C'A'B'CA'BC'A'BCAB'C'AB'CABC'ABC
CA B
01234567
S2
3:8 DEC
S1 S0
“1”
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F1
F2
F3
Demultiplexers as General-Purpose Logic(cont’d) F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D’ + A B C
F3 = (A' + B' + C' + D')
A B
0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD
4:16DECEnable
C D
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0 A'B'C'D'E'1234567
S2
3:8 DEC
S1 S0
A B
0123S1
2:4 DEC
S0
F
012 A'BC'DE'34567
S2
3:8 DEC
S1 S0
EC D
0 AB'C'D'E'1234567 AB'CDE
Cascading Decoders
5:32 decoder 1x2:4 decoder 4x3:8 decoders
3:8 DEC
01234567 ABCDE
EC D
S2 S1 S0 S2
3:8 DEC
S1 S0
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decoder
0 n-1
Address
2 -1n
0
1 1 1 1
word[i] = 0011
word[j] = 1010
bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches)
j
i
internal organization
word lines (only one is active – decoder is just right for this)
Read-only Memories
Two dimensional array of 1s and 0s Entry (row) is called a "word" Width of row = word-size Index is called an "address" Address is input Selected word is output
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F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
truth table
A B C F0 F1 F2 F30 0 0 0 0 1 00 0 1 1 1 1 00 1 0 0 1 0 00 1 1 0 0 0 11 0 0 1 0 1 11 0 1 1 0 0 01 1 0 0 0 0 11 1 1 0 1 0 0
block diagram
ROM8 words x 4 bits/word
address outputsA B C F0F1F2F3
ROMs and Combinational Logic
Combinational logic implementation (two-levelcanonical form) using a ROM
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ROM Structure
Similar to a PLA structure but with a fully decodedAND array Completely flexible OR array (unlike PAL)
n address lines
• • •
inputs
decoder 2n wordlines
• • •
outputs
memoryarray
(2n wordsby m bits)
m data lines
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ROM vs. PLA
ROM Design time is short (no need to minimize output functions) Most input combinations are needed (e.g., code converters) Little sharing of product terms among output functions Size doubles for each additional input Can't exploit don't cares Cheap (high-volume component) Can implement any function of n inputs Medium speed
PLA Design tools are available for multi-output minimization There are relatively few unique minterm combinations Many minterms are shared among the output functions Most complex in design, need more sophisticated tools Can implement any function up to a product term limit Slow (two programmable planes)
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PLAs: 100s of gate equivalents FPGAs: 1000-10000s gates Logic blocks
Implement combinationaland sequential logic
Interconnect Wires to connect inputs and
outputs to logic blocks I/O blocks
Special logic blocks atperiphery of device forexternal connections
Key questions: How to make logic blocks programmable? How to connect the wires? After the chip has been fabbed
Field-Programmable Gate Arrays
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Tradeoffs in FPGAs
Logic block - how are functions implemented: fixed functions(manipulate inputs) or programmable? Support complex functions, need fewer blocks, but they are bigger
so less of them on chip Support simple functions, need more blocks, but they are smaller so
more of them on chip
Interconnect How are logic blocks arranged? How many wires will be needed between them? Are wires evenly distributed across chip? Programmability slows wires down – are some wires specialized to
long distances? How many inputs/outputs must be routed to/from each logic block? What utilization are we willing to accept? 50%? 20%? 90%?
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IOB IOB IOB IOB
CLB CLB
CLB CLBIO
BIO
BIO
BIO
B
Wiring Channels
Xilinx 4000 Series Programmable GateArrays CLB - Configurable Logic Block
5-input, 1 output function or 2 4-input, 1 output functions optional register on outputs
Built-in fast carry logic
Can be used as memory
Three types of routing direct general-purpose long lines of various lengths
RAM-programmable can be reconfigured
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The Xilinx 4000 CLB
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Two 4-Input Functions, RegisteredOutput
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5-Input Function, CombinationalOutput
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CLB Used as RAM
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Xilinx 4000 Interconnect
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Xilinx FPGA Combinational Logic Examples
Key: General functions are limited to 5 inputs (4 even better - 1/2 CLB) No limitation on function complexity
Example 2-bit comparator:
A B = C D and A B > C D implemented with 1 CLB(GT) F = A C' + A B D' + B C' D'(EQ) G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D
Can implement some functions of > 5 input
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CLB
5-input Majority Circuit
CLB
CLB
CLB
7-input Majority Circuit
CLB
CLB
9 Input Parity Logic
Xilinx FPGA Combinational Logic
Examples N-input majority function: 1 whenever n/2 or more inputs are 1 N-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs!
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Xilinx FPGA Adder Example Example
2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout
CLB
A0 B0 Cin
S0
CLB
A1 B1
S1
CLB
A2 B2
C1S2
CLB
A3 B3
C2S3 C0Cout
S0
S1
C2
A1 B1 CinA0 B0
CLBS2
S3
Cout
A3 B3A2 B2
CLB
Full Adder, 4 CLB delays tofinal carry out
2 x Two-bit Adders (3 CLBseach) yields 2 CLBs to finalcarry out
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Combinational Logic ImplementationSummary
Regular Logic Structures Programmable Logic Arrays
Programmable connections: AND-OR (NOR-NOR) Arrays Multiplexers/decoders
Multipoint connections for signal routing Lookup Tables
ROMs Truth table in hardware
Field Programmable Gate Arrays (FPGAs) Programmable logic (LUTs, Truth Tables) and connections
Advantages/disadvantages of each