progresses in semiconductor industry introduction to digital ...8085 8086 286 386 486 pentium® p6...

B.Supmonchai June 13, 2005

2102-545 Digital ICs 1

Introductionto

Digital IC Design

Boonchuay SupmonchaiJune 6th, 2006

2102-545 Digital ICs Introduction 2

B.Supmonchai

Outlines Historical Perspectives

Progresses in Semiconductor Industry

Digital Design Metrics


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Questions to be answered What is driving the IC

industry?

Why is designing digitalICs today different than itwas before?

Will it change in future?


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The First Computer

The BabbageDifference Engine(1832)

Mechanical

25,000 parts

Cost £17,470




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The First Electronic Computer

ENIAC(1946)

17,468 VacuumTubes

167 sq.m.

160 KW

$500,000 and 18months to build

Unreliable


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The Transistor Revolution

First Transistor(1947)

Bardeen, Brattain,Shockley at Bell Lab

Point Contact

Germanium & Gold


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The First Integrated Circuit

First IC(1947)

7/16 in.

If he’d only gone to vacation…

Kilby at TI

Assembled Solid StateOscillator (a transistor+ components)

Germanium


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The Monolithic ICs

ECL 3-input Gate, Motorola 1966

First MonolithicBJT IC(1961)

Fairchild

Flipf-lop with 4 BJTsand 2 resistors

Commercial




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197110 micron2300 transistors800 KHz operation

Intel 4004- Microprocessor


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Intel Pentium IV - Microprocessor

20000.18 micron42 million transistors1.5 GHz operation


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More Recently

Ultra Large Scale Integration

System On Chip

More than 30 million transistors in 2002

Chip complexity has increased 1000 folds since its inceptionthirty years ago.

The term “Very Large Scale Integration” remains universal todenote any high-complexity chip.


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Economics of Semiconductor Market

0

50

100

150

200

1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

Global Sem

iconductor Billings

(Billions of U

S$)

1018 transistors manufactured in 2003 100 million for every human on the planet!

One of the fastest growing sectors in theworldwide economy


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In 1965, Gordon Mooreof Bell Lab noted thatthe number of transistorson a chip doubled every18 to 24 months

So he made a boldprediction that

“Semiconductortechnology will doubleits effectiveness every18 months”

Moore’s Law

161514131211109876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LO

G2 O

F T

HE

NU

MB

ER

OF

CO

MP

ON

EN

TS

PE

R IN

TE

GR

AT

ED

FU

NC

TIO

N


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Transistors on Lead Microprocessors double every 2 years

40048008

80808085 8086

286386

486Pentium®

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Moore’s Law in Microprocessors

Pentium IVPentium III

Pentium II


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40048008

80808085

8086286

386486

Pentium ®P6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s Law

Die Size Growth

Pentium IV

Pentium IIIPentium II




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Lead Microprocessors frequency doubles every 2 years

Doubles every2 years

Frequency

P6Pentium ®

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

Pentium IVPentium III

Pentium II


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P6Pentium

486386

2868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Pow

er (W

atts

)

Lead Microprocessors power continues to increase

Power Dissipation


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5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

Power delivery and dissipation will be prohibitive

Power will be a major problem


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400480088080

8085

8086

286 386486

Pentium® procP6

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low temp

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2)

Power Density




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Not Only Microprocessors - DRAM


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Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435MAnalog

Baseband

Digital Baseband(DSP + MCU)

PowerManagement

SmallSignal RF

PowerRF

(data from Texas Instruments)

Cell Phone

Not Only Microprocessors - Cell Phone


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Looking into the Future …

More portable, wearable, and more powerful devicesfor ubiquitous and pervasive computing…


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Logic Tr./ChipTr./Staff Month.

xxxxxx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

Source: Sematech

2003

1981

1983

1985

1987

1989 19

9119

93

1995

1997

1999

2001

2005

2007

2009

10,000

1,000

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

Chi

p(M

)

0.01

0.1

1

10

100

1,000

10,000

100,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

- Mo.

Com

plex

ity

Courtesy, ITRS Roadmap

Complexity outpaces Design Productivity!

Productivity Trends




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Technology shrinks by a factor of 0.7/generation

With every generation can integrate 2x morefunctions per chip; chip cost does not increasesignificantly

Cost of a function decreases by 2x But …

How to design chips with more and more functions? Design engineering population does not double every

two years…

Impact of Technology Scaling


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Design Productivity Crisis

We urgently need more efficient design methods! Exploit automation in various levels of abstraction

☞ Computer-Aided Design (CAD) Tools


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“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

α DSM α 1/DSM

?

Major Challenges in Digital Designs




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Design in Deep Submicron Design in the deep submicron (DSM) era creates

new challenges Devices become somewhat different

Global clocking becomes more challenging

Interconnect effects play a more significant role

Power dissipation may be the limiting factor

We must understand and be able to designdigital ICs in advanced technologies (at orbelow 180 nm)


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How to evaluate performance of a digital circuit(gate, block, …)? Cost (Yield) Reliability (Noise Immunity) Scalability (Fan-In, Fan-out) Speed (delay, operating frequency)

Power dissipation Energy to perform a function

Design Metrics


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NRE (non-recurrent engineering) costs design time and effort, mask generation

one-time cost factor

Recurrent costs silicon processing, packaging, test

proportional to volume

proportional to chip area

Cost of Integrated Circuits


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NRE Cost is increasing




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From http://www.amd.com

Going up to 12” (30cm)

Die Cost

Single Die

Wafer


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Fabrication capital cost per transistor (Moore’s law)

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.11

1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Cost (¢-per-transistor)

Year

Cost Per Transistor


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Yield

€

Y =No. of good chips per wafer

Total number of chips per wafer×100%

€

Die cost =Wafer cost

Dies per wafer ×Die yield

€

Dies per wafer =π × Wafer diameter/2( )2

Die area−π ×Wafer diameter

2 ×Die area


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�α is approximately 3

Defects

€

Die yield= 1+Defects per unit area× die area

α

−α

€

Die cost = f (Die area)4




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$4179%402961.5$15000.803Pentium

$27213%482561.6$17000.703SuperSparc

$14919%532341.2$15000.703DEC Alpha

$7327%661961.0$13000.803HP PA 7100

$5328%1151211.3$17000.804Power PC601

$1254%181811.0$12000.803486 DX2

$471%360431.0$9000.902386DX

DiecostYieldDies/

waferAreamm2

Def./cm2

Wafercost

Linewidth

MetallayersChip

Some Examples (in 1994)


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i(t)

Inductive coupling Capacitive coupling

v(t)

Power and groundnoise

VDD

Reliability

Noise in Digital Integrated Circuits


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V(x)

V(y)

VOH

VOL

VM

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

Voltage Transfer Characteristics

DC Operations


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V IL V IH Vin

Slope = -1

Slope = -1

V OL

V OH

Vout

“0” VOL

VIL

VIH

VOH

UndefinedRegion

“1”

Mapping between Analog and Digital




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Noise margin high

Noise margin low

Undefined Region

Gate Output Gate Input

VIH

VIL

"1"

"0"

VOH

VOL

NM H

NM L

Definition of Noise Margins


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Key Reliability Properties Absolute noise margin values are deceptive.

A floating node is more easily disturbed than a nodedriven by a low impedance (in terms of voltages)

Noise Immunity is the more important metric The capability to suppress noise sources

(Regenerative property)

Key metric: Noise transfer functions, Output impedance of the driver, and Input impedance of the receiver.


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A chain of inverters

v0 v1 v2 v3 v4 v5 v6

Regenerative Property

Ability to recover a corrupted signalto a well-defined digital signal


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Regenerative Property I

Regenerative

Vout

v0v2

v1

v3f(v)

finv(v)

VinNon-Regenerative

Vout

v0 v2

v1

v3 f(v)

finv(v)

Vin




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N

Fan-out N Fan-in M

M

Fan-in and Fan-outIndirectly define scalability


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Delay Definitions

Vout

tf

tpHL tpLH

trt

Vin

t

90%

10%

50%

50%

tpHL : High-to-Low propagation delay

tpLH : Low-to-High propagation delay

tr : Rise Time

tf : Fall Time


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Ring Oscillator

v0 v1 v 2 v 3 v4 v 5

v0 v 4 v 5V

t

An example of how to find delay of an inverter

T = 2 tp× N

tp


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vout

v in C

R

tp = ln (2) τ = 0.69 RC

An Important model – matches delay of inverter

Delay Model

€

vout(t)=V ⋅ 1−e−t /τ( )

τ = RC

A First-order RC Network




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Instantaneous power:p(t) = v(t) i(t) = Vsupply i(t)

Average power:

€

Pave =1T

p(t)dt =Vsupply

Tisupply t( )dt

t

t+T∫t

t+T∫

Power Dissipation

Peak power:Ppeak = Vsupply ipeak

i(t)

Vsupply

GND


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Power-Delay Product (PDP) =E = Energy per operation = Pav × tp

Energy-Delay Product (EDP) = Quality metric of gate = E × tp

Energy and Energy-Delay Product

Energy is limited in certain situations such as inCell Mobile phone, PC Notebooks, etc.


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Energy Calculation Examples

vout

v in C

R

€

vout(t)=V ⋅ 1−e−t /τ( )

First-order RC Network

€

E0→1 = P(t)0

T

∫ dt =Vdd isupply (t)0

T

∫ dt =Vdd CL0

Vdd

∫ dVout = CLVdd2

€

ECap = PCap (t)0

T

∫ dt = VoutiCap (t)0

T

∫ dt = CL0

Vdd

∫ VoutdVout = 12CLVdd

2


B.Supmonchai

Summary Digital integrated circuits have come a long way

and still have quite some potential left for thecoming decades

Some interesting challenges ahead Getting a clear perspective on the challenges and

potential solutions is the purpose of this course.

Understanding the design metrics that governdigital design is crucial Cost, reliability, speed, power and energy

dissipation.

progresses in semiconductor industry introduction to digital ...8085 8086 286 386 486 pentium® p6...

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