project characterization implementing a compressor in software and decompression in hardware...
TRANSCRIPT
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Project Characterization
Implementing a compressor in software and decompression in hardware
Presents by - Schreiber Beeri
Yavich Alon
Guided by – Porian Moshe
16.11.2010
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Intro
142❤
Compressed data(Wireless)
Gym
132❤
170❤ 79❤
130❤ 127❤
Gym Control Room
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Intro (Cont.)
Problem
Data transmission timeProcessing timeComplex layout
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Solution
Transmitter Compresses the dataReceiver extracts and displays
the data
Intro (Cont.)
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Project’s goalImplement a software
compressor with a hardware extractor.
◦Compressor -> Matlab ◦Extractor -> FPGA
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Algorithm
Run Length
Transmit Value & Repetitions
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Algorithm -simple Example
Picture pixel’s Values:
Transmitted data :repetition value
6 0
3 255
1 120
0 0 0 0 0 0 255 255 255 120
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Project’s requirements
1. Input of 640*480 picture resolution.2. Programming “Run length
algorithm” in Matlab, using it as the compressor.
3. Creating a data array from the algorithm’s output and wrapping it in a pre determined packet.
4. Sending the packet to the FPGA through serial communication using RS-232 protocol.
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5. Checking the compressed data in the FPGA for errors with a pre determined CRC.
6. Storing the compressed data to an external memory - SDRAM
7. Implementation of the extractor within the FPGA using VHDL.
8. Presenting the extracted data on display with VESA protocol.
Project’s requirements (Cont.)
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Project’s requirements
Picture to be compressed(640x480)
Displayed Picture(800x600)
HOST
VGA
DE2 Board
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Message Pack Structure
SOF
Type
Address
Data Length
Data (Payload)
CRC
EOF
8 bits
1 Byte
1 Byte
3 Bytes
1 Bytes
Up to 1 Kbytes(2 SDRAM’s full page)
1 Bytes
1 Bytes
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TOP ARCHITECTURE
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VGA
Display
HostMatlab
UART RXP
UART TXP
Message Decoder
RAM
MU
XMessage Encoder
RAM DEC
Display Controlle
r
RunLen Decoder
CRC
IS42S16400 SDRAM
SDRAM Controller
Arbiter
Mem Write
Mem Read
REGISTERS
Packet TX
Packet RX
Ext. Clk
PLL
ResetD’ bouncer
Ext. Reset
Sys.
ClkSys.
Rst
FPGA – Cyclone II
TX
RX
VESA
11
5,2
00K
Bit/se
c
800x600
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Matlab GUI (debug version)
Compression TimeCompression Ratio
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Compressed Data ExampleCompressed: Decompressed:
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MICRO ARCHITECTURE
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DATA
Ad
dr
DATA
COLOR
DATA
VALID
Message Decoder
RAM
DEC
Mem Write
Arbiter
SDRAM Controlle
r Mem Read
RunLen DecoderREGISTER
S
VGA Display
TX PACKPLL
Reset Debounc
er
Resets
SDARM
UART
Matlab
UART RXP
RAM Controlle
r
Display Controlle
r
FIFO(dual clock
)
UART TXP
REG Controlle
r
Addr REG
TYPE REG
CRC RX
REG
CRC CLC REG
Len REG
CM P
UART RXD
UART TXD from UART TX
VALID
DATA
REG CRC STATUS
ISEOF FROM MSG_DEC
MP REGS
RES
ET
FR
OM
M
SG
_DEC
RESET TO CMP
REQ
Byte_in_pack
VALIDISEOF FROM MSG_DEC
DATA
WR
EN
WR_addr
RD_adress
Type
DATA
DATA
REQ
REQ
EN
EN
REQ
AC
K
REQ
REQ
Adress
ACK VA
LID
DATA RX
_RD
Y t
o
MEM
REA
D
RX
_RD
Y f
rom
M
EM
RE
AD
DATA
_RD
Y t
o
ME
M R
EA
D
DATA
_RD
Y f
rom
M
EM
RE
AD
REP
VALID
DATA
COLOR CO
L_EN
DATA
RGB
UART TXD to UART TX
50MHZ
40MHZ (VESA)133MHZ (SDRAM, System – optional )80MHz (System - optional)
1 bit8 bits
10 bits16 bits22 bits
Line legend
Data &
Control
Data &
Control
MSG_OK
Num Pixels
n_p
ix
40MHz
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Schedule To do… Date Num.
Theoretical self-instruction 1.10 – 16.10 1
Run length algorithm implementation
17.10 – 23.10 2
SDRAM Controller implementation 24.10 – 30.10 3
Architecture definition 31.10 – 15.11 4
Project Characterization presentation 16.11 5
Full characterization of all blocks 17-1.12 6
Implement UART RX-MP & TB 2.12-8.12 7
Implement UART TX-MP & TB 9-15.12 8
Prepare Mid. Presentation 16-27.12 9
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Schedule To do… Date Num.
Implement Display Controller & TB 28.12-12.1 10
Implement RAM controller & TB 6.1-19.1 11
Exams!!! Prepare documentation to existing models, end of semester presentation, and final semester A
report
20.1-22.2 12
Present end of semester presentation
23.2 13