project report
DESCRIPTION
mnbnTRANSCRIPT
BATTERY OPERATED WHEEL CHAIR
B.Tech. Project Report
MOHD MAQBOOL AHMED AZIZ
P.ARUN KUMAR
N.KUSHAL
Department of Mechanical Engineering
BHASKAR ENGINEERING COLLEGE(Affiliated to JNTU-HYD & Approved by AICTE )
Yenkapally, Moinabad Mandal,R R Dist. Telangana – 500075
2011-2015
BATTERY OPERATED WHEEL CHAIR
Project report Submitted in partial fulfilment
of the requirements for the degree of
BACHELOR OF TECHNOLOGY
IN
MECHANICAL ENGINEERING
BY
MOHD MAQBOOL AHMED AZIZ 11GE1A0332P.ARUN KUMAR 11GE1A0339N.KUSHAL 11GE1A0334
Under the Esteemed Guidance of
P.Sreenivasulu
Assistant Professor
Department of Mechanical Engineering
BHASKAR ENGINEERING COLLEGE(Affiliated to JNTU-HYD & Approved by AICTE )
Yenkapally, Moinabad Mandal,R R Dist. Telangana – 500075
2011-2015
BHASKAR ENGINEERING COLLEGE(Accredited by NBA, Affiliated to JNTU-H & Approved by AICTE)
Yenkapally, Moinabad Mandal, R.R.Dist., Telangana 500075. Website: www.bec.ac.in
CERTIFICATE
This is to certify that the project work entitled “BATTERY OPERATED WHEEL
CHAIR” is a bonafide work carried out by
MOHD MAQBOOL AHMED AZIZ 11GE1A0332
P.ARUN KUMAR 11GE1A0339
N.KUSHAL 11GE1A0334
in partial fulfilment of the requirements for the degree of BACHELOR OF TECHNOLOGY in
MECHANICAL ENGINEERING by the JNTU-HYD, Hyderabad during the academic years
2011-15
The results embodied in this report have not been submitted to any other University or
Institution for the award of any degree or diploma.
INTERNAL GUIDE HEAD OF THE DEPARTMENT
EXTERNAL EXAMINER PRINCIPAL
ACKNOWLEDGEMENT
We are highly indebted to our Faculty Liaison Mr.P.Sreenivasulu, Mechanical
Engineering Department, who has given us all the necessary technical guidance in carrying out
this Project.
We wish to express our sincere thanks to our principal Dr.TOWHEED
SULTANA(M.E,Ph.D) & Dr. SRINIVAS THRIDANDAPANY(M.TECH Ph.D), Head of the
Department of Mechanical Engineering, Bhaskar Engineer College., for permitting us to pursue
our Project and encouraging us throughout the Project.
Finally, we thank all the people who have directly or indirectly help us through the
course of our Project.
We express our deep sense of gratitude to our Guide Mr.P.Sreenivasulu, for his valuable
guidance and encouragement in carrying out our Project
MOHD MAQBOOL AHMED AZIZ _________________
P.ARUN KUMAR _________________
N.KUSHAL _________________
ABSTRACT
A Battery operated wheelchair, power chair, electric wheelchair or electric-powered
wheelchair (EPW) is a wheelchair that is propelled by means of an electric motor rather than
manual power.
Battery operated wheelchairs are useful for those unable to propel a manual wheelchair or
who may need to use a wheelchair for distances or over terrain which would be fatiguing in a
manual wheelchair.
They may also be used not just by people with 'traditional' mobility impairments, but also
by people with cardiovascular and fatigue based conditions. Battery operated wheelchairs extend
the capabilities of traditional powered devices by introducing control and navigational
intelligence. These devices can ease the lives of many disabled people, particularly those with
severe impairments, by increasing their range of mobility.
A battery operated wheelchair has been under development at the University of
Wollongong for some years. This thesis describes ongoing work towards the ultimate aim of an
intelligent and useful device.
LIST OF FIGURES
Fig No Name of the Figure Page No
LIST OF TABLES
Fig No Name of the Table Page No
TABLE OF CONTENTS
CERTIFICATE ii
ACKNOWLEDGEMENTS iii
ABSTRACT iv
LIST OF FIGURES v
LIST OF TABLES vi
CHAPTER 1. INTRODUCTION
1.1 Aim of the project
1.2 Significance and applications
1.3 Organization of the report
CHAPTER 2. OVERVIEW
2.1 Block Diagram
2.2 Circuit Diagram
2.3 Description
CHAPTER3. HARDWARE DESCRIPTION
3.1 Microcontroller
3.1.1 A Brief History of AVR
3.1.2 Description of AVR ATmega8 Microcontroller
3.1.3 Block Diagram of the AVR MCU Architecture
3.1.4 Pin Configurations
3.1.5 Timers/Counter
3.1.6 Interrupts3.1.7 AVR ATmega8 Memories
3.2 Regulated Power Supply
3.2.1 Description
3.2.2 General Description
3.2.3 Features
3.2.4 Pin Description
3.2.6 Applications
3.3 DTMF MT8870D3.3.1 Features
3.3.2 Pin Configuration
3.3.3 Functional Description
3.3.4 Applications
CHAPTER 4. SOFTWARE DESCRIPTION
4.1 WinAVR
4.1.1 History of WinAVR
4.1.2 Composition
4.1.3 Steps to write code
4.1.4 Important Notes
4.2 HIDBootFlash
CHAPTER 5. ALGORITHM
5.1 Algorithm
CHAPTER 6. ADVANTAGES & LIMITATIONS
6.1 Advantages
6.2 Limitations
CHAPTER 7. CONCLUSIONS
7.1 Conclusions and Future scope
BIBLOGRAPHY
CHAPTER-1
INTRODUCTION
CHAPTER-1
INTRODUCTION
Robotic technologies have the potential to improve the lifestyles of people suffering from
one or more disabilities. Related developments are often grouped under the terms Rehabilitation
Technologies or Assistive Technologies. They attempt to restore human abilities that have been
reduced or lost by disease, accident, or old age. Mobility is one such function.
There are many reasons why a person may not be able to travel freely, including motor
control problems, spinal injuries, and amputation. A wheelchair is a mechanical device that can
often assist. It effectively uses wheels and mechanical support to overcome a loss of legs or leg
control. Manual wheelchairs can be operated by persons who have the use of their upper body or
someone available to assist. Powered wheelchairs have been developed for when either of these
cases does not apply.
However, these devices typically require a high level of user control and this is
something precluded by many severe forms of disablement. In recent decades many groups have
researched the possibilities of robotic wheelchairs. These endeavours are aimed at creating
‘intelligent’ devices that can sense information from their environment and respond in useful
ways.
A robotic wheelchair has been under development at the University of Wollongong since
1989.
A Robotic Wheelchair was developed from scratch. It consists of a car seat, two
pneumatic tyres and two castor wheels mounted on a metal chassis. The system is powered by
two 12V batteries stowed beneath the seat. An unusual feature of this design is that the drive
wheels are located at the front and the supporting castor wheels are at the rear. Most similar
designs use a contrary placement of wheels. This configuration allows the chair to cross more
obstacles than would otherwise be possible, but it also complicates the system dynamics and
makes control more difficult.
Optical position encoders are installed in the wheelchair motor casings. These sensors
provide feedback for speed and position control. Four ultrasonic sensors, two at the front and one
on each side, provide information for navigation and obstacle avoidance.
The electronic subsystems are mounted behind the chair on a metal platform. There are
circuits for power supply filtering, motor operation, feedback control, sensor operation and
autonomous control.
The UOW Robotic Wheelchair is distinguished from most other similar projects in its
attempts to produce practical results using a minimum of equipment and computing power.
These aims can be further defined through three distinct criteria; 1. Cost Effectiveness A robotic
wheelchair will benefit the most individuals if the cost is not prohibitive. This factor currently
precludes certain types of sensor, such as laser range finders and GPS units. 2. It must use
practical components. Components should consider total system weight and dimensions.
They should seek to maximise on-board battery life through power efficiency and
minimise maintenance concerns through simplicity and durability. 3. It must respond smoothly in
real-time. The wheelchair should not require any offline processing, nor should it halt to evaluate
information whilst operationally engaged.
The wheelchair control system is composed of Power Electronics, a Drive Controller and
a Master Controller.
These subsystems are interconnected :-
Drive Controller
Power Electronics
Master Controller
Analog Joystick
Left DC Motor & Gear Box
Right DC Motor & Gear Box
Left Position Encoder
Right Position Encoder
Front-Left Ultrasonic Sensor
Front-Right Ultrasonic Sensor
Side-Left Ultrasonic Sensor
Side-Right Ultrasonic Sensor
The Power Electronics controls current to both DC motors in order to create the torque
requested by the Drive Controller.
The Drive Controller receives input from either an analogue joystick or the Master
Controller. It combines this information with position and velocity feedback from position
encoders by way of two control loops to determine appropriate signals for the Power Electronics.
It aims to move the wheelchair in a specified direction at a given speed.
The Master Controller receives environmental information from four ultrasonic sensors
and movement information from the Drive Controller. It is able to instruct the Drive Controller
via a serial connection.
The UOW Robotic Wheelchair has been under development for several years. Early work
was concerned with the mechanics, power electronics, speed measurement and digital control
systems [2, 3, 4, 5]. Later work has concentrated on implementing aspects of intelligent control
such as sonar ranging sensors, Master Controller serial communications, obstacle avoidance and
autonomous navigation [6, 7, 8].
This report documents work aimed at simplifying and consolidating the existing robotic
wheelchair. Specifically, existing microprocessors will be exchanged for newer more powerful
versions. New programs and interface electronics will be developed and tested.
This report began with an introduction to Assistive Technologies and the UOW Robotic
wheelchair project. A review of existing robotic wheelchair literature and several related areas of
research follows. The updated Drive Controller unit is described before techniques used to tune
and test it are presented. Aspects of the updated Master Controller are detailed, followed by a
chapter describing the testing approach employed and its results. The report closes with a
summary and recommendations for future work.
1.2 CAD/CAM DESIGN
CHAPTER -2
MECHANICAL DESIGN
CASTER WHEEL
A caster (or castor) is an undriven, single, double, or compound wheel that is designed
to be mounted to the bottom of a larger object (the "vehicle") so as to enable that object to be
easily moved. They are available in various sizes, and are commonly made of rubber, plastic,
nylon, aluminium, or stainless steel.
Casters are found in numerous applications, including shopping carts, office chairs, and
material handling equipment. High capacity, heavy duty casters are used in many industrial
applications, such as platform trucks, carts, assemblies, and tow lines in plants. Generally,
casters operate well on smooth and flat surfaces.
Types
Casters may be fixed to roll along a straight line path, or mounted on a pivot such that the
wheel will automatically align itself to the direction of travel.
Rigid casters
A basic, rigid caster consists of a wheel mounted to a stationary fork. The orientation of
the fork, which is fixed relative to the vehicle, is determined when the caster is mounted to the
vehicle. An example of this is the wheels found at the rear of a shopping cart. Rigid casters tend
to restrict vehicle motion so that the vehicle travels along a straight line.
Swivel casters
Like the simpler rigid caster, a swivel caster incorporates a wheel mounted to a fork, but
an additional swivel joint above the fork allows the fork to freely rotate about 360°, thus
enabling the wheel to roll in any direction.
Fig 2.1 A swivel caster.
This makes it possible to easily move the vehicle in any direction without changing its
orientation. Swivel casters are sometimes attached to handles so that an operator can manually
set their orientation.
When in motion along a straight line, a swivel caster will tend to automatically align to,
and rotate parallel to the direction of travel. This can be seen on a shopping cart when the front
casters align parallel to the rear casters when traveling down an aisle. A consequence of this is
that the vehicle naturally tends to travel in a straight direction. Precise steering is not required
because the casters tend to maintain straight motion.
This is also true during vehicle turns. The caster rotates parallel to the turning radius and
provides a smooth turn. This can be seen on a shopping cart as the front wheels rotate at different
velocities, with different turning radius depending on how tight a turn is made.
The angle and distance of the wheel axles and swivel joint can be adjusted for different
types of caster performance.
Caster flutter
One major disadvantage of the casters is flutter. A common example is on a supermarket
shopping cart, when one caster rapidly swings side-to-side. This oscillation is known as shimmy
or caster flutter and occurs naturally at certain speeds. The speed at which a caster flutters is
based on the weight on the caster and the distance between the wheel axle and steering joint.
This distance is known as trailing distance. Increasing this distance can eliminate flutter at
moderate speeds. Generally, flutter occurs at high speeds.
What makes flutter dangerous is that it can cause a vehicle to suddenly move in an
unwanted direction. Flutter occurs when the caster is not in full contact with the ground and
therefore its orientation is uncontrollable. As the caster regains full contact with the ground, it
can be in any orientation.
This can cause the vehicle to suddenly move in the direction that the caster is pointed. At
slower speeds, the caster’s ability to swivel can correct the direction and can continue travel in
the desired direction. But at high speeds this can be dangerous as the wheel may not be able to
swivel quickly enough and the vehicle may lurch in any direction.
Electric and racing wheelchair designers are very concerned with flutter because the chair
must be safe for riders. Increasing trailing distance can increase stability at higher speeds for
wheelchair racing, but may create it at lower speeds for everyday use. Unfortunately, the more
trail the caster has, the more space the caster requires to swivel. Therefore, in order to
accommodate this extra swivel space, lengthening of frame or extending the footrests maybe
required. This tends to make the chair more cumbersome. Caster flutter can be controlled by
adding dampers or increasing the friction of the swivel joints.
A simple method for completing is by adding washers to the swivel joint. The friction
increases as the weight on the front of the chair increases. Anytime the caster begins to flutter, it
slows the chair and shifts weight to the front wheels. There are several online anti-flutter kits for
retrofitting wheel chair casters in this manner.
FRAME
Drive Wheels
Industrial drive wheels are used throughout industry. The applications are varied, but all
involve fixing a wheel to a shaft. The most common means of securing a wheel to a shaft is with
a keyway and/or setscrews. Other set-ups include tapered locking bushing, welding, interference
fit, nuts and bolts, and cotter pins.
Keyways can be machined in most wheel sizes. The wheel hub diameter must be large
enough to allow 1/4” of metal between the hub outside diameter and the bottom of the keyway.
Because of the extra stress involved with keyed wheels, capacity ratings should be
reduced by 75% and our normal warranty does not apply. When ordering, please specify shaft
size as well as the width and depth of desired keyway. The chart at right shows the standard
keyway dimensions in relation to the shaft diameter.
Set screws are also available. Unless otherwise specified, if one set screw is desired it
will be placed over the keyway. If two, the second will be at 90° from the keyway.
CHAIR
CHAPTER-3
DRIVE SECTION
SERVO MOTORS
BATTERIES
JOYSTICK
PLATFORM
CHAPTER 4
ELECTRONIC DESCRIPTION
CHAPTER 4
ELECTRONIC DESCRIPTION
4. ELECTRONIC DESCRIPTION
The block diagram of the system is as shown in the fig. The system basically consists of a
1. Micro controller,
2. DC motor,
3. LED,
4. Power supply,
5. Printed circuit boards
4.1 MICROCONTROLLER ARCHITECHTURE
4.1.1 A Brief History of 8051
In 1981, Intel Corporation introduced an 8 bit microcontroller called 8051.
This microcontroller had 128 bytes of RAM, 4K bytes of chip ROM, two timers, one
serial port, and four ports all on a single chip. At the time it was also referred as “A
SYSTEM ON A CHIP”
The 8051 is an 8-bit processor meaning that the CPU can work only on 8 bits
data at a time. Data larger than 8 bits has to be broken into 8 bits pieces to be
processed by the CPU. The 8051 has a total of four I\O ports each 8 bit wide.
There are many versions of 8051 with different speeds and amount of on-chip
ROM and they are all compatible with the original 8051. This means that if you write
a program for one it will run on any of them.
The 8052 is an original member of the 8051 family. There are two other
members in the 8051 family of microcontrollers. They are 8052 and 8031. All the
three microcontrollers will have the same internal architecture, but they differ in the
following aspects.
1. 8031 has 128 bytes of RAM, two timers and 6 interrupts.
Of the three microcontrollers, 89S51 is the most preferable. Microcontroller supports
both serial and parallel communication.
In the concerned project 89S52 microcontroller is used. Here microcontroller used
is AT89S52, which is manufactured by ATMEL laboratories.
4.1.2 Description of 89S52 Microcontroller
The AT89S52 provides the following standard features: 8Kbytes of Flash, 256 bytes
of RAM, 32 I/O lines, three 16-bit timer/counters, six-vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is
designed with static logic for operation down to zero frequency and supports two software
selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue functioning. The Power down
Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions
until the next hardware reset.
By combining a versatile 8-bit CPU with Flash on a monolithic chip, the
AT89S52 is a powerful microcomputer which provides a highly flexible and cost
effective solution to many embedded control applications.
Features of Microcontroller (89S52)
1. Compatible with MCS-51 Products
2. 8 Kbytes of In-System Reprogrammable Flash Memory
3. Endurance: 1,000 Write/Erase Cycles
4. Fully Static Operation: 0 Hz to 24 MHz
5. Three-Level Program Memory Lock
6. 256 x 8-Bit Internal RAM
7. 32 Programmable I/O Lines
8. Three 16-Bit Timer/Counters
9. Eight vector two level Interrupt Sources
10. Programmable Serial Channel
11. Low Power Idle and Power Down Modes
12. In addition, the AT89S52 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port
and interrupt system to continue functioning. The Power down Mode saves the RAM
contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.
4.1.3 Block Diagram of Microcontroller
Fig 4.1: Functional block diagram of AT89S52
4.1.4 Pin Configurations
Figure 4.2 Pin Diagram of 89S52
Pin Description
VCC
Pin 40 provides Supply voltage to the chip. The voltage source is +5v
GND.
Pin 20 is the grounded
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port from pin 32 to 39. As an output
port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins
can be used as high-impedance inputs. Port 0 may also be configured to be the
multiplexed low-order address/data bus during accesses to external program and data
memory. In this mode P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming, and outputs the
code bytes during program verification. External pull-ups are required during
program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups from pin 1 to 8. The
Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1
pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source current (IIL) because of
the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external
count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively,
as shown in following table.
Port 1 also receives the low-order address bytes during Flash programming and
program verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups from pin 21 to 28.
The Port 2 output buffers can sink / source four TTL inputs. When 1s are written to Port
2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups from pin 10 to 17. The
Port 3 output buffers can sink / source four TTL inputs. When 1s are written to Port 3
pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source current (IIL) because of the
pull-ups.
Port 3 also serves the functions of various special features of the AT89C52 as listed
below:
Table 4.1 Special Features of port3
RST
Pin 9 is the Reset input. It is active high. Upon applying a high pulse to this pin,
the microcontroller will reset and terminate all activities. A high on this pin for two
machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch is an output pin and is active high. Address Latch Enable output
pulse for latching the low byte of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Flash programming. In normal
operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes.
Note, however, that one ALE pulse is skipped during each access to external Data
Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.
With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise,
the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the
microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory. When the
AT89S52 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
EA/VPP
External Access Enable EA must be strapped to GND in order to enable the
device to fetch code from external program memory locations starting at 0000H up to
FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on
reset. EA should be strapped to VCC for internal program executions. This pin also
receives the 12-volt programming enable voltage (VPP) during Flash programming when
12-volt programming is selected.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on chip oscillator, as shown in Figure
5.4. Either a quartz crystal or ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while XTAL1 is driven .
Fig. 4.3 Crystal Connections
Fig. 4.4 External Clock Drive Configuration
There are no requirements on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divide-by two flip-flop, but minimum and
maximum voltage high and low time specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain
active. The mode is invoked by software. The content of the on-chip RAM and all the
special functions registers remain unchanged during this mode. The idle mode can be
terminated by any enabled interrupt or by a hardware reset. It should be noted that when
idle is terminated by a hardware reset, the device normally resumes program execution,
from where it left off, up to two machine cycles before the internal reset algorithm takes
control.
On-chip hardware inhibits access to internal RAM in this event, but access to the port
pins is not inhibited.
Power down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes
power down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the power down mode is terminated. The only exit from
power down is a hardware reset. Reset redefines the SFRs but does not change the on-
chip RAM. The reset should not be activated before VCC is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
Table 4.2 Status Of External Pins During Idle and Power Down Mode
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be
programmed (P) to obtain the additional features listed in the table 5.4. When lock bit 1 is
programmed, the logic level at the EA pin is sampled and latched during reset. If the
device is powered up without a reset, the latch initializes to a random value, and holds
that value until reset is activated. It is necessary that the latched value of EA be in
agreement with the current logic level at that pin in order for the device to function
properly.
Table 4.3 Lock Bit Protection Modes
TIMERS
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer
1 in the AT89S52.
Register pairs (TH0, TL1), (TH1, TL1) are the 16-bit counter registers for timer/c;
ounters 0 and 1.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event
counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three
operating modes: capture, auto-reload (up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 5.2. Timer 2 consists of two 8-bit
registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12
of the oscillator frequency.
Table 4.4 Timer 2 Operating Modes
In the Counter function, the register is incremented in response to a 1-to-0 transition
at its corresponding external input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a high in one cycle and a low
in the next cycle, the count is incremented. The new count value appears in the register
during S3P1 of the cycle following the one in which the transition was detected. Since two
machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the
maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is
sampled at least once before it changes, the level should be held for at least one full machine
cycle.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit
can then be used to generate an interrupt. IfEXEN2 = 1, Timer 2 performs the same
operation, but a 1-to-0 transition at external input T2EX also causes the current value in
TH2 and TL2 to be captured into RCAP2H andRCAP2L, respectively. In addition, the
transition at T2EXcauses bit EXF2 in T2CON to be set. The EXF2 bit, likeTF2, can
generate an interrupt.
Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit
auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit
located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that
timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down,
depending on the value of the T2EX pin.
Table4.5: T2MOD-Timer 2 Mode Control Register
Table4.6: T2CON-Timer/Counter2 Control Register
4.1.5 Interrupts
The AT89C52 has a total of six interrupt vectors: two external interrupts (INT0
and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 2.5
Each of these interrupt sources can be individually enabled or disabled by setting
or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA,
which disables all interrupts at once.
Fig. 4.5 Interrupts Source
Note that Table 5.3 shows that bit position IE.6 is unimplemented. In the
AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to
these bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the service routine is
vectored to. In fact, the service routine may have to determine whether it was TF2 or
EXF2 that generated the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in
which the timers overflow. The values are then polled by the circuitry in the next cycle.
However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which
the timer overflows.
Table 4.7 Interrupts Enable Register
4.1.6 Special function registers:
Special function registers are the areas of memory that control specific
functionality of the 89c52 microcontroller.
a) Accumulator (0E0h)
As its name suggests, it is used to accumulate the results of large no. of
instructions. It can hold 8 bit values.
b) B register (oFoh)
The B register is very similar to accumulator. It may hold 8-bit value. The B
register is only used by MUL AB and DIV AB instructions. In MUL AB the higher byte
of the products gets stored in B register. In DIV AB the quotient gets stored in B with the
remainder in A.
c) Stack pointer (081h)
The stack pointer holds 8-bit value. This is used to indicate where the next value
to be removed from the stack should be taken from. When a value is to be pushed on to
the stack, the 8052 first store the value of SP and then store the value at the resulting
memory location. When a value is to be popped from the stack, the 8052 returns the value
from the memory location indicated by SP and then decrements the value of SP.
d) Data pointer (Data pointer low/high, address 82/83h)
The SFRs DPL and DPH work together to represent a 16-bit value called the data
pointer. The data pointer is used in operations regarding external RAM and some
instructions code memory. It is a 16-bit SFR and also an addressable SFR.
e) Program counter
The program counter is a 16 bit register, which contains the 2 byte address, which
tells the next instruction to execute to be found in memory. When the 8052 is initialized
PC starts at 0000h and is incremented each time an instruction is executes. It is not
addressable SFR.
f) PCON (power control, 87h)
The power control SFR is used to control the 8052’s power control modes.
Certain operation modes of the 8052 allow the 8052 to go into a type of “sleep mode”
which consumes low power.
g) TCON(Timer control, 88h)
The timer mode control SFR is used to configure and modify the way in which
the 8052’s two timers operate. This SFR controls whether each of the two timers is
running or stopped and contains a flag to indicate that each timer has overflowed.
Additionally, some non-timer related bits are located in TCON SER. These bits are used
to configure the way in which the external interrupt flags are activated, which are set
when an external interrupt occur.
h)TMOD(Timer Mode,89h)
The timer mode SFR is used to configure the mode of operation of each of the
two timers. Using this SR your program may configure each timer to be a 16-bit timer, or
13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may
configure the timers to only count when an external pin is activated or to count “events”
that are indicated on an external pin.
Gate C/ T M1 M0 Gate C/ T M1 M0
TIMER1 TIMER0
i) T0 (Timer 0 low/ high, address 8A/ 8C h)
These two SFRs together represent timer 0. Their exact behavior depends on how
the timer is configured in the TMOD SFR; however, these timers always count up. What
is configurable is how and when they increment value.
j) T1 (Timer 1 low/ high, address 8B/ 8D h)
These two SFRs together represent timer 1. Their exact behavior depends on how
the timer is configured in the TMOD SFR; however, these timers always count up. What
is configurable is how and when they increment in value.
k) P0 (Port 0, address 80h, bit addressable)
This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0
of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.
l) P1(Port 1, address 90h, bit addressable)
This is port 1 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 1 is first written on P1 register. For e.g., bit 0
of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.
m) P2 (Port 2, address 0A0h, bit addressable)
This is port 2 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 2 is first written on P2 register. For e.g., bit 0
of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.
n) P3 (Port 3, address 0B0h, bit addressable)
This is port 3 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 3 is first written on P3 register. For e.g., bit 0
of port 3 is pin P4.0, bit 7 is pin P4.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.
o) IE (Interrupt Enable, 0A8h)
The interrupt enable SFR is used to enable and disable specific interrupts. The
low 7 bits of the SFR are used to enable/disable the specific interrupts, where the MSB
bit is used to enable or disable all the interrupts. Thus, if the high bit of IE 0 all interrupts
are disabled regardless of whether an individual interrupt is enabled by setting a lower
bit.
p) IP (Interrupt Priority, 0B8h)
The interrupt priority SFR is used to specify the relative priority of each interrupt. On
8052, an interrupt may be either low or high priority. An interrupt may interrupt interrupts.
For e.g., if we configure all interrupts as low priority other than serial interrupt. The serial
interrupt always interrupts the system; even if another interrupt is currently executing no
other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt
routine has the highest priority.
_ _ _ _ _ _
PT2 PS PT1 PX1 PT0 PX0
q)PSW (Program Status Word, 0D0h)
The Program Status Word is used to store a number of important bits that are set
and cleared by 8052 instructions. The PSW SFR contains the carry flag, the auxiliary
carry flag, the parity flag and the overflow flag. Additionally, it also contains the register
bank select flags, which are used to select, which of the “R” register banks currently in
use.
CY AC F0 RS1 RS0 OV - - - - P
r) SBUF (Serial Buffer, 99h)
SBUF is used to hold data in serial communication. It is physically two registers.
One is writing only and is used to hold data to be transmitted out of 8052 via TXD. The
other is read only and holds received data from external sources via RXD. Both mutually
exclusive registers use address 99h.
4.1.7 Memory Organization
The total memory of 89C52 system is logically divided in Program memory and
Data memory. Program memory stores the programs to be executed, while data memory
stores the data like intermediate results, variables and constants required for the execution
of the program. Program memory is invariably implemented using EPROM, because it
stores only program code which is to be executed and thus it need not be written into.
However, the data memory may be read from or written to and thus it is implemented
using RAM.
Further, the program memory and data memory both may be categorized as on-chip
(internal) and external memory, depending upon whether the memory physically exists on the
chip or it is externally interfaced. The 89C52 can address 8Kbytes on-chip memory whose map
starts from 0000H and ends at 1FFFH. It can address 64Kbytes of external program memory
under the control of PSEN (low) signal.
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a
parallel address space to the Special Function Registers. That means the upper 128bytes have
the same addresses as the SFR space but are physically separate from SFR space. When an
instruction accesses an internal location above address 7FH, the address mode used in the
instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR
space. Instructions that use direct addressing access SFR space. For example, the following
direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper128 bytes of RAM. For
example, the following indirect addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose address is 0A0H)
.MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128
bytes of data RAM are available as stack space.
4.2. REGULATED POWER SUPPLY
4.2.1 Description
A variable regulated power supply, also called a variable bench power supply, is
one where you can continuously adjust the output voltage to your requirements. Varying
the output of the power supply is the recommended way to test a project after having
double checked parts placement against circuit drawings and the parts placement guide.
This type of regulation is ideal for having a simple variable bench power supply. Actually
this is quite important because one of the first projects a hobbyist should undertake is the
construction of a variable regulated power supply. While a dedicated supply is quite
handy e.g. 5V or 12V, it's much handier to have a variable supply on hand, especially for
testing. Most digital logic circuits and processors need a 5 volt power supply. To use
these parts we need to build a regulated 5 volt source. Usually you start with an
unregulated power supply ranging from 9 volts to 24 volts DC (A 12 volt power supply is
included with the Beginner Kit and the Microcontroller Beginner Kit.). To make a 5 volt
power supply, we use a LM7805 voltage regulator IC .
Fig.4.6 Diagram of Power Supply
The LM7805 is simple to use. You simply connect the positive lead of your unregulated
DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the
negative lead to the Common pin and then when you turn on the power, you get a 5 volt
supply from the Output pin.
Circuit Features:
· Brief description of operation: Gives out well regulated +5V output, output current
capability of 100 mA
· Circuit protection: Built-in overheating protection shuts down output when regulator IC
gets too hot
· Circuit complexity: Very simple and easy to build
· Circuit performance: Very stable +5V output voltage, reliable operation
· Availability of components: Easy to get, uses only very common basic components
· Design testing: Based on datasheet example circuit, I have used this circuit successfully
as part of many electronics projects
· Applications: Part of electronics devices, small laboratory power supply
· Power supply voltage: Unregulated DC 8-18V power supply
· Power supply current: Needed output current + 5 mA
· Component costs: Few dollars for the electronics components + the input transformer
cost
4.2.2 IC Voltage Regulators:
Voltage regulators comprise a class of widely used ICs. Regulator IC units
contain the circuitry for reference source, comparator amplifier, control device, and
overload protection all in a single IC. Although the internal construction of the IC is
somewhat different from that described for discrete voltage regulator circuits, the external
operation is much the same. IC units provide regulation of either a fixed positive voltage,
a fixed negative voltage, or an adjustably set voltage.
A power supply can be built using a transformer connected to the ac supply line to
step the ac voltage to desired amplitude, then rectifying that ac voltage, filtering with a
capacitor and RC filter, if desired, and finally regulating the dc voltage using an IC
regulator. The regulators can be selected for operation with load currents from hundreds
of mill amperes to tens of amperes, corresponding to power ratings from mill watts to
tens of watts.
Three-Terminal Voltage Regulators:
Fixed Positive Voltage Regulators:
Vin IN OUT Vout
C1 78XX C2
GND
Fig shows the basic connection of a three-terminal voltage regulator IC to a load.
The fixed voltage regulator has an unregulated dc input voltage, Vi, applied to one input
terminal, a regulated output dc voltage, Vo, from a second terminal, with the third terminal
connected to ground. While the input voltage may vary over some permissible voltage
range, and the output load may vary over some acceptable range, the output voltage remains
constant within specified voltage variation limits. A table of positive voltage regulated ICs
is provided in table. For a selected regulator, IC device specifications list a voltage range
over which the input voltage can vary to maintain a regulated output voltage over a range of
load current. The specifications also list the amount of output voltage change resulting from
a change in load current (load regulation) or in input voltage (line regulation).
4.3 RELAYS:
A relay is an electrically operated switch. Current flowing through the coil of
the relay creates a magnetic field which attracts a lever and changes the switch contacts.
The coil current can be on or off so relays have two switch positions and they are
double throw (changeover) switches.
Relays allow one circuit to switch a second circuit which can be completely
separate from the first. For example a low voltage battery circuit can use a relay to switch
a 230V AC mains circuit. There is no electrical connection inside the relay between the
two circuits, the link is magnetic and mechanical.
ADVANTAGES OF RELAYS:
· Relays can switch AC and DC, transistors can only switch DC.
· Relays can switch high voltages, transistors cannot.
· Relays are a better choice for switching large currents (> 5A).
· Relays can switch many contacts at once.
DISADVANTAGES OF RELAYS:
· Relays are bulkier than transistors for switching small currents.
4.4 ULN DRIVER
ULN is mainly suited for interfacing between low-level circuits and multiple
peripheral power loads,. The series ULN20XX high voltage, high current Darlington
arrays features continuous load current ratings. The driving circuitry in- turn decodes
the coding and conveys the necessary data to the stepper motor, this module aids in the
movement of the arm.
Fig.4.8 ULN Pin Connection and Block Diagram
Relay Driver ULN 2803
The ULN2803A is a high-voltage, high-current Darlington transistor array. The
device consists of eight npn Darlington pairs that feature high-voltage outputs with
common-cathode clamp diodes for switching inductive loads. The collector-current rating
of each Darlington pair is 500 mA. The Darlington pairs may be connected in parallel for
higher current capability.
Features:
1. 500-mA Rated Collector Current (Single Output)
2. High-Voltage Outputs . . . 50 V
3. Output Clamp Diodes
4. Inputs Compatible With Various Types of Logic
5. Relay Driver Applications
6. Compatible with ULN2800A Series
CHAPTER-5
OVERVIEW
MOUNTING POSTION ON JOYSTICK