proposal : design of a 2.5 gbps radiation tolerant serdes for the cbm–daq in 180 nm cmos process

ProposalProposal:: Design of a 2.5 Design of a 2.5 Gbps Radiation Tolerant Gbps Radiation Tolerant SerDes for the CBM–DAQ in SerDes for the CBM–DAQ in 180 nm CMOS process180 nm CMOS process

Pradeep Banerjee,Pradeep Banerjee,

Dr. T. K. Bhattacharyya, E & ECE Dept.,Dr. T. K. Bhattacharyya, E & ECE Dept.,

Indian Institute of Technology, KharagpurIndian Institute of Technology, Kharagpur

CBM Collaboration Meeting, VECC, KolkataCBM Collaboration Meeting, VECC, Kolkata

3131stst July, 2010 July, 2010

3131stst July, 2010 July, 2010 CBM Collaboration Meeting, CBM Collaboration Meeting,

VECCVECC

OutlineOutline

New Proposal for a separate Data Aggregation chip

Architecture and Circuit Options for the High speed Serializer

Some aspects of Radiation Tolerant design in deep submicron CMOS

Budget Proposal Activities at the RF IC group at AVLSI Lab, IIT KGP


VECCVECC3

The CBM Generic Read-out The CBM Generic Read-out ChainChainDetectorFront-End

BoardRead-OutController

Active BufferBoard

FEB ROC ABB

Data CombinerBoard

DCB

First LevelEvent Selector

FLES

TNet

Data

Control

Data &Control

Sync

Data

DigitizationCustom ASIC

FEE DAQInterfaceLocal Pre-Processing

BufferingSystem

Synchronization

DAQFLESInterface

FPGA Coprocessor

Event SelectionCPU Farm

DAQ chainDetector Sub-System FLES

Slide Info: Slide Info: Walter F.J. Müller, GSI

DCS


VECCVECC4

STS Data Rates – Aggregation STS Data Rates – Aggregation

Hit rate [MHz]

Sta0

Sta 1

Sta 2

Sta 3

Sta 4

Sta 5

Sta 6

Sta 7

Total

32-64 21 14 9 1 0 0 0 0 45

16-32 67 72 157 116 73 60 1 1 547

8-16 208 357 477 555 325 430 157 189 2698

4-8 494 521 250 440 964 785 1048

753 5255

2-4 441 376 51 24 219 294 693 1079

3177

1-2 104 51 0 0 3 5 21 90 274

0.5-1 1 1 0 0 0 4 0 0 6

Total 1336 1392 944 1136 1584 1578

1920

2112

12002

Very few chip in inner region have hit rate > 32 MHz > 90% of chips have hit rates in 2...16 MHz range AMPLE SCOPE FOR DATA AGGREGATION AMPLE SCOPE FOR DATA AGGREGATION

Hit rate per chip StatisticsHit rate per chip StatisticsAu+Au @ 25 AGevAu+Au @ 25 AGev

101077 evt/sec evt/sec

Slide Data from: Slide Data from: Walter F.J. Müller, GSI

31.25 MHz hit rate (80 bits/hit) 31.25 MHz hit rate (80 bits/hit) 2.5 2.5 Gbps Gbps


VECCVECC

STS FEB Type and Link DistributionSTS FEB Type and Link Distribution

38 chips exceed 2.0 Gbps: 29 with 2.0 … 2.4; 9 with 2.4 … 3.2; # of FEBs and type distributions varies for stations All 8 chips combined give less than 2.5 Gbps (Aggregation Possible) --> FEBa8 A single chip gives data worth 2.5 Gbps (No Aggregation possible) --> FEBa1

Slide Data from: Slide Data from: Walter F.J. Müller, GSI

5


VECCVECC

Data Aggregation on separate chip - Data Aggregation on separate chip - Communication hubCommunication hub Motivation:

Data Aggregation: In most cases 2,4, or 8 CBM-XYTER chips (FEBa2, FEBa4, FEBa8, resp.) can be aggregated to fill a 2.5 Gbps link

Increase the bandwidth available per link Reduce the number of Optical Links

Schemes: Embedded (aggregation integrated in CBM-XYTER)

Data aggregation and Traffic Management with a separate Communication Controller Asic

Communication ‘hub’

Clock Distribution Slow control traffic Data Readout traffic

6


VECCVECC

A peep into some feasible ‘Hub’ ASIC A peep into some feasible ‘Hub’ ASIC Requirements – Requirements – Initial Proposal from Dr. MullerInitial Proposal from Dr. Muller

Capacity for data aggregation from several Readout-ASICs into a single output link 1 ‘hub’ ASIC may contain 6 high speed Serializers : 6 Tx for data 15 Gbps

serviceable data bandwidth 1 Rx – 1 Tx channel for clock, sync, control 250 MHz sys clock as Transmit clk 500 Mbps (DDR LVDS) input interface 5-8 LVDS o/p links (each 500 Mbps) per chip (8 chips per FEB)

FEBa8 case : 1 LVDS link per chip: combine data upto 6 FEBs (48 LVDS links) per Hub FEBa1 case : All 6 LVDS links (single chip) per Serializer

Cross-Connect Topology: Dynamic load balancing b/w the 6 output links desirable

Xyter #1 SerDes #1

#6

5-8 LVDS links (500 Mbps)

per chip

Xyter #2

#8

FEB HUB Asic

Detector i/f

Six 2.5 Gbps o/p links

clock, sync, control i/f

7‘‘Hub’ Idea: Hub’ Idea: Walter F.J. Müller, GSI

sys_clk

SerDes #2

LVDS I/O

PM

Hub-Core@250 MHz

Sys_clk


VECCVECC

HUB Asic

2.5 Gbps o/p links


2.5 Gbps o/p links



per chip

FEB Tx

sys_clk


per chip

sys_clk

FEB Rx

Serializer #1

Serializer #2

DeSerializer#1

DeSerializer#2

CDR + Jitter Cleaner

CMULV

DS

Rx

LVD

S T

xHUB COREP

RO

TO

CO

LE

NG

INE

PR

OT

OC

OL

EN

GIN

E

PR

OT

OC

OL

EN

GIN

E

PR

OT

OC

OL

EN

GIN

E

SE

RD

ES

SE

RD

ES

@250 MHz @2.5 GHz


VECCVECC

High Speed Serializer CoreHigh Speed Serializer Core Design of the following functional blocks:

High speed SerDes (2.5 Gbps) Clock Multiplier Unit (CMU) Clock and Data Recovery (CDR) Output Driving Logic (impedance matched)

Technology: CMOS process of interest: UMC 180 nm (Available

through Europractice) Beneficial Features for Radiation tolerant design:

Retrograde wells Shallow Trench Isolation

8


VECCVECC

Serializer “Primer”Serializer “Primer” Parallel-load Shift register:

Cascade of flip-flops and 2-to-1 multiplexers Operation speed is limited by:

Clock to Q delay Mux delay Flip-flop setup time

Maximum frequency: 1/(tcq + tmux + tsetup)

Static Flip-Flops: Operation @ 2.5 Gbps T = 400 ps Speed constraint

Can we use Dynamic Flip-Flops? No, they are sensitive to SEUs

Other high speed options: Current Mode Logic

9


VECCVECC

2.5 Gbps Serializer ASIC block 2.5 Gbps Serializer ASIC block diagram diagram

10

BIST gen

d(0:9)

D(0:9) 2.5 Gbps TXP10 bit

Serializer

50 ohmdriver

Word Mux

PLL Clock Generator

PLL Ref

Tx Clk

25

0 M

Hz

1.2

5 G

Hz

load

2.5

GH

z

2.5 GHz

Not shown: FIFOs, Arbitration logic (token ring), 8B/10B Encoders

TXN


VECCVECC

Multiple Serializer Core: Design Multiple Serializer Core: Design ChallengesChallenges Jitter-free Clock signal Minimize noise contribution of VCO (Total serial

o/p jitter < 120 ps for BER ~ 10-12)

Switching noise generated by digital logic in ASIC

Constant phase relationship b/w VCO and Sys clock (400 ps bit time)

Multiple Serializer cores per chip: Power efficiency, ASIC footprint Sharing a single frequency multiplier among several Serializer cores in the same ASIC :

Distributing multi-gigahertz clocks over an extended distance consumes lot of power Signal integrity issues percentage of area saved as a function of the number of cores for a PLL that is half the size of a Serializer core saturates beyond 4 Careful planning on circuit layout buffering high speed clock in cascade actually worsens jitter performance

De-Serializer: CDR complexity

11


VECCVECC

Serializer – Dual phase Serializer – Dual phase ArchitectureArchitecture

12


VECCVECC

Serializer – Dual phase Serializer – Dual phase Architecture …Architecture …

Word-clock = (1/10) * VCO Clock ( VCO Clock= 2.5 GHz) Bit-clock = (1/2) * VCO Clock Multiphase Clock generation for further reduction of clocking speed Issues: Duty cycle distortion jitter

13


VECCVECC

Main Contribution to Serial Data Jitter: Bandwidth limited Channel Jitter (White Noise spectrum)

Jitter Tolerance vs Jitter Transfer Trade-off The jitter tolerance of CDR has the same corner frequency as that of the jitter

transfer function, f-3dB Trade-off in Loop Bandwidth Setting b/w the i/p Jitter Filtering and Jitter Tolerance

CDR SpecificationsCDR Specifications


VECCVECC

Low Jitter CDR Architecture I


VECCVECC

Low Jitter CDR Architecture II


VECCVECC

Background – Rad-hard Background – Rad-hard designdesign Ionizing radiation effects on CMOS ICs:

Total Ionizing Dose (TIID) Effects Issues : threshold-voltage shifts, mobility degradation, and isolation related

leakage Remedy : “Radiation tolerant Layout techniques” – Systematic use of

Annular Symmetric Enclosed Layout Transistors (ELT) and p+ guard rings between the n+ diffusions

Single Event Effects (SEE) Variants:

Non-Destructive : Single Event Upset (SEU), Single Event Transient (DSET) Destructive : Single Event Latch-Up (SEL)

Issues: SEU : Depending on the LET, if parasitic charge > node critical charge, a

logical switch may occur (bit flip) DSET : Error rate depends linearly on Clock frequency (glitch) SEL : Parasitic thyristor structure leading to latch-up

Remedy: SEU/DSET: Temporal Sampling – Triple Modular Redundancy (TMR), Error

Detection and Correction (EDAC); Add Capacitance to sensitive nodes to increase ‘critical charge’

SEL : Radiation tolerant Layout techniques and usage of p+ guard rings

14


VECCVECC

Observations/Experience in CBM Radiation Environment:

TID : MUCH plane 1 (at 130 cm) : deposited energy (rad/CBM-yr) at perimeter: ~30krad/yr, in center: ~500krad/yr Not necessary to have all transistors with ELT layout

SEL : Not seen as an issue in tests so far in deep submicron CMOS

SEU/SET : MUCH plane 1 (at 130 cm) : fluence hadron E>20 MeV

(/cm2/CBM-yr) at perimeter: ~2·105 h/cm2/s, at center: ~2·106 h/cm2/s Hadrons flux VERY Significant for SEUs

Background cont ... Rad-hard Background cont ... Rad-hard designdesign

15


VECCVECC

Approach: Work Plan Freeze System level/Interface Specs

Design an appropriate architecture for the High speed Serializer core

Design and Implementation of the Peripheral cores in UMC 180μm process: CMU CDR Serializer and 50 ohm output Impedance driver

Characterization of UMC 0.18μm CMOS process concerning the vulnerability against SEU / SETs SEU cross section for different High speed Flip-Flop, Multiplexer designs and

layouts Characterization of the critical charge Qcrit /Linear Energy Transfer (LETcrit) SET sensitivity of the UMC 0.18μm process

Testing : Functionality/Performance : Design of different Testing/Digital blocks:

Pseudo Random Sequence generator (PRSG) 8B/10B encoder, FIFOs FPGA devices to program the Serializer Test Configuration generation of Test data patterns monitor PLL’s locking state, etc.

Radiation Tolerance

16


VECCVECC

Approach: Work Plan – Year 1I. Complete literature review and definition of a suitable architecture

for the SerDes for operation up to 2.5 Gbps.

II. Top level modeling of the RF Front end blocks (CMU, CDR) with System level software.

III. Set up complete process flow for UMC 180 nm CMOS.

IV. Assess the SEU sensitivity of important sub-blocks, including the VCO, PLL loop filter, etc. and identify design criteria, simulation method and means of alleviating the same.

V. Design/Tape-out (Phase I) of transistor test structures as well as primitives like high speed multiplexers, latches, flip flops with standard and enclosed layouts for technology evaluation and for precise modeling of radiation hard devices.

VI. Complete design, layout and simulation of the CDR and CMU


VECCVECC

Approach: Work Plan – Year 2I. Complete design, layout and simulation of the Serializer core with the 50 ohm

output Impedance driver.

II. Testing for functionality/radiation tolerance for test structures taped out(Phase I).

III. Tape-out (Phase II) of different CDR/CMU test structures.

IV. Design of appropriate Bias generation schemes and incorporating this in full system simulation.

V. System integration with proper digital control unit for process compensation and other corrections.

VI. Testing for functionality/radiation tolerance for test structures taped out in Phase II.

VII. Tape-outs (Phase III) for the complete SerDes.

VIII. Post Layout simulation and PCB Design of the full system.

IX. Testing for functionality and radiation tolerance for previously taped out system (Phase III).


VECCVECC

Resources Available at AVLSI Lab, IIT KGPName of Equipment Status

Cadence Spectre Simulation software Functional

Cadence Virtuoso Layout Editor Functional

Agilent Advanced Design System Functional

Agilent Golden Gate, Momentum, EMDS Functional

Full Synopsys software suite for Digital design Functional

Agilent Network Analyzer Functional

Rhode and Schwartz Signal generator (up to 3 GHz) Functional

Agilent Spectrum Analyzer (up to 26.5 GHz) Functional

Agilent 3 GHz oscilloscope Functional

Agilent Logic Analyzer Functional

Agilent Semiconductor parameter Analyzer Functional

Agilent Noise Figure Meter (up to 11 GHz) Functional

Agilent 1 GHz continuous RF source Functional

Agilent Precise Voltage source Functional

Functional generator (15 MHz and 75 MHz) Functional

Four port Vector Network Analyzer (up to 26.5 GHz) Functional

Probe Station (Cascade Microtech) Procured

21


VECCVECC

Budget Details for Different Overhead - I

21

Budget Head First Year

Second Year

HIRING PROJECT STAFF AT IIT KHARAGPUR = Rs 16,80,000

1 PhD scholar + 2 Project Staff Rs 8,40,000 Rs 8,40,000

CONTINGENCY & OVERHEAD FOR IIT KHARAGPUR = Rs 6,00,000

Contingent items including Software license fees for CAD tools for VLSI design, publications, report writing, etc.

Rs 3,00,000 Rs 3,00,000

MOBILITY COST OF RESEARCHERS (Travel Cost only) = Rs 12,00,000

From India to GSI: Short Term Visit: 2 visits of Project Coordinator/year + 3 visits of Project based staff: 1 PhD scholar, 2 Project Staff/yearFrom GSI to India: Short Term Visits: 6 visits for 18 man months over three years (Short term visits: either of 10 days or up to 3 months duration/year) + Local Hospitality

Rs 3,50,000Rs 2,50,000

Rs 3,50,000Rs 2,50,000

CONSUMABLES = Rs 5,00,000

Passive components, Test Boards (Multilayer), Silicon wafers Rs 2,50,000 Rs 2,50,000

FABRICATION & PACKAGING RELATED COSTS = Rs 22,00,000

TOTAL Rs 61,80,000


VECCVECC

Budget Details for Equipments Required-IIName of Equipment Approximate

Valuation (INR)

Probe cards Rs 21,00,000

RF GSG Standard Probe Rs 70,000

RF LCR Meter (1 MHz to 3 GHz) Rs 15,00,000

Serial BER Tester (150 Mbps - 3.60 Gbps) Rs 55,00,000

TOTAL Rs 91,70,000

TOTAL BUDGET (I+II) (Including Institute Overhead Charges of 20%)

Rs 1,91,87,500


VECCVECC 17


VECCVECC 18


VECCVECC 19


VECCVECC 20


VECCVECC

THANK YOUTHANK YOU

FOR YOUR ATTENTIONFOR YOUR ATTENTION

22

proposal : design of a 2.5 gbps radiation tolerant serdes for the cbm–daq in 180 nm cmos process

Documents