Akira Matsuzawa

Tokyo Institute of Technology, Japan

Proposing

An Interpolated Pipeline ADC

Matsuzawa& Okada Lab.

38GHz long range mm-wave system

Background

Role of long range mm-wave

Optical fiber

Optical fiber

Connect with mm-wave

Current

Future

Base stationsfor WiFi and WiMAX

Not flexible

Very flexible

38GHz long range mm-wave system

realized 1Gbps long range mm-wave systems

Current system: 80Mbps!!

System configuration

RJ-

45

Gig

abit

Eth

erne

tTr

ansc

eive

r

Bas

eban

d S

oC LPF

LPF

PA

LNA

BPF

TX A

NT

Eth

erne

t Cab

le

Sur

ge P

rote

ctor

RJ-

45

LPF

BPF

BPF

RX

ANT

PoE

Inte

rface

RJ-

45

Sur

ge P

rote

ctor

PoE

Inte

rface

Compatible with Gbit EthernetHole system is integrated with planar antenna

Mixed signal BB SoC

Base band SoC

ADC & DAC 90nm CMOS40M Transistors

A mixed signal SoC has been developed to realize64QAM (1Gbps) with BW of 260MHz.

Co-developed with JRC

Developed ADC

10b, 320 MSps, 40mW ADC

Developed new 10b ADC to address 64 QAM.

M. Miyahara, A. Matsuzawa, VLSI-CS, 2011.

Interpolated pipeline schemeNo need of high gain OP amps

Suitable for low gain and low VDD scaled CMOS

BER vs. SNR

C/N vs 64QAM_BER on B-B pair

1.E-14

1.E-13

1.E-121.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-061.E-05

1.E-04

1.E-03

1.E-02

20 25 30 35 40 45C/N [dB]

BER

Measurement

ENOB=6.0 (600Mbps version)

ENOB=6.25

ENOB=6.5 (1Gbps version 2009)

ENOB=6.75

ENOB=7.0

ENOB=7.4

ENOB=8.5 (ADC design target)

ENOB=7.15 (1Gbps version 2010)

2008

2009

2010

C/N vs 64QAM_BER on B-B pair

1.E-14

1.E-13

1.E-121.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-061.E-05

1.E-04

1.E-03

1.E-02

20 25 30 35 40 45C/N [dB]

BER

Measurement

ENOB=6.0 (600Mbps version)

ENOB=6.25

ENOB=6.5 (1Gbps version 2009)

ENOB=6.75

ENOB=7.0

ENOB=7.4

ENOB=8.5 (ADC design target)

ENOB=7.15 (1Gbps version 2010)

2008

2009

2010

BER for 64QAM has been reduced to the idealENOB of ADC is increased

9

Tokyo Tech. Model Network

W8

I6

I1

S3 H100

M1

#2

#1

#3

#4

#5

#6#7

#8

#9

#10

Tokyo Tech. O-Okayama Campus

Ten mm-wave base stations in our campus

Expand the area to NEC (4km)

4km1km

NEC

Tokyo Tech

Challenge for 4km mm-wave communication

11

Outline

• Introduction• Interpolation Techniques• Circuit Implementation• Measurement Results• Conclusions

Conventional Pipelined ADC

12

Conventional pipelined ADC requires accurate MDAC

Pipelined ADC Conversion

13

FSino1 2

12 VVVinVResidue

Output CODE 1

FS2o3o 2

12 VVV

1

000001010011100101110111

2oV 3oV

FSV

0

FS21V

FS41V

FS43V MDAC1

MDAC2

MDAC3

Input

x2 x2

o1o2 2VV

0

1oV

Threshold

1 0

x2.1

Conventional MDAC• High DC gain OpAmp

– Difficult to realize in scaled technology• Closed-loop MDAC leads to lower speed

14

106)dB(0 NG

SNFGBW

N: Number of bitsFs: Sampling freq.

Vin

Vout

Dout

C

mC

G0

MDAC Implementationm bit

U1-

VO

UT

/ mV

-800

-600

-400

-200

0

200

400

600

800

Time/mSecs 200uSecs/div

0 0.2 0.4 0.6 0.8 1

VO

UT

/ mV

-800

-600

-400

-200

0

200

400

600

800

OpAmp gain and conversion error

)(106 dBNG

370 372 374 376 378 380

VO

UT

/ mV

-280

-270

-260

-250

-240

-230

)(

23

LSB

N

G

G

N

LSB23

)(

10bit ADC

Gain>70dB

Large error occurs

40dB gain

Recent Works• Digital compensation technique [1, 2]

– Capacitor mismatch, gain error and opamp nonlinearity can be corrected

• Simple analog circuit design– Foreground compensation

• PVT variation degrade the performance– Long compensation time

• Increase of test cost

16

[1] B. Murmann and B. E. Boser, Dec., 2003.[2] A. Verma and B. Razavi, Nov., 2009.

Proposed ADC

17

• Target : 10bit, Fs> 300 MS/s• Interpolation and pipelined operation

– Moderate relative gain • G/G < 5% for 10bit• Open-loop amplifiers can be used• No need of linearity compensation

– Insensitive to settling time• High speed• Low power

Interpolation Architecture

Vin

Vout

CMP

Voa

Vob

1a

1b

Inter-polator CMP

Voa

Vob

18

Interpolation Architecture

Vin

Vout

CMP

Vob

Voa : Vob = 1 : 1Voa

1a

1b

Inter-polator CMP

Voa

Vob

1a

1b

CMP

19Interpolator example [3,4]

R

R

[3]A. Matsuzawa, et al. Feb. 1990.[4]C. Mangelthdolf, et al. , Feb. 1993.

Interpolation Architecture

Vin

Vout

CMP

Vob

Voa : Vob = 2 : 2Voa : Vob = 3 : 1

Voa : Vob = 1 : 3

Conversion error is not occurred by changing gain

Voa

1a

1b

Inter-polator CMP

Voa

Vob

20

1a

1b

CMP

Interpolator example

3R

1R

Interpolated Pipeline ADC Structure

21Pi

pelin

e St

age

Pipe

line

Stag

e

Interpolation technique is used for 2-4th stage.Each stage has an 1-bit redundancy.

1st stage 2nd stage 3rd stage 4th stage

Interpolation methods

22Resistive

(Series) [3,4]Capacitive

(Series)Capacitive(Weighted)

• Static current• Good linearity• Imbalance settling

• No static current• Cp causes

nonlinearity

• No static current• Good linearity• Heavy load

Vin

Cp

Cp

1a

1b

Cp

Cu

Cu

Cua1 Cub1

CuaN CubN

2a

2b

2a

2b

2a

2b

1a

1b

1a 1b

Ex. 3bit1:8

2:6

3:5

8:1

Total:36Cu

Proposed Weight Controlled Capacitor Array

23

1a

1b

1a

1b

2a

2b

2a

2b

Voa

Vob

Vxa

Vxb

Sub-ADC controls the capacitor weight.Load capacitance is reduced from 36Cu to 16Cu (3bit).

Total:16Cu

16Cu

16Cu

Weight Controlled Capacitor Array

24

rbinbrainax VVG

nmnVVG

nmmV

off_bbob

off_aaoa

off_brbinbob

off_arainaoa

''

VGVVGV

VVVGVVVVGV

Ga, Gb: Gain of A1a and A1bVoa, Vob : Output voltage Voff_a, Voff_b: Offset voltageVra, Vrb: Reference voltagem, n : Capacitor weight

Offset voltage can be cancelled in interpolation phase

Interpolated Output

Vin

Vx

Vob

Voa

Vxa

Vxb

Voa

Vob CMP2

VxaVxb

1bit redundancy

mC nC mC nC

Vxa

Vob Voa

31 71

25

Sub-ADC StructureGate-width-weighted interpolation comparators with capacitive offset calibration is used.

– Offset voltage < 2 mV ()

26

1a

1b2nd

1st stageSense

2nd stageLatch

Wa

VINNbVINNaVINPbVINPa

Wb Wa Wb

CLKDD

OUTP

OUTN

[1] V. Giannini, ISSCC 2008[5] Y. Asada, A-SSCC 2009

Requirements for An Amplifier

• Absolute Gain error ⇒ No error• Offset voltage ⇒ DNL error

– Offset voltage < 1LSB• Offset voltage can be negrected by

output offset cancel technique.

• Gain mismatch ⇒ DNL error• Linearity ⇒ DNL and INL error

27

Amplifier : Schematic

28

1st stage amplifier require good linearity=>CMOS input with source degenerations

Gain mismatch < 2.1%(3)

Amplifiers : Simulation results

29

1st stage a3/a1 < 1.3 2nd stage a3/a1 < 6.2

3in3in1out aa VVV

Gain matching requirement

30

8.8

9.0

9.2

9.4

9.6

9.8

10.0

0 2 4 6 8 10

ENO

B [b

it]

∆G/G (%)

G-G

G+G

Gain mismatch of 1st stage amplifiers < 2.1%(3s)

Linearity Requirement

31

8.68.89.09.29.49.69.8

10.0

0 2 4 6 8 10 12 14 16 18

ENO

B [b

it]

a3/a1

3in3in1out aa VVV

1st stage a3/a1 < 1.3, 2nd stage a3/a1 < 6.2

Chip photo

32

• 90 nm 10M1P CMOS technology • Chip area of 0.46mm2

Timing generator & Clock lines

4thstage

5th

Logic

3rdstage

2ndstage

1ststage

1120 m

415 m

DNL, INL

33

-2.0-1.5-1.0-0.50.00.51.01.52.0

0 256 512 768 1024

DN

L [L

SB]

OUTPUT CODE

-4.0-3.0-2.0-1.00.01.02.03.04.0

0 256 512 768 1024

INL

[LSB

]

OUTPUT CODE

DNL +0.9/-0.6

INL +1 .4 / -1 .8

This periodical error is due to bad layout, not essential issue.

Sampling Frequency vs. SNDR

34

Input Frequency = 1 MHz

Input Frequency vs. SNDR

35

Sampling Frequency = 320 MS/s

Performance summary

36

This Work [2] [6] [7]Resolution (bit) 10 10 10 10Fsample (MS/s) 320 500 205 320VDD (V) 1.2 1.2 1.0 -Power (mW) 40 55 61 42ENOBpeak (bit) 8.5 8.5 8.7 8.7FoMFs/ FoMERBW (pJ/c.-s) 0.35 / 0.77 0.31 0.65 0.36/0.44Technology (nm) 90 90 90 90Active Area (mm2) 0.46 0.5 1 0.21Amplifier type Open Closed Closed ClosedLinearity Compensation No Yes No Yes

[2] A. Verma and B. Razavi, IEEE J. Solid-State Circuits, vol. 44, Nov., 2009.[6] S. Lee, Y. Jeon, K. Kim, J. Kwon, J. Kim, J. Moon, and W. Lee,” ISSCC, 2007.[7] H. Chen, W. Shen, W. Cheng, and H. Chen, A-SSCC, 2010.

Conclusions

37

• An interpolated pipelined ADC using open-loop amplifier has been proposed.– Interpolation architecture

• G/G < 5% for 10bit• Using simple open-loop amplifiers enables high

speed operation• No need of a linearity compensation

– Weight Controlled Capacitor Array• Load capacitance is reduced from 36Cu to 16Cu

• Offset voltage of the amplifier can be cancelled– 10bit, 320MS/s, 40 mW ADC has been realized

Future Prospect

• Issue: Need twice larger circuits– Same capacitance as for the conventional pipeline

ADC can be used by modifying circuits.– Area and power can be reduced, since lower

bandwidth is acceptable.

• Still need the pipelined ADC?– SAR ADC: lowest FoM, but low fs and low resolution.– SAR-Pipeline: higher resolution, but lower fs due to

multi step conversions. – Interleaving: effective for low resolution ADC, but need

totally large capacitance.