PSPICE 计算机仿真

Simulation Program with Integrated Circuit Emphasis

CH7

THE STEP RESPONSE AND SWITCHES

阶跃响应

7.1 Simple step response

Fig. 69

Example 11 a) The switch in the circuit shown

in Fig. 69 is closed at t=0. At the instant the switch is closed, the initial current in the 10 mH inductor is 90 mA, and the voltage across the capacitor is 10 V.

Fig. 69 also shows the references for these initial conditions. Make a preliminary analysis of the step response, and calculate the maximum value of Vc and the time at which it occurs.

b) Create a PSpice schematic, perform transient analysis, and plot Vc versus t from 0 to 3000 µs.

c) Compare the PSpice solution with the preliminary analysis.

Solution a) From the solution of Example 10, we

already know that the response is underdamped.

Furthermore, we know that the damped period is 897.60 µs, and that

70001000

70001000

2

1

js

js

The step-response solution for Vc takes the form

tfc etBtBvv 1000'

2'1 7000sin7000cos

The initial values of Vc and dVc/dt are the same as in Example 10, and the final value is 21 V. Hence B’1=-31 V and B’2=2 V, so

0,7000sin27000cos3121 1000 tettv tc

The maximum value of Vc is 41.22 V at 419.32 µs.

Solution b) In Fig. 71, we used two cursors this

time, and moved the second cursor by holding down the Shift key while using the left and right arrow keys. The cursors allow you to read the values of Vc (max) and Td directly from the Probe plot.

Fig. 70 schematics

Fig. 71 probe

Solution c) The output of the PSpice analysis yields

Vv

sT

Vv

f

d

c

21

503.899

361.41max

7.2 Piecewise Linear Sources( 分段线性电源 )

Example 12 illustrates the use of the piecewise linear source for modeling the switching that takes place in a transient analysis problem.

Example 12 The circuit shown in Fig. 72 has

been in operation for a long time. At t=0, the 80 V source drops instantaneously to 20 V. Construct a PSpice schematic, using a PWL source, to model this circuit. The results of the analysis should be a plot of Vo (t) versus t.

Solution

Fig. 73 Ex12_ddb

Fig. 74 Schematic

注意 V2 正负极 V2 属性 (Fig. 75)

Fig. 75 PWL Property Editor

Fig. 75a Simulation Profile

Fig. 76 Probe

Results The Probe plot in Fig. 76, which uses

the cursors to determine the output voltage at t=40 ms and t=80 ms, yields the following results:

t Vo(t)0 6440 33.698 ( 书上 :33.654)80 22.489 ( 书上 :22.498)

Furthermore, you can see from the Probe plot that Vo(t) approaches 16 V as t approaches ∞.

7.3 Realistic Switches( 实际开关 )

We illustrate the use of the normally-opened switch in Example 13 to examine the effect of nonzero switch resistance on the step response of the RLC circuit.

Fig. 69

Example 13 Use PSpice to model the circuit

shown in Fig. 69, with some modifications. Assume that the voltage source is the

same as that used in Example 10, and use the same values in specifying transients analysis.

But assume that the resistance of the switch in the ON position is 10 Ω.

Then generate a plot of Vc versus t. Compare the results here with those in Example 10.

Fig. 77 Schematic

Components EVAL/Sw_tClose

Fig. 78 Property

Fig. 79 Probe