IEER TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-21, NO. 2, MAY 1972

ter performance can be obtained with faster IC com-ponents (say 50 MHz).

2) A precision always less than 0.2 percent in a widerange from 0-7800 r/min is available.

3) A high rate of information from 1600 samples/s atzero speed up to 16 700 samples/s meet most require-ments. The sampling rate increases with speed.

4) Zero speed is detectable without quantization noisewith a fairly high rate of information (1600 samples/s)and a maximum accuracy (0.02 percent).

5) Results are available in digital form almost in-stantaneously (16 Its after sampling is completed).

6) The sampling time being very short (ranging from

0.61 to 0.068 ms), the average speed reading obtained canbe considered as instantaneous in all physical systems.The simple implementation of the design allows a low-

cost instrument presenting a much wider range of per-formance than any other means known to the authors.Moreover, some simple modifications can transform

this instrument into an accelerometer presenting thesame advantages.

[1]

[2]

REFERENCESG. Hoffman de Visme, "Digital processing unit for evaluatingangular acceleration," Electron. Eng., pp. 183-188, Apr. 1968.A. Dunworth, "Digital instrumentation for angular velocityand acceleration," IEEE Trans. Instrum. Meas., vol. IM-18,pp. 132-138, June 1969.

Pulse Generator and Flip-Flops

IAN P. MACFARLANE

Abstract-A simple pulse generator can be constructed usingIC gates. Such a pulse generator is described and its use to constructedge-triggered ffip-flops is demonstrated. A ffip-flop for use in a

phase comparator is described. Desirable and undesirable charac-teristics for this application are discussed and examples of R-Sand J-K flip-flops given.

I. INTRODUCTION

LIP-FLOPS can be used to perform many func-

tions. To perform a desired function the inputs tothe flip-flop, in general, must be activated in a

specific way. They are either static or dynamic inputs.The pulse generator described is suitable for creating

a dynamic (or edge-triggered) input to a flip-flop. It can

be used in a variety of ways to create different types offlip-flop.' By describing the design of a flip-flop particu-larly suitable for phase comparison applications, theadvantages and disadvantages of different modes of flip-flop operation are indicated for other applications.

It is well known that a flip-flop can be used to measure

the phase difference between the pulses constituting twoseparate pulse trains having nominally equal frequency.The pulses of one pulse train are used to SET the flip-flopand the pulses of the other pulse train are, used to RESET

the flip-flop.The phase difference information obtained from a flip-

Manuscript received August 2, 1970; revised November 4, 1971.The author is with the Research Laboratories, Australian Post

Office, Melbourne, Victoria, Australia.1 Commonwealth of Australia Patent 32 612/71.

flop is provided by the duty cycle of the flip-flop output.The average value or dc content of the rectangular out-put waveform is proportional to the duty cycle and thusto the phase difference to be measured. It can be seen thenthat if the relative phase of the two trains of pulses is O0(or 360°) the flip-flop output waveform should haveclose to zero (or maximum) duty cycle. Between theselimits the duty cycle should change linearly with changeof relative phase-hence the description linear phasecomparison.An undesirable characteristic for a flip-flop to possess

in a linear phase comparator is an ability to toggle. Ifthe flip-flop can or will toggle-producing an even duty-cycle output-when the input pulse trains are coincidentor nearly so, a phase indicator driven by the flip-flopwill erroneously indicate 180' phase difference insteadof the required 0° or 360° [1]. A flip-flop having a J-Kcharacteristic is therefore unsuitable for such applica-tions.

It is also undesirable for the flip-flop to have unequalSET and RESE;T propagation delays. Such unequal delays,particularly at high pulse-repetition rates, cause theduty cycle of the flip-flop output to be an unfaithfulreplica of the phase difference between pulses.A flip-flop to be described below is an R-S flip-flop

with no inherent toggling mechanism. The logic formused to construct the flip-flop and its inherent propaga-tion delays will determine the maximum operating fre-quency for a given accuracy in a phase comparator ap-plication.

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MA\CF\RLA\NE: IPULSEI GENEFRATOI ANI) FLIP-FLOPS

II. DEI(N- STEPS

TTL logic has been used in the flip-flops described.Howev-er, other logic forms are equally applicable if theysuit particular applications.

A. Basic Latch

The latch circuit shown in Fig. 1 is the basis of theflip-flops. The state of the latch can be changed onlyby applying a LOW signal to the appropriate input. Ifboth inputs are driven LOW together and then releasedHIGH, the REST state of the latch will be unpredictable.The REST state will be decided by the input that islast to be effectively released. If both inputs are releasedtogether, the dither effect may be observed on the latchoutput as it oscillates several times before settling to onestate or the other. The dither effect should not be allowedin a phase comparator flip-flop for obvious reasons.To make the basic latch useful in a phase comparison

application some additional circuitry is required. Themost important requirement is for pulse generators tosupply short LOW signals to the latch inputs. The timefor which each latch input is LOW must be independentof the duty cycle of the pulses in the pulse trains beingcompared. In other words, the eventual flip-flop de-veloped must be edge-triggered [2].An important parameter of the latch is the latch-up

time. This is the time, after activation, for the latch tosettle to its final state. It is equal to the sum of thepropagation delay of a gate going HIGH and a gate goingLOW.

tL tPDH + tPDL* (1)

B. Pulse Generator

A pulse generator is shown in Fig. 2. It produces oneshort LOW-going output pulse every time the input linecarries a LOW to HIGH logic-level transition. The use ofa latch, gates A and B, in the pulse generator ensuresthat only one output pulse is produced for each HIGH-going input transition. Pulse generation is a compelledsequence and the pulse length is solely a function ofpropagation delay through the gates. This has certainadvantages compared with the diode, R and C methodof pulse generation used in discrete component circuitswhere the pulse time constant chosen must be necessarilybased on worst case considerations.The pulse generator shown has the additional advan-

tage that there is only one gate delay between the ini-tiating input transition and the output leading edge fol-lowed by three gate delays to the output trailing edge.When the input signal is LOW, the outputs of gates

B and C are HIGH and thus the output of gate A is LOW.When the input signal goes HIGH the output of gate Cgoes LOW until the latch A--B changes state (activatedby the LOW from gate C). Then gate B applies a LOW togate C, returning the output of gate C to the HIGH state.The latch A-B now rests in the state A output HIGH, B

14ft

s

R

Fig. 1. Basic latch.

I/P >-

tPL(2)

o/P

Fig. 2. Pulse generator.

output LOW until the input signal goes I.ow. Then thelatch is reset to A output LOW, B output HIGH. The pulsegenerator is now ready to operate from the next LOW toHIGH input signal transition.The output pulse length tpL is equal to the sum of the

propagation delay time of A going HIGH tPDAH, the delaytime of B going LOW tPDBL and the delay time of C goingHIGH tPDCI.

tpjL = tPDAH + tPDBL + tPDCll- (2)

C. Simple Flip-Flop

Using the pulse generator and basic latch just describedthe simple R-S flip-flop shown in Fig. 3 can be con-structed. The requirement that the flip-flop be edgetriggered has been satisfied. The flip-flop possesses noinherent toggle mechanism.The flip-flop can be constructed using two packages

A and B of four gates each. However, the circuit showncan still suffer from the dither effect and therefore hasonly limited usefulness.A simple modification to the circuit is shown in Fig. 4.

It results in the flip-flop becoming an edge-triggered un-clocked J-K flip-flop. The J-K flip-flop will alwaystoggle when the input pulses are coincident. Toggling isensured in this case by taking the pulse-generator feed-back lines from the cross-coupled outputs of the outputlatch. Triggering of the J-K flip-flop is a compelledsequence and no problems will be met with incompatiblepulse-generator pulse lengths and output latch latch-uptimes.The simple edge-triggered J-K flip-flop, is very useful

in situations where unclocked J-K operation is desired.Since the flip-flop toggles for coincident input pulses, nodither effect will be observed, but it cannot be used forphase comparison.

D. Modified R-S Flip-FlopIt will now be apparent that to overcome the dither

effect but still preserve immunity to toggling, one coin-

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, MAY 1972

:S

,R

Q Si

Fig. 3. Simple edge-triggered R-S flip-flop.

J

K

Q

Fig. 4. Simple edge-triggered J-K flip-flop.

cident input signal must be allowed to override the other.It is also apparent that triggering of the output latchcannot be made a compelled sequence, as such will in-evitably lead to the J-K toggling action described above.'Therefore, disposition of the gates from various packageswill have to be done with care to ensure that the pulsesgenerated by the input pulse generators will be longenough to ensure latch-up of the output latch.Regard must be had for the spread in propagation

delays encountered with gates from different packages.A suitable modified R-S flip-flop is shown in Fig. 5.

When input signals are coincident, the RESET pulse gen-

erator overrides the SET pulse generator. T'hus the SET

and RESET pulses cannot release the output latch togetherand no dither effect can occur. Immunity to toggling isstill obtained.

Inputs S, and R1 are edge triggered. Inputs 82 and R2are direct and will override S, and R1. S2 and R2 can beprovided because of the use of three-input gates and may

Fig. 5. Modified edge-triggered R-S flip-flop.

be used as zero and full-scale forcing inputs when settingup a phase comparator.

Note, however, that although a LOW signal on eitherthe S2 or R, input will force the output latch to stay ineither the SET or RESET state, respectively, the SET andRESET pulse generator will still be operated if signals areapplied to inputs Si and RI. This means, for example,that if the forcing input R2 is held LOW while input signalscontinue to be applied to SI and R1, output Q will remainHIGH steadily but output Q will remain LOW with veryshort HIGH spikes caused by the LOW spikes from the SETpulse generator. This effect is not generally important in aphase-comparator application. If the effect is undesirableit can be eliminated either by preventing the applicationof input signals to S, and R, while forcing the state of theoutput latch or by using four-input gates in the pulsegenerators in the manner shown in Section IV-A.

Gates labeled A are in package A, those labeled Band C are in packages B and C, respectively. T'he dis-position of gates shown ensures that the pulse generatorswill provide pulses longer than the latch-up time of theoutput latch for the full range of propagation delaysquoted in the manufacturers data for 74N and 9000series TTL. An example of pulse-length calculations isgiven in the Appendix.

III. ACCURACY

The flip-flop of Fig. 5 does not suffer from toggle ordither effect. When used in a phase-comparison applica-tion, limitations on accuracy are created by two effects.These are unequal SET and RESET delays to the Q (or Q)output and the flip-flop "dead" time created by the over-riding RESET characteristic that was introduced to re-move the dither effect.The two, effects affect phase comparison accuracy in

totally different ways.The unequal SET and RESET delays introduce a constant

"offset" in the flip-flop duty cycle. The effect of the

150

MACFARLXNE: PULSE GENERATOR AND FLIP-FLOPS

flip-flop dead time is harder to characterize apart fromthe fact that it is only important at the phase comparisonlimits of O0 and 3600.

A. OffsetCalculation of the difference between SET and RESET

delays to the Q output for the combinations of packagespeeds considered in the Appendix provides a worst casedifferential delay of 16.6 ns for 9000-series TTL gates.This figure is obtained for package speed combinationc) (see the Appendix, Table II) and makes use of thetoleranced propagation delays shown in Table I.The offset in a phase comparator resulting from such

a differential delay leads to the choice of an upper fre-quency limit for a given percentage error of reading re-ferred to full scale

differential delayfractional offset error = (3)

input period

In the present case, if the limit for percentage offseterror is placed at 1 percent, the maximum input fre-quency is limited to 603 kHz for a worst case differentialdelay of 16.6 ns. If some attempt were to be made toselect packages matched in delay characteristics, sucha frequency limit could be raised accordingly.

Similar calculations carried out for 74N-series gatesindicate a worst case differential delay of 19.8 ns, which,for a maximum 1 percent offset error, sets an upper fre-quency limit of 505 kHz. The reliability of this calcula-tion is not high because of the difficulty of estimatingminimum gate delays for 74N-series logic.

B. Dead Time

Dead time of the flip-flop occurs when the input pulsesare coincident or nearly so. It is caused by the RESETinput overriding the SET input. Over a range near zerorelative phase of the two pulse inputs, the Q and Q out-puts of the flip-flop remain constant.A worst case estimate of the magnitude of this effect

can be made using the package speeds given in the Ap-pendix, with the additional assumption that package Bis always slow. The result is as follows.The worst case occurs when all three packages are

slow. The calculated dead time for 9000-series logic isthen 55.5 ns. If this effect is to represent only a 1 percentdeparture from ideal operation in a phase comparatorthe maximum frequency must then be limited to 180kHz.A similar calculation for 74N series logic can be made.

The worst case dead time is 77 ns. For a 1 percent de-parture from ideal operation near 0- or 3600 in a phasecomparator, the maximum frequency should thereforebe limited to 130 kHz.

PackageSpeed

Fast

Slow

TABLE I(CtATE PROPAG.TICON I)DEIAYS

HIGH-GoingPropagation Delay

tPDH(ns)

+10 percent3 3.3

-10 percent15 13.5

LOW-GoingPropagation Delay

tPDL(ns)

3

13

+10 percent3.3-10 percent11.7

It can be seen from the previous results that the deadtime effect is in general the most important limitationon the use of the flip-flop as a phase comparator.

IV. GENERAL PURPOSE CIRCUITS

Integrated circuits made according to the principlesdescribed previously are expected to have some generalusefulness.

A. Flip-Flops

A general-purpose means of implementing, in inte-grated-circuit form, the flip-flops described previouslyis shown in Fig. 6. By allowing access to the labeledpoints of the integrated circuit the user can implementany of the flip-flops at will.For example, the R-S flip-flop of Fig. 5 can be created

by connecting L1 to F1, L2 to F2 and H1, and returningH2 to a HIGH logic level.The J-K flip-flop of Fig. 4 can be implemented by con-

necting L1 to Q, L2 to Q, H1 and H2 to a HIGH logic level,and leaving F1 and F2 unconnected. S2 and R2 may thenserve as forcing inputs that were not available in the-original flip-flop of Fig. 4.

In all cases, using the flip-flop of Fig. 6, when forcingthe state of the flip-flop using either input S2 or input R2there will be, no spikes on the flip-flop outputs if signalsat S, and R1 continue to be applied as was mentioned inSection II-D. The effect has been prevented by thecouplings, X and Y, shown from the S2 and R2 forcinginputs to the RESET and SET pulse generators, respectively.Note that four-input gates are required in the pulsegenerators, to preserve flexibility of use of the flip-flopif inputs H1 and H2 are to remain free for coupling toF2 or F1, respectively.

B. Pulse Generators

The pulse generator can be made in integrated-circuitform as indicated in Fig. 7.By means of connecting appropriate time-delay ele-

ments D between the output and L1, the output pulsescan be "stretched" to a required length. Four such pulsegenerators may be mounted in a single 14-lead package.The output pulse length so generated is equal to the-

length produced by the pulse generator alone [see (2)]

151

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, MAY 1972

APPENDIX

Fig. 6. General purpose flip-flop showingbrought out in IC version.

connections to be

I/P >-

Fig. 7. General purpose pulse generator and delay element usedto "stretch" output pulse.

plus the time delay of the delay element to a LOW-goinglogic signal tDL

tPLD = tPDAH + tPDBL + tPDCH + tDlL. (4)

V. CONCLUSIONS

Some fundamental considerations in the design of anedge-triggered flip-flop, have been described. In particularthose factors affecting the use of a flip-flop a,s a phase-comparator have been indicated and their interrelation-ships demonstrated. The prevention of the toggle effect,the removal of dither, and the operating limits definedby the resulting dead time have been explained. The in-evitable offset error has been shown to be of less concern,in the general case, than dead time, which is of greatermagnitude.The necessity for careful consideration of the disposi-

tion of gates among the packages used to con,struct theflip-flops, to ensure that pulse generator pulse lengthsare long enough to achieve latch-up of the output latch,has been emphasized. The fact that use of a compelledsequence to achieve latch-up also leads to toggling hasbeen demonstrated, by showing the construction of aJ-K flip-flop as a simple variation of the other flip-flopsdescribed.

It can also be pointed out here that many of the abovefactors would be simplified or eliminated if the flip-flopwere to be constructed as a single monolithic circuit.

To determine that the latch-up time of the outputlatch will always be shorter than the activating pulsesgenerated by the SET and RESET pulse generators, caremust be taken in the disposition of gates from the threepackages used to construct the flip-flop of Fig. 5.The output latch contains gates from package A and

package C only. To ensure a worst case calculation, itwill be assumed that package, B is always a "fast"package.An assumption must also be made concerning the

spread in speed of gates within a given package. Theassumption made is that 1) in the case of a "fast" packagethe slowest gate in the package will have a propagationdelay no more than 10 percent longer than the fastestgate in the package and 2) in the case of a "slow" pack-age the fastest gate in the package will have a propaga-tion delay no more than 10 percent shorter than theslowest gate in the package. The assumption for a typicalpackage is that the spread in propagation delays amongthe gates in the package is no greater than + 5 percent.Only fast packages and slow packages will be furtherconsidered in worst case calculations. Gate propagationdelays, with the above tolerances, are shown in Table Ifor 9000-series TTL, gates (0-75°C range).Four speed combinations of the two packages A and C

must be checked: a) both packages fast, b) both pack-ages slow, c) package A fast, package C slow, and d)package A slow, package C fast.For the pulse-generator pulse length we use (2). For

the output latch latch-up time we use (1).Case a), both packages fast:

SET and RESET pulse length (minimum)

= 3+3+3= 9 ns.

output latch-up time, SET and RESET, (maximum)

- 3.3 + 3.3

= 6.6 ns.

(2a)

(la)

It can be seen that for the speed combination con-sidered the pulse generated is longer than the latchingoperation it initiate,s and latch-up will always take place.Now consider speed combination case c), package A

fast, package C slow:

SET and RESET pulse length (minimum)

= 3 + 3 + 13.5

= 19.5 ns. (2c)

output latch-up time (SET) (maximum)= 3.3 + 13

= 16.3 ns. (lC)'

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-21, NO. 2, MAY 1972

TABLE IICORRESPONDING MINIMUM PULSE LENGTHS AND MAXIMUM REQUIRED LATCH-UP TIMES (9000-SERIES TTL GATES, 0-750C RANGE):

PACKAGE B IS ASSUMED FAST IN ALL CALCULATIONS

Set Pulse Latch-Up Time RESET Pulse Latch-Up TimeLength (minimum) (SET) (maximum) Length (minimum) (RESET) (maximum)

Package Speed Combination (ns) (ns) (ns) (ns)

a) Both packages fast 9 6.6 9 6.6b) Both packages slow 30 28 30 28c) Package A fast, package C slow 19.5 16.3 19.5 18.3d) Package A slow, package C fast 19.5 18.3 19.5 16.3

The puilse generated is always longer than the latching operation it initiates and latch-up will always take place.

output latch-up time (RESET) (maximum)

= 15 + 3.3

= 18.3 ns. (1c)"

After carrying out similar calculations for speed com-binations b) and d), Table II can be constructed. Itshows the relative values for worst case conditions of

minimum available pulse lengths from the SET and RESETpulse generators and corresponding maximum latch-uptimes required by the output latch.

REFERENCES[11 K. A. Steele, "Application of digital integrated circuits to

linear phase detection," Electron. Eng., pp. 240-241, May1968.

[2] H. Ebenhoech, "Make IC digital frequency comparators,'YElectron. Des., vol. 14, pp. 62-64, July 5, 1967.

Oscillator Circuit for a Vibrating Capacitor

Driven by an RF Electric Field

AART G. VAN NIE

Abstract-The vibrating capacitor to be discussed consistsof a metalized membrane, clamped at its edges, between twoelectrodes. The membrane is driven by an RF electric field (309kHz), which is amplitude modulated at the natural frequency(6 kHz) of the membrane. This RF field is caused by a voltageapplied to one of the electrodes, which, together with the membrane,forms the driving capacitor. The other electrode, and the membrane,constitute the vibrating capacitor.A special RF oscillator has been designed, of which an essential

part is the driving capacitor. This capacitor causes the RF voltageto be amplitude modulated at the natural frequency of the mem-brane. The oscillation conditions of this electromechanical systemare derived from the equation of motion of the membrane andthe electrical properties of the driving circuit. An oscillator circuitwith optimum performance is designed with the aid of a computer.Finally, the computed results are verified by measurements.

I. INTRODUCTION

tHHE vibrating capacitor is a basic component in a

class of instruments for measuring electric chargesor weak currents, such as electrometers, dose

Manuscript received September 14, 1970.The author is with the Philips Research Laboratories, N. V.

Philips' Gloeilampenfabrieken, Eindhoven, the Netherlands.

meters, etc. [1]-[3]. Currents down to 10-17 A can bedetected with the aid of such a capacitor [4]. The currentto be measured is transformed by a known resistanceRm into a voltage, which is applied to the vibratingcapacitor C,. The basic circuit is shown in Fig. 1. The devoltage obtained is converted into an ac voltage bythe vibrating capacitor and this ac voltage is amplifiedand measured. The vibrating capacitor can be consideredas a parametric amplifier. Given perfect insulationresistances of the capacitor Cm and the coupling capacitorC., no energy is drawn from the signal source (exceptenergy needed for charging the input capacitance) and theenergy delivered to the ac amplifier is drawn from thevibrating capacitor in an amount determined by theinput signal.The principle of a vibrating capacitor driven by an

RF electric field has been described in an earlier paper [5].This method of driving, proposed by Zaalberg van Zelst,has the advantage that the relatively high driving voltagedoes not disturb the weak signal to be measured. Thisspecial vibrating capacitor consists of two fixed electrodesbetween which a metalized membrane is clamped as

153,