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Quarterly Technical Report IIIfor

Pittsburgh Digital Greenhouse

Kyusun Choi

The Pennsylvania State UniversityComputer Science and Engineering Department

High Speed CMOS A/D Converter Circuitfor Radio Frequency Signal

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Project Goals for This Quarter

Design and Fab 2nd Prototype chip

1. Design 6 and 8 bit TIQ ADC Circuits

2. Design 6 and 8 bit ADC Layouts

3. Design 2nd Prototype Chip

4. Fabricate 2nd Prototype Chip

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Accomplished Project Milestones

1. Total 10 ADCs are designed (0.18um)• 6bit ADC with L=0.18um and ROM Decoder• 6bit ADC with L=0.50um and ROM Decoder• 6bit ADC with L=1.00um and ROM Decoder• 6bit ADC with L=1.00um and FAT Decoder• 6bit ADC with L=1.00um and Pipeline, ROM• 6bit ADC with L=1.00um and S&H, ROM• 8bit ADC with L=0.50um and ROM Decoder• 8bit ADC with L=1.00um and ROM Decoder• 9bit ADC with L=1.00um and ROM Decoder• 9bit ADC with L=1.50um and ROM Decoder

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Accomplished Project Milestones

2. Layout Design for 10 ADCs, Complete

3. 2nd Prototype Chip Design, Complete

4. Chip Fabrication, Submitted:• Submission date: 10/8/2001• Vendor: MOSIS with TSMC 0.18 m foundry• Expected delivery date: December 2001

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2nd Prototype Chip Summary

1. Die Size: 2.64mm X 2.64mm

2. 0.18um Digital CMOS Process

3. Total 56,069 Transistors

4. 84 Pins, 18 Power pins

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Chip Layout

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Chip Block Diagram

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Chip Layout Dimension

ADCs Size (W*H) um Area (mm2)6bit 0.18um ROM 188.840 * 194.700 0.03686bit 0.50um ROM 188.980 * 239.500 0.04536bit 1.00um ROM 255.020 * 290.700 0.07426bit 1.00um FAT 251.850 * 272.300 0.06866bit 1.00um Pipe 294.530 * 290.710 0.08576bit 1.00um S/H 251.850 * 316.490 0.07988bit 0.50um ROM 202.250 * 815.550 0.16508bit 1.00um ROM 266.400 * 1019.780 0.27179bit 1.00um ROM 438.660 * 1225.100 0.53759bit 1.50um ROM 375.630 * 1583.500 0.5949

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Layout : 6bit, L=0.18um, ROM

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Layout : 6bit, L=1.00um, FAT

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Layout : 8bit L=0.5 um & 9bit, L=1.00um

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Block Diagram : 6bit ADCs

ADCs

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Block Diagram : 8bit ADCs

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Block Diagram : 6bit, Pipe & S/H

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Block Diagram : Pads

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Simulation: Speed and Power

1. Maximum Speed• Designed with TSMC_TT parameter• With linear step from 0.5V to 1.1V• Other processes

- MOSIS parameters (5)- TSMC parameters (4)

2. Power• Analog• Digital

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Simulation Results

ADCsMax. speed

(MSPS)Max.Speed(process)

Analog Power(mW)

6bit 0.18um ROM 2000 1250 149.1986bit 0.50um ROM 1667 1000 62.036bit 1.00um ROM 1111 667 54.476bit 1.00um FAT 1111 714 36.418bit 0.50um ROM 2000 1000 181.128bit 1.00um ROM 1667 714 151.139bit 1.00um ROM 667 476 269.539bit 1.50um ROM 500 400 153.89

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Simulation Results Worst-case delay

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Simulation Results Worst-case delay (input swing: 0 V to 1.8 V)

• TSMC_TT (nSec)

ADCs t_comp t_gb t_rom t_out

6bit 0.18um ROM 0.084 0.358 0.893 1.030 6bit 0.50um ROM 0.237 0.521 1.200 1.320 6bit 1.00um ROM 0.540 0.837 2.170 2.3306bit 1.00um FAT 0.540 0.784 1.670 1.690

8bit 0.50um ROM 0.240 0.525 0.935 1.040 8bit 1.00um ROM 0.538 0.836 1.940 2.070 9bit 1.00um ROM 0.549 0.932 2.610 2.780 9bit 1.50um ROM 0.984 1.380 2.900 3.030

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Simulation Results Worst-case delay (input swing: 0.5 V to 1.1 V)

• TSMC_TT (nSec)

ADCs t_comp t_gb t_rom t_out

6bit 0.18um ROM 0.122 0.395 0.969 1.090 6bit 0.50um ROM 0.338 0.623 1.470 1.580 6bit 1.00um ROM 0.867 1.160 3.750 3.8906bit 1.00um FAT 0.867 1.110 1.960 1.980

8bit 0.50um ROM 0.340 0.624 1.090 1.210 8bit 1.00um ROM 0.868 1.170 2.810 2.950 9bit 1.00um ROM 0.896 1.280 3.540 3.720 9bit 1.50um ROM 1.660 2.060 4.720 4.860

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Simulation Results DNL and INL• TSMC_TT: 8bit 0.50um

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Simulation Results DNL and INL (LSB)

ADCs TSMC_TT TSMC_FSDNL INL DNL INL

6bit 0.18um 0.003 0.003 0.023 0.2266bit 0.50um 0.005 0.007 0.082 0.2716bit 1.00um 0.008 0.006 0.035 0.3518bit 0.50um 0.090 0.076 0.209 1.1198bit 1.00um 0.084 0.077 0.199 1.4509bit 1.00um 0.150 0.104

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Simulation Results DNL and INL (LSB)

ADCs T12K_LO_EPI T16X_LO_EPIDNL INL DNL INL

6bit 0.18um 0.032 0.177 0.056 0.7296bit 0.50um 0.115 1.016 0.115 1.6896bit 1.00um 0.156 1.313 0.150 1.8138bit 0.50um 0.259 4.349 0.291 6.9238bit 1.00um 0.257 5.461 0.241 7.5009bit 1.00um 0.436 11.501 0.446 15.338

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Simulation Summary

1. High-speed with 0.18 um• Approximately 50% higher speed than 0.25um• Process variation problems

2. Power consumption• Lower power consumption

3. Chip area• Higher circuit density

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1. Report III• http://www.cse.psu.edu/~chip/pdg/report3.html• Slide : http://www.cse.psu.edu/~chip/pdg/p3.ppt

2. Report II• http://www.cse.psu.edu/~chip/pdg/report2.html• Slide : http://www.cse.psu.edu/~chip/pdg/p2.ppt

3. Report I• http://www.cse.psu.edu/~chip/pdg/rp1/report.html• Slide : http://www.cse.psu.edu/~chip/pdg/rp1/p1.ppt

URLs for The Reports

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Publications1. New Paper Accepted

• “Design Method and Automation of Comparator Generation for Flash A/D Converter”, ISQED 2002 (March)

2. Previous Paper Published• “A 1-GSPS CMOS Flash Analog-to-Digital

Converter for System-on-Chip Applications”, WVLSI 2001

• “Future-Ready Ultrafast 8bit CMOS ADC for System-on–Chip Applications”, 14th ASIC/SOC 2001

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CONCLUSIONAccomplished Milestones:

• Total 10 ADCs Designed: 6 bit, 8 bit, and 9 bit ADCs

• 2nd Prototype Chip Design

• Chip Fabrication, Submitted• MOSIS 10/8/2001• 0.18 m Digital CMOS• Return: December 2001

• Speed Increased Over 1st Proto Chip

• More ADCs on 2nd Proto Chip