quartus ii training

8/3/2019 Quartus II Training

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Copyright 2005 Altera Corporation

Quartus II Basic TrainingQuartus II Basic Training


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Copyright 2005 Altera Corporation2

Structured ASIC HardCopy II, HardCopy Stratix

High & Medium Density FPGAs

Stratix II, Stratix, APEX II, APEX20K, & FLEX 10K

Low-Cost FPGAs

Cyclone II & Cyclone

FPGAs with Clock Data Recovery

Stratix II GX

CPLDs

MAX II, MAX 7000 & MAX 3000

Embedded Processor Solutions NiosII

Configuration Devices

Serial (EPCS) & Enhanced (EPC)

Programmable Logic FamiliesProgrammable Logic Families


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MAX 7000A & MAX 3000A Family

Overview

MAX 7000A & MAX 3000A Family

Overview

Useable Gates

Macrocells

Maximum User

I/O Pins

tPD (ns)

fCNT (MHz)

tSU (ns)

tCO1 (ns)

600

32

34

4.5

227

2.9

3.0

Parameter

1,250

64

66

4.5

222

2.8

3.1

2,500

128

96

5.0

192

3.3

3.4

5,000

256

158

7.5

127

5.2

4.8

10,000

512

208

7.5

116

5.6

4.7

EPM3032A

EPM3064A

EPM3128A

EPM3256A

EPM3512A

MAX 3000A

600

32

36

4.5

227

2.9

3.0

1,250

64

68

4.5

222

2.8

3.1

2,500

128

100

5.0

192

3.3

3.4

5,000

256

164

5.5

172

3.9

3.5

10,000

512

212

7.5

116

5.6

4.7

EPM7032AE

EPM7064AE

EPM7128AE

EPM7256AE

EPM7512AE

MAX 7000A


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Complete Voltage PortfolioComplete Voltage Portfolio

MAX 7000S MAX 7000AE

MAX 3000A

MAX 7000B Performance

Leader

Feature Leader Wide Range of

Package Offerings

Industrial-GradeOfferings

High Performance Feature Leader Wide Range of

Package Offerings

Price Leader Feature & Package

Subset ofMAX 7000AE

High Performance Feature Leader Wide Range of

Package Offerings

5.0 V 2.5 V3.3 V


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MAX Device Block Diagram


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MAX MacrocellGlobalClock

GlobalClear

36 Programmable

Interconnect

Signals 16 Expander

Product Terms

to I/O

Control

Block

7000 has two Global Clock

Product-

Term

Select

MatrixVCC

D

ENA

PRn

CLRn

Q

Clear

Select

Clock/

Enable

Select

Register

Bypass

Shared Logic

Expanders

Parallel Logic

Expanders(from other MCs)

to PIA

Programmable

Register


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MAX II: The Lowest-Cost CPLD EverMAX II: The Lowest-Cost CPLD Ever

New Logic Architecture 1/2 the Cost

1/10 the Power Consumption

2X the Performance

4X the Density

Non-Volatile, Instant-On

Supports 3.3-, 2.5- & 1.8-V

Supply Voltages

Breakthrough Technologyto Expand the Market


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Flexible Supply VoltageFlexible Supply Voltage

On-Chip VoltageRegulator

Accepts 3.3-, 2.5- &

1.8-V Supply Inputs Internally Converted to

1.8-V Core Voltage

Convenience of 3.3 V withthe Power & Performance of 1.8 V


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MAX II Device FamilyMAX II Device Family

Device

Logic

Elements

(LEs)

Typical

Macro-

cells

User

I/O

Pins

Speed

Grades

Fastest

tpd1(ns)

User

Flash

Memory

(bits)

EPM240 240 192 80 3, 4, 5 4.7 8,192

EPM570 570 440 160 3, 4, 5 5.5 8,192

EPM1270 1,270 980 212 3, 4, 5 6.3 8,192

EPM2210 2,210 1,700 272 3, 4, 5 7.1 8,192


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Device100-Pin TQFP1

0.5-mm Pitch

16 x 16 mm

144-Pin TQFP0.5-mm Pitch

22 x 22 mm

256-Pin FBGA2

1.0-mm Pitch

17 x 17 mm

324-Pin FBGA1.0-mm Pitch

19 x 19 mm

EPM240 80

EPM570 76 116 160

EPM1270 116 212

EPM2210 204 272

MAX II Packaging & User I/O PinsMAX II Packaging & User I/O Pins

Denotes Vertical Migration

Notes:

1. TQFP: thin quad flat pack

2. FineLine BGA package (1.0-mm pitch)


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New Small PackagesNew Small Packages

Packages minimize PCB area and optimizeease-of-use Partial arrays allow for 2 layer PCB break out

T1000.5mm TQFP

16x16mm

Partial

M100

0.5mm MBGA

6x6mm

Partial

M256

0.5mm MBGA

11x11mm

F256

1.0mm FBGA

17x17mm

New Packages


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MAX II ArchitectureMAX II Architecture

StaggeredI/O Pads

User FlashMemory

LogicElements(LEs)

JTAG &ControlCircuitry

ConfigurationFlash Memory


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MAX II Logic Element (LE)MAX II Logic Element (LE)

data1

addnsub

data2

data34-Input

LUT

4-Input

LUTcin

data4

Register

Chain

RegReg

sload sclear aload

clock

ena

aclr

Row,Column

& Direct

Link

Routing

Local

Routing

LUT

Chain

Register

Chain


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User Flash MemoryUser Flash Memory

Feature Flash Memory

Storage Bank

8,192 Bits Per Device

Interface to SPI, I

2

C,Parallel, or ProprietaryBuses

Applications Store Revision & Serial

Number Data Store Boot-Up &

Configuration Data

IndustryFirst!

User FlashMemory Block


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MAX & MAX II ComparisonMAX & MAX II ComparisonParameter MAX MAX II

Process Technology 0.3-um EEPROM 0.18-um Flash

Logic Architecture Product Term Look-Up Table (LUT)

Density Range 32 to 512 Macrocells 128 to 2210 Macrocells

(240 to 2,210 LEs)

Routing Architecture Global Row & ColumnOn-Chip Flash Memory None 8 Kbits

Maximum User I/O

Pins

212 272

Supply Voltage 5.0 V, 3.3 V, 2.5 V 3.3 V/2.5 V, 1.8 V

I/O Voltages 5.0 V, 3.3 V, 2.5 V, 1.8 V 3.3 V, 2.5 V, 1.8 V, 1.5 VGlobal Clock Networks 2 per Device 4 per Device

Output Enables (OEs) 6 to 10 per Device 1 per I/O Pin

Schmitt Triggers None 1 per I/O Pin


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What is Nios II?What is Nios II?

Alteras Second Generation Soft-Core 32 Bit RISC Microprocessor Developed Internally By Altera

Harvard Architecture

Royalty-Free

FPGA

- Nios II Plus All Peripherals Written In HDL

- Can Be Targeted For All Altera FPGAs

- Synthesis Using Quartus II Integrated Synthesis

AvalonSwitchFabric

UART

GPIO

Timer

SPI

SDRAMController

On-ChipROM

On-ChipRAM

Nios IICPUDebug C

ache


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Nios II Processor ArchitectureNios II Processor Architecture

Classic Pipelined RISC Machine 32 General Purpose Registers

3 Instruction Formats

32-Bit Instructions

32-Bit Data Path

Flat Register File

Separate Instruction and Data Cache (configurable sizes)

Tightly-Coupled Memory Options

Branch Prediction

32 Prioritized Interrupts On-Chip Hardware (Multiply, Shift, Rotate)

Custom Instructions

JTAG-Based Hardware Debug Unit


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Problem: Reduce Cost, Complexity &PowerProblem: Reduce Cost, Complexity &Power

Flash

SDRAM

CPU

DSP

I/O

I/O

I/O FPGA

I/O I/O I/O

CPU DSP

Solution: Replace External Deviceswith Programmable Logic

FPGA


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Problem: Reduce Cost, Complexity &PowerProblem: Reduce Cost, Complexity &Power

Flash

SDRAM

Solution: Replace External Deviceswith Programmable Logic

CPU is a Critical Control FunctionRequired forSystem-Level Integration

System On A Programmable Chip (SOPC)System On A Programmable Chip (SOPC)

FPGA


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LicensingLicensing

Nios II Delivered As Encrypted Megacore Licensed Via Feature Line In Existing Quartus II License File

Consistent With General Altera Megacore Delivery Mechanism

Enables Detection OfNios II In Customer Designs (Talkback)

No Nios II Feature Line (OpenCore Plus Mode)

System Runs If Tethered To Host PC System Times Out If Disconnected from PC After ~ 1 hr

Nios II Feature Line (Active Subscriber) Subscription and New Dev Kit Customers Obtain Licenses From

www.altera.com

Nios II CPU RTL Remains Encrypted

Nios II Source License Available Upon Request On Case-By-Case Basis

Included With Purchase OfNios II ASIC License


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Quartus II Basic TrainingQuartus II Basic Training

Quartus II Development System

Feature Overview

Quartus II Development System

Feature Overview


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Software & Development ToolsSoftware & Development Tools

Quartus II All Stratix, Cyclone & Hardcopy Devices APEX II, APEX 20K/E/C, Excalibur, &

Mercury Devices

FLEX 10K/A/E, ACEX 1K, FLEX 6000Devices

MAX II, MAX 7000S/AE/B, MAX 3000ADevices

Quartus II Web Edition Free Version

Not All Features & Devices Included See www.altera.com for Feature

Comparison

MAX+PLUS II All FLEX, ACEX, & MAX Devices


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Quartus II Development SystemQuartus II Development System

Fully-Integrated Design ToolMultiple Design Entry Methods

Logic Synthesis

Place & Route

Simulation

Timing & Power Analysis

Device Programming


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Typical PLDDesign Flow

Synthesis- Translate Design into Device Specific Primitives

- Optimization to Meet Required Area & Performance Constraints

- Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA,

Quartus II

Design Specification

Place & Route- Map Primitives to Specific Locations inside

Target Technology with Reference to Area &

Performance Constraints

- Specify Routing Resources to Be Used

Design Entry/RTL Coding- Behavioral or Structural Description of Design

RTL Simulation

- Functional Simulation (Modelsim, Quartus II)

- Verify Logic Model & Data Flow

(No Timing Delays)

LEM512

M4K I/O


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Typical PLDDesign Flow

Timing Analysis- Verify Performance Specifications Were Met- Static Timing Analysis

Gate Level Simulation- Timing Simulation

- Verify Design Will Work in Target Technology

PC Board Simulation & Test- Simulate Board Design

- Program & Test Device on Board

- Use SignalTap II for Debugging

tclk


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Design Entry MethodsDesign Entry Methods

Quartus II Text Editor

AHDL

VHDL

Verilog

Schematic Editor

Block Diagram File Graphic Design File

Memory Editor HEX

MIF

3

rd

-Party EDA Tools EDIF HDL

VQM

Mixing & Matching Design Files Allowed

Top-level design files can

be schematic, HDL or 3rd-Party Netlist File

BlockFile

SymbolFile

TextFile

TextFile

TextFile

Imported from 3rd-PartyEDA toolsGenerated within Quartus II

TextFile

TextFile

.v, vlg,.vhd, .vhdl,

vqm

.edf.edif

.v.vhd.tdf.bsf.bdf.gdf

Top-Level

File


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Quartus II Basic TrainingQuartus IIQuick Start

LAB1


LAB1


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ObjectivesObjectives

Create a projectusing the New ProjectWizard

Name the project

Add design filesPick a device


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Step 1 (Setup Project for QII5_1)Step 1 (Setup Project for QII5_1)

Under File, Select New Project Wizard.A new window appears. If an Introduction

screen appears, click Next.


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Step 2 (Setup Project for QII5_1)Step 2 (Setup Project for QII5_1)Page 1 of the wizard should be completed with the following

working directory for this project \Dsp_7_segment\

name of project Dsp_7_segment

top-level design entity Dsp_7_segment

Copy state_machine.v and past in

Dsp_7_segment

Click Nextto advance to the

Project Wizard: Add Files [page 2 of 5].


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Step 3 (Setup Project for QII5_1)Step 3 (Setup Project for QII5_1)

Using the browse button, select state_machine.vAdd to the project. Click Next.


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Step 4 (Setup Project for QII5_1)Step 4 (Setup Project for QII5_1)On page 3, select Stratix as the Family. Also, in the Filters section,

set Package to FBFA, Pin count to 780, and Speed grade to 5.Select the EP1S25F780C5 device from

the Available devices: window. Click Next.


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Step 5 (Setup Project for QII5_1)Step 5 (Setup Project for QII5_1)On page 4 , you can specify any third party EDA tools you may be using

along with Quartus II. Since these exercises will be done entirely within

Quartus II, click Next.


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Step 6 (Setup Project for QII5_1)Step 6 (Setup Project for QII5_1)The summary screen appears as shown. Click Finish.

The project is now created.


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LAB2


LAB2


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Create a counterusing the MegaWizardPlug-in Manager

Build a design using the schematic editor

Analyze and elaborate the design to checkfor errors


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Step 1 Create schematic fileStep 1 Create schematic fileSelect File New and select Block Diagram/Schematic File. Click OK.

Select File Save As and save the file as \Dsp_7_segment\ Dsp_7_segment.bdf


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Step 2 Build an 23 bits counter using the MegaWizard Plug-in ManagerStep 2 Build an 23 bits counter using the MegaWizard Plug-in Manager1.Choose Tools MegaWizard Plug-In Manager. In the window that appears,

select Create a new custom megafunction variation. Click on Next.2.On page 2a of the MegaWizard expand the arithmetic folder and select

LPM_COUNTER.

3.Choose Verilog HDL output For the name of the output file, type timer_1s.

Click on Next


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Step 3Step 31. Set the output bus to 27 bits. For the remaining settings in this window,

use the defaults that appear .. Select next2. .Turn on Modulus , with a count modulus ofand key in 79999999

3. Select finish


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Step 4Step 4In the Graphic Editor, double-click in the screen so that the Symbol Window

appears. Inside the symbol window, click on to expand the symbols definedin the Project folder. Double-click on timer_1s. Click the

left mouse button to put down the symbol inside the schematic file.. The symbol

fortimer_1s now appears in the schematic.


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Step 5Step 5

1. From the File menu, open the file state_machine.v2. From the File menu, go the Create/Update menu option and select

Create Symbol Files for Current File. ClickYes to save changes

to Dsp_7_segment.bdf.

3. Once Quartus II is finished creating the symbol, click OK. Close the

state_machine.v file

4. In the Graphic Editor, double-click in the screen so that the SymbolWindow appears again. Double-click on state_machine in the

Project folder. Click OK... The symbol forstate_machine now

appears in the schematic.


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Step 6 Add Pins to the DesignStep 6 Add Pins to the Design

Input Output

sys_clk 7_out[6..0]

reset Dig1

For each of the pins listed in left Table , you must insert

a pin and change its name

1. To place pins in the schematic file, go to Edit Insert Symbol OR

double-click in any empty location of the Graphic Editor.

2. Browse to libraries primitives pin folder. Double-click on input

oroutput int:T

o insert mu

ltiple pins selectR

epeat Inser

t Mode.3. To rename the pins double-click on the pin name after it has been

inserted.

4. Type the name in the Pin name(s) field and Click OK

.


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43

Step 7 Connect the Pins and Blocks in the SchematicStep 7 Connect the Pins and Blocks in the Schematic1. In the left hand tool bar click on button to draw a wire and button to draw a bus.

Another way to draw wires and busses is to place the cursor next to the port of anysymbol. When you do this, the wire or bus tool will automatically appear.

2. Connect all of the pins and blocks as shown in the figure below


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44

Step 8 Save and check the schematicStep 8 Save and check the schematic

1. Click on the Save button in the toolbar to save the schematic.

2. From the Project menu, select Add/Remove Files in Project.Click on the browse button to make sure the Dsp_7_segment.bdf,

timer_1s and state_machine are added to the project.

3. From the Processing menu, select Start Start Analysis & Elaboration.

Analysis and elaboration checks that all the design files are present and

connections have been made correctly.4. ClickOKwhen analysis and elaboration is completed


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LAB3


LAB3


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46


Pin assignmentPerform full compilation Build a design

using the schematic editor

How to Download programming file


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47

Step 1Step 11. Choose AssignmentsAssignment editor.

2. From the View menu, select Show All Know Pin Names.3. Please click Pin in Category


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48

Step 2Step 21. Pls install DSP Development Kit Stratix edtion CD

2. Open ds_stratix_dsp_bd.pdf from C:\megacore\stratix_dsp_kit-v1.1.0\Doc3. Check clk , pushbotton and seven segment display pin location from

ds_stratix_dsp_bd.pdf

4. Key your pin number in location

5. Click on the Save button in the toolbar

6. From Assignments, select Device. Click Device & Pin options. Click

Unused pins .Select As input tri-stated from Reserve all unused pins7. From the Processing menu, select Start Compilation


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49

Step 3Step 31. From the Tools menu, select programmer

2. Click on Add File. Select Dsp_7_segment.sof.3. Check Hardware Setup. Select your download cable on

Currently selected hardware(ByteBlasterII)

4. Select JTAG from Mode


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50

Step 4Step 41. Turn on Program/configure. Or see figure below

2. Click Start3. See 7-segment status


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51

SignalTap II AgendaSignalTap II Agenda

SignalTap II Overview & FeaturesUsing SignalTap II Interface

Advanced Triggering


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52

SignalTap II ELASignalTap II ELASignalTap II ELASignalTap II ELA

Captures the Logic State of FPGA InternalSignals Using a Defined Clock Signal

Gives Designers Ability to Monitor Buried Signals

Connects to Quartus II through FPGA JTAG Pins

Captures Real-Time Data Up to 200 Mhz

Is Available for Free Installed with Full Subscription or Web Edition

Installed with Stand-Alone Programmer


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53

SignalTap II Device SupportSignalTap II Device Support

Stratix & Stratix IIStratix GX

Cyclone & Cyclone II

ExcaliburMercury

APEX II

APEX 20K/E/C


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54

How Does It Work?How Does It Work?How Does It Work?How Does It Work?

1. Configure ELA

2. Download ELA into

FPGA along with

Design

3. ELA Samples Internal

Signals4. Quartus II

Communicates with

ELA through JTAG


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55

Stratix/Cyclone Sample Resource UsageStratix/Cyclone Sample Resource Usage

Number of

Channels

Logic Elements

Trigger Level 1 Trigger Level 2 Trigger Level 3

8 316 371 426

32 566 773 981

256 2900 4528 6156

Number of

Channels

M4Ks Based on Sample Depth

256 512 2K 8K 32K

8 < 1 1 4 16 64

32 2 4 16 64 256256 16 32 128 512


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56

Modes of OperationModes of OperationModes of OperationModes of Operation

Three Different Configurations Internal RAM ELA Configuration

Debug Port ELA Configuration

Hybrid Approach

Provides Flexibility Based on AvailableDevice Resources

Memory Resources Are Limited

Use Debug Port Configuration Pin Resources Are Limited

Use Internal RAM Configuration


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57

Supported Download CablesSupported Download Cables

USB Blaster USB Port Cable

ByteBlaster II

Parallel Port Cable

ByteBlasterMV

Parallel Port

MasterBlaster

USB / Serial Port Cable


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58

SignalTap II Key FeaturesSignalTap II Key Features

SetupData Triggering

Data Capture

Data Analysis


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59

Setup FeaturesSetup Features

Up to 1024 Data ChannelsMultiple Analyzers in One Device

Supports Analysis of Multiple Clock

Domains

Each Analyzer Can Run Simultaneously

Resource Usage Estimation Incremental Design Support

Setup

Data Triggering

Data Capture

Data Analysis


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Data Triggering FeaturesData Triggering Features

Up to 10 Trigger Levels Per Channel Allows Application of Simple (Basic) &

Complex (Advanced) Triggering Schemes

Defines a Sequential Pattern of Logic Conditions

Each Trigger Level is Logically ANDED If (L1 & L2 ... & L10) == TRUE Data Capture

Setup

Data Triggering

Data Capture

Data Analysis


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Data Triggering Features (Cont.)Data Triggering Features (Cont.)

Three Main Trigger Positions

Trigger Input Setup External Trigger to Trigger the Analyzer

Trigger Output Signifies Trigger Event Occurred with SignalTap II

Use One ELAs Trigger Output as TriggerInput for Another

Data Triggering

Setup

Data Triggering

Data Capture

Data Analysis

TIME

Old Samples New Samples

trigger

Samples CapturedSamples Captured


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62

Data Capture FeaturesData Capture Features

Up to 128K Samples Per Channel Increases Chance of Catching Target

Event

Two Methods of Data Acquisition

1. Circular

2. Segmented

Mnemonic Tables Create User-Defined Labels for Bit Sequences

(Ex. State Machine)

Setup

Data Triggering

Data Capture

Data Analysis


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63

SignalTap II Design FlowSignalTap II Design Flow

1) Use SignalTap II File (.STP) Use Quartus II GUI

STP Separate from Design Files

2) Use Quartus II MegaWizard Instantiate Directly into HDL


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64

Using STP FileUsing STP File

1. Create .STP File Assign Sample Clock

Specify Sample Depth

Assign Signals to STP File Specify Triggering

Setup JTAG

2. Save .STP File & Compile with Design

3. Program Device

4. Acquire Data


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65

1) Creating a New .STP File1) Creating a New .STP File1) Creating a New .STP File1) Creating a New .STP File

To Create a .STP File Method 1

Select the in Quartus II

Method 2Select New (File Menu)

Other FilesSignalTap II File

Default File Name Will Be STP1.stp


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66

Main .STP File ComponentsMain .STP File Components

Signal Configuration

JTAG Chain

Configuration

Waveform Viewer

.STPFileInstance Manager


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67

Instance ManagerInstance Manager

Instance Manager Selects Current ELA to Setup/View

Displays the Current Status of each Instance

Displays Size (Resource Usage) of ELA


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68

Assign Sample ClockAssign Sample Clock

Use Global Clock for BestResults

Data Written to Memory onEvery Sample Clock RisingEdge

Clock Signal Cannot BeMonitored as Data

External Clock Pin CreatedAutomatically if ClockUnassigned auto_stp_external_clock

ELA Expects External Signal tobe Connected to Clock Pin


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69

Specify Sample DepthSpecify Sample Depth

Sample Depth Set Number of Samples

Stored for each Data Signal

0 to 128K Sample Depth

0 Selected When ExternalAnalyzer Is Used

Select RAM Type for Stratix

& Stratix II Devices

Useful when Preserving aSpecific Memory Type is

Necessary


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70

Data CaptureData Capture

Circular Specify Trigger Position

Pre

Center

Post

Continuous

Segmented

Specify Segment Depth


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71

TriggeringTriggering

Trigger Levels Indicate up to 10 Trigger Conditions

Trigger-In

Any I/O Pin Can Trigger the

SignalTap II Analyzer

Generates auto_stp_trigger_in_n Pin

Trigger-Out

Indicates When a Trigger Pattern

Occurs

Generates auto_stp_trigger_out_n Pin

Delayed 4 Clock Cycles after Actual

Trigger Event


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72

Waveform ViewerWaveform Viewer

Setup Tab Describes the Signal Settings Data Signals vs. Trigger Signals

Sets up Each Triggering Level (L1 L10)

Data Tab Displays Captured Data


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73

STP File Waveform ViewerSTP File Waveform Viewer

Setup Tab

Data Tab


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74

Basic TriggeringBasic Triggering

Right-Click

to Set Value

All Signals Must BeTrue for Level to

Cause Data Capture


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75

Debug PortDebug Port

Routes Data Signals to Spare I/O Pins forCapture by External Logic Analyzer

Quartus II Automatically Generates

auto_stp_debug_out_m_n Pin

m Represents the Instance Number of the Analyzer

n Represents the Order the Debug Port Pin Occurs

in the Signal List


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76

Mnemonic TableMnemonic Table

Allows a Set of Bit Patternsto Be Assigned User-

Defined Names

Right-Click in the Setup View

of an STP File & Select

Mnemonic Setup Select Add Table

Select Add Entry

Ex. State Machines or

Decoders/Encoders


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77

JTAG Chain ConfigurationJTAG Chain Configuration

Select Programming HardwareScan Chan Button Automatically

Determines Devices Physically Connected

to the ChainDetects Non-Altera Devices & Displays Them asUnknown


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78

2) Save .STP File & Compile2) Save .STP File & Compile

SignalTap II Logic Analyzer Control in CompilerSettings

Assignments Settings

Specify the STP File to Compile with Project


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3) Program Device(s)3) Program Device(s)

Use Quartus II Programmer or STP File Program Button in the SignalTap II Interface Only

Configures the Selected Device in Chain

Use Quartus II Programmer to Program Multiple

DevicesCan Create a STP File for each Device in the JTAG Chain

4) A i D4) A i D


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4) Acquire Data4) Acquire Data

SignalTap II Toolbar & STP File Controls

Run

Autorun

Stop

Read Data (Reads in Data from Last Analysis)

Di l i A i d D tDi l i A i d D t


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Displaying Acquired DataDisplaying Acquired Data

Display Signal as Bar or Line Chart

Export to Other Tools for Viewing or Analysis(File Menu) Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File

Format in Time or

Sample Number

U i STP Fil R iU i STP Fil R i


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82

Using STP File ReviewUsing STP File Review

1. Create .STP File Assign Sample Clock

Specify Sample Depth

Assign Signals to STP File

Specify Triggering

Setup JTAG

2. Save .STP File & Compile with Design

3. Program Device

4. Acquire Data

R il tiR il ti


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RecompilationRecompilation

Recompilation RequiredAddition/Removal of Instance, Data or Trigger

Modifying the Sample Clock or Buffer Depth

Enabling/Modifying Trigger-In/Trigger-Out

Enabling the Debug Port

Lock Mode Prevents Changes RequiringRecompilation

R d i R il ti TiR d i R il ti Ti


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Reducing Recompilation TimesReducing Recompilation Times

Incremental Compilation Maintains Design Synthesis & Placement

Recompiles Only Logic AnalyzerChange SignalTap II Configuration without Affecting Existing

Logic

Incremental Routing Allows Switching Trigger & Data Nodes without Full

Recompilation

Cannot Be Used Together in 5.0 Use Incremental Compilation First, Switch to Routing

Will Be Supported in Future Version of Quartus II

Si lT II I t l C il tiSi lT II I t l C il ti


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SignalTap II Incremental CompilationSignalTap II Incremental Compilation

1) Enable Full Incremental Compilation Any User-Defined

Partitions Must Be

Removed

(5.0 Limitation)

2) Set Netlist Type of Top-Level Partition to Post-Fit

Assignments Menu

Si lT II I t l C il tiSi lT II I t l C il ti


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SignalTap II Incremental CompilationSignalTap II Incremental Compilation

3) Compile Design

4) Enable SignalTap II Incremental Compilation

Only Post Fitting Nodes Can Be Incrementally Compiled

Quartus II Will Automatically Convert Pre-Synthesis Nodes to

Post-Fitting

Si lT II I t l R tiSi lT II I t l R tiSi lT II I t l R tiSi lT II I t l R ti


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SignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental Routing

1) Enable Smart Recompilation

2) Manually Set the Number of Allocated Nodes Nodes Acts as Place Holders for Real Signals that Can Be Added

Later

Auto Creates Enough Nodes for Current Number of Data/Triggers

Si lT II I t l R tiSi lT II I t l R tiSi lT II I t l R tiSi lT II I t l R ti


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SignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental Routing

3) Add Post-Fitting nodes to STP file SignalTap II: Post-Fitting Nodes Always Incrementally Routed

SignalTap II: Pre-Synthesis Nodes Always Cause Full

Recompilation if Added Later

Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes

is They Can Be Removed & Replaced with Post-fittingNodes

without Total Recompilation

Pre-SynthesisNodes

Post-fittingNodes

Q t II N tli t O ti i tiQ t II N tli t O ti i ti


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Quartus II Netlist OptimizationQuartus II Netlist Optimization

New Synthesis Optimization Features Do

NotWork Well with SignalTap II

SignalTap II Nodes may Disappear

Register Re-timing & WYSIWYG Re-Synthesis Should

be Disabled if SignalTap II is Used

Set Netlist Optimizations LogicOption to Never

Allowon Entities which Have SignalTap II Nodes

Performance Preser ationPerformance Preser ation


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Performance PreservationPerformance Preservation

SignalTap II can Potentially Effect thePerformance of a Design

Routing and/or Placement Can Change

Possible Solution Back-Annotate Design before Adding

SignalTap II

See Quartus II Handbook, Volume 3, Chapter

10 for More Suggestions


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Thank YouThank You

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