quiz on ch - faculty website listing · pdf filequiz on ch.7 1] explain the ... do you notice...
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Week 14, Lect.1/2
Quiz on Ch.7
1] Explain the operation of this T Flip-Flop with Enable:
How does the circuit operate when EN= 1? (Words and diagram)
When EN = 0?
2] Explain in a short paragraph the meaning of Setup time and Hold time.
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Ch.8 Designing Synchronous Sequential Circuits
Motivation: In Ch.7 we have seen several times the idea of mixing
sequential and combinational circuits in order to obtain larger
circuits with desired behavior,
e.g. binary counter:
e.g. the control unit for register-swapping:
… but all these are “just so” contraptions! (similar to the MUX for
combinational circuits)
Is there a general method to design our own sequential circuits from
scratch? (similar to the truth table + SOP method for combinational)
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Q: What is the state of a sequential circuit?
A: The combination of the states (Q values) of all flip-flops.
Finite state machine (FSM)
→ with N flip-flops, how many states are possible?
Synchronous FSM (SFSM?)
the CLKs of all flip-flops are connected in parallel to a “master
CLK” signal
structure of an (S)FSM:
Moore → All paths between I and O go through a Flip-Flop
Mealy → There is at least one path between I and O that does
not go through a FF
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Pattern recognition: Moore or Mealy? (Not in text!)
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End – Moore or Mealy
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Name the parts of a Moore/Mealy machine (not in text!):
As with combinational circuits, problems involving FSMs can be of
two types:
Analysis → Given the circuit, figure out the sequence of states
Design (a.k.a. synthesis) → Given the sequence of states,
design a machine that implements it
Asynchronous
I/O path
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8.1 Basic design steps
Problem: Design the following sequence detector:
One input w
One output z
All changes occur at positive edge of CLK
z = 1 if during the two immediately preceding CLK cycles the
input w was 1
z = 0 otherwise
Design algorithm
Draw the symbol (black-box) for the circuit, w/inputs and outputs
Decide if a sequential circuit is needed
To answer this, we may want to try out some sequences of inputs,
like this:
Conclusion: The output does not depend on input alone!
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Draw the state diagram
Extra-credit: Can you tell just by looking at the diagram if it’s
Moore or Mealy? (Must explain for credit!)
Draw the next state table
Perform state assignment …
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Draw the state-assigned table
Sketch the outline of a Moore/Mealy machine, with the required
number of flip-flops
Choose type of Flip-Flops → We’ll only use D (JK may lead to
simpler next-state logic, read Section 8.7 FYI)
From the state-assigned table, extract separate truth tables for the D
input of each FF.
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Design the next-state logic and output logic (all combinational!) Here we can use all the design and optimization techniques we learned for
combinational circuits: canonical SOP, K-maps, functional
decomposition, multiple-output optimization
Draw final circuit diagram
The text includes a timing diagram after this, but it’s really an
analysis tool …
To do in notebook for next time:
READ and take notes → Section 8.1 (pp.487-497)
Understand Example 8.1/494
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Quiz:
What does FSM stand for?
Moore or Mealy?
Explain and mark the relevant path(s) on the diagram (handout)
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Another application of flip-flops: Remember the CPLD blocks …
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Application of FSM
Algorithm for swapping contents of R1 and R2, using R3:
CLK1 Load R2 into R3 signals …
CLK2 Load R1 into R2 signals …
CLK3 Load R3 into R1 signals …
Turn on additional output Done
R3
R3in R3out
n
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Moore or Mealy?
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8.2 State assignment
By assigning the binary codes for the states in a clever way,
we can minimize the hardware required!
To do in notebook for next time: Example 8.2
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The simplest combinational logic: “one-hot”
Advantage: Next-state combinational logic is simpler.
Disadvantage: # of Flip-Flops is equal to # of states (instead
of logarithmic)
To do in notebook for next time: Example 8.3
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8.3 Designing Mealy machines
Problem: “11 detector”, but we want the output to turn to 1 in the same cycle
in which the second one is detected!
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How to turn a Mealy into a Moore:
For more practice:
Implement a two-input Mealy machine that produces a 1 at its single
output when the values of the two inputs differ at the time of the
previous clock pulse. Show your state -diagram or ASM chart.
Describe what each of your states is supposed to represent.
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8.4 Designing FSMs with VHDL
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SKIP the rest of Section 8.4
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8.5 Design example: SERIAL ADDER
All the combinational adders we studied in Ch.5 perform the
additions of the bits (more or less) in parallel
Advantage: Speed!
Disadvantage: Lots of hardware!
O(n) for ripple-carry, a little higher if we want lookahead
If speed is not an issue, serial adders can save a lot of
hardware!
O(log n)
Let’s design the Adder FSM!
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Do you notice any parity pattern in s?
Moore or Mealy?
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SKIP the rest of Section 8.5
This concludes the material required for the final
Tuesday class → REVIEW!
See you this afternoon for our last lab!