racyics® abx platform

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Body biasing is a disruptive 22FDX® feature enabling on-the- fly adaption of transistor threshold voltages. Racyics® adaptive body biasing platform (Racyics® ABX Platform) provides reliable and predictable ultra-low voltage (ULV) operation down to 0.4V, compensating process, supply voltage and temperature variations (PVT) to guarantee timing and power with high yield. Í Comprehensive Racyics® ABX Platform for ULV operation Í Racyics® adaptive body bias generator, standard cells, SRAM Í Up to 9X performance 1 Í 75% leakage reduction 2 Í Corner tightening and adaptive body biasing- aware implementation for improved PPA Í Guaranteed performance and power Í Easy-to use turnkey Racyics® ABX solution based on standard design flow and sign-off Í No overhead in test and operation CHALLENGE KEY FACTS TARGET APPLICATION PLATFORM KIT Í Automotive Í Low Power Í IoT Í High Speed Computing 1 at 0.50V compared to zero bias 2 at 0.50V compared to fixed bias IP Type Supplier Description Ready for Evaluation Ready for Testchip Ready for Production Standard Cell Libraries incl. PMK Racyics 104CPP 9T CNRX STD-cell library, fully ABX enabled (FBB, RBB), supply voltages 0.40V/0.45V/0.50V/0.60V/0.80V now now now Racyics 116CPP 8T CNRX STD-cell library, fully ABX enabled (FBB, RBB), supply 0.40V/0.45V/0.50V/0.60V/0.80V now now now SRAM Racyics Dual-Rail SP SRAM generator for ULV designs, supply 0.40V/0.45V/0.50V/0.60V/0.80V (core) 0.80V (bitcells) now now now ABX Generator IP Racyics Racyics® ABB generator, includes PVT monitors, bias generator, digital control loop, supports FBB and RBB now now now IP OFFERING ABX SPEED AND LEAKAGE IMPROVEMENTS EXAMPLE ULV SOC WITH RACYICS® ABX IP Racyics® ABX Platform GLOBALFOUNDRIES® 22FDX® [email protected] +493514188720 www.racyics.com Standard Cells incl. PMK Dual Rail SRAM ABX Generator IP IO Library Clock Generation (ADPLL) controller ULV logic (0.4V … 0.6V) ULV SRAM (Dual Rail 0.4V..0.6V,0.8V) ULL logic (0.8V) Analog (0.8V) Interfaces (1.8V/0.8V) BBGEN (VNW, VPW) PVT monitors ABB domain ABB Generator IP 0.00 0.01 0.10 1.00 00 .1 0.20 .3 0.40 .5 C 5 2 1 % 0 1 + D D V f f n i ] . u . a [ k a e l I Frequency [a.u.], in ss VDD -10% -40C worst speed corner r e n r o c e g a k a e l t s r o w ABB ZBB 9x speed -75% leakage

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Page 1: Racyics® ABX Platform

Body biasing is a disruptive 22FDX® feature enabling on-the-fly adaption of transistor threshold voltages. Racyics® adaptive body biasing platform (Racyics® ABX Platform) provides reliable and predictable ultra-low voltage (ULV) operation down to 0.4V, compensating process, supply voltage and temperature variations (PVT) to guarantee timing and power with high yield.

Í Comprehensive Racyics® ABX Platform for ULV operation

Í Racyics® adaptive body bias generator, standard cells, SRAM

Í Up to 9X performance1

Í 75% leakage reduction2

Í Corner tightening and adaptive body biasing-aware implementation for improved PPA

Í Guaranteed performance and power

Í Easy-to use turnkey Racyics® ABX solution based on standard design flow and sign-off

Í No overhead in test and operation

CHALLENGE

KEY FACTS

TARGET APPLICATION

PLATFORM KIT

Í Automotive

Í Low Power

Í IoT

Í High Speed Computing

1 at 0.50V compared to zero bias2 at 0.50V compared to fixed bias

IP Type Supplier Description Ready for Evaluation

Ready for Testchip

Ready for Production

Standard Cell Libraries incl.

PMK

Racyics104CPP 9T CNRX STD-cell library, fully ABX enabled (FBB, RBB), supply voltages 0.40V/0.45V/0.50V/0.60V/0.80V

now now now

Racyics116CPP 8T CNRX STD-cell library, fully ABX enabled (FBB, RBB), supply 0.40V/0.45V/0.50V/0.60V/0.80V

now now now

SRAM RacyicsDual-Rail SP SRAM generator for ULV designs,

supply 0.40V/0.45V/0.50V/0.60V/0.80V (core) 0.80V (bitcells)

now now now

ABX Generator IP RacyicsRacyics® ABB generator, includes PVT monitors, bias generator, digital control loop, supports FBB and RBB

now now now

IP OFFERING

ABX SPEED AND LEAKAGE IMPROVEMENTS

EXAMPLE ULV SOC WITH RACYICS® ABX IP

Racyics® ABX PlatformGLOBALFOUNDRIES® 22FDX®

[email protected] +493514188720www.racyics.com

Standard Cells incl.

PMK

Dual RailSRAM

ABX Generator IP

IO Library

Clock Generation

(ADPLL)controller

ULV logic (0.4V … 0.6V)

ULV SRAM(Dual Rail 0.4V..0.6V,0.8V)

ULL logic(0.8V)

Analog(0.8V)

Interfaces(1.8V/0.8V)

BBGEN (VNW, VPW)

PVT monitors

ABB domain

ABB Generator IP

0.00

0.01

0.10

1.00

00 .1 0.20 .3 0.40 .5

C521 %01+

DDV ff

ni

].u.a[

kaelI

Frequency [a.u.], in ss VDD -10% -40C

worst speed corner

renroc egakael

tsrow

ABBZBB 9x speed

-75% leakage

Page 2: Racyics® ABX Platform

Racyics GmbHBergstraße 56 • 01069 Dresden • Germany