Radiation Tolerance

D. C. Christian, J. A. Appel, G. Chiodini,

Tests of a Prototype

B. Hall, J. Hoff, S. Kwan, A. Mekkaoui,

Pixel Readout Chip

R. Yarema, W. Wester, S. Zimmermann,

For BTeV

Fermilab

1TeV p

1TeV p

Luminosity=

2x1032 cm-2s-1

(<2> interactionseach 132 ns)

FPIX Roadmap

• Pixel size = 50 x 400 (matches ATLAS n+ on n test sensors)

• Target rad-hard technology = Honeywell 0.5 CMOS (SOI)(3 metal, 3.3V) (1 metal layer used for shield between sensor & R/O chip)

• FPIX0 (1997) HP 0.8 CMOS•Close to final analog front end•R/O pixel includes a peak sensor – digitized off chip•Array size = 12 x 64•Bench tests and beam tests

• FPIX1 (1998) HP 0.5 CMOS•Optimized front end•4 comparators per cell (2-bit FADC)•New fast R/O architecture, allows both self-triggered and externally-triggered operation•Array size = 18 x 160•Bench tests and beam tests

• Then (Dec, 1998), a change of plans•Try to use deep-submicron CMOS•All subsequent prototypes should be rad-hard.

FPIX2 Roadmap• 0.25 CMOS

• (5 metal [6 possible], 2.5V)

• Design for 2 vendors (“lowest common denominator” design rules):• “CERN” – Very favorable contract, but problems with US Gov. restrictions• Taiwan Semiconductor Manufacturing Corp (TSMC) – Available through MOSIS

• PreFPIX2T (1999) TSMC 0.25 CMOS•New analog front end, with new leakage current compensation strategy•8 comparators per cell (3-bit FADC); no EOC logic included•Array size = 2 x 160•Bench tests ( radiation exposure)

• PreFPIX2I (2000) “CERN” 0.25 CMOS•Same front end•Complete “core” – including new, simplified EOC & R/O (self-triggered only)•Array size = 18 x 32•Bench tests (proton exposure)

• PreFPIX2Tb (2000) TSMC 0.25 CMOS•New programming interface•Internal DAC’s – no external currents required; only external voltages are 2.5V & ground.•Array size = 18 x 64•Bench tests (proton exposure)

• FPIX2 (2001) 0.25 CMOS - Final BTeV R/O chip!!??

Total Dose Tolerance

• Threshold shifts – and hadrons.– Small as expected.

• Surface leakage currents – and hadrons.– Negligible by design (gate all around NFET’s and

guard rings).

• Bulk damage – hadrons.– Small, manageable, increase in leakage due to

parasitic device formation.

Single Event Effect Tolerance

• Catastrophic events – gate rupture, latch up.– None observed rate guaranteed to be

acceptable to BTeV.

• Soft errors – single event upset.– Small cross sections measured:

(1 – 6 x 10-16/cm2) no need for redundant logic or other design measures.

Positive charge trapped in the oxide layer effectively biases the transistors.

Gate oxide

n+ n+

Source(normally connected to gnd)

Drain

Conductive channel is induced bypositive voltage applied to the gate

Gate

p bulk

“Threshold voltage” shifts with exposure to radiationBUT, the effect gets smaller as the oxide gets thinner (with smaller feature size)… by 0.25 the threshold shifts are small enough to be “benign.”

Radiation damage to CMOS transistors

Trapped charge in the field oxide also causes leakage currentin nmos devices by inducing an n-channel in the p-bulk.

source drain

pmos leakage current does not increase (glass charges +; doesn’tinduce a p-channel).

Radiation induced leakage current

Rad-hard nfet layout (very schematic!)

Or, impossible!

Large W/L is “easy” Small W/L is hard

“gate all around” layout (guard rings to prevent current between devices (can cause latchup) not shown)

Irradiation Tests

• Irradiation (60Co at Argonne National Lab) – individual transistors and FE prototype: 58 MRad, preFPIX2T: 33 MRad.

• 200 MeV proton irradiation (Indiana University Cyclotron Facility) – preFPIX2I: 26 MRad (4.4x1014/cm2), preFPIX2Tb: 43 MRad (7.4x1014/cm2).

Front end response, before and after 33 MRad 60Co

Front end response, before and after 26 MRad 200 MeV p

DC shift believedto result fromincreased leakageto bulk.

preFPIX2I noise,beforeand after26 MRad proton irradiation

PreFPIX2Tb DAC Response

Total Dose: Effect on FPIX

• Small increase in gain = decrease in dynamic range.

• Small increase in DAC nonlinearity.• Small decrease in front end noise.• Small decrease in discriminator

threshold dispersion. Design verified to be sufficiently

radiation tolerant.

200 MeV proton irradiation tests

2.5V Power Supplies

LVDS driver board Laptop

LVDS driver board

PCI-PTA Card

GPIB 100 foot twist-n-flatto PTA card

200 MeV

Protons

Concrete walls

Devices Under Test

• SEU Test Procedure: download pattern, wait 1 minute, read back & check for errors, repeat.• Irradiation done in air at room temperature.• No low energy particle or neutron filter.• Nominal flux 2 x 1010 protons/(cm2s).• 1.5 cm beam spot diameter measured with a sensitive film (flux 90% center value).• Laser spot alignment and remote video monitoring.• Dosimetry : Faraday cup + SEM.

FF in DAC (112 in chip)

FF in SR (1152 in chip)

Due to the symmetric configuration:0 1 and 1 0 are expected to beequally likely.

Due to asymmetric configuration:1 0 SEU is expected to be two times more likely than 0 1.

Single Event UpsetExpectations

Single Event Upset Cross Sections

Time Board Fluence [cm-2]

Bit errors in SR[2x576 bits]

Bit errors in DAC [8x14 bits]

Apr.01 1 2.33E14 53=18+35 10=8+2

Aug.01 2 3.65E14 74=22+52 19=9+10Aug.01 3 3.65E14 86=27+59 19=8+11

Aug.01 1 3.65E14 80=23+57 20=8+12Aug.01 4 (450) 3.65E14 77=14+63 31=19+12

216,

21601,,

21601,

21610,

10)6.05.5(

10)2.12.4(

10)7.07.2(

10)1.00.1(

cm

cm

cm

cm

DACSEU

clockedSRSEU

SRSEU

SRSEU

216,

21601,

21610,

10)2.18.3(

10)5.06.2(

10)3.03.1(

cm

cm

cm

DACSEU

SRSEU

SRSEU

April 01April 01 +Aug 01

= transition from 0 to 1.

= transition from 1 to 0.

Estimated SEU Rate in BTeV

Ch.Had. E>10MeV

NeutronsE>14MeV

NeutronsE<14MeV

e , E>0.1MeV

Flux per plane [Hz]

1.4E8 0.15E8 0.20E8 3E7, 1.4E8

Pixel Kill SR [SEU/hr]

10 < 1 < 1.4 0

DAC [SEU/hr] 2 < 0.2 < 0.3 0

24 bit Data Output Serializer

[SEU/hr]

1 0.1 0.1 0

DACSEUSerSEU

DACSEU

SRSEU

cm

cm

,,

216,

21610,

2

10)6.05.5(

10)1.00.1(