Spectral

Monitoring/

SigInt

Radio

Prototyping

RF Test &

Measurement

1

Horizontal

Technologies

Horizontal

Technologies LabVIEWLabVIEW

RIO for RF (FPGA-based processing)RIO for RF (FPGA-based processing)

PXI Platform (Chassis, controllers, baseband modules)PXI Platform (Chassis, controllers, baseband modules)

RF hardware building blocks – synthesizers, microwave components,… RF hardware building blocks – synthesizers, microwave components,…

Communications Design

(initial prototype)

• Low Cost

• Flexible

• Portable

• Radio

(design verification)

• Calibration

• Low Phase Noise

• Precise measurement

• Real-time

2

• Radio • Real-time

• High Bandwidth

Communications Design in LabVIEW LabVIEW Modulation Toolkit

• Analog and Digital modulation formats� AM, FM, PM

� ASK, FSK, MSK, GMSK, PAM, PSK, QAM

� Custom

• Visualization� 2D and 3D Eye, Trellis, Constellation

• Modulation Analysis

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• Modulation Analysis� BER, MER, EVM, burst timing,

frequency deviation, ρ (rho)

• Impairments� Additive White Gaussian Noise (AWGN)

� DC offset, Quadrature skew, IQ gain imbalance, phase noise

• Equalization, Channel Coding, Channel Models

FPGA Processing with NI FlexRIO

• Xilinx Virtex-5 SXT-series FPGAs

4

• Xilinx Virtex-5 SXT-series FPGAs

• Direct access to FPGA GPIO

• Use with adapter module for I/O

• Peer-to-peer streaming

• 800 MB/s across PXI Express backplane

• 16 simultaneous streams

• Onboard DRAM

• 2x 256 MB banks

• 1.6 GB/s per bank

• Enhanced Synchronization

• Share PXI 10 MHz reference clock or DSTAR_A with adapter module

http://zone.ni.com/devzone/cda/tut/p/id/4799

http://sine.ni.com/nips/cds/view/p/lang/it/nid/208164

Field Programmable Gate Array (FPGA)

PROGRAMMABLE

INTERCONNECTI/O BLOCK

Source: Xilinx

5

A semi-conductor device containing many gates (logic devices). A

wiring list downloaded to the FPGA determines the gate connections

and the functionality.

5

CONFIGURABLE LOGIC BLOCK (CLB)

LabVIEW FPGA Code Abstraction

Counter Analog I/O I/O with DMA

6

LabVIEW FPGA VHDL ~4000 lines

How: From LabVIEW to Hardware

Translation Optimization Synthesis Bit Stream

VHDL Generation AnalysisLogic Reduction

Place and RouteTiming Verification

GenerationDownload / Run

7

Maths

Signal Processing

Data Manipulation and Transfer

RF and Communications

Digital Protocols

Data Acquisition

ni.com/ipnet

LabVIEW FPGA

IPNet

8

Signal Generation

Control

Sensor Simulation

Encryption

Vision

More than 200 IP cores and examples

IP Integration Node

Use Core

Generator

or Custom

VHDL

Configure IP Integration Node

and Generate Simulation ModelUse the IP Block

Using Standard

LabVIEW I/O

Interfaces

9

VHDL Interfaces

Direct Access to Preexisting Xilinx CORE

Generator IP Libraries

10

NI PXI Express System Streaming Rates

800 MB/s

Streaming to/from Streaming to/from Streaming to/from Streaming to/from

Controller MemoryController MemoryController MemoryController MemoryCan sustain 7 unidirectional streams

at 800 MB/s for a total of 5.6GB/s5.6GB/s5.6GB/s5.6GB/s

700 MB/s

Streaming to/from DiskStreaming to/from DiskStreaming to/from DiskStreaming to/from DiskCan sustain 4 streams at 700

MB/s for 2.8GB/s/direction2.8GB/s/direction2.8GB/s/direction2.8GB/s/direction

(5.6GB/s5.6GB/s5.6GB/s5.6GB/s total system)

PeerPeerPeerPeer----totototo----Peer Streaming Peer Streaming Peer Streaming Peer Streaming Can sustain 8 streams at 700

MB/s for 5.6GB/s/direction5.6GB/s/direction5.6GB/s/direction5.6GB/s/direction

(11.2GB/s11.2GB/s11.2GB/s11.2GB/s total system)

700 MB/s

Host PC

Payload

Generation

FPGA

Coding

Arbitrary

Waveform

Generater

Upconverter

RF OUTPUT

Vector Signal Generator

RF INPUTRF INPUTDecoding

Demodulation

Modulation

Payload

Analysis

An example...

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Downconverter

Digitiser

Vector Signal

Analyser

Downconverter

Digitiser

Vector Signal

Analyser

Diversity Processing

Shared Local Oscillator

PXIe-8133

Payload

Generation

PXIe-7965R

Coding

Arbitrary

Waveform

Generater

Upconverter

RF OUTPUT

PXIe-5663

RF INPUTRF INPUTDecoding

Demodulation

Modulation

Payload

Analysis

An example...

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Downconverter

Digitiser

PXIe-5673

Downconverter

Digitiser

PXIe-5673

Diversity Processing

Shared Local Oscillator

NI-Ettus Research “USRP”:

Universal Software Radio Peripheral

• Most popular R&D platform for SDR / Communications

• PC-hosted computation:

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• PC-hosted computation: USB 2.0 / Gigabit Ethernet

GNU Radiothe gnu software radio C++

Software Radio | Receiver

BUS

Sig

nal P

roce

ssin

g (P

C)

SMA

TX

?

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Sig

nal P

roce

ssin

g (P

C)

SMA

RX ?

Software Radio | Receiver

ADC

BUS

Sig

nal P

roce

ssin

g (P

C)

Mixer

)2sin()()2cos()( tftQtftI cc ππ +

I(t)

16

ADC

ADC

0o

90o

Tunable Oscillator

Amp

Sig

nal P

roce

ssin

g (P

C)

Mixer

Mixer

SMA

RX

fc Q(t)

fc = center frequency of interest

Software Radio | Receiver

ADCLPF

Switch BUS

Sig

nal P

roce

ssin

g (P

C)

Mixer

Support

multiple

antennas

Anti-

aliasing

filters

SMA

RX 1

1 Gb

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ADC

ADC

LPF

LPF

0o

90o

Tunable Oscillator

Amp

Sig

nal P

roce

ssin

g (P

C)

Mixer

Mixer

SMA

RX 2

40 MHz

LPF

100 MS/s

ADC

1 Gb

Ethernet

900 MHz

• Low pass filters chosen to be below 50MHz Nyquist criteria.

Software Radio | Receiver

ADCLPF

Switch BUS

Sig

nal P

roce

ssin

g (P

C)

Mixer

SMA

RX 1

1 Gb

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ADC

ADC

LPF

LPF

0o

90o

Tunable Oscillator

Amp

Sig

nal P

roce

ssin

g (P

C)

Mixer

Mixer

SMA

RX 2

40 MHz

LPF

100 MS/s

ADC

Data Rate Calculation: 100 Million Samples/sec x 16 bits/Sample x 2 = 3.2 Gigibits/second

BUS = 1 Gb Ethernet … down-conversion is needed to ~ 25 MS/s or less.

1 Gb

Ethernet

900 MHz

3.2 Gb/s

FPGA

Software Radio | Receiver

ADCLPF

Switch BUS

Sig

nal P

roce

ssin

g (P

C)

Mixer

SMA

RX 1

1 GbDDC: Digital

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ADC

ADC

LPF

LPF

0o

90o

Tunable Oscillator

Amp

Sig

nal P

roce

ssin

g (P

C)

Mixer

Mixer

SMA

RX 2

900 MHz40 MHz

LPF

100 MS/s

ADC

Data Rate Calculation: 100 Million Samples/sec x 16 bits/Sample x 2 = 3.2 Gigibits/second

BUS = 1 Gb Ethernet … down-conversion is needed to ~ 25 MS/s or less.

1 Gb

Ethernet

Down-converter

DDC: Digital

Down-converter

RX Control

Radio | NI USRP System Diagram

FPGA

ADC

DAC

DACLPF

LPF

LPF

0o

90o

Tunable Oscillator

Amp

Mixer

Mixer

Switch BUS

Sig

nal P

roce

ssin

g (P

C)

Digital Up-

converter

DUC: Digital

Up-converter

DDC: DigitalMixer

TX Control

SMA

RX 1

TX 1

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ADC

ADC

LPF

LPF

0o

90o

Tunable Oscillator

Amp

Sig

nal P

roce

ssin

g (P

C)

Down-converter

DDC: Digital

Down-converter

Mixer

Mixer

RX Control

SMA

RX 2

NI USRP-2920 System Diagram

PXI RF SystemNI PXIe-8133

Controller

NI PXIe-5450

RF Signal GeneratorNI PXIe-5611 RF

Upconverter

NI PXI-5652

NI PXI-5690

Gain/Attenuator

NI PXI-2598

RF Switch

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NI PXI-5652

RF Signal Generator

NI PXIe-5622

RF Signal Analyzer

NI PXIe-5601

RF Downconverter

NI PXI-5690

NI PXIe-1075

Chassis

NI USRP Tunable RF Transceiver

Front Ends� Frequency Range

50 MHz – 2.2 GHz (NI-2920)

2.4 GHz & 5.5 GHz (NI-2921)

Signal Processing

and Synthesis� NI LabVIEW to develop

and explore algorithms

� NI Modulation Toolkit and

LabVIEW add-ons to

simulate or process live

signals

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1 Gigabit Ethernet to PC� Plug-and-play capability

� Up to 25 MS/s baseband IQ

streaming

Applications

� FM Radio

� TV

� GPS

� GSM

� ZigBee

� Safety Radio

� OFDM

� Passive Radar

� Dynamic Spectrum Access

NI-USRP Driver SoftwareInitialize Configure Start Read IQ Stop Close

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NI-USRP Driver SoftwareInitialize Configure Start Read IQ Stop Close

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Teaching Lab | Packet Radio & OFDMCommunications Systems Labs

by Dr. Sachin Katti, Stanford

1 Source Coding

2 Packet Communication, Sync, and

Channel Correction

3 Modulation

Digital Communications Labs

by Dr. Robert Heath, UT Austin

1 AWGN Simulator

2.1 Modulation /Demodulation

2.2 Pulse Shaping

3 Energy Detection

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3 Modulation

4 Demodulation

5 Design Challenge:

Packet based Transceiver

3 Energy Detection

4 Equalization

5 Frame Detection

6 Intro to OFDM

7 Frequency Correction & Sync

8 OFDM Channel Coding

(FREE: ni.com/courseware)(Ships in Bundle)

Digital Communication System

Source Coding

Channel Coding

Modulation

Upconversion

Communications Channel

26

Downconversion

Dem

odulation

Channel Decoding

Source Decoding

Communications Channel

Digital Communication System

NI Modulation Toolkit

27

NI Modulation Toolkit

NI Modulation Toolkit

NI USRP

Digital Communication System

28

NI Modulation Toolkit

NI USRP

Stanford University - Networked Systems Group

Needs:

• Exposure to real-world signals

• Recruit students to RF/Communications early

• Prepare students for research

Solution:

• SDR Platform

• Lower learning curve

• Maintainable

• Affordable

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Stanford, CA

“The course evaluations for our class was fantastic.

Students rated the class 4.94/5.0, likely one of the

highest ratings among all classes in the School of

Engineering at Stanford.” Dr. Sachin Katti, ECE