raio ra8806mar 02, 2009 · (zrw) i . write/read-write . when mpu i/f is 8080 series, this pin...

RAiO RA8806

Two Layers

CharacterGraphic LCD Controller Specification

Preliminary Version 12

March 2 2009

RAiO Technology Inc copyCopyright RAiO Technology Inc 2008 2009

RAiO TECHNOLOGY INC 1183 wwwraiocomtw

Preliminary Version 12 Two Layers CharacterGraphic LCD Controller

RA8806

Update History

Version Date Description

10 March 25 2008 Preliminary Version

11 June 20 2008

1 6-4-3 Touch panel sampling time reference table 2 Add Section 6-15 Eliminating Flicker Mode 3 Update table 8-2 DC characteristic 4 Add Section 8-3 for RA8806 driver IF timing chart 5 Update font table of Appendix D and Appendix E

12 March 2 2009

1 Add the description of Japanese Kanji font version of RA8806-J2 Update Figure 6-38Figure 6-39 PWM Reference Circuits 3 Update the Section 6-10-1-3 for the usage of Chinese font and

Japanese Kanji font



RA8806

Chapter Content Page

1 General Description 6

2 Feature 6

3 Block Diagram 7

4 Pin Definition 8 4-1 MPU Interface 8 4-2 Clock Interface8 4-3 Peripheral Interface9 4-4 LCD Driver Interface10 4-5 Power 10

5 Register Description 11 5-1 Register List Table 11 5-2 Register Description 13

6 Function Description 27 6-1 MPU Interface 27

6-1-1 MPU Type 27 6-1-2 Command Write 30 6-1-3 Memory WriteRead 31 6-1-4 Status Read 31

6-2 Driver Interface32 6-2-1 Display Resolution 35 6-2-2 Display Window and Active Window 35 6-2-3 ComSeg Scan Direction 38 6-2-4 Idle Time Counter (ITCR) 38

6-3 Display Data RAM (DDRAM)40 6-3-1 Display Layer and Display Mode Selection 40 6-3-2 Access Memory Selection 40

6-4 Touch Panel 41 6-4-1 Auto Mode 43 6-4-2 Manual Mode 45

6-4-2-1 External Interrupt Mode 45 6-4-2-2 Polling Mode 48

6-4-3 Touch Panel Sampling Time Reference Table 51 6-5 Key-Scan52 6-6 Clock and Reset 59

6-6-1 OSC Circuit 59 6-6-2 External Clock 59 6-6-3 Reset 60

6-7 Power 61 6-7-1 Power Architecture 61 6-7-2 3V Application Circuit 61 6-7-3 5V Application Circuit 62



RA8806

6-7-4 Sleep Mode 63 6-8 Interrupt and Busy 64

6-8-1 Interrupt 64 6-8-2 Busy 65

6-9 PWM 68 6-10 Display Function70

6-10-1 CharacterGraphic Mode 70 6-10-1-1 Graphic Display 70 6-10-1-2 Half Size Font 71 6-10-1-3 Full Size Font 72 6-10-1-4 Bold and Inverse 75 6-10-1-5 Two Layer Display 76 6-10-1-6 Line Gap 77

6-10-2 Gray Scale Display 77 6-10-3 Font Size Adjustment and Font Write-Time 80 6-10-4 Font Vertical Display 82

6-11 User-Defined Font 84 6-11-1 Create Font in CGRAM 84 6-11-2 Create Font in DDRAM 88 6-11-3 Create Symbol 92

6-12 Scroll Function 94 6-12-1 Horizontal Scrolling 94 6-12-2 Vertical Scrolling 96

6-13 Cursor97 6-13-1 Cursor Position and Shift 97 6-13-2 Full Alignment 97 6-13-3 Cursor Blinking 100 6-13-4 Cursor Width and Height 100

6-14 Extension Mode for Display101 6-15 Eliminating Flicker Mode 104

7 Package Information 108 7-1 Bonding Pad 108 7-2 Pad XY Coordinate 109 7-3 Pin Assignment 110 7-4 Package Dimension 111 7-5 Part Number115

8 Electrical Characteristic 116 8-1 Absolute Maximum Ratings 116 8-2 DC Characteristic 117 8-3 Timing Characteristic Wavaform 118

Appendix A Application Circuit119

Appendix B Frame Rate Table120

Appendix C Font Table - ASCII123

Appendix D Font Table - GB Code131



RA8806

Appendix E Font Table - BIG-5 Code153

Appendix F Font Table - JIS Code184



RA O TECHNOLOGY INC 6184 wwwraiocomtw i

RA8806

1 General Description

RA8806 is a LCD controller for Dot-Matrix type STN-LCD which supports both character and graphic mode display The RA8806 has built-in two Display Data RAM(DDRAM) for two layers display and has an embedded font ROM which is capable of displaying the full-size(16x16 pixels) traditional Chinese font(BIG5 13973 characters) or simplified Chinese font(GB 9216 characters) RA8806-J is one controller in this series that consisting of Kanji and Hiragana according to the JIS standard Level-1 amp 2 Kanji font (6355 characters) RA8806 also contains 4x256 embedded half-size (8x16 pixels) characters that can display ISO8859-1 ~ 4(or called Latin-1 ~ 4) alphabets using at most of English speaking and Europe countries RA8806 supports 80806800 MPU protocol interface which is capable of switching the interface with 4-bits or 8-bits data bus For LCD driver interface it can be set to 4-bits or 8-bits data bus The maximum resolution of RA8806 is 320x240 pixels in normal mode and 640x240 or 320x480 pixels in extension mode By using the font rotation mode which can implement the ldquoverticalrdquo font display The embedded intelligence touch panel controller provides the 4-wires resistance-type Touch Panel interface The PWM output provides an easy contrast or back-light control method for LCD panel RA8806 also provides a 4x8(32 keys) or 8x8(64 keys) powerful and smart Key-Scan interface includes long-key function The flexible interrupt and polling mechanism can make it easy to control touch panel key-scan and power mode functions Also it can greatly reduce the MPU loading The embedded 512Byte character generation RAM (CGRAM) allows user to build maximum 16 full-size or 32 half-size fonts Even with the single layer display the other unused layer can be used as CGRAM too In this setting the amazing 300 full-size and 600 half-size user created fonts or symbols are supported In addition RA8806 supports 4-gray-scale display in FRC mode The bit-arrangement is compatible for most gray level picture and easy to program RA8806 also includes many useful functions like area scroll font inverse font bold font enlargement memory clear function and so on An innovative mechanism of ldquono-flickerrdquo mode is provided in RA8806 Itrsquos effective for removing the ldquoflickerrdquo in frequently display data ReadWrite User can easily improve the display quality by RA8806

RA8806 is a powerful and flexible LCD controller It provides the total solution for the middle-size mono LCD controller User can save large amount of time for system development and the cost of hardware system

2 Feature

Support text and graphics mode Maximum resolution 320x240 with 2-Layers overlay display (AND OR NOR and XOR) Extension Mode 640x240 or 320x480 with single layer Support 48-bits of 68008080 MPU interface and 48-bits driver interface Built-In smart 8x8 or 4x8 key-scan circuit with programmable long key function Support horizontal and vertical area scrolling Built-In GBBIG5 and ASCII font ROM Support 90deg 180deg 270deg font and display rotation Support font enlargement(x1 ~ x4 in Horizontal and Vertical direction) Built-In 512Byte CGRAM for user-created font

_ Half-size 8x16 _ Full-size 16x16

Un-used DDRAM could be used as a CGRAM of 300 full-size or 600 half-size characters Flexible interruptpolling mechanism for touch panel key-scan and power mode programming Support font alignment function Support 4-gray-scale display (FRC mode) Support bold font and row-row interval setting Built-In smart resister type touch panel controller Built-In PWM for contrast or back-light control Power mode to reduce power consumption Clock source 4M ~ 12MHz crystal or external clock Built-In a 5V-to-3V DCDC converter Power supply 24V ~ 55V Package Die LQFP-100 TQFP-80 Pins


RA8806

3 Block Diagram

Figure 3-1 is the internal block diagram of RA8806 The RA8806 consists of two Display Data RAM Font ROM Register Block Analog to Digital Converter (ADC) Pulse Width Modulation (PWM) LCD driver interface and microprocessor interface Figure 3-2 is the system block for application of RA8806

MCU Interface

Oscillator

Registers

Touch PanelController

PWMController

Display Timing

Generator

LPFRYDZDOFFXCKLD[70]

X1X2Y1Y2

ZCS1

CS2

ZWR

ZRD RS

INT

BU

SYD

ATA

[70

]ZR

ST MI

DW DB

CLK

_OU

T

512KByteFont ROM

512ByteCGRAM

Smart Key-ScanController

KIN[70]KOUT[70]

PWM_OUT

XG

XD

System Configure

Display Data RAM(96KByte x 2)

DDRAM1DDRAM2

Figure 3-1 RA8806 Block Diagram

RA8806

MPU

HW Set Up

LCD Driver

Booster(Contrast Adj)

Touch Panel

LCD Panel

8x8 Key Pad

Xrsquotal

LCD Driver

Figure 3-2 RA8806 System Block Diagram



RA8806

4 Pin Definition

4-1 MPU Interface

Pin Name IO Description

DATA[70] IO

Data Bus These are data bus for data transfer between MPU and RA8806 The high nibble DATA[74] is output and should keep floating when 4-bits data bus mode is used

ZRD (EN)

I

EnableRead Enable When MPU interface(IF) is 8080 series this pin (ZRD) is used as data read active low When MPU IF is 6800 series this pin (EN) is used as Enable active high

ZWR (ZRW)

I

WriteRead-Write When MPU IF is 8080 series this pin (ZWR) is used as data write active low When MPU IF is 6800 series this pin(ZRW) is used as data readwrite control Active high for read and active low for write

RS I

Command Data Select Input The pin is used to select commanddata cycle RS = 0 data ReadWrite cycle is selected RS = 1 status readcommand write cycle is selected In 8080 interface usually it connects to ldquoA0rdquo address pin

RS ZWR Access Cycle 0 0 Data Write 0 1 Data Read 1 0 CMD Write 1 1 Status Read

ZCS1 CS2

I Chip Select Input The MPU interface of RA8806 is active only when ZCS1 is low and CS2 is high

INT O Interrupt Signal Output The interrupt output for MPU to indicate the status of RA8806 It could be setup active high or low

BUSY O

Busy Signal Output This is a busy output to indicate the RA8806 is in busy state It could be set to active high or active low by register The RA8806 canrsquot access MPU cycle when BUSY pin is active It could be used for MPU to poll busy status by connecting it to IO port

4-2 Clock Interface


XG I Xrsquotal Input In internal clock mode this pin connects to external Xrsquotal(4M ~ 12MHz) In external clock mode it connects to external clock

XD O Xrsquotal Output This pin connects to external Xrsquotal(4M ~ 12MHz) In external clock mode it keeps floating



RA8806

4-3 Peripheral Interface


ZRST I

Reset Signal Input This active-low input performs a hardware reset on the RA8806 It is a Schmitt-trigger input with pull-up resistor for enhanced noise immunity however care should be taken to ensure that it is not triggered if the supply voltage is lowered

X1 I Touch Panel Input The left analog input pin(XL) of 4-wires touch panel

X2 I Touch Panel Input The right analog input pin(XR) of 4-wires touch panel

Y1 I

Touch Panel Input The top analog input pin(YU) of 4-wires touch panel If user want to use Touch Panel function please add a 39K~51Kohm external pull-up resistor on this pin

Y2 I Touch Panel Input The bottom analog input pin(YD) of 4-wires touch panel

PWM_OUT O PWM Output Signal This output signal is used to control back-light module or booster circuit

KIN[70] I Key Pad Input These pins are keypad inputs with pull-up resistors For un-used input please keep floating

KOUT[70] O Key Pad Output These pins are keypad outputs For un-used pin please keep floating

CLK_OUT O

Clock Output This is a multi-function output pin that depending on the value of register REG[01h] Bit-6 REG[01h] Bit-6 = 0 The pin is the output of internal system clock REG[01h] Bit-6 = 1 The pin indicate the SLEEP state of Status Register(0 Normal Mode 1 Sleep Mode)

DW I

LCD Driver Data Bus Select This pin is used to select data bus of LCD driver is 8-bits or 4-bits 0 LCD driver data bus is 4-bits LD[30] is used 1 LCD driver data bus is 8-bits LD[70] is used When 4-bits data bus is used LD[74] need to keep floating RA8806T1N does not support this function its LCD driver data bus is fix 4-bits

MI I

MPU Type Select This pin is used to select MPU interface protocol 0 Intel 8080 series MPU interface 1 Motorola 6800 series MPU interface

DB I

80806800 MPU Data Bus Select This pin is used to select data bus width 0 4-bits MPU IF DATA[30] is used 1 8-bits MPU IF DATA[70] is used When 4-bits data bus is used DATA[74] need to keep floating




RA8806

4-4 LCD Driver Interface


YD O Start Signal of LCD Per Frame YD is the reset pulse for the COM driver itrsquos active during the last COM period of each frame and latched by LP signal

FR O LCD AC Wave Output This signal controls the Level Shift of LCD driver Normally it works as VDDGND interlacing to prevent the liquid cystal polarization

LP O LCD Common Latch LP is the latch pulse for the shift register of SEG driver to SEG output It is also used as COM driver shift clock

XCK O

LCD Clock XCK is the latch pulse of the LCD driver data(LD[70]) for SEG driver The falling edge of XCK will latch the LD[70] (or LD[30] for 4-bits driver) to the shift register

ZDOFF O

LCD Display Off This signal is used to control the LCD Display On or Off 0 Display off 1 Display on

LD[70] O

LCD Driver Data Bus When 8-bits LCD driver IC is used LD[70] are connected to LCD driver data bus When 4-bits driver is used LD[30] are connected to LCD driver data bus and LD[74] keep floating RA8806T1N supports LD[30] only

4-5 Power


VDDH P 5V Power This is the source power for DC to DC converter In 5V power application it is connected to 5V If 3V application is used then keep this pin floating

VDD P

3V Power If the pin VDDH connects to 5V power then the pin will driving 3V power and must add an external 1uF capacitor to GND If 3V application is used then connecting this pin to external 3V power directly

VDDP P Power for IO Buffer VDDP can be 3V or 5V

AVDD P Analog Power for ADC Touch Panel Controller AVDD can be 3V or 5V

GND GNDP

P Ground

AGND P Analog Ground for ADC Touch Panel Controller Connect this pin to 0V earth ground(GND)

TESTMD I Test Mode This pin is used for test only It has internal pull-low and need to keep floating

TESTI I Test Pin The pin is used for test function It has internal pull-low and need to keep floating


RA8806

5 Register Description

5-1 Register List Table

Table 5-1 Cycle List Table

CYC_NAME RS ZWR Description CMD 1 0 Command write cycle for writting register number(REG)

STATUS 1 1 Status read cycle using to check Interrupt or Sleep status DATW 0 0 Data write cycle using to write register data or memory data DATR 0 1 Data read cycle using to read register data or memory data

Table 5-2 Register Table

REG Name D7 D6 D5 D4 D3 D2 D1 D0 Default

-- STATUS MBUSY SBUSY SLEEP WAKE_STS KS_STS TP_STS --

00h WLCR PWR LINEAR SRST -- TEXT_MD ZDOFF GBLK GINV 00h

01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV

INT_LEV XCK_SEL1 XCK_SEL0 SDIR CDIR 04h

03h ADSR SCR_PEND -- -- -- BIT_INV SCR_DIR SCR_HV SCR_EN 00h

0Fh INTR -- WAKI_EN KEYI_EN TPI_EN TP_ACT WAK_STS KEY_STS TP_STS 00h

10h WCCR CUR_INC FULL_OFS BIT_REV BOLD T90DEG CUR_EN CUR_BLK --- 00h

11h CHWI CURH3 CURH2 CURH1 CURH0 ROWH3 ROWH 2 ROWH 1 ROWH 0 00h

12h MAMR CUR_HV DISPMD2 DISPMD1 DISPMD0 L_MIX1 L_MIX 0 MW_MD1 MW_MD0 11h

20h AWRR -- -- AWR5 AWR4 AWR3 AWR2 AWR1 AWR0 27h

21h DWWR -- -- DWW5 DWW 4 DWW 3 DWW 2 DWW 1 DWW 0 27h

30h AWBR AWB7 AWB6 AWB5 AWB4 AWB3 AWB2 AWB1 AWB0 EFh

31h DWHR DWH7 DWH6 DWH5 DWH4 DWH3 DWH2 DWH1 DWH0 EFh

40h AWLR -- -- AWL5 AWL4 AWL3 AWL2 AWL1 AWL0 00h

50h AWTR AWT7 AWT6 AWT5 AWT4 AWT3 AWT2 AWT1 AWT0 00h

60h CURX -- -- CURX5 CURX4 CURX3 CURX2 CURX1 CURX0 00h

61h BGSG -- -- BGSG5 BGSG4 BGSG3 BGSG2 BGSG1 BGSG0 00h

62h EDSG EDSG7 EDSG6 EDSG5 EDSG4 EDSG3 EDSG2 EDSG1 EDSG0 00h

70h CURY CURY7 CURY6 CURY5 CURY4 CURY3 CURY2 CURY1 CURY0 00h

71h BGCM BGCM7 BGCM6 BGCM5 BGCM4 BGCM3 BGCM2 BGCM1 BGCM0 00h

72h EDCM EDCM7 EDCM6 EDCM5 EDCM4 EDCM3 EDCM2 EDCM1 EDCM0 00h

80h BTMR BLKT7 BLKT6 BLKT5 BLKT4 BLKT3 BLKT2 BLKT1 BLKT0 00h

90h ITCR ITC7 ITC6 ITC5 ITC4 ITC3 ITC2 ITC1 ITC0 00h

A0h KSCR1 KEY_EN KEY4X8 KSAMP1 KSAMP0 LKEY_EN KF2 KF1 KF0 00h

A1h KSCR2 KWAK_EN -- -- -- LKEY_T1 LKEY_T0 KEYNO1 KEYNO0 00h

A2h KSDR0 KSD07 KSD06 KSD05 KSD04 KSD03 KSD02 KSD01 KSD00 00h



B0h MWCR MWD7 MWD6 MWD5 MWD4 MWD3 MWD2 MWD1 MWD0 --

B1h MRCR MRD7 MRD6 MRD5 MRD4 MRD3 MRD2 MRD1 MRD0 --



RA8806

(Continued)


C0h TPCR1 TP_EN TP_SMP2 TP_SMP1 TP_SMP0 TPWAK _EN

ACLK2 ACLK1 ACLK0 00h

C1h TPXR TPX9 TPX8 TPX7 TPX6 TPX5 TPX4 TPX3 TPX2 00h C2h TPYR TPY9 TPY8 TPY7 TPY6 TPY5 TPY4 TPY3 TPY2 00h C3h TPZR TPX1 TPX0 -- -- TPY1 TPY0 -- -- 00h C4h TPCR2 MTP_MD -- -- -- -- -- MTP_PH1 MTP_PH2 00h D0h PCR PWM_EN PWM_DIS_

LEV -- -- PCLK_R3 PCLK_R2 PCLK_R1 PCLK_R0 00h

D1h PDCR PDUTY7 PDUTY6 PDUTY5 PDUTY4 PDUTY3 PDUTY2 PDUTY1 PDUTY0 00h E0h PNTR PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0 00h F0h FNCR ISO8859_E

N -- -- -- MCLR ASC ASC_SEL1 ASC_SEL0 00h

F1h FVHT FH1 FH0 FV1 FV0 -- -- -- -- 00h



RA8806

5-2 Register Description

STATUS Register (RS = 1 ZWR = 1)

Bit Description Access

7

Memory Write Busy Flag 0 Not busy 1 Busy when font write or memory clear cycle is running the busy

flag = 1 R

6

SCAN_BUSY 0 Not busy 1 When driver scan logic is not idle(ie XCK is active) SCAN_BUSY

= 1

R

5 SLEEP 0 Normal mode 1 Sleep mode

R

4-3 NA R

2 Wakeup Status bit (The same with REG[0Fh] Bit-2) R

1 KS Status bit (The same with REG[0Fh] Bit-1) R

0 TP Status bit (The same with REG[0Fh] Bit-0) R

REG [00h] Whole Chip LCD Controller Register (WLCR)

Bit Description Default Access

7

Power Mode 0 Normal Mode All of the functions of RA8806 are available in this

mode 1 Sleep Mode When RA8806 is in Sleep mode all of functions enter

off mode except the wake-up trigger block If wake-up event occurred RA8806 would wake-up and return to Normal mode

0 RW

6

Linear Decode mode This bit is used to define the Font ROM address mapping rule The standard product is set to 0 And 1 for special application that when user a want to create a new Mask Code 0 BIG5GB ROM mapping rule 1 User-defined ROM mapping rule

0 RW

5

Software Reset 0 Normal Operation 1 Reset all registers except the contents of Display Data RAM (Only

work at Normal mode) When this bit set to ldquo1rdquo the next MPU cycle for RA8806 have to wait 3 clocks at least

0 RW

4 Reserved 0 R

3

Text Mode Selection 0 Graphical Mode The written data will be treated as a bit-map

pattern 1 Text Mode The written data will be treated as an ASCII BIG5 or

GB code

0 RW



RA8806

2

Set Display OnOff Selection The bit is used to control LCD Driver Interface signal ndash ldquoDISP_OFFrdquo 0 DISP_OFF pin output low(Display Off) 1 DISP_OFF pin output high(Display On)

0 RW

1 Blink Mode Selection 0 Normal Display 1 Blink Full Screen The blink time is set by register BTMR

0 RW

0 Inverse Mode Selection 0 Normal Display 1 Inverse Full Screen It will cause the display inversed

0 RW

REG [01h] Misc Register (MISC)


7 Eliminating Flicker 1 Eliminating flicker mode scan will auto-pending when busy 0 Normal mode

0 RW

6

Clock Output (Pin CLK_OUT) Control 1 The pin ldquoCLK_OUTrdquo indicates the SLEEP state of Status Register(0

Normal Mode 1 Sleep Mode) 0 The pin ldquoCLK_OUTrdquo is the output of Internal system clock

0 RW

5 Busy Polarity (for ldquoBUSYrdquo pin) 1 Set Active High 0 Set Active Low

0 RW

4 Interrupt Polarity (for ldquoINTrdquo pin) 1 Set Active High 0 Set Active Low

0 RW

3-2

Driver Clock Selection These two bits are used to select the clock frequency of XCK

0 0 XCK = CLK8 0 1 XCK = CLK4 (Default) 1 0 XCK = CLK2 1 1 XCK = CLK The ldquoCLKrdquo means system clock

01 RW

1 SEG Scan Direction(SDIR) 0 SEG order is 0 ~ 319 1 SEG order is 319 ~ 0

0 RW

0 COM Scan Direction(CDIR) 0 COM order 0 ~ 239 1 COM order 239 ~ 0

0 RW

REG [03h] Advance Display Setup Register (ADSR)

Bit Description Default Access7 Scroll Function Pending

1 Scroll function pending 0 Scroll function keep active

Note When SCR_HV(Bit-1) and SCR_EN(Bit-0) are changed the function does not support

0 RW

6-4 Reserved 000 R



RA8806

3

BIT_ORDER(Set driver data output bit order) 1 Inverse driver output data order(Bit-7 to Bit-0 Bit-6 to Bit-1 and so on) 0 Normal Mode

0 RW

2

SCR_DIR(Scroll Direction) When SCR_HV = 0(Horizontal Scroll) 0 Left Right 1 Right Left When SCR_HV = 1(Vertical Scroll) 0 Top Bottom 1 Bottom Top

0 RW

1 SCR_HV(Scroll HorizontalVertical) 0 Segment Scrolling(Horizontal) 1 Common Scrolling(Vertical)

0 RW

0 SCR_EN(Scroll Enable) 1 Scroll function enable 0 Scroll function disable

0 RW

REG [0Fh] Interrupt Setup and Status Register (INTR)

Bit Description Default Access7 Reserved 0 R

6 Wakeup Interrupt Mask 1 Enable wake-up Interrupt 0 Disable wake-up Interrupt

0 RW

5 Key-Scan Interrupt Mask 1 Enable Key-Scan Interrupt 0 Disable Key-Scan Interrupt

0 RW

4 Touch Panel Interrupt Mask 1 Generate interrupt output if touch panel was detected 0 Donrsquot generate interrupt output if touch panel was detected

0 RW

3 Touch Panel Event(Only activate in TP Manual mode) 1 Touch panel is touched 0 Touch panel is not touched

0 R

2

Wakeup Interrupt Status bit 1 Interrupt that indicate wake-up event happen from Sleep mode 0 No wake-up interrupt happen User must write ldquo0rdquo to clear the Status bit

0 RW

1

Key-Scan Interrupt Status bit 1 Key-Scan Detects Key Input 0 Key-Scan doesnrsquot Detect Key Input User must write ldquo0rdquo to clear the Status bit

0 RW

0

Touch Panel Detect Status bit 1 Touch Panel Touched 0 Touch Panel Untouched User must write ldquo0rdquo to clear the Status bit

0 RW



RA8806

REG [10h] Whole Chip Cursor Control Register (WCCR)


7

CUR_INC (Auto Increase Cursor Position in ReadingWriting DDRAM Operation) 1 Disable 0 Enable(Auto Increase)

0 RW

6

FULL_OFS (Full-size and Half-size Character Alignment) 1 Enable in Full-size and Half-size character mixed mode Chinese

always start at full-size alignment 0 Disable

0 RW

5

Reversed Data Write mode 0 Store Current Data to DDRAM Directly 1 Store Current Data to DDRAM Inversely(ie 01101101

10010010)

0 RW

4 Bold Font (Character Mode Only) 1 Bold Font 0 Normal Font

0 RW

3 Font Rotate mode(T90DEG) 1 Font rotates 90 degree (See Section 6-10-4 for detail) 0 Normal font

0 RW

2 Cursor Display 1 Set Cursor Display On 0 Set Cursor Display Off

0 RW

1 Cursor Blinking 1 Blink Cursor The blink time is determined by register BTMR 0 Normal

0 RW

0 Reserved 0 R

REG [11h] Cursor Height and Word Interval Register (CHWI)


7-4

Set Cursor Height 0000 b Height = 1 pixel 0001 b Height = 2 pixels 0010 b Height = 3 pixels

1111 b Height = 16 pixels

Note In normal font the cursor width fixed to one byte(8 pixels) And cursorrsquos height is from 1~16pixels that depends on Bit[74] In vertical font the cursor height fixed to 16 pixels and width is from 1~8 pixels that depends on Bit[64]

0000 RW

3-0

Set Line Gap 0000 b Gap = 1 pixel 0001 b Gap = 2 pixels 0010 b Gap = 3 pixels

1111 b Gap = 16 pixels

0000 RW



RA8806

REG [12h] Memory Access Mode Register (MAMR)


7

Cursor Auto Shifting Direction 0 Cursor moves horizontally (left to right) first then vertically (top to

down) 1 Cursor moves vertically first then horizontally

Note In graphic mode the cursor moving is treated as unit of bytes in horizontal direction At vertical direction itrsquos treated as unit of bit At text mode the bit is ignored and the cursor moving is always in horizontal direction

0 RW

6-4

Display Layer and Display Mode Selection 0 0 0 Gray Mode In this mode each pixel consists with 2 continuous

bits in memory data With the FRC methodology 4-level-gray mode is implemented The bit mapping is list as below

bit1 bit0 Gray --------------------------------------------------- 0 0 Level1 (Lightest) 0 1 Level2 1 0 Level3 1 1 Level4 (Darkest)

Note Gray mode doesnrsquot support text-mode input

0 0 1 Show DDRAM1 data on screen 0 1 0 Show DRRAM2 data on screen 0 1 1 Show Two Layer Mode The display rule depends on Bit-3 and

Bit-2 as following 1 0 X NA 1 1 0 Extension Mode (1) the panel will show both DDRAM1 and

DDRAM2 data on the screen The RA8806 is available for 640x240 pixels panel

1 1 1 Extension Mode (2) the panel will show both DDRAM1 and DDRAM2 on the screen The RA8806 is available for 320x480 pixels panel

001 RW

3-2

Two Layer Mode Selection Combine the data of DDRAM1 and DDRAM2 on the screen when Bit[64] is set as ldquo011rdquo

0 0 DDRAM1 ldquoORrdquo DDRAM2 0 1 DDRAM1 ldquoXORrdquo DDRAM2 1 0 DDRAM1 ldquoNORrdquo DDRAM2 1 1 DDRAM1 ldquoANDrdquo DDRAM2

00 RW

1-0

MPU ReadWrite Layer Selection 0 0 Access CGRAM(512Byte) 0 1 Access DDRAM1 1 0 Access DDRAM2 1 1 Access both DDRAM1 and DDRAM2 concurrently

01 RW



RA8806

REG [20h] Active Window Right Register (AWRR)

Bit Description Default Access7-6 Reserved 00 R

5-0 Active Window Right Position Segment-Right

Note AWRR must be equal or larger then AWLR and less or equal then the value 27h (40 in decimal)

27h RW

Note REG[20h 30h 40h and 50h] are used to dominate an active window for linerow changing when writing data Users can use these four registers to set the leftrighttopbottom boundary of active window When data goes beyond the right boundary of it the cursor will automatically change the next line to write data It will move to the left boundary of new line in active window When the data comes to the right-bottom corner the next write will cause the cursor to move to the left-top corner

REG [21h] Display Window Width Register (DWWR)


5-0

Set Display Window Width Position Segment-Width

Segment-Right = (Segment Number 8) ndash 1

If LCD panel resolution is 320x240 the value of the register is

( 320 8 ) - 1 = 39 = 27h

27h RW

Note REG[21h 31h] are used to set Display Window Resolution Users can set the viewing scope of Display Data RAM Column width (DWWR) of RA8806 can be set between 0h ~ 27h and Row height (DWHR) can be set between 0h ~ EFh

REG [30h] Active Window Bottom Register (AWBR)


7-0 Active Window Bottom Position Common-Bottom Note AWBR must be equal or larger then AWTR and less or equal then the value EFh(239 in decimal)

EFh RW

REG [31h] Display Window Height Register (DWHR)


7-0

Display Window Height Position Common- Height

Common_ Height = LCD Common Number ndash1


240 ndash 1 = 239 = EFh

EFh RW



RA8806

REG [40h] Active Window Left Register (AWLR)


5-0 Active Window Left Position Segment-Left Note AWLR must be equal or less then AWRR and less then the value 27h(39 in decimal)

00h RW

REG [50h] Active Window Top Register (AWTR)


7-0 Active Window Top Position Common-Top Note AWTR must be equal or less then AWBR and less then the value EFh (239 in decimal)

00h RW

REG [60h] Cursor Position X Register (CURX)


5-0

Cursor Position of Segment RAM0 Address[40] Define the cursor address of segment a value from 0h ~ 27h(0 ~ 40 in decimal) When CGRAM write mode is selected (REG[12h] Bit[10] = 00b) the Bit[40] is the address for writing bit-map data When create a full-size font normally set to 0 When create an odd half-size font normally set to 0 and set 10h for even font

00h RW

REG [61h] Begin Segment Position Register of Scrolling (BGSG)


5-0

Segment Start Position of Scrolling Mode

REG[61h] defines the start position (left boundary) of scroll window it must be a value that less or equal to the REG[62h] which defines the end position(right boundary) of scroll window Also it must be less then the value of 27h (40 in decimal) for the Display Data RAM limit

00h RW

Note REG[61h 62h 71h 72h] dominate a named scroll window for scroll function They must be set before the scroll function is enable

REG [62h] End Segment Position Register of Scrolling (EDSG)


5-0

Segment End Position of Scrolling Mode

REG[62h] defines the end position(right boundary) of scroll window it must be a value that larger or equal to the REG[61h] which defines the end position(left boundary) of scroll window Also it must be less or equal then the value of 27h(40 in decimal) for the Display Data RAM limit

00h RW



RA8806

REG [70h] Cursor Position Y Register (CURY)


7-0

Cursor Position of Common RAM0 Address[85] Define the cursor address of common a value from 0h ~ EFh(0 ~ 239 in decimal) When CGRAM write mode is selected (REG[12h] Bit[10] = 00b) the Bit[30] is indicate which font will be created And Bit[74] are not available

00h RW

REG [71h] Scrolling Action Range Begin Common Register (BGCM)


7-0

Common Start Position of Scrolling Mode REG[71h] defines the begin position(top boundary) of scroll window it must be a value that less or equal to the REG[72h] which defines the end position(bottom boundary) of scroll window Also it must be less then the value of EFh (239 in decimal) for the Display Data RAM limit

00h RW

REG [72h] Scrolling Action Range END Common Register (EDCM)


7-0

Common Ending Position of Scrolling Mode REG[72h] defines the end position(bottom boundary) of scroll window it must be a value that larger or equal to the REG[71h] which defines the end position(top boundary) of scroll window Also it must be less or equal then the value of EFh (239 in decimal) for the Display Data RAM limit

00h RW

REG [80h] Blink Time Register (BTMR)


7-0

Cursor Blink Time and Scroll Time

Blinking Time = Bit[70] x (Frame width)

Frame width = 1Frame Rate

The Frame Rate is depends on the DWWR and DWHR and ITCR setting

00h RW

Notes 1 The Setting also determines the scroll moving speed 2 The Frame width is the time that the controller scan whole panel it depends on the system clock

frequency setting of display window driver interface (4-bits8-bits) Idle time (ITCR) and dual mode or gray scale mode etc



RA8806

REG [90h] Idle Time Counter Register (ITCR)


7-0

Idle Time Setting in count of system clock The value can determine the scan time of each COM of the LCD

COM_PRD = ( COM_SCAN + ITCR) x XCK_PRD

In which

COM_SCAN = (SEG_NOLD_WIDTH) x (1 + EXT_MD)

XCK_PRD = 1 XCK

COM_PRD The finally scan period for each COM(Unit ns) COM_SCAN The really scan time for each COM XCK_PRD One cycle time of XCK XCK is depends on the system

clock(CLK) and REG[01h] Bit[32] If system clock is 8MHz REG[01h] Bit[32] = 10b then XCK_PRD = 250ns

SEG_NO Segment number ie 240x160 panel SEG_NO = 240 EXT_MD In extension mode1 or 2(REG[12h] Bit[64] = 111b or 110b)

the EXT_MD = 1 otherwise EXT_MD = 0 LD_WIDTH Driver data width If LCD driver data bus is 4-bits then

LD_WIDTH = 4 If LCD driver data bus is 8-bits then LD_WIDTH = 8 Please refer pin ldquoDWrdquo description of Section 4-3

00h RW

REG [A0h] Key-Scan Control Register 1 (KSCR1)


7 Key-Scan Enable Bit 1 Enable 0 Disable

0 RW

6 Key-Scan Matrix Selection 1 4x8 Matrix(KOUT[30] is used KOUT[74] please keep floating) 0 8x8 Matrix(KOUT[70] is used)

0 RW

5-4

Key-Scan Data Sampling Times De-bounce times of scan frequency 0 0 4 0 1 8 1 0 16 1 1 32

00 RW

3 LNGKEY_EN Long Time Key Function Enable LNGKEY_EN = 0 Long key function is disable LNGKEY_EN = 1 Long key function is enable

0 RW



RA8806

2-0

KF2-0 Key-Scan frequency If system clock is 10MHz then the related Key-Scan timing are as following

KF2 KF1 KF0 Key-Scan

Pulse Width(KOUT period)

Key-Scan Cycle (4x8)


0 0 0 16micros 64micros 128micros 0 0 1 32micros 128micros 256micros 0 1 0 64micros 256micros 512micros 0 1 1 128micros 512micros 1024ms 1 0 0 256micros 1024ms 2048ms 1 0 1 512micros 2048ms 4096ms 1 1 0 1024ms 4096ms 8192ms 1 1 1 2048ms 8192ms 16384ms

000 RW

REG [A1h] Key-Scan Controller Register 2(KSCR2)


7 Key-Scan Wakeup Function Enable Bit 0 Key-Scan Wakeup function is disable 1 KEY-SCAN Wakeup function is enable

0 RW

6-4 Reserved 000 R

3-2

Long Key Timing Adjustment 00 About 0625sec(for 8MHz Clock source) 01 About 125sec(for 8MHz Clock source) 10 About 1875 sec(for 8MHz Clock source) 11 About 25 sec(for 8MHz Clock source)

00 RW

1-0

Numbers of Key Hit 00 No key is pressed 01 One key is pressed read REG[A2h] for the key number 10 Two key is pressed read REG[A2h ~ A3h] for the key number 11 Three key is pressed read REG[A2h ~ A4h] for the key number

00 R

REG [A2h ~ A4h] Key-Scan Data Register (KSDR0 ~ 2)


7-0 Key Strobe Data The corresponding key number that is pressed Please reference Section 6-5 Key-Scanrdquo

00h R

REG [B0h] Memory Write Command Register (MWCR)


7-0 Memory data write command from the cursor position

Note Write memory data user must write the MWCR command first then write DATA cycle

NA RW

REG [B1h] Memory Read Command Register (MRCR)



RA8806


7-0

Memory data read command from the cursor position

Note Memory read cycle in text mode the cursor move in same behavior like graphic mode B1h will perform a pre-read function So the cursor position will increase after the MRCR command is write

NA RW

REG [C0h] Touch Panel Control Register 1 (TPCR1)


7 Touch Panel Enable Bit 1 Enable 0 Disable

0 RW

6-4

TP Sample Time Adjusting 000 Wait 50micros for ADC data ready 001 Wait 100micros for ADC data ready 010 Wait 200micros for ADC data ready 011 Wait 400micros for ADC data ready 100 Wait 800micros for ADC data ready 101 Wait 16ms for ADC data ready 110 Wait 32ms for ADC data ready 111 Wait 64ms for ADC data ready Note When touch panel detects the Touch event to avoid the signal instability the sampled time is delayed to wait the signal stable The TP Sample Time Adjusting and ADC Clock Convert Speed relation just refer to Section 6-4-3

000 RW

3

Touch Panel Wake-up Enable 1 Touch panel can wake-up the Sleep mode(At the condition that

ADC is enabled) 0 Disable the touch panel wake-up function

0 RW

2-0

ADC Clock Convert Speed 0 0 0 CLK 4 0 0 1 CLK 8 0 1 0 CLK 16 0 1 1 CLK 32 1 0 0 CLK 64 1 0 1 CLK 128 1 1 0 CLK 256 1 1 1 CLK 512 The ldquoCLKrdquo means system clock

000 RW

REG [C1h] Touch Panel X High Byte Data Register (TPXR)

Bit Description Default Access7-0 Touch Panel X Data Bit[92](Segment) 00h R

REG [C2h] Touch Panel Y High Byte Data Register (TPYR)

Bit Description Default Access7-0 Touch Panel Y Data Bit[92] (Common) 00h R



RA8806

REG [C3h] Touch Panel SegmentCommon Low Byte Data Register (TPZR)

Bit Description Default Access7-4 Reserved 0000 R 3-2 Touch Panel Y Data Bit[10] (Common) 00 R 1-0 Touch Panel X Data Bit[10] (Segment) 00 R



7 TP Manual Mode Enable 1 Using the manual mode 0 Auto mode

0 RW

6-2 Reserved 00h R

1-0

Mode selection for TP Manual Mode 00 IDLE mode ADC idles 01 Wait for TP event touch panel event could cause the interrupt or

be read from REG[0Fh] B3 10 Latch X data in the phase X Data can be latched in REG[C1h]

and REG[C3h] 11 Latch Y data in the phase Y Data can be latched in REG[C2h]

and REG[C3h]

00 RW

REG [D0h] PWM Control Register (PCR)


7 PWM enable 1 Enable 0 Disable PWM_OUT level depends on the REG[D0h] Bit-6

0 RW

6 PWM Disable Level 0 PWM_OUT is Normal L when PWM disable or Sleep mode 1 PWM_OUT is Normal H when PWM disable or Sleep mode

0 RW

5-4 Reserved 00 R

3-0

PWM Clock Source Divide Ratio 0000 b CLK 1 0001 b CLK 2 0010 b CLK 4 0011 b CLK 8

1111 b CLK 32768

The ldquoCLKrdquo means system clock For example CLK is 8MHz

0000 b PWM clock source = 8MHz 0001 b PWM clock source = 4MHz

1111 b PWM clock source = 244Hz

0000 RW



RA8806

REG [D1h] PWM Duty Cycle Register (PDCR)


7-0

PWM Cycle Duty Selection Bit 00h 1 256 01h 2 256 High period 02h 3 256 High period FFh 256 256 High period

00h RW

REG [E0h] Pattern Data Register (PNTR)


7-0

Data Written to DDRAM(Display Data RAM) The pattern that will be filled to active window in memory clear function When REG[F0h] Bit-3 is lsquo1rsquo the data in the REG[E0h] will be filled to the whole active window

00h RW

REG [F0h] Font Control Register (FNCR)


7

ISO8859 Mode 0 Disable The contents of ASCII block 1 ~ 4 are show as Table C-1~

Table C-4 of Appendix B 1 Enable The ASCII block 1 ~ 4 indicate the ISO8859-1 ~ 4

standard and show as Table C-5 ~ Table C-8 of Appendix C

0 RW

6-4 Reserved 000 R

3

Memory Clear Function Write Function 0 No Action 1 Memory clear function active fill the data of FNTR to Active

window When this bit is set to ldquo1rdquo RA8806 will automatically read PNTR data and fill it to Active window (Range [AWLR AWTR] ~ [AWRR AWBR]) after clear completed this bit will be cleaned to ldquo0rdquo

0 RW

2

ASCII Mode Enable 1 All input data will be decoded as ASCII (00h ~ FFh) 0 In text mode (REG[00h] Bit-3) the RA8806 will check the first

written byte data first If less then 80h then itrsquos treated as ASCII (Half-size) Or itrsquos treated as a full-size text(GB BIG5 or User-created font)

0 RW

1-0

ASCII Blocks Select 0 0 Map to ASCII block 1 (Table C-1 and Table C-5 of Appendix C) 0 1 Map to ASCII block 2 (Table C-2 and Table C-6 of Appendix C) 1 0 Map to ASCII block 3 (Table C-3 and Table C-7 of Appendix C) 1 1 Map to ASCII block 4 (Table C-4 and Table C-8 of Appendix C)

00 RW




RA8806

REG [F1h] Font Size Control Register (FVHT)


7-6

Set Character Horizontal Size 0 0 One Time of normal font width 0 1 Two Times of normal font width 1 0 Three Times of normal font width 1 1 Four Times of normal font width

00 RW

5-4

Set Character Vertical Size 0 0 One Time of normal font height 0 1 Two Times of normal font height 1 0 Three Times of normal font height 1 1 Four Times of normal font height

00 RW

3-0 Reserved 0000 R


RA8806

6 Function Description

6-1 MPU Interface

6-1-1 MPU Type The RA8806 support 8080 or 6800 compatible MPU interface When the pin ldquoMIrdquo is pull low then the MPU interface is set to 8080 compatible If ldquoMIrdquo pulls high then the MPU interface is defined as 6800 compatible And the pin ldquoDBrdquo is used to select the 8080 MPU data bus is 4-bits or 8-bits When ldquoDBrdquo is pulled low then the data bus for data transition is 4-bits If pin ldquoDBrdquo pull high the data transition is 8-bits The option of 4-bits or 8-bits data bus is for both 8080 and 6800 MPU Of course if used 4-bits interface then the 8080 MPU has to take double time to communicate with RA8806 In order to reduce the transmission line interference between MPU interface and RA8806 we suggest that a small capacitor to the GND should be added at the signal of ZCS1ZRDZWR please see the following Figure 6-1

8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI

Figure 6-1 8080 (48-bits) MPU Interface

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8

Figure 6-3 8080 MPU Interface Waveform

Table 6-1 8080 MPU Interface Timing

Rating Symbol Description

Min Max Unit Condition

tCYC8 Cycle time 2tc -- ns

tCC8 Strobe Pulse width 50 -- ns

tAS8 Address setup time 0 -- ns

tAH8 Address hold time 20 -- ns

tDS8 Data setup time 30 -- ns

tDH8 Data hold time 20 -- ns tACC8 Data output access time 0 20 ns tOH8 Data output hold time 0 10 ns

tc = one system clock period



RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6











tc is one system clock period

tc = 1CLK



RA8806

6-1-2 Command Write According to the Table 5-1 RA8806 accept 4 cycles through MPU interface If users want to write command to RA8806 then a Command cycle has to execute first and then execute a Data Write cycle The ldquoCommand Writerdquo means write function data to register After these two cycles the Data will write into the indicative Register Please see the following Figure 6-5 (1) In Table 6-1 of Section 6-1-1 each command of RA8806 is take 2 cycles and the minimum cycle time is 2tc So totally the minimum time of command write need 4tc See following Table 6-3 If the secondary cycle is a ldquoData Readrdquo then user could read the register content See the following Figure 6-5 (2) Note the Figure 6-5 to Figure 6-7 are use the 8080 MPU interface as examples

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

(1) Command Write (Write Data to Register)

(2) Read Data from Register

Figure 6-5 Command Write and Register Read Cycle

Table 6-3 Command Access Time Table System Clock Command Access Time

4MHz 1micros 6 MHz 667ns 8 MHz 500ns 10 MHz 400ns 12 MHz 333ns



RA8806

6-1-3 Memory WriteRead When users want to write data to memory ndash DDRAM or CGRAM then a special Command cycle has to execute first the register have to assign to ldquoB0hrdquo on Data Bus Then the following Data Write cycle will write data into memory If users want to read data from memory then the register has to assign to ldquoB1hrdquo on Data Bus in Command Write cycle Please see the following Figure 6-6 (1) and (2)

RS

ZCS1

ZWR

ZRD

DATA[70] B0h DATA1 DATA2 DATAn

(1) Memory Write (Write Data to DDRAM)

(2) Memory Read (Read Data from DDRAM)

B1h DATA1 DATA2 DATAn

RS

ZCS1

ZWR

ZRD

DATA[70]

Figure 6-6 Memory WriteRead Cycle

6-1-4 Status Read RA8806 provides a dedicate Status Read cycle to help users know the status of RA8806 Please refer to following Figure 6-7 and the beginning of Section 5-2 ldquoRegister Descriptionrdquo

RS

ZCS1

ZWR

ZRD

DATA[70] Status DATA

Status Register Read

Figure 6-7 Status Read Cycle



RA8806

6-2 Driver Interface

The main function of Driver Interface is to generate Frame (Pin ldquoFRrdquo) Latch Pulse (Pin ldquoLPrdquo) ldquoYDrdquo and Data Bus (LD[70]) for external LCD driver IC RA8806 could both support 4-bits and 8-bits LCD driver interface Pin ldquoDWrdquo is for LCD driver data bus selection If ldquoDWrdquo pulls high then 8-bits LCD driver is used If pull low then 4-bits LCD driver is used Figure 6-8 is the LCD interface of RA8806

YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806

STN Dot MatrixLCD Panel

Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver

Figure 6-8 The Interface of RA8806 and LCD Driver

Figure 6-9 is the timing waveform of RA8806 and LCD Driver Users could also refer to Section 4-4 ldquoLCD Driver Interfacerdquo for LCD driver pin description

F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )

F or 320x240 T o ta l 240 LP fo r each F ram e

1st line

Figure 6-9 The Waveform of RA8806 and LCD Driver



RA8806

Figure 6-10 is the application diagram of RA8806 In this example we use 80-channels LCD Drivers to process Common and Segment activity of 320x240 LCD Panel RA8806 send FR LP YD Data Bus(LD[30] and clock(XCK) signals to SegmentCommon drivers The Figure 6-11 is the example for 160x160 panel application

Figure 6-10 Application Circuit Diagram for 320x240 Panel



RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7

160-channel(Com mon)

FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7

160-channel(Segm ent)

DISPO

FF

Y1~Y160

Y1~Y160160160 Dot LCD Panel

VDD

VSS


Table 6-4 is the RA8806 driver signals mapping to different driver ICsrsquo pin names Note do not need add any capacitor on these for LCD driver signals If add external capacitor on these pins to ground or VDD then the maximum limitation is 30pF

Table 6-4 Driver IC IF Name vs RA8806 RA8806

Driver IF Driver IC IF Name Definition of Driver IC IF

LP Data Latch Clock Latch Pulse in one line

LOAD Latch pulse of display data LP

CL1 Data Latch Pulse

CP Data Shift Clock Clock pulse for segment shift register

SCP Shift Clock Pulse for X-Drivers CL2 Data Shift Pulse

XCK

HSCP Shift Clock Pulse

FLM Scan Start-up Signal First Line Marker

FR Frame Pulse

FRAME Frame start signal(First line mark of common signal)

YD

CDATA Synchronous Data

FR DF(M) Switch signal to convert LCD drive waveform into AC

LD[70] D[70] LCD Data Bus DISPOFF Display OFF

DOFF Display OFF ZDOFF DISP Display OFF



RA8806

6-2-1 Display Resolution RA8806 support many different resolution of LCD panel For different resolution of panel RA8806 could change the setting of some registers like DWWR and DWHR to modify display window size And use registers AWRR AWBR AWLR and AWTR to change the active window size

For example if 320x240 LCD panel is used then the related register setting is as following

DWWR = (320 8) - 1 = 39 = 27h DWHR = 240 ndash 1 = 239 = EFh

The active window range is less than display window So user has to care the rule as following

1 DWWR ge AWRR ge AWLR 2 DWHR ge AWBR ge AWTR

RA8806 supports a variety of LCD modules the setting of register depnding on different resolution of LCD module is list at below table

Table 6-5 Registers Setting for LCM Resolution

Panel Resolution

Segment CommonREG[21h]

DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh

6-2-2 Display Window and Active Window The RA8806 provides two windows for real application -- Display Window and Active Window The Display Window is the actual resolution of LCD panel Active is a sub-window in Display Window The boundary of cursor shift depends on the active window The relative registers of the two windows are as the following table

Table 6-6 Reg Bit_Num Description Reference

AWLR Bit [50] Define left boundary of the active window REG[40h] AWRR Bit [50] Define right boundary of the active window REG[20h] AWTR Bit [70] Define top boundary of the active window REG[50h]

AWBR Bit [70] Define bottom boundary of the active window

REG[30h]

DWWR Bit [50] Define the width of the display window REG[21h] DWHR Bit [50] Define the height of the display window REG[31h]



RA8806

For RA8806 if LCD panel resolution is 320x240 pixels then the display window resolution is 320x240 We can create an active window in the display window like Figure 6-12 This figure show the display resolution is 320x240 and a 160x160 active window is on the upper-middle The relative setting of the active window as following

LCD_CmdWrite ( 0x40 ) AWLR = 09h = 9 ( 80 8) ndash 1 LCD_DataWrite ( 0x09 )

LCD_CmdWrite ( 0x20 ) AWRR = 1Dh = 29 ( 240 8 ) ndash 1 LCD_DataWrite ( 0x1D )

LCD_CmdWrite ( 0x50 ) AWTR = 00h = 0 LCD_DataWrite ( 0x00 )

LCD_CmdWrite ( 0x30 ) AWBR = 9Fh = 159 160 ndash 1 LCD_DataWrite ( 0x9F )

LCD_CmdWrite ( 0x21 ) DWWR = 27h = 39 ( 320 8 ) ndash 1 LCD_DataWrite ( 0x27 )

LCD_CmdWrite ( 0x31 ) DWHR = EFh = 239 240 ndash 1 LCD_DataWrite ( 0xEF )

320

240

Display Window320 x 240

Active Window160 x 16080 80

80

0 1 2 helliphellip79 80 helliphelliphelliphelliphelliphelliphelliphelliphelliphellip 239 240 helliphelliphellip319012

159160

239

Figure 6-12 RA8806 Display Window and Active Window



RA O TECHNOLOGY INC 37184 wwwraiocomtw

RA8806

For RA8806 if LCD resolution is 240x160 pixels then the display window resolution is 240x160 We can create an active window in the display window like Figure 6-13 This figure show the display resolution is 240x160 and a 120x120 active window is on the upper-left The relative setting of the active window as following

LCD_CmdWrite ( 0x40 ) AWLR = 00h = 0 LCD_DataWrite ( 0x00 )

LCD_CmdWrite ( 0x20 ) AWRR = 0Eh = 14 ( 120 8 ) ndash 1 LCD_DataWrite ( 0x0E )


LCD_CmdWrite ( 0x30 ) AWBR = 77h = 119 120 ndash 1 LCD_DataWrite ( 0x77 )

LCD_CmdWrite ( 0x21 ) DWWR = 1Dh = 29 ( 240 8 ) ndash 1 LCD_DataWrite ( 0x1D )

LCD_CmdWrite ( 0x31 ) DWHR = 9Fh = 159 160 ndash 1 LCD_DataWrite ( 0x9F )

240

160


Active Window120 x 120

012

119120

159

0 1 2 helliphelliphelliphelliphelliphelliphelliphelliphellip 119 120 helliphelliphelliphelliphelliphelliphelliphelliphellip　239

Figure 6-13 Display Window and Active Window

i


RA8806

6-2-3 ComSeg Scan Direction RA8806 supports a special feature to reverse the Common and Segment signal User could use this feature to change the direction of cursor and display data If use text rotate function and set CDIR = 1 then use could show text in vertical display Please refer to Section 6-10-4

Table 6-7

Reg Bit_Num Description Reference

Bit 1 Define the order of Segment signals (SDIR)MISC

Bit 0 Define the order of Common signals (CDIR)REG[01h]

(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1

SEG0 helliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphelliphellip SEG319COM0

COM239

COM0

COM239

Cursor Moving way Cursor Moving way

Figure 6-14 Example for Change Segment Direction

6-2-4 Idle Time Counter (ITCR) ITCR(REG[90h]) is used to determine the idle time during the LP peer-to-peer time It has following meanings in function

1 Adjusting the Frame Rate(By extending the scan time of each COM)

2 Avoiding the generation of ldquoFlickerrdquo

The ldquoFlickerrdquo is generated by the violation of LCD scan cycle and Memory write cycle ldquoFlickerrdquo means the noise of the scan data at such violation By setting the ITCR user can write the display memory only at ldquoIdlerdquo time to eliminate the ldquoFlickerrdquo

XCLK

LP

T_COM

ITCR COM_SCAN

Figure 6-15 Idle Time Period

RA8806 scan time of each COM line can be calculated by the formulas



RA8806

COM_PRD = ((SEG_NOLD_WIDTH) x (1 + EXT_MD)) ＋ ITCR ) x XCK_PRD

In which the EXT_MD means extension mode is set or not if REG[12h] Bit[64] = 110b111b EXT_MD = 1 or EXT_MD = 0 The ldquoXCK_PRDrdquo is one clock period of XCK The XCK frequency is base on the system clock It depends on the setting of Bit[32] of REG[MISC] As to the Frame time and frame rate calculation It would be

FRM_PRD = COM_PRD x COM

And

FRM_Rate = 1 FRM_PRD

For example when panel size is set to 320x240 system clock frequency is 8MHz REG[MISC] Bit[32] = 10b LCD driver data bus width is 4-bits what the frame rate would be The System Clock(CLK) is 8MHz and REG[MISC] Bit[32] = 10b XCK = CLK2 so the XCK_PRD is 250ns

XCK_PRD = 1 (CLK2) = 14MHz = 250ns

COM_PRD = ( 320 4 ＋ ITCR) x XCK_PRD = (80+ ITCR) x 250(ns)

If the ITCR = A0h(160 in decimal)

COM_PRD = (80+160) x 250ns = 240 x 250ns = 60micros

The COM number is 240 so the frame period is

FRM_PRD = 60micros x 240 = 144 ms

And the frame rate is

Frame Rate = 1 144 ms = 694 Hz

We can see the effect that the ITCR setting to the corresponding frame rate So we can use it to adjust the frame rate Please refer to Appendix B - the Table B-1 ~ Table B-3 In those tables we show some Frame Rate setting for difference resolution system clock But note the display quality is also depends on the module design and the material of liquid crystal

Table 6-8


ITCR Bit [70] Define the idle time during the LP peer-to-peer time REG[90h]

MISC Bit [32] Select the clock frequency of XCK REG[01h]



RA8806

6-3 Display Data RAM (DDRAM)

The RA8806 embedded two 96Kbyte Display Data RAMs ndash DDRAM1 and DDRAM2 It can use for two layers mono-display or one layer 4-gray-levels display The maximum resolution of supporting LCD panel is 320Column x 240Row There are two modes to write the DDRAM text mode and graphics mode It provides a flexible and easy way to make the display

6-3-1 Display Layer and Display Mode Selection

There are 4 possible displays way at 2 Modes combination 1 Only show DDRAM1 or DDRAM2 One DDRAM data will show on the screen and another one

DDRAM can be standby or as a CGRAM to created special font or symbol by users Please refer to Section 6-11 ldquoUser Defined Fontrdquo for detail description

2 Two Layer Mode In this mode the screen will show the combination data of DDRAM1 and

DDRAM2 There are 4 types combination that set by REG[12H] Bit[32]

DDRAM1 ldquoORrdquo DDRAM2 DDRAM1 ldquoXORrdquo DDRAM2 DDRAM1 ldquoNORrdquo DDRAM2 DDRAM1 ldquoANDrdquo DDRAM2

For detail please refer to Section 6-10-1-5 ldquoTwo Layer Displayrdquo 3 4-Gray-level Mode In gray mode each pixel consists with 2 continuous bits in both DDRAM 4 Extension Mode Two extension modes is support and both DDRAM1 and DDRAM2 data will

show on the screen

Horizontal extension mode (Max resolution is 640 x 240 pixels) Vertical extension mode (Max resolution is 320 x 480 pixels)

6-3-2 Access Memory Selection

There are one 512Byte CGRAM and two 96KByte DDRAMs in RA8806 The 512Byte CGRAM is used to generate user-define font and the two DDRAM are used to store the display data One of both DDRAM can be also store special font or symbol that when only one DDRAM is active on the screen Which RAM is available for MPU access is depending on the REG[12h] Bit[10] Please refer to Section 5-2 ldquoRegister Descriptionrdquo


Bit [64] Display Layer and Display Mode Selection

Bit [32] Two Layer Mode Selection MAMR

Bit [10] MPU ReadWrite Memory Selection

REG[12h]



RA8806


6-4 Touch Panel

RA8806 built in a 10-bit ADC and control circuits to connect with 4-wires resistance type touch panel Resistive Touch Panel is composed of two layer extremely thin resistive panel such as Figure 6-16 There is a small gap between these two-layer panels When external force press a certain point the two-layer resistive panels will be touched which is short Because the end points of two-layer have electrodes (XL XR YU YD) such as Figure 6-17 a comparative location will be detected with some switches in coordination

YU

XL

YDXR

Electrode

X Plate

Y Plate

Figure 6-16Touch Panel

SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL

Figure 6-17 Control Switch of Touch Panel

Users only need to connect the touch panel signals -- XL XR YU and YD to RA8806 It will continuously monitor the panel and wait for touch event When the event is occurred a divided voltage on panel caused by touch is sensed and transferred by ADC to determine the location After the value of X-axis and Y-axis are transferred and stored in corresponding registers respectively the touch panel controller will issue an interrupt to inform MPU to process it


RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

Figure 6-18 RA8806 Touch Panel Circuit

RA8806 provides 2 modes (Auto and Manual) for touch panel application

Table 6-10

Operation mode

Event detection Description

Auto Interrupt When touch event happens Read the corresponding X Y coordination

Interrupt When touch event happens Read the corresponding X Y coordination

Manual Polling Polling the touch event and read the corresponding X Y

coordination



RA8806

6-4-1 Auto Mode Auto mode is the easiest way to implement touch panel application Please refer to the flow chart below (1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

Figure 6-19 Auto Mode Flowchart for Touch Screen

Table 6-11 lists the used registers


TPCR1 Bit 7 EnableTouch Panel function REG[C0h]

TPCR2 Bit 7 ldquoAuto-Moderdquo or ldquoManual Moderdquo selection bit REG[C4h]

Bit 4 Touch Panel Hardware Interrupt enable bit INTR

Bit 0 Touch event status bit REG[0Fh]

TPXR Bit [70] Touch Panel SEG data MSB byte REG[C1h]

TPYR Bit [70] Touch Panel COM data MSB byte REG[C2h]

Bit [32] Touch panel COM data LSB 2bit TPZR

Bit [10] Touch panel SEG data LSB 2bit REG[C3h]




RA8806

(2) Program Example

Unsigned char X1X2Y1Y2 Touch_Panel_Enable ( ) Set TPCR1 Bit 7 to 1 TP_Auto_Enable ( ) Set TPCR2 Bit 7 to 0 TP_INT_Mask_Enable ( ) Set INTR Bit-4 to 1

Execute other function Jump to ISR when interrupt Int EXT_INT_Service_Routine ISR entry LCD_CmdWrite ( INTR ) Check INT status INT_Sta = LCD_DataRead ( )

If ( INT_Sta amp 0x01 ) Check If TP interrupt LCD_CmdWrite(TPXR) X1 = LCD_DataRead( ) MSB of X LCD_CmdWrite(TPYR) Y1 = LCD_DataRead( ) MSB of Y LCD_CmdWrite(TPZR) X2 = LCD_DataRead( ) amp 0x03 LSB two Bits of X LCD_CmdWrite(TPZR) Y2 = LCD_DataRead( ) amp 0x0C Least two Bits of Y

Execute corresponding function LCD_CmdWrite ( INTR ) Clear Touch Panel status temp = LCD_DataRead ( ) amp 0xfe LCD_CmdWrite ( INTR ) LCD_DataWrite ( temp ) Else if (INT_Sta amp 0x02) Check if Key-Scan interrupt Else if (INT_Sta amp 0x04) Check if Wakeup interrupt


RA8806

6-4-2 Manual Mode The ldquo Manual Moderdquo means that the operation process from ldquoTouch event checking functionrdquo to ldquoinput Latch X data Y datardquo the whole operation and setting process ( includes TPCR2[10]) and receiving data from XY coordinates are manual operated by programmer The advantage of using Manual Mode is it allows programmer more flexible applications In the condition that is over the range of RA8806 register setting the user can still use the software method to control the TP function in a correct way

Touch Event can be detected from ldquoInterrupt Moderdquo or ldquoPolling Moderdquo that depend on the system configuration The difference between the ldquoInterrupt Moderdquo and ldquoPolling Moderdquo are explained as following

6-4-2-1 External Interrupt Mode Under the ldquoInterrupt Moderdquo the touch event detecting way is almost the same as ldquo Auto Moderdquo The major processes are list as follows

1 Enable Touch Panel function 2 Change mode to ldquoManual moderdquo 3 Set the switch to 「Wait for touch event 」 Set TPCR2[10] to 01b 4 When interrupt asserts check if TP interrupt 5 If yes change the switch to 「Latch X data」 Set TPCR2[10] to 10b wait for enough time

to make the latch data stable and latched to TPXR and TPZR 6 Change the switch to「Latch Y data」 Set TPCR2[10] to 11b wait for enough time to

make the latch data stable and latched to TPYR and TPZR 7 Read X Y data from TPXR TPYR and TPZR and clear the interrupt status

The registers for Interrupt Mode are explained as below


TPCR1 Bit 7 Enable Touch Panel function REG[C0h]

Bit 7 TP Manual mode enable TPCR2

Bit [10] Mode selection for TP manual mode REG[C4h]

Bit 4 Touch Panel Interrupt Mask INTR

Bit 0 Touch Panel Detect Status bit REG[0Fh]

TPXR Bit [70] Touch Panel X Data Bit[92](Segment) REG[C1h]

TPYR Bit [70] Touch Panel Y Data Bit[92](Common) REG[C2h]

Bit [32] Touch Panel Y Data Bit[10] (Common) TPZR

Bit [10] Touch Panel X Data Bit[10] (Segment) REG[C3h]



RA8806

Please refer to the following flow chart and the setting examples for applying Interrupt Mode (1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

Wait for TP event Mode

( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Figure 6-20 Manual Mode Flowchart for Touch Screen



RA8806

(2) Program Example

Unsigned char X1X2Y1Y2 Touch_Panel_Enable ( ) Set TPCR1 Bit-7 to 1 TP_Manual_Enable ( ) Set TPCR2 Bit 7 to 1 TP_INT_Mask_Enable ( ) Set INTR Bit-4 to 1 Switch_Wait_TP_Event( ) Set TPCR2[10] to 01b Execute other function Jump to ISR when interrupt Int EXT_INT_Service_Routine ISR entry LCD_CmdWrite ( INTR ) Check INT status INT_Sta = LCD_DataRead ( )

If ( INT_Sta amp 0x01) Check If TP interrupt Switch_Latch_X_data( ) Set TPCR2[10] to 10b Delay_Time( ) Delay enough time for X data stable Switch_Latch_Y_data( ) Set TPCR2[10] to 11b Delay_Time( ) Delay enough time for Y data stable LCD_CmdWrite(TPXR) X1 = LCD_DataRead( ) MSB of X LCD_CmdWrite(TPYR) Y1 = LCD_DataRead( ) MSB of Y LCD_CmdWrite(TPZR) X2 = LCD_DataRead( ) amp 0x03 LSB two Bits of X LCD_CmdWrite(TPZR) Y2 = LCD_DataRead( ) amp 0x0C LSB two Bits of Y




RA8806

6-4-2-2 Polling Mode Under the rdquoPolling Moderdquo users need to decide and set the de-bounce time after the touch event as well as the sampling time after latch by considering the real situation thus more flexibilities for users apply this mode The development procedures are explained as follows

1 Enable Touch Panel function 2 Change mode to ldquoManual moderdquo 3 Set the switch to「Wait for Touch event」 ie set TPCR2[10] to 01b 4 Read Touch Panel Event status from status register check if the ldquoTouch eventrdquo happens 5 When touch event happens confirm the stability of it and set the switch to 「Latch X data」

ie TPCR2[10] set to 10b wait for enough time to make the latch data stable and latched to TPXR and TPZR

6 Set the switch to「Latch Y data」 ie TPCR2[10] set to 11b wait for enough time to make the latch data stable and latched to TPYR and TPZR

7 Read X Y data from TPXR TPYR and TPZR and clear the interrupt status

The settings for manual interrupt mode are described in the following table



Bit 7 Select operation mode to Auto-mode or Manual-mode TPCR2

Bit [10] The switch of ADC controller for manual mode

REG[C4h]

Bit 3 Touch panel event(Only activate in TP Manual mode) INTR

Bit 0 Touch Panel Detect Status bit

REG[0Fh]


TPYR Bit [70] Touch Panel Y Data Bit[92] (Common) REG[C2h]



Programmer can check the status of Touch Panel Event from the Bit-3 or Bit-0 of INTR the difference between those two bits is

1 The Bit-3 of INTR reflects the current Touch status When Touch event occurs the Bit-3 is 1 When there is no Touch event Bit-3 will be 0 and read only

2 The Bit-0 of INTR records the Touch status When a Touch event occurs the Bit-3 will be 1 and however it wonrsquot be clear automatically it has to clear by programmer

It needs to be noted is that the REG[0Fh] Bit-3 is the direct output from ADC circuit when touch panel is touched the bit will respond with the event When touch event is not stable it needs to be de-bounced to check if itrsquos legal The bit is only active at ldquoManual moderdquo When setting RA8806 to ldquoAuto-mode the touch event will be automatically checked if itrsquos legal or not Only the legal touch event will cause the interrupt




RA8806

Please refer to the flowchart and setting examples for applying above methods

(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid

Figure 6-21 Polling Mode Flowchart for Touch Screen

i


RA8806

(2) Program Example

Touch_Panel_Enable ( ) Set REG[C0h] Bit-7 = 1 TP_Manual_Enable ( ) Set REG[C4h] Bit-7 = 1 Switch_Wait_TP_Event( ) Set REG[C4h][10] = 01 Touch_Sta_Valid = 0 Initial Touch state

LCD_CmdWrite ( INTR ) INT_Sta = LCD_DataRead ( )

If ( INT_Sta amp 0x08 ) Check INTRBit-3 for ( count = 0 count lt 100 count++ ) Check 100 times LCD_CmdWrite ( INTR ) INT_Sta = LCD_DataRead( ) if (INT_Sta == 0) When no touch Touch_Sta_Valid = 0 Touch is invalid break if ( count == 99 ) When count 100 times touch is valid Touch_Sta_Valid = 1 if (Touch_Sta_Valid ) Switch_Latch_X_data( ) Set REG[C4h][10] = 10 Delay_Time( ) Delay enough time Switch_Latch_Y_data( ) Set REG[C4h][10] = 11 Delay_Time( ) Delay enough time LCD_CmdWrite(TPXR) X1 = LCD_DataRead( ) Read high byte of X-axis LCD_CmdWrite(TPYR) Y1 = LCD_DataRead( ) Read high byte of Y-axis LCD_CmdWrite(TPZR) X2 = LCD_DataRead( ) amp 0x03 Read Least two Bits of X-axis LCD_CmdWrite(TPZR) Y2 = LCD_DataRead( ) amp 0x0C Read Least two Bits of Y-axis

Execute corresponding function LCD_CmdWrite ( INTR ) Clear REG[0Fh] Bit-0 temp = LCD_DataRead ( ) amp 0xfe LCD_CmdWrite ( INTR ) LCD_DataWrite ( temp )

Execute other function



RA8806

6-4-3 Touch Panel Sampling Time Reference Table When using the auto mode of touch panel function It is suggested to select suitable TP Sampling wait time while the ADC Clock Convert speed change in order to avoid the TP Sample wait time error Please refer to the following table for the ADC Sampling wait time REG[C0h][64]

Figure 6-21-A Touch Panel Sampling Time Reference Table

ADC Sampling Wait Time - REG[C0h] Bit[64]

SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan

RA8806 features with Key-Scan circuit and could be used as Keyboard function It will help to integrate the system circuit that includes keyboard application The below Figure 6-22 shows the basic application circuit of 8x8 Key-Pad RA8806 already built-in pull-up resistors in the pins ldquoKIN[70]rdquo

KIN0KIN1KIN2KIN3KIN4KIN5KIN6KIN7

KOUT0KOUT1KOUT2KOUT3KOUT4KOUT5KOUT6KOUT7

RA8806

Figure 6-22 8x8 Key-Pad Application

The related Registers of Key-san function are KSCR KSDR and KSER The RA8806 Key-Scan controller features are given below

1 Support with 4x8 or 8x8 Key-Scan Matrix 2 Programmable setting of sampling times and scan frequency of Key-Scan 3 Adjustable long key-press Timing 4 Multi-Key is available ( maximum three keys at the same time) 5 Allows the function of ldquo Key press to wake-up the systemrdquo

Table 6-14 is the key code of mapping to key-pad matrix for normal press The key code will be stored in REG[A2h] when key was pressed If it was a long time press then the key code is show as Table 6-15

Table 6-14 Key Number Mapping Table (Normal Key)

07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806

Table 6-15 Key Number Mapping Table (Long Key)

87h86h85h84h83h82h81h80h

F7hF6hF5hF4hF3hF2hF1hF0h

E7hE6hE5hE4hE3hE2hE1hE0h

D7hD6hD5hD4hD3hD2hD1hD0h

C7hC6hC5hC4hC3hC2hC1hC0h

B7hB6hB5hB4hB3hB2hB1hB0h

A7hA6hA5hA4hA3hA2hA1hA0h

97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7

When the Multi-Key function is applied the pressed keys will be saved in the system each with KSDR0 KSDR1 and KSDR2 Note that the priority of keys saving is determined on the value size of Key-code not the orders of keys pressing please refer to the following example Press the Key-code in turn of 0x44 0x00 and 0x22 press Multi-Key at the same time the Key-code will be saved in KSDR

KSDR0 = 0x00 KSDR1 = 0x22 KSDR2 = 0x44

The definition of Key-code is described in the registers KSDR0 ~ 2 [A2h ~ A4h] The basic features of above Key-Scan settings are introduced as follows


Bit 7 Key-Scan enable bit

Bit 6 Key-Scan size selection

Bit [54] Key-Scan sampling times setting

Bit 3 Long key function enable

KSCR1

Bit [20] Key-Scan scan frequency setting

REG[A0h]

Bit [32] long key timing adjustment KSCR2

Bit [10] Pressed key number REG[A1h]

KSDR0

KSDR1

KSDR2

Bit [70] Key code for pressed key REG[A2h ~ A4h]

Bit 5 Key-Scan interrupt enable INTR

Bit 1 Key-Scan Interrupt Status bit REG[0Fh]



RA8806

Besides in the Sleep Mode RA8806 allows the ldquoWake-up on Keystrokerdquo function if any key is pressed the System Clock starts to oscillate and de-bounce to check if the wake-up event is legal If legal then after two Frame time the Display on the panel will be lighted then system will recover from the Sleep Mode If not legal the system clock is off again and keeps on the Sleep mode Please refer to the description of ldquoPower Moderdquo for the detail introduction of ldquoSleep Moderdquo The settings for Wake-up function are explained as follows


KSCR2 Bit 7 Enable Key-Scan wake-up function REG[A1h]

Bit 6 Wake-up interrupt enable bit INTR

Bit 2 Wake-up Interrupt Status bit REG[0Fh]

Enabling the Key-Scan functions programmer cans uses following methods to check keystroke

1) Software check method to know the key be pressed from keeping check the status of Key-Scan (Bit-1 of INTR)

2) Hardware check method to know the key be pressed from external interrupt signal

Please be aware that the status of Key-Scan (Bit-1 of INTR) has been set to ldquo1rdquo no matter which method is used programmer have to clear the status to 0 after reading the correct Key Code otherwise the interrupt will be kept that no more interrupt is visible again




RA8806

The flowchart and sample settings for above applications are shown as follows 1 Software Method

(1) Flowchart

Start

Enable Key Scan( KS )

( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End

Figure 6-23 Key-Scan Flowchart (1)

i


RA8806

(2) Program Example

Key-Scan_Enable ( ) KSCR Bit-7 is set to 1 while (1) LCD_CmdWrite ( INTR ) Check Key-Scan status KS_Sta = LCD_DataRead ( ) KS_Sta = KS_Sta amp 0x02 If ( KS_Sta ) LCD_CmdWrite ( KSDR0 ) Read first Key Code KeyCode1 = LCD_DataRead ( ) Switch ( KeyCode1 ) Execute corresponding action case 0 break case 1 LCD_CmdWrite ( INTR ) Clear Key-Scan status temp = LCD_DataRead ( ) temp = temp amp 0xfd LCD_CmdWrite ( INTR ) LCD_DataWrite ( temp )




RA8806

2 Hardware Method

(1) Flowchart

Start

Enable Key Scan ( KS )

( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask

( REG[0Fh] B5 = 1 )Check KS Status

( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806

(2) Program Example Key-Scan_Enable ( ) Set Reg KSCR1 Bit-7=1 Key-Scan_INT_Mask_Enable ( ) Set Reg INTR Bit-5=1 Execute other functions Jump to ISR when external interrupt Int EXT_INT_Service_Routine ISR entry LCD_CmdWrite ( INTR ) Check INT status INT_Sta = LCD_DataRead ( ) If ( INT_Sta amp 0x02 ) Check if Key-Scan interrupt LCD_CmdWrite ( KSDR0 ) Read Key Code KeyCode1 = LCD_DataRead ( ) Switch ( KeyCode1 ) Execute keystroke function case 0 break case 1 LCD_CmdWrite ( INTR ) Clear Key-Scan status temp = LCD_DataRead ( ) temp = temp amp 0xfd LCD_CmdWrite ( INTR ) LCD_DataWrite ( temp ) else if (INT_Sta amp 0x01) Check if Touch Panel interrupt else if (INT_Sta amp 0x04) Check if Wakeup interrupt



RA8806

6-6 Clock and Reset

RA8806 supports internal or external clock source without extra select pin

6-6-1 OSC Circuit RA8806 contains a built-in OSC circuits It generates corresponding clock by connecting an external 4M ~ 12MHz crystal between XG and XD pins Figure 6-25 is the clock circuit for Xrsquotal oscillator and external clock

XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK

Figure 6-25 Clock Circuit

6-6-2 External Clock

RA8806 can also accept external clock for system clock source The external clock source can directly connect to XG pin and XD pin must be kept floating

EXT￠0tWL

tRCL

tWH

tFCL

tC Figure 6-26 External Clock

Table 6-18 Clock Timing Ta = ndash20 to 75 VDD = 5V VDD = 33V Signal Symbol Parameter

Min Max Min Max Unit Condition

tRCL External clock rise time mdash 10 mdash 10 ns tFCL External clock fall time mdash 10 mdash 10 ns

tWH External clock HIGH-level pulse width Note 1 Note 2 Note 1 Note 2 ns

tWL External clock LOW-level pulse width Note 1 Note 2 Note 1 Note 2 ns

EXT Φ0

tC External clock period 666 mdash 833 mdash ns

Notes

1 WLWHFCLRCLC tt1000475)ttt( lttimesminusminus

2 WLWHFCLRCLC tt1000525)ttt( gttimesminusminus



RA8806

6-6-3 Reset The RA8806 requires a reset pulse at least 1024tc long after power-on in order to re-initialize its internal state If the oscillator frequency is 6Mhz then the Reset pulse is at least 1707micros For maximum reliability it is not recommended to apply a DC voltage to the LCD panel while the RA8806 is reset Turn off the LCD power supplies for at least one frame period after the start of the reset pulse

RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW

Figure 6-27 Examples of ZRST Pin

Figure 6-27 is an example for ZRST application circuit It could be controlled by MPU such as (1) of Figure 6-27 Or generated by a RC circuit such as (2) of Figure 6-27 The RA8806 cannot receive commands while it is reset Commands to initialize the internal registers should be issued soon after a reset During reset the LCD drive signals XD LP and FR are halted A delay of 1ms (minimum) is required following the rising edges of both ZRST and VDD to allow for system stabilization Please refer to Figure 6-28 for more detail description

VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD

tc ()1024----Reset active timetRST

ms1----Reset hold timetRH

ms1----Reset setup timetRS

UnitMinTypMax

tC is the period of system clock for example 10MHz tC = 100ns

Figure 6-28 Reset Timing



RA8806


6-7 Power

6-7-1 Power Architecture

The power architecture of RA8806 is shown as Figure 6-29 VDDP GNDP are IO powers and AVDD AGND are analog powers for internal ADC There is an embedded 5V-to-3V DCDC Converter which is without any external controlled pin The application circuits of 5V and 3V system will be described below

RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC

Figure 6-29 Power Architecture

6-7-2 3V Application Circuit When RA8806 operates in 3V system the power consumption will be smaller The Figure 6-30 is the example for 3V system Users need to connect 3V power to VDDP VDD and AVDD respectively The DCDC Converter is not used so VDDH needs to be kept floating

RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)

Figure 6-30 The Power Connection of 3V



RA8806

6-7-3 5V Application Circuit

When RA8806 operates in 5V system 5V power inputs from VDDH and 3V power will output at VDD that is the power to supply internal core Users need to add 1microF and 01microF capacitors in parallel at VDD to increase power stability Please note that DC-to-DC converter will increase some power consumption So if the RA8806 enter Sleep mode then it will keep around 20microA static current

RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806

6-7-4 Sleep Mode The RA8806 provide two operation modes Normal mode and Sleep mode Please refer to Chapter 5 ldquoRegister Descriptionrdquo for Register WLCR explanation RA8806 will shut down the system clock to achieve the minimum power consumption When RA8806 is under the Sleep mode only the status register can be read other registers are not allowed to read Other command besides REG[00h] Bit-7(Sleep mode) canrsquot be written When RA8806 is under Sleep Mode it can accept the following three methods to wake-up

1 Write REG[00h] Bit-7 = 0 then it will return to Normal Mode

2 Touch event is detected

3 Key-Scan is detected

When RA8806 quit from Sleep mode to avoid the incorrect activity RA8806 must de-bounce the wake-up event for enough time(about 1000 system clock periods) to make sure it then quit from Sleep mode Besides when MPU program RA8806 to enter Sleep mode RA8806 canrsquot receive command from MPU anymore till quit the Sleep mode The command will be lost User program must avoid the possibility of the condition For example if RA8806 be programmed to Sleep mode at the same time the MPU receives an external interrupt and cause the MPU enter the Interrupt Service Routine(ISR) That will cause RA8806 canrsquot correctly receive and recognize the command

From the view of hardware design the condition canrsquot be prevented Because the external interrupt is an individual mechanism of MPU We canrsquot predicate the happen of it from the role of RA8806 Itrsquos a possible risk even the possibility is rare

So itrsquos suggested that MPU must be mask the interrupt for RA8806 before commanding the RA8806 to enter the Sleep mode The interrupt mask is off after RA8806 quit from Sleep mode Besides because the status register can be read normally at Sleep mode Also user can check the status in the ISR for judgment If RA8806 is checked under Sleep mode MPU can quit ISR and execute nothing to prevent incorrect activity


WLCR Bit 7 Normal mode and Sleep mode selection

REG[00h]



RA8806

6-8 Interrupt and Busy

The RA8806 provides an interrupt output (INT) for MPU to indicate the status of RA8806 And a busy output to indicate the RA8806 is in busy state Both signals could be set to active high or active low by register

6-8-1 Interrupt RA8806 provides an Interrupt signal (INT) for following event

Touch Panel touched event is happen

Key-Scan enable and key is pressed

Wake-up event occurs when Sleep mode

These interrupt events can be masked or active respectively It is controlled by the REG[0Fh] the mask and status registers Besides RA8806 also provide a software access interrupt function When user system donrsquot support hardware interrupt signal they can use polling method to achieve the software interrupt To access hardware interrupt user needs to set corresponding Interrupt Mask bit to 1(Refer to register INTR) The steps are

RA8806 generate the interrupt signal to MPU

After finishing the current instruction MPU hardware will jump the PC(Program counter) to Interrupt Service Routine(ISR)

In the same time that RA8806 generate the interrupt the interrupt status is set to rdquo1rdquo(REG[0Fh] Bit[20]) (For example if key-scan interrupt activates the Key-Scan status will be set to 1)

To apply the software interrupt method users donrsquot need extra setting Just reading the status bit of register INTR to check the interrupt event BTW interrupt mask can only disable the hardware interrupt but canrsquot disable the status of INTR Example-1 The Figure 6-32 is an example of INT timing for Wake-up event RA8806 provides three wake-up event Please refer to Section 6-7-4 ldquoSleep Moderdquo for the detail

Wake-Up Event

INT

t INTST

Figure 6-32 Interrupt Timing(1)



RA8806

t INTST = Clock Stable Time + 1024t C

If user use a 6MHz Xrsquotal for system clock the Clock Stable Time is about 3~35ms and t C is 167ns

Example-2 The Figure 6-33 is an example of INT timing for Key-Scan event

Key-ScanEvent

INT

t INTST


t INTST = De-bounce Time + t CKEY

The ldquoDe-bounce Timerdquo is set by REG[A0h] Bit[54] and the tCKEY is the Key-Scan Cycle that depends on the setting of REG[A0h] Bit[20] Additionally because the status bit will not be cleared to 0 automatically So user must manually clear it after processing the interrupt routine

6-8-2 Busy The RA8806 also provides a ldquoBUSYrdquo signal When Busy Flag is ldquo1rdquo which means RA8806 is in busy state that RA8806 couldnrsquot access data from DDRAM Two busy conditions are provided One is Scan Busy and another is Memory Write Busy The detail explains is as follows

Scan Busy When LCD panel displays RA8806 scan circuit will access the DDRAM If another DDRAM access cycle happens It will cause the data lose in one of them So when scan circuit is active it causes a busy condition called Scan Busy Figure 6-34 shows the data flow diagram of scan circuit and MPU memory access cycle Figure 6-35 is same as Figure 6-15 to show RA8806 scan waveform It describes the condition that RA8806 scan the display for each COM line The COM scan time is combined with an Idle time and a Scan time The Idle time period can be set by register ITCR The Scan period is the time of Scan Busy Also accessing data at Scan Busy time will cause the scan data lose But it will not cause a fatal error The scan data lose will cause the display defect But if itrsquos not too frequent the defect will not infect the display too much



RA8806

RA8806

MCU

DisplayData RAM

Memory-Write LCD-Scan

InterfaceController

LCDDriver

Figure 6-34 Data Flow of DDRAM

XCLK

LP

T_COM

ITCR COM_SCAN

Figure 6-35 Scan for Each COM Line

Memory Write Busy Following two conditions will cause the Memory write busy

1 When MPU write data in text-mode Depending on different size of font it needs an enough

time to write the font to DDRAM At the period RA8806 canrsquot access the DDRAM again itrsquos a memory write busy condition

2 When MPU program RA8806 as a memory clear function(FNCR Bit-3 = 1) The period of clear DDRAM also cause a memory write busy

It will cause the DDRAM lost when accessing DDRAM in the period of Memory Write Busy So user must check the busy status after the upper two conditions is done Besides RA8806 provide polarity setting for ldquoBUSYrdquo and interrupt ldquoINTrdquo pin (Please refer to register MISC) Normally this ldquoBUSYrdquo pin is connected to MPU IO input and then MPU have to monitor this pin before accessing RA8806 The following is the timing of BUSY pin The BUSY can be active high or low that depend on the setting of REG[01h] Bit-5



RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY

Figure 6-36 BUSY Timing Chart

Table 6-20 Busy Timing

Rating Signal Symbol Parameter

Min MaxUnit Condition

Half Size Font 150 -- ns t BST Busy Setup Time

Full Size Font 250

Half Size Font -- 50t c ns BUSY

t BUSY Busy Active TimeFull Size Font -- 100t c ns

System Clock 8MHz VDD 5V t c = 125ns



RA8806

6-9 PWM

RA8806 provide a set of programmable PWM (Pulse Width Modulation) for LCD contrast adjustment The PWM frequency and duty can be set by register And the driving capability of PWM output pin is larger than other output pin about 4 multiples of normal output Besides if the PWM function is disable it can use as normal IO signal The relative function setting please refers to the table below


Bit 7 PWM function enable PCR

Bit [30] Clock source divide ratio select REG[D0h]

PDCR Bit [70] PWM Duty Cycle Select REG[D1h]

The following are two examples for the PWM output (pin ldquoPWM_OUTrdquo)

TH TL

Example-1System Clock = 10Mhz Register PCR Bit[30] = 0001b Clock Source = 10MHz2 = 5MHz

TPWM = 256(15MHz) = 512microsRegister PDCR Bit[70] = 0Fh

TH = 16(15MHz) = 32micros TL = (256-16) (1 5MHz) = 48micros


TPWM = 256(125MHz) = 1024 microsRegister PDCR Bit[70] = 7Fh


TH TL

TPWM

TPWM

Figure 6-37 PWM_OUT Pulse



RA8806

Figure 6-38 shows the reference circuit of PWM contrast application for positive VLCD voltage Figure 6-39 shows the reference circuit for negative VLCD voltage

Figure 6-38 PWM Reference Circuit for Positive VLCD

Figure 6-39 PWM Reference Circuit for Negative VLCD



RA8806

6-10 Display Function

6-10-1 CharacterGraphic Mode There are two modes for MPU to write data to RA8806 ie character mode and graphic mode In graphic mode data is written directly to DDRAM in bit-map format In character mode data is written in code format the font bit-map in the CGROM will be written to DDRAM by this way RA8806 stores two different sizes of characters in its font ROM - 1) half size font(8x16 pixels) 2) full size font(16x16) Figure 6-40 shows the examples

16X16 font 8X16 font16X16 font 8X16 font Figure 6-40 Full Size and Half Size Font

6-10-1-1 Graphic Display

The RA8806 graphics mode is use bit map to fill the data on the DDRAM The Figure 6-41 is an example to show how to set graphics mode

1 Setup Register WLCR TEXT_MD = 02 Write bit map to Display Data Memory directly

Figure 6-41 Graphics Mode The RA8806 support maximum resolution is 320x240 pixels therefore it need 96Kbyte(320x2408 = 9600) Display Data RAM(DDRAM) to store each pixel data Figure 6-42 is an example to show the DDRAM data mapping to the LCD panel



RA8806

0 1 2 3 4 5 6 7 hellip

Display Data RAM Display On LCD

1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment

Figure 6-42 The Mapping of Display Data to LCD Panel

The RA8806 provide an Auto-Write feature to fill a data to all of the DDRAM At first user writes the data to Register PNTR then initials the Auto-Write function(Register FNCR Bit-3) RA8806 will fill the data to DDRAM in very short time Normally this feature is used to clear screen or want to fill fixed pattern or background on screen


WLCR Bit 3 Text Mode Selection REG[00h]

6-10-1-2 Half Size Font RA8806 built in 4 half-size font blocks each block contains 0h ~ FFh(256) characters and could be selected by register REG[F0h] Bit[10] By setting the REG[F0h] Bit[10] the corresponding table is selected About the font table please reference Appendix C The RA8806 also supports ISO8859 standard (ISO - International Organization for Standardization) Which can fully supports most Latin characters set REG[F0h] Bit-7 is the option of RA8806 default coding or ISO8859 mode In this mode RA8806 internal ASCII table1 ~ 4 is mapping to the coding of ISO8859-1 ~ ISO8859-4


Bit 7 ISO8859 mode

Bit 2 ASCII Mode Enable FNCR

Bit [10] ASCII Blocks Select

REG[F0h]



RA8806

6-10-1-3 Full Size Font

There are three types of CGROM in RA8806 ie RA8806-S RA8806-T and RA8806-J RA8806-S contains the Simplified Chinese characters with the coding of GB standard RA8806-T contains the Traditional Chinese characters with the coding of BIG5 standard RA8806-J contains the JIS Japanese Kanji Level 1 amp 2 font characters About the detail please refer the Appendix D Appendix E and Japanese Kanji font code table (RA8806_DS_V12_Font_JISpdf)

Table 6-24



The RA8806 displays the Chinese characters in text mode Key in the Chinese code (GB or BIG5 code) directly then it will display the Chinese characters in cursor position If display Chinese RA8806-S accepts the GB code RA8806-T accepts the BIG-5 code The Chinese character occupies two Byes hence the MPU should write the Chinese code (High Byte amp Low Byte) separate into RA8806 in case the MPU interface is 8-Bit The English code or numeric code occupies only one Byte hence it will write the code into the RA8806 at a time ie for RA8806-T the BIG-5 code of character rdquo世rdquo is ldquoA540rdquo MPU will send the ldquoA5rdquo and ldquo40rdquo in proper order to RA8806-T then it will display the Chinese character of rdquo世rdquo If use the Japanese Kanji font version of RA8806 that is RA8806-J it should transfer the JIS code for a start then the MPU send the code to RA8806-J Firstly add 80h to the Hi-Byte of JIS code then to judge the Low-Byte if it is larger or equal to 60h then adds 40h otherwise adds 20h Then it will display the Japanese Kanji font if the new code sends to RA8806-J by MPU ie the JIS code of character rdquo粟rdquo is ldquo3040rdquo to transfer to the new code is ldquoB060rdquo to send the ldquoB0rdquo and ldquo60rdquo in proper order then it will display the Japanese Kanji font of rdquo粟rdquo The Font ROM of RA8806-J mainly refer to the coding of JIS code if the user use Shift-JIS code (called for short S-JIS) then it should be transfered by another procedure firstly transfer S-JIS code to JIS code It is in common use of S-JIS coding for Japanese computer system because it contains the full font and half font of Latin character Hiragana Katakana notation and the Japanese Kanji font It is named by Shift_JIS for put in full font to avoid put in the 0xA1~0xDF of the Half-width Katakana The Figure 6-43 is the flow chart for the S-JIS code transfers to JIS code and JIS code transfers to RA8806-J furthermore the attachment is the program for the user to refer ie the S-JIS code of character rdquo粟rdquo is ldquo88BErdquo transfers to JIS code is ldquo3040rdquo as the description above JIS transfers new code to ldquoB060rdquo then send ldquoB0rdquo and ldquo60rdquo in proper order to RA8806-J it will display the Japanese Kanji font of rdquo粟rdquo ie the character rdquo 甌rdquo of J-JIS code is ldquoE14Drdquo transfers to JIS code is ldquo612Erdquo as the mention above the JIS transfer new code to ldquoE14Erdquo then send ldquoE1rdquo and ldquo4Erdquo in proper order to RA8806-J in the meantime display the Japanese Kanji font of rdquo 甌rdquo



RA8806

-81h -C1h

81h ～ 9Fh E0h ～ FFh

00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h

21h ~ 7Eh(JIS-High Byte)

21h ~ 7Eh(JIS-Low Byte)

+80h If gt=0x60 If lt 0x60

+20h+40h

SJIS-High Byte SJIS-Low Byte

A1h ~ FEh(RA8806 ROM Code-High Byte)

A0h ~ BEh 41h ~ 7Fh(RA8806 ROM Code-Low Byte)

-1Fh

Figure 6-43 The flow chart of the S-JIS code transfer to RA8806-J

=================================================== Main Program =================================================== void main(void) LCD_Reset() LCD_Initial() LCD_ON() Turn on the screen LCD_Clear() Clear display memory all LCD_Text() Switch display mode to ldquoText moderdquo LCD_GotoXY(0 0) LCD_Print_J_Str(SJIS_string 20) SJIS_string is a string include Shifit - JIS Code =================================================== Subroutine Transform SJIS to JIS =================================================== void LCD_Print_JIS_Str(uchar ptr int char_num) string pointer char numbers int temp = 0 unsigned char SJIS_HB SJIS_LB JIS_HB JIS_LB LSB



RA8806

while(temp lt char_num) if(ptr[temp] lt= 0x7F) ASCII Code 0x00 ～ 0x7F LCD_DataWrite(ptr[temp]) temp++ else Full Size font display SJIS_HB = ptr[temp] temp++ SJIS_LB = ptr[temp] temp++ ======================================== Transform SJIS Low Byte ======================================== if(SJIS_LB gt= 0x9F) JIS_LB = SJIS_LB - 0x7E LSB = 0x01 else if(SJIS_LB lt= 0x7E) JIS_LB = SJIS_LB - 0x1F LSB = 0x00 else JIS_LB = SJIS_LB - 0x20 LSB = 0x00 ======================================== Transform SJIS High Byte ======================================== if(SJIS_HB gt= 0xE0) SJIS_HB = SJIS_HB - 0xC1 else if(SJIS_HB lt= 0x9F) SJIS_HB = SJIS_HB - 0x81 JIS_HB = (((SJIS_HB ltlt 1) amp 0xFE) | LSB) + 0x21 ======================================== Write JIS Code ======================================== JIS_HB = JIS_HB + 0x80 if(JIS_LB gt= 0x60) JIS_LB = JIS_LB + 0x40 else JIS_LB = JIS_LB + 0x20



RA8806

LCD_DataWrite(JIS_HB) LCD_DataWrite(JIS_LB)

6-10-1-4 Bold and Inverse The RA8806 supports the bold and inverse font The user only needs to set up the related register bit that before send the character code to RA8806 Figure 6-44 shows the examples

16X16 inverse font 8X16 inverse font

16X16 bold font 8X16 bold font Figure 6-44 Inverse and Bold Font Example


Bit 3 Text Mode Selection

Bit 2 Set Display OnOff Selection

Bit 1 Blink Mode Selection WLCR

Bit 0 Inverse Mode Selection

REG[00h]

WCCR Bit 4 Bold Font (Character Mode Only) REG[10h]



RA8806

6-10-1-5 Two Layer Display The RA8806 embedded two DDRAM for two layers display The register MAMR is used to show the visible display for DDRAM1 and DDRAM2 It provides six display modes

Display DDRAM1 Display DDRAM2 Display DDRAM1 OR DDRAM2 Display DDRAM1 XOR DDRAM2 Display DDRAM1 NOR DDRAM2 Display DDRAM1 AND DDRAM2

Please refer Figure 6-45 and Register description of MAMR Bit[64] and Bit[32]

Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND

Figure 6-45 Two Layers Display


Bit [64] Display Layer Selection MAMR

Bit [32] Two Layer Mode Selection REG[12h]



RA8806

6-10-1-6 Line Gap The RA8806 provide Line Gap feature Especially in Chinese display if add some space in each line will look better The range of line gap is 1 ~ 16 pixel Once the line gap is setup the cursor will automatically move to property position for each line

Setting the low nibble of the register CHWI user can adjust the line gap To deserve to be mentioned when RA8806 operating in 90 degree mode the line gap is either 0 pixel or 8 pixels no matter what the font size The selection of two conditions is according to Bit-3 of the register CHWI


Bit [74] Set Cursor Height CHWI

Bit [32] Set Line Gap REG[11h]

6-10-2 Gray Scale Display The RA8806 also provide 4-gray-scale display implemented by FRC method In gray level display mode RA8806 combines the data of DDRAM1 and DDRAM2 as a gray picture Each gray pixel occupies 2 bits of DDRAM data for display Data [00b] indicate an empty pixel display and [11b] is solid display [01b] amp [10b] will be time sharing as 13 and 23 lightness Please refer to Figure 6-46

DDRAM2

Gray-Scale Display

DDRAM1

411301210100

Gray-LevelBit-bBit-a

3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

DDRAM1 Display Data RAM 1DDRAM2 Display Data RAM 2In Gray-Scale mode both DDRAM are used

Figure 6-46 Mapping Rule of 4-Gray-Scale Display

According to the data write order RA8806 support 2 data input methodology for Gray-Scale display User can write the data as the same way of mono graphic display

1 Horizontal moving first then Vertical refer Figure 6-47

2 Vertical moving first then Horizontal refer Figure 6-48



RA8806

N+40th byteN+3th byteN+2th byteN+1th byte

120th byte83th byte82th byte81th byte


40th byte3rd byte2nd byte1st byte

Horizontal-Write (Panel Resolution 320 x 240)

Figure 6-47 Horizontal Write

N+240th byte480th byte240th byte

N+2th byte243th byte3rd byte


Nth byte241nd byte1st byte

Vertical-Write (Panel Resolution 320 x 240)

Figure 6-48 Vertical Write

About the register setting please refer to following register


Bit 7 Cursor Auto Shifting Direction MAMR

Bit [64] Gray Mode selection REG[12h]



RA8806

The picture below is an example of 4-gray-level picture the program example are attached below it

Figure 6-49 4-Gray-Scale Example

Program Example

LCD_Graphic() Set graphic mode Gray_Mode() Set REG[12h] Bit[64] to 000b as gray level display

Scan_Diret_H_V() Set REG[12h] Bit-7 to 0 Cursor moves from left to right LCD_GotoXY( 0 0 ) LCD_CmdWrite( 0xB0 ) Write memory command for ( i = 0 I lt 4800 i++ ) Write data LCD_DataWrite( 0x00 ) Gray Level 1 ( 00 ) for ( i = 0 I lt 4800 i++ ) LCD_DataWrite( 0x55 ) Gray Level 2 ( 01 ) for ( i = 0 I lt 4800 i++ ) LCD_DataWrite( 0xAA ) Gray Level 3 ( 10 ) for ( i = 0 I lt 4800 i++ ) LCD_DataWrite( 0xFF ) Gray Level 4 ( 11 )



RA8806

6-10-3 Font Size Adjustment and Font Write-Time RA8806 supports Font size adjustment There are two types of characters stored in RA8806 font ROM - Half size (8x16 pixels) and full size (16x16 pixels) characters Theldquo Font size adjustmentrdquo function supports the font enlargement from 1 to 4 times bigger in vertical and horizontal respective directions Programmer can adjust the character size from setting FVHT[74]


Bit [76] Horizontal width adjustment for character FVHT

Bit [54] Vertical width adjustment for character REG[F1h]

Figure 6-50 shows the example of character enlargement

2x1 enlarged 8x16 font


Figure 6-50 Font Size Adjustment

Additionally the Font Sized Adjustment is not only available for the character display mode but also for the following display modes

For displaying the user created fonts 90deg font and display rotation




RA8806

After writing completed font code(One byte for half size font and two bytes for full-size font) it will takes an enough time for data to be written into the DDRAM In the mean while no data can be read or wrote into DDRAM (Please refer to Section 6-8 ldquoInterrupt and Busyrdquo the description of ldquoMemory Write Busyrdquo) The writing time is differing from the enlargement multiplier of font size Its calculation formula is as follows

Tfw = ( 16tc + 32tc x ( HW x VH ) ) x ( 1 + 10 ) Tfw Font Write time tc System clock period HW Horizontal enlargement multiplier VH Vertical enlargement multiplier

Here 10 is for the flexible error consideration Please refer to the following examples (Estimate the system clock is 4MHz and the tc is 250ns)

Table 6-29 Delay Time for Font Enlargement

Font enlargement multiplier Standard delay time(μS) Suggested delay time(μS)

1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452

In addition to calculate writing time and delay programmer can also check the ldquoBusyrdquo status to know if font characters were written into the DDRAM Please refer to the ldquo Status Registerrdquo for the description of ldquoBusyrdquo


RA8806

6-10-4 Font Vertical Display RA8806 features of its ldquoFont Vertical Displayrdquo function This function enables the normal display change to vertical display This means the original 320x240 panel can be used as a 240x320 panel to display embedded character font or data in vertical way and no need to change scan direction or the LCD driver layout The LCD panel could display from both vertical and horizontal ways This function is option on setting the Bit-3 of register WCCR When WCCR Bit-3 =1 (Font Rotation Mode) the font character will be written in vertical display Figure 6-51 shows the example of font vertical display

0

15

0 7

0 150

7

Normal DisplayVertical Display

Figure 6-51 Font Vertical Display Function

Under the vertical display mode the cursor moves from the direction of up to down And the cursor display is also differing to normal display mode (Please refer to Section 6-13-4 ldquoCursor Width and Heightrdquo for detail descriptions) Due to the advance rotate function if user chose a 240x160 module then it will be very easy to use same module but as an 160x240 module The following Figure 6-52 shows the example of 320x240 panel rotate to as 240X320 application In normal mode if write text font ldquoRAIOrdquo then the screen show as (1) of Figure 6-52 If set the T90DEG(Bit-3 of REG[10h]) = 1 and CDIR(Bit-0 of REG[01h]) = 1 first then write text font ldquoRAIOrdquo the screen will show as (2) of Figure 6-52

RAiO

(1) 320x240 for Normal use

SEG0 SEG319COM0

COM239

RAiO

(2) As a 240x320 ApplicationT90DEG = 1 CDIR = 1

COM239 COM0SEG0

SEG319

Figure 6-52 Font Display in Rotate Mode



RA8806

The relative register list about font rotation function is


WCCR Bit 3 Font rotation mode enable REG[10h]

MISC Bit 0 COM direction selection REG[01h]

Besides the cursor display function the other functions in the font rotation mode work as the same behavior as normal mode including

1) Font enlargement function 2) Full alignment function 3) Line Gap adjustment function 4) Scroll function



RA8806

6-11 User-Defined Font

The RA8806 embedded a 512Byte CGRAM for user to create new character The user could create font special symbol or pattern in this memory If user only uses one DDRAM then the other one could also use as CGRAM Therefore the RA8806 provides 3 regions for user to create new character(symbol or pattern) as following 1 512 Bytes CGRAM 2 96K Bytes DDRAM1 (When user only shows DDRAM2 data on screen) 3 96K Bytes DDRAM2 (When user only shows DDRAM1 data on screen)

Table 6-31 Font Code for User-Created Region Size Code and Range Capacity

CGRAM 512 bytes Half-Size 8F00h ~ 8F1Fh Full-Size 9F00h ~ 9F0Fh

32 Half-Size chars 16 Full-Size chars

DDRAM1 96 Kbytes Half-Size 8000h ~ 8E27h Full-Size 9000h ~ 9E13h




6-11-1 Create Font in CGRAM

The CGRAM is a 512Byte RAM so it could create 32 Half-Size or 16 Full-Size characters The Table 6-32 is the font code mapping table in CGRAM Note the font codes were fix in RA8806 And the Font was defined in Bit[30] of REG[CURY]

Table 6-32 CGRAM Font Code Mapping Table

8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1

8F0C8F0A8F078F03Half-Size

9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567

(1) Full-size Font (2) Half-size Font

Figure 6-53 Example of Created Font Bit-map Data According to the user-created font register setting in CGRAM please refer to the below table

Table 6-33 Register Definition for Created-font in CGRAM Reg Bit_Num Description Reference

Bit 7 Cursor Increase enable

Bit [64] Display mode MAMR

Bit [10] Select memory for write cycle

REG[12h]

CURX Bit [40]

The Bit[40] is the address for writing bit-map data of create font When create a full-size font normally set to 0 When create an odd half-size font normally set to 0 and set 10h for even font

REG[60h]

CURY Bit [30] Indicate which font code data will be created

REG[70h]



RA8806

CGRAMCreate Font

Set CURY(It indicates which font will

be created) (1)

Set the CURX to 0(First byte in font)

Set display data is DDRAM1 or DDRAM2

Write the corresponding code to show the font on active

display layer (3)

Set MAMR to access CGRAM Write memory write command

(B0h) and write the font data sequentially (2)

Figure 6-54 The Flow-chart of User-created Font on CGRAM

Note

1 CGRAM contains 512 bytes and can contain 16 16x16 full-size or 32 8x16 half-size user-created font Each full-size font contains 32bytes

2 For created full-size font after CURY is assign(0~15) and CURX is set to 0 a created-font bit-map can be filled by the 32 continuous memory writes cycle And then CURY will be increased by 1 Please refer the following Program Example(1) The result is show (1) of Figure 6-53 on screen

3 For created half-size font after CURY is assign(0~15) and CURX is set to 0(odd font) or 10h(even font) a created-font bit-map can be filled by the 16 continuous memory writes cycle Please refer the following Program Example(2) The result is show (2) of Figure 6-53 on screen

4 The CGRAM font code is 8F00~8F1F for Half-size font and 9F00~9F0Fh for full-size font Refer to Table 6-31

Program Example(1) Create a full-size font in CGRAM and show on the screen

font_data[] = 00 00 07 1F 20 67 68 09 1A 15 16 15 12 1F 00 00 00 00 E0 F8 04 E6 16 90 58 A8 68 A8 48 F8 00 00

Access_CGRAM() MAMR[10] = 00b Only_Show_DDRAM1() MAMR[64] = 001b LCD_CmdWrite( CURY ) Create 6th full-size character LCD_DataWrite( 0x05 ) LCD_CmdWrite( CURX ) Write font-data from 1st byte LCD_DataWrite( 0x00 ) LCD_CmdWrite( MWCR) B0h Memory write command for( i = 0 i lt 32 i++ ) 32 continuous write for font bit-map LCD_DataWrite( font_data[i] ) Delay2us(50)

Access_DDRAM1() LCD_Text()

LCD_GotoXY( 5 5 ) Set Cursor position ( 5 5 ) LCD_CmdWrite( MWCR) Corresponding font code( 9F05h ) LCD_DataWrite( 0x9F )



RA8806

LCD_DataWrite( 0x05 ) Show as (1) of Figure 6-53



RA8806

Program Example(2)

Create a half-size font in CGRAM and show on the screen

font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00

Access_CGRAM() MAMR[10] = 00b Only_Show_DDRAM1() MAMR[64] = 001b LCD_CmdWrite( CURY ) Create 6th half-size char LCD_DataWrite( 0x02 ) LCD_CmdWrite( CURX ) Write font-data from 1st byte LCD_DataWrite( 0x10 ) LCD_CmdWrite( MWCR) B0h Memory write command for( i = 0 i lt 16 i++ ) 16 continuous write for font bit-map LCD_DataWrite( font_data[i] ) Delay2us(50)




6-11-2 Create Font in DDRAM

The DDRAM are 96KByte RAM so it could create 600 Half-Size or 300 Full-Size characters Table 6-35 is the font code mapping table in DDRAM for Half-Size characters Table 6-36 is the font code mapping table in DDRAM for Full ndashSize characters These font codes were also fix in RA8806 The register CURX and CURY are used to point the address that bit-map data to create font According to the register setting of user-created font in DDRAM please refer to the below table

Table 6-34 Register Definition for Created-font in DDRAM Reg Bit_Num Description Reference




REG[12h]

CURX Bit [50] REG[60h]

CURY Bit [70] Both registers are Indicate which font code data will be created REG[70h]



RA8806

Table 6-35 DDRAM1 and DDRAM2 Half-size Font Code Mapping

CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000

Table 6-36 DDRAM1 and DDRAM2 Full-size Font Code Mapping Table

CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813

9A00 9A01 9A02 9A03 9A04 9A05 9A06 9A07 9A08 9A09 9A0A 9A0B 9A0C 9A0D 9A0E 9A0F 9A10 9A11 9A12 9A139A00 9A01 9A02 9A03 9A04 9A05 9A06 9A07 9A08 9A09 9A0A 9A0B 9A0C 9A0D 9A0E 9A0F 9A10 9A11 9A12 9A13

9B00 9B01 9B02 9B03 9B04 9B05 9B06 9B07 9B08 9B09 9B0A 9B0B 9B0C 9B0D 9B0E 9B0F 9B10 9B11 9B12 9B139B00 9B01 9B02 9B03 9B04 9B05 9B06 9B07 9B08 9B09 9B0A 9B0B 9B0C 9B0D 9B0E 9B0F 9B10 9B11 9B12 9B13

9C00 9C01 9C02 9C03 9C04 9C05 9C06 9C07 9C08 9C09 9C0A 9C0B 9C0C 9C0D 9C0E 9C0F 9C10 9C11 9C12 9C139C00 9C01 9C02 9C03 9C04 9C05 9C06 9C07 9C08 9C09 9C0A 9C0B 9C0C 9C0D 9C0E 9C0F 9C10 9C11 9C12 9C13

9D00 9D01 9D02 9D03 9D04 9D05 9D06 9D07 9D08 9D09 9D0A 9D0B 9D0C 9D0D 9D0E 9D0F 9D10 9D11 9D12 9D139D00 9D01 9D02 9D03 9D04 9D05 9D06 9D07 9D08 9D09 9D0A 9D0B 9D0C 9D0D 9D0E 9D0F 9D10 9D11 9D12 9D13

9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913

9E139E00 9E01 9E02 9E03 9E04 9E05 9E06 9E07 9E08 9E09 9E0A 9E0B 9E0C 9E0D 9E0E 9E0F 9E10 9E11 9E129E00 9E01 9E02 9E03 9E05 9E06 9E07 9E08 9E09 9E0A 9E0B 9E0C 9E0D 9E0E 9E0F 9E10 9E11 9E12

CURY 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 1415 16 17 18 19 1A1B 1C1D1E 1F 20 21 22 23 24 25 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )

Set Cursor shifting Direction vertical

first then horizontal( REG[12h] B7 = 1 )

Set XY -axis ( X Y )

( Set REG[60h][70h] )

Write Left-half font data to DDRAM1

Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )

Write Right-half font data to DDRAM1

Y add 1

(Set REG[70h])

Yes

N0Write 16 bytes data

Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )

Set Cursor shifting Direction horizontal

first then vertical( REG[12h] B7 = 0 )

Set XY -axis ( X Y )and execute Memory

Write CMD

Write font data that already defined at

DDRAM1 to DDRAM2

Figure 6-55 Flowchart of User-created font in DDRAM1

The above flow-chart is an example to create a Full-size in DDRAM1 and show the new font on screen(DDRAM2) At first user have to set up the CURX and CURY to define which code data will be created and then write 32Bytes bit-map data to DDRAM1 The CURX need to set twice for each 16Bytes data ndash the left and right of full-size font Please refer the following Program Example(3) If we want to create a full-size font as (1) of Figure 6-53 to mapping code ndash 9205h in Table 6-36 The result is show (1) of Figure 6-53 on screen



RA8806

Program Example(3)

Create a full-size font in DDRAM1 and show on the screen font_data[] = 00 00 07 1F 20 67 68 09 1A 15 16 15 12 1F 00 00 00 00 E0 F8 04 E6 16 90 58 A8 68 A8 48 F8 00 00

Access_DDRAM1() MAMR[10] = 01 Only_Show_DDRAM2() MAMR[64] = 010 LCD_Graphic() WLCR Bit-3 = 0 Cursor_Shift_Direct_VH() MAMR Bit-7 = 1 Set the cursor moving in vertical LCD_GotoXY(0x0A 0x20) Write the left part of full-size font LCD_CmdWrite( MWCR) Memory write command for(i=0ilt16i++) LCD_DataWrite(font_data_L[i]) Delay2us(50) LCD_GotoXY(0x0B 0x20) Write the right part of full-size font LCD_CmdWrite( MWCR) Memory write command for(i=16ilt32i++) LCD_DataWrite(font_data_R[i]) Delay2us(50) Access_DDRAM2() MAMR[10] = 10 LCD_Text() WLCRBit-3 = 1 Cursor_Shift_Direct_HV() MAMR Bit-7 = 0 LCD_GotoXY( 3 3 ) set coordinate to ( 3 3 ) LCD_CmdWrite( MWCR) Memory write command LCD_DataWrite(0x92) Write the code(9205h) of user-defined font LCD_DataWrite(0x05) Show as (1) of Figure 6-53 Delay2us(50)



RA8806

6-11-3 Create Symbol

RA8806 provides font creator function that allows user to design and create new fonts special symbols or logos and store into its embedded CGRAM or DDRAM The user-created characters each defined as a full-size (16x16) or half-size (8x16) character bitmap font formats thus 24x16 40x16 16x32 or bigger sized fonts are also possible to create accordingly The following Figure 6-56 represents a user created symbol with size 24x16

Figure 6-56 A 24x16 Symbol Example

For creating a new symbol in addition to write command to CGRAM or DDRAM note the setting of the font codes before trying to write characters to be displayed See the following 2 examples of creating this 24x16 symbol in DDRAM

When the first address - (CURX CURY) of data write to DDRAM is (0 0) the font code of this symbol are 0x8000 0x8001 and 0x8002 as Figure 6-57 below When the first address of date write to DDRAM is (2 10h) the font code of this symbol are 0x81050x81060x8107 and so on Please refer the following Program Example(4) The result is show Figure 6-56 on screen

Font Code0x8107Font Code0x8106Font Code0x8105 Figure 6-57 Font Code of Userrsquos Created Symbol for Program Example(4)



RA8806

Program Example(4)

Create a 24x16 symbol in DDRAM1 and show on the screen font_data[] = 00 02 06 0A 12 23 40 80 40 23 12 0A 06 02 00 00 00 00 00 00 00 FF 00 00 00 FF 00 00 00 00 00 00 00 80 C0 A0 90 88 04 02 04 88 90 A0 C0 80 00 00

Access_DDRAM1() MAMR[10] = 01 Only_Show_DDRAM2() MAMR[64] = 010 LCD_Graphic() WLCR Bit-3 = 0 Cursor_Shift_Direct_VH() MAMR Bit-7 = 1 Set the cursor moving in vertical LCD_GotoXY(0x02 0x10) Write the left part of symbol LCD_CmdWrite( MWCR) Memory write command for(i=0ilt16i++) LCD_DataWrite(font_data_L[i]) Delay2us(50) LCD_GotoXY(0x03 0x10) Write the middle part of symbol LCD_CmdWrite( MWCR) Memory write command for(i=16ilt32i++) LCD_DataWrite(font_data_R[i]) Delay2us(50)

LCD_GotoXY(0x04 0x10) Write the right part of symbol

LCD_CmdWrite( MWCR) Memory write command for(i=32ilt48i++) LCD_DataWrite(font_data_R[i]) Delay2us(50) Access_DDRAM2() MAMR[10] = 10 LCD_Text() WLCRBit-3 = 1 Cursor_Shift_Direct_HV() MAMR Bit-7 = 0 LCD_GotoXY( 3 3 ) set coordinate to ( 3 3 ) LCD_CmdWrite( MWCR) Memory write command LCD_DataWrite(0x81) Write the code(8102 8103 8104) of symbol LCD_DataWrite(0x02) Show as Figure 6-57

Delay2us(10) LCD_DataWrite(0x81) LCD_DataWrite(0x03)

Delay2us(10) LCD_DataWrite(0x81) LCD_DataWrite(0x04) Delay2us(10)

Besides note the display address for each of the font code to be display on the LCD screen




RA8806

especially under Rotate 90 degree and Font Enlargement mode 6-12 Scroll Function

6-12-1 Horizontal Scrolling The RA8806 provide Horizontal Scrolling function You can assign an area by Register BGSG and EDSG Once start the horizontal scrolling the assigned area will shift step by step and each step is 8 pixels width

About Horizontal Scrolling register setting please refer to the list below


Bit 2 SCR_DIR(Scroll direction)

Bit 1 SCR_HV(Scroll HorizontalVertical) ADSR

Bit 0 SCR_EN(Scroll Enable)

REG[03h]

BGSG Bit [50] The SEG start address in scroll mode REG[61h]

EDSG Bit [50] The SEG end address in scroll mode REG[62h]

BGCM Bit [70] The COM start address in scroll mode REG[71h]

EDCM Bit [70] The COM end address in scroll mode REG[72h]

(1)Flowchart The flow-chart of horizontal scrolling is as following

Start

Set Scrolling Window Boundary( Set REG[61h][62h][71h][72h])

Write Chinese font filled with the screen

Set Scrolling Direction Left to Right

( Set REG[03h][21] = 0 0 )

Enable Scrolling Function( REG[03h]B0 = 1 )

Figure 6-58 Horizontal Scrolling

i


RA8806

(2)Program Example LCD_Text() Text Mode ================================================ Set Scrolling Window ================================================ LCD_CmdWrite(0x61) SEG Start Position of Scrolling Mode LCD_DataWrite(0x05) LCD_CmdWrite(0x62) SEG End Position of Scrolling Mode LCD_DataWrite(0x22) LCD_CmdWrite(0x71) COM Start Position of Scrolling Mode LCD_DataWrite(0x20) LCD_CmdWrite(0x72) COM End Position of Scrolling Mode LCD_DataWrite(0xd0) for( i = 0 i lt 300 i++ ) Write the font to fill the screen LCD_DataWrite( RAiO [ i ] ) Delay2us(50) ================================================ Set Scrolling Direction and Enable scroll function ================================================ LCD_CmdWrite(0x03) LCD_DataWrite(0x01) L R LCD_DataWrite(0x05) R L



RA8806

6-12-2 Vertical Scrolling The RA8806 also provide Vertical Scrolling function You can start the scrolling by control Register ADSR Bit-2 Once start the vertical scrolling the whole screen will shift step by step and each step is 1 pixel height

(1)Flowchart The flow-chart of vertical scrolling is as following

Start



Set Scrolling Direction Top to Bottom

( Set REG[03h][21] = 0 1 )


Figure 6-59 Vertical Scrolling (2)Program Example LCD_Text() Text Mode LCD_CmdWrite(0x61) SEG Start Position of Scrolling Mode LCD_DataWrite(0x05) LCD_CmdWrite(0x62) SEG End Position of Scrolling Mode LCD_DataWrite(0x22) LCD_CmdWrite(0x71) COM Start Position of Scrolling Mode LCD_DataWrite(0x20) LCD_CmdWrite(0x72) COM End Position of Scrolling Mode LCD_DataWrite(0xd0) for( i = 0 i lt 300 i++ ) Fill Chinese font on the screen LCD_DataWrite( RAiO [ i ] ) Delay2us(50) LCD_CmdWrite(0x03) Scrolling Enable LCD_DataWrite(0x03) T B LCD_DataWrite(0x07) B T



RA8806


6-13 Cursor

6-13-1 Cursor Position and Shift The cursor-moving unit of segment is one byte(or eight pixels) But the moving unit of common is one pixel The cursor position is controlled by Register CURX and CURY for both text and graphics mode You can also setup the Auto-Increase mode for write to DDRAM or read data from DDRAM The cursor-moving boundary depends on the active window

6-13-2 Full Alignment

The ldquoFull alignment functionrdquo provides the ldquoAuto-Alignrdquo feature when full-size and half-size characters combined display Programmer can adjust it from the settings of Bit-6 of WCCR (Refer to register WCCR for detail description)

Appendix A Appendix B

When Bit-6 is 1 the auto-align feature is enabled When Bit-6 is 0 the auto-align feature is not being used

The Figure 6-60 and Figure 6-61 shows the above settings

With full alignment function

佑科技有限公司瑞

Figure 6-60 Font Write with Full Alignment


RA8806

Without full alignment function


Figure 6-61 Font Write without Full Alignment

When the rdquoFull-alignmentrdquo feature is used the display shows all the full-size characters start from the set start address And there will be an even bytes alignment space between these fonts For half-size character the function doesnrsquot restrict the position of it

1 Cursor set at 5rsquoth bytes

佑科技股份有限公司

瑞

2 write characters3 Line changing and alignment setting is reset

cursor

CASE 1

Figure 6-62 Full-alignment Example(1)

The full-alignment display rule is base on cursor position be set at 1st row After changing row the alignment base is reset That is the start segment address of active window There are serial conditions for the changing line with the full alignment feature Please refer to below figures for the condition




RA8806


瑞

2 Write to the end of the line3 Line changing

and alignment setting is reset

cursor

CASE 2

1 Cursor set


1 Cursor set


瑞

2 No enough space for writing a full-size character after consider full-alignment

3 Line changing and alignment setting is reset

cursor

CASE 3


i


RA8806

6-13-3 Cursor Blinking The user could control cursor OnOff or Blinking The register [80h] BTMR is used to set up the blinking time

Blinking Time = BTMR[80h] Bit[70] x (1Frame_Rate)

6-13-4 Cursor Width and Height The cursor height is controlled by register CHWI Bit[74] and the height is setting from 1 ~ 16 pixel It does depend on userrsquos requirement In normal font the cursor width fixed to one byte(8 pixels) And cursorrsquos height is from 1~16pixels that depends on CHWI Bit[74] In vertical font the cursor height fixed to 16 pixels and width is from 1~8 pixels that depends on CHWI Bit[64] See Figure 6-65 and Figure 6-66 as following

Cursor movement for Normal-Font Cursor movement for Vertical-Font

瑞佑科技

Figure 6-65 Cursor Movement

Cursor Size(Height) for Normal-Font

1 pixel 2 pixel 3 pixel 16 pixel

Cursor Size(Width) for Vertical-Font


Figure 6-66 Cursor Size



RA8806

6-14 Extension Mode for Display

Normally the maximum support resolution of RA8806 is 320x240 dots But RA8806 support a special display mode ndash Extension mode And the maximum support resolution is 640x240 or 320x480 dots In Extension mode the dual DDRAM data can be show on the bigger panel This mode is set by the Bit[64] of register MAMR Please refer to Figure 6-68 of the example by using 640x240 panel and Figure 6-69 by using 320x480 panel

RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver

Figure 6-67 Maximum Resolution for RA8806

320320

240 DDRAM1 DDRAM2Data Data

Figure 6-68 Extension Mode(1) Register MAMR Bit[64] = 110h

If MAMR Bit[64] = 110b then RA8806 supports maximum resolution is 640x240 pixels The left side of screen shows the DDRAM1 data the right side shows the DDRAM2 data Please refer to Figure 6-68 If MAMR Bit[64] = 111b then RA8806 supports maximum resolution is 320x480 pixels The up side of screen shows the DDRAM1 data the down side shows the DDRAM2 data Please refer to Figure 6-69



RA8806

320

240DDRAM1

Data

DDRAM2Data240

Figure 6-69 Extension Mode(2) Register MAMR Bit[64] = 111h Note that the extension mode is only display the combination of the DDRAM1 and DDRAM2 data The cursor movement or characters display is not continuous across them So user must set two pages separately on the screen The RA8806 will combine the DDRAM1 and DDRAM2 data as a single display in extension mode So there is some limitation on Extension Mode For example if RA8806 set to Extension Mode(1) as Figure 6-68 for 640x240 dots panel The data have to write into DDRAM1 and DDRAM2 But the cursor moving of Common is not from 0 to 639 The users have to separate the screen into 2 blocks and write data into DDRAM1 and DDRAM2 to create a complete 640x240 dots picture The Figure 6-70 shows the description

DDRAM1 DDRAM2

Figure 6-70Extension Mode(1) Cursor Moving

Of course if use Horizontal Scrolling then the screen is like the following Figure 6-71



RA8806

DDRAM1 DDRAM2

Figure 6-71Extension Mode(1) Horizontal Scrolling

But if RA8806 use Extension mode(2) like Figure 6-69 for 320x480 dots panel then the cursor moving is same as normal mode ndash the Common is from 0 to 319 The data scan of DDRAM is as Figure 6-72 The effect of Horizontal Scrolling is show as Figure 6-73

DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806

6-15 Eliminating Flicker Mode

RA8806 also provides ldquoEliminating Flicker Moderdquo in order to eliminate display errors at scanMPU confliction When the scan logic is processing scan task and at the same time the DDRAM is accessed by the MPU the scan data will force to get a wrong one and may experience side effects such as ldquoflickerrdquo When the flicker is too much it will infect the display effect

Therefore RA8806 is designed to disable scan logic when MPU is accessing the DDRAM And after it is completed the scan logic active again The ldquoEliminating Flicker Moderdquo separate Write and Read operating therefore no confliction will happen between scan logic and MPU cycle That is no data will lose Ideally it will have great improvement at display effect In real application sometimes the cycle time that MPU writes data will be different(font write and memory clear) although it accesses the RA8806 periodly On the other hand the display performance is still limited when operating under the eliminating-flicker mode in some conditions The limits are

(1) The eliminating-flicker mode is suggested to operate under the graphic mode(bit-7 of register[01h] is setting 1)

(2) Please disable eliminating-flicker function before the memory clear mode After the memory clear function is finished then the eliminating-flicker function could be enable again

Figure 6-74 Eliminating Flicker Mode


MISC Bit 7 The LCD Driver-Scan will auto-pending when busy

REG[01h]

Additionly RA8806 also supply a method to eliminate flicker by check status By check the status bit-6(SCAN BUSY) user can know whether can access memory that doesnrsquot conflict the scan data period The application figure is below



RA8806

Start

Check status bit-6(SCAN BUSY)

Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR

Check status bit-6 = 1 Memory access cycle

Check status bit-6 = 0

Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Figure 6-75 Eliminate Flicker (1) Ideal

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

Figure 6-76 Eliminate Flicker (1) Confliction

The ideal condition just likes the Figure 6-75 But if the condition likes Figure 6-76 the little part of confliction that we can not avoid So if user wants to eliminate the flicker completely by checking SCAN_BUSY user can use the method just like the Figure 6-77



RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low


In order to improve the effect of eliminating flicker by check busy we have two suggestions in real application

MPU speed cannot be too slow(The MPU cycle period cannot be too long just like Figure 6-78) otherwise the effect of eliminating flicker will be not eminent

The ITCR value cannot be set too small(just like Figure 6-79) otherwise the effect of eliminating flicker will be not eminent

So if you want to eliminate flicker by check busy of this way we support a suggestion ITCR setting value just like Figure 6-80 and Figure 6-81

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

Figure 6-78 Eliminate Flicker (2) MPU Cycle Too Long




RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

ITCR period too short

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


Figure 6-79 Eliminate Flicker (2) ITCR Cycle Too Short

MPU 8080 The Worst case

SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration

tsys = 1CLK CLK system clockM REG[01h] = 00h M=8

REG[01h] = 01h M=4REG[01h] = 10h M=2REG[01h] = 11h M=1

So ITCR suggestion value is ITCR duration=ITCR x tc x M gt 25 x Tcyc

Read Status cycleMEM write cycle

Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle

Figure 6-80 The Suggestion ITCR value for MPU 8080 Interface to Eliminate Flicker


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration

tc = 1CLK CLK system clockM REG[01h] = 00h M=8



Read Status cycle Read Status cycle MEM write cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806


7 Package Information

7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH

GNDFRLPYDXCKZDOFFLD7LD6LD5LD4LD3LD2LD1LD0GNDP

PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Figure 7-1 RA8806 Bonding Pad


RA8806

7-2 Pad XY Coordinate

Table 7-1 RA8806 Pad Coordinate

Pad No Pad Name X Y Pad No Pad Name X Y

1 GNDP 230105 -164970 35 DATA0 142980 1833052 LD0 230105 -153680 36 DATA1 131480 1833053 LD1 230105 -142180 37 DATA2 119980 1833054 LD2 230105 -130680 38 DATA3 108480 1833055 LD3 230105 -119180 39 DATA4 96980 1833056 LD4 230105 -107680 40 DATA5 85480 1833057 LD5 230105 -96180 41 DATA6 73980 1833058 LD6 230105 -84680 42 DATA7 62480 1833059 LD7 230105 -73180 43 XD 50980 183305

10 ZDOFF 230105 -61680 44 XG 39480 18330511 XCK 230105 -50180 45 ZRST 27980 18330512 YD 230105 -38680 46 TESTI 16480 18330513 LP 230105 -27180 47 TESTMD 4980 18330514 FR 230105 -15680 48 CLK_OUT -6520 18330515 GND 230105 -3970 49 KIN0 -6520 -18330516 VDD 230105 7530 50 KIN1 4980 -18330517 VDDH 230105 18610 51 KIN2 16480 -18330518 BUSY 230105 30320 52 KIN3 27980 -18330519 INT 230105 41820 53 KIN4 39480 -18330520 AGND 230105 70220 54 KIN5 50980 -18330521 AVDD 230105 81720 55 KIN6 62480 -18330522 Y2 230105 93430 56 KIN7 73980 -18330523 X2 230105 104930 57 KOUT0 85480 -18330524 Y1 230105 116430 58 KOUT1 96980 -18330525 X1 230105 127930 59 KOUT2 108480 -18330526 PWM_OUT 230105 139430 60 KOUT3 119980 -18330527 PWM_OUT 230105 150930 61 KOUT4 131480 -18330528 ZCS1 230105 162430 62 KOUT5 142980 -18330529 CS2 211980 183305 63 KOUT6 154480 -18330530 RS 200480 183305 64 KOUT7 165980 -18330531 GNDP 188770 183305 65 DB 177480 -18330532 VDDP 177270 183305 66 MI 188980 -18330533 ZWR 165980 183305 67 DW 200480 -18330534 ZRD 154480 183305 68 VDDP 212190 -183305



RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1

NCKIN0KIN1KIN2KIN3KIN4KIN5KIN6KIN7


DBMI

DW

TESTMDTESTIZRSTXGXDNCDATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0ZRDZWR

GNDPRSCS2

VDDPDate Code (Year 2008)

5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC

Figure 7-2 LQFP-100Pin Pin Assignment

RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

KIN1KIN2KIN3KIN4KIN5KIN6KIN7


DBMI

VDDPGNDP

LD0

Date Code(Year 2008)

5 10 15 20

25

30

35

40 TESTMDTESTIZRSTXGXDDATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0ZRDZWR

GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP

Figure 7-3 TQFP-80Pin Pin Assignment



RA8806

7-4 Package Dimension

E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm

Figure 7-4 LQFP-100Pin Mechanical

i


RA8806

Table 7-2 LQFP-100 Package Dimension

Dimensions in Millimeters Dimensions in Inches Symbols

Min Typ Max Min Typ Max

A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008

θ 0 35deg 7deg 0 35deg 7deg

θ1 0 -- -- 0 -- --

θ2 11deg 12deg 13deg 11deg 12deg 13deg


Note Dimension ldquoD1rdquo and ldquoE1rdquo do not include mold protrusion Allowable protrusion is 025mm per side ldquoD1rdquo and ldquoE1rdquo are maximum plastic body size dimensions including mold mismatch



RA8806

Figure 7-5 TQFP-80Pin Mechanical



RA8806

Table 7-3 TQFP-80 Package Dimension



A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number

Table 7-4 Part Number

Product Name (Full Name)

Resolution (Max)

Package Font ROM ASCII ROM RoHs

Compliance

RA8806L2N-T Traditional Chinese

(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-S Simple Chinese

(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)

Japanese Kanji ISO-8859-1 ~ 4 Yes

RA8806T1N-T Traditional Chinese

(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-S Simple Chinese

(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)

Japanese Kanji (Note 3)

ISO-8859-1 ~ 4 Yes

RA8806-T Traditional Chinese ISO-8859-1 ~ 4 Yes RA8806-S

320x240 (Note 1)

Die Simple Chinese ISO-8859-1 ~ 4 Yes

Notes

1 In Extension Mode the maximum resolution is 640x240 or 320x480 See Section 6-14 ldquoExtension Mode and Displayrdquo

2 In both Traditional and Simple Chinese font it built-in 52 basic Japanese font 3 LCD driver data bus of RA8806T1N is 4-bits 4 All of the parts of RA008 are RoHS compliance and pass the detection of free PFOS and PFOA

Table 7-5 RA8806L2N vs RA8806T1N

Difference RA8806L2N RA8806T1N

Package LQFP-100Pins 20mm x 14mm

TQFP-80Pins 10mm x 10mm

LCD Data Bus 4-bits or 8-bits 4-bits



RA8806

8 Electrical Characteristic

8-1 Absolute Maximum Ratings

Table 8-1 Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage Range VDD -03 to 65 V

Input Voltage Range VIN -03 to VDD+03 V

Power Dissipation (VDD = 5V) PD ≦30 mW

Operation Temperature Range TOPR -30 to +85

Storage Temperature TST -45 to +125

Soldering temperature (10 seconds) See Note 1 TSOLDER 260

Notes 1 The humidity resistance of the flat package may be reduced if the package is immersed in

solder Use a soldering technique that does not heat stress the package 2 If the power supply has a high impedance a large voltage differential can occur between the

input and supply voltages Take appropriate care with the power supply and the layout of the supply lines

3 All supply voltages are referenced to Gnd = 0V




RA8806

8-2 DC Characteristic

Table 8-2 DC Characteristic

Parameter Symbol Min Typ Max Unit Condition

Operating Voltage(1) VDDP VDDH 45 50 55 V VDDP = VDDH

(Refer to Figure 6-31)

Operating Voltage(2) VDDP VDD 24 33 36 V VDDP = VDD VDDH Open(Refer to

Figure 6-30)

Oscillator frequency FOSC 4 8 12 MHz VDD = 5V

External clock frequency FCLK 4 8 12 MHz VDD = 5V

DC to DC Output Voltage VDD 28V 30 33 V Add external 1uF Capacitor

Input Input High Voltage VIH 08xVDD -- VDD V See Note 1 3Input Low Voltage VIL Gnd -- 02xVDD V See Note 1 3Output Output High Voltage VOH VDD-04 -- VDD V See Note 2 3Output Low Voltage VOL Gnd -- VDD+04 V See Note 2 3Schmitt-trigger Output High Voltage VOH 05xVDD 07xVDD 08xVDD V See Note 4 Output Low Voltage VOL 02xVDD 03xVDD 05xVDD V See Note 4 Input Leakage Current 1 IIH -- -- +1 μA Input Leakage Current 2 IIL -- -- -1 μA Operation Current IOPR 1 5 10 mA

-- 15 18 mA Case1 Standby Mode Current (Normal Mode Current)

ISB 18 21 mA Case2

-- 120 140 μA Case1 Display Off Current IDISPLAY

140 160 μA Case2 -- 05 1 μA Case1

Sleep Mode ISLP -- 20 25 μA Case2

Notes 1 ZCS1 CS2 ZWR ZRD RS MI DW DB KIN[70] TESTMD and TESTI are inputs KIN[70]

built-in pull up resistors The TESTMD and TESTI built-in pull down resistors 2 INT BUSY CLK_OUT PWM_OUT KOUT[70] LP FR YD ZDOFF XCK and LD[70] are

outputs 3 DATA[70] are Bi-direction 4 The ZRST are Schmitt-trigger with pull-up input The pulse width on ZRST must be at least

1024tc Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel

Case1 VDDP = VDD = AVDD = 33V VDDH = NC LCD Driver VDD = 5V CLK = 4MHz CLK_OUT

Off Segment=160 Common=160 FRM = 78Hz TA=25 Case2 VDDP = VDDH = 5V VDD = AVDD = 3V LCD Driver VDD = 33V CLK = 4MHz CLK_OUT

Off Segment=160 Common=160 FRM = 78Hz TA=25


RA8806

8-3 Timing Characteristic Wavaform

Figure 8-1 is timing characteristic waveform and parameters for RA8806 driver interface signal

LP

XD[70] LAST DATA TOP DATA

tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

Figure 8-1 Timing Characteristic Waveform

Table 8-3 Parameters

2nstWCK2 -10tLSLatch Clock Rise to Shift Pulse Rise Time

2nstWCK2 -10tLHLatch Clock Rise to Shift Pulse Rise Time

nstWCK2 +10tWCK2 -10tSLShift Clock Fall to Latch Pulse Fall Time

ns0tLDShift Clock Rise to Latch Pulse Rise Time

nstWCK+10tWCK-10tWLPHLatch Pulse ldquoHrdquo Pulse Width

nstWCK2 +30tWCK2tDHData Hold Time

nstWCK2tWCK2 -30tDSData Setup Time

nstWCK2 +10tWCK2 -10tWCKLShift Clock ldquoLrdquo Pulse Width

nstWCK2 +10tWCK2 -10tWCKHShift Clock ldquoHrdquo Pulse Width

1nsTsysDtWCKShift Clock period

NoteUnitMaxTypMinconditionSymbolParameter












Note

1 Tsys system clock period(ie System clock = 12MHz Tsys = 833ns)

D Driver clock selection(REG[01h] B3-2) 0 0 XCK = CLK8 0 1 XCK = CLK4（initial value） 1 0 XCK = CLK2 1 1 XCK = CLK

2The period also depends on the setting of register ITCR



RA8806


Appendix A Application Circuit

Figure A-1 Application Circuit for 3V or 5V


RA8806


Appendix B Frame Rate Table

Table B-1 Frame Rate Table(1) XCK=CLK2

REG[01h] Bit[32] = 10 XCK=CLK4


REG[01h] Bit[32] = 00 Seg Com CLK (MHz) Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65

Table B-2 Frame Rate Table(2)


RA8806

XCK=CLK2 REG[01h] Bit[32] = 10



Seg Com CLK (MHz) Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) ITCR Frame Rate (Hz)

REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253

Note The value of ITCR is in decimal




RA8806

Appendix C Font Table - ASCII When Bit-7 of register ldquoFNCRrdquo is ldquo0rdquo the contents of ASCII Block Tables 1-4 are show as following Table C-1~ Table C-3

Table C-1 ASCII Block 1

0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806

When Bit-7 of register ldquoFNCRrdquo is ldquo1rdquo the contents of ASCII Block Tables 1-4 are show as following Table C-5 ~ Table C-8 Table C-5 shows the standard character encoding of ISOIEC 8859-1 ISO means International Organization for Standardization The ISO 8859-1 also less formally called ldquoLatin-1rdquo is he first eight-bits coded character sets that developed by the ISO It refers to ASCII that consisting of 192 characters from the Latin script in range 0xA0-0xFF This character encoding is used throughout Western Europe includes Albanian Afrikaans Breton Danish Faroese Frisian Galician German Greenlandic Icelandic Irish Italian Latin Luxembourgish Norwegian Portuguese Rhaeto-Romanic Scottish Gaelic Spanish Swedish English letters with no accent marks also can use ISO 8859-1 In addition it also commonly used in many languages outside Europe such as Swahili Indonesian Malaysian and Tagalog

Table C-5 ASCII Block 1(ISO 8859-1)

i


RA8806

Table C-6 shows the standard characters of ISOIEC 8859-2 ISO 8859-2 also cited as Latin-2 is the part 2 of the eight-bits coded character sets developed by ISOIEC 8859 These code values can be used in almost any data interchange system to communicate in the following European languages Croatian Czech Hungarian Polish Slovak Slovenian and Upper Sorbian The Serbian English German Latin can use ISO 8859-2 as well Furthermore it is suitable to represent some western European languages like Finnish (with the exception of aring used in Swedish and Finnish)





RA8806

Table C-7 shows the standard characters of ISOIEC 8859-3 ISO 8859-3 also known as Latin-3 or ldquoSouth Europeanrdquo is an eight-bits character encoding third part of the ISO 8859 standard It was designed originally to cover Turkish Maltese and Esperanto though the introduction of ISO 8859-9 superseded it for Turkish The encoding remains popular with users of Esperanto and Maltese though it also supports English German Italian Latin and Portuguese


i


RA8806

Table C-8 shows the standard characters of ISOIEC 8859-4 ISO 8859-4 is known as Latin-4 or ldquo North Europeanrdquois the forth part of the ISO 8859 eight-bits character encoding It was designed originally to cover Estonian Greenlandic Latvian Lithuanian and Sami This character set also supports Danish English Finnish German Latin Norwegian Slovenian and Swedish




RA8806


Appendix D Font Table - GB Code


RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806




RA8806

Appendix E Font Table - BIG-5 Code

A1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ 4 hellip 5 middot ｜ ndash ︱ mdash ︳︴﹏（）︵ 6 ︶｛｝︷︸［］︹︺【】︻︼《》︽ 7 ︾〈〉＾﹀「」﹁﹂『』﹃﹄ ﹙ ﹚ Ａ ﹛ ﹜ ﹝ ﹞ lsquo rsquo ldquo rdquo 〝〞 prime Ｂ sect Ｃ macr ￣＿ ˍ ﹍﹎＋Ｄ－ times divide plusmn radic ＜＞＝ ≦ ≧ ne infin ≒ equiv ﹢ ﹣ Ｅ ﹤ ﹥ ﹦ ～ cap cup perp ang ∟ ⊿ int ∮ ∵ there4 Ｆ uarr darr larr rarr ∥ ∣

A2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ 4 frasl ＄￥￠￡ ﹩ 5 deg 兙兛兞兝兡兣嗧 6 瓩糎 7 Ａ 0 Ｂ 1 2 3 4 5 6 7 8 9 Ⅰ Ⅱ Ⅲ Ⅳ Ⅴ Ⅵ Ⅶ Ｃ Ⅷ Ⅸ Ⅹ 〡〢〣〤〥〦〧〨〩十卄卅ＡＤＢＣＤＥＦＧＨＩＪＫＬＭＮＯＰＱＥＲＳＴＵＶＷＸＹＺａｂｃｄｅｆｇＦｈｉｊｋｌｍｎｏｐｑｒｓｔｕｖ

A3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ 4 ｗｘｙｚ Α Β Γ Δ Ε Ζ Η Θ Ι Κ Λ Μ 5 Ν Ξ Ο Π Ρ Σ Τ Υ Φ Χ Ψ Ω α β γ δ 6 ε ζ η θ ι κ λ μ ν ξ ο π ρ σ τ υ 7 φ χ ψ ω ㄅㄆㄇㄈㄉㄊㄋㄌㄍㄎㄏＡㄐㄑㄒㄓㄔㄕㄖㄗㄘㄙㄚㄛㄜㄝㄞＢㄟㄠㄡㄢㄣㄤㄥㄦㄧㄨㄩ ˊ ˇ ˋ ＣＤＥ euro Ｆ


RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 一乙丁七乃九了二人儿入八几刀刁力

5 匕十卜又三下丈上丫丸凡久么也乞于

6 亡兀刃勺千叉口土士夕大女子孑孓寸

7 小尢尸山川工己已巳巾干廾弋弓才Ａ丑丐不中丰丹之尹予云井互五亢仁

Ｂ什仃仆仇仍今介仄元允內六兮公冗凶

Ｃ分切刈勻勾勿化匹午升卅卞厄友及反

Ｄ壬天夫太夭孔少尤尺屯巴幻廿弔引心

Ｅ戈戶手扎支文斗斤方日曰月木欠止歹

Ｆ毋比毛氏水火爪父爻片牙牛犬王丙

A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 世丕且丘主乍乏乎以付仔仕他仗代令

5 仙仞充兄冉冊冬凹出凸刊加功包匆北

6 匝仟半卉卡占卯卮去可古右召叮叩叨

7 叼司叵叫另只史叱台句叭叻四囚外Ａ央失奴奶孕它尼巨巧左市布平幼弁

Ｂ弘弗必戊打扔扒扑斥旦朮本未末札正

Ｃ母民氐永汁汀氾犯玄玉瓜瓦甘生用甩

Ｄ田由甲申疋白皮皿目矛矢石示禾穴立

Ｅ丞丟乒乓乩亙交亦亥仿伉伙伊伕伍伐

Ｆ休伏仲件任仰仳份企伋光兇兆先全

A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 共再冰列刑划刎刖劣匈匡匠印危吉吏

5 同吊吐吁吋各向名合吃后吆吒因回囝

6 圳地在圭圬圯圩夙多夷夸妄奸妃好她

7 如妁字存宇守宅安寺尖屹州帆并年Ａ式弛忙忖戎戌戍成扣扛托收早旨旬

Ｂ旭曲曳有朽朴朱朵次此死氖汝汗汙江

Ｃ池汐汕污汛汍汎灰牟牝百竹米糸缶羊

Ｄ羽老考而耒耳聿肉肋肌臣自至臼舌舛

Ｅ舟艮色艾虫血行衣西阡串亨位住佇佗

Ｆ佞伴佛何估佐佑伽伺伸佃佔似但佣

Example The BIG-5 code of ldquo中rdquo is A4 A4 and BIG-5 code of ldquo世rdquo is A5 40




RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 作你伯低伶余佝佈佚兌克免兵冶冷別

5 判利刪刨劫助努劬匣即卵吝吭吞吾否

6 呎吧呆呃吳呈呂君吩告吹吻吸吮吵吶

7 吠吼呀吱含吟听囪困囤囫坊坑址坍Ａ均坎圾坐坏圻壯夾妝妒妨妞妣妙妖

Ｂ妍妤妓妊妥孝孜孚孛完宋宏尬局屁尿

Ｃ尾岐岑岔岌巫希序庇床廷弄弟彤形彷

Ｄ役忘忌志忍忱快忸忪戒我抄抗抖技扶

Ｅ抉扭把扼找批扳抒扯折扮投抓抑抆改

Ｆ攻攸旱更束李杏材村杜杖杞杉杆杠

A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 杓杗步每求汞沙沁沈沉沅沛汪決沐汰

5 沌汨沖沒汽沃汲汾汴沆汶沍沔沘沂灶

6 灼災灸牢牡牠狄狂玖甬甫男甸皂盯矣

7 私秀禿究系罕肖肓肝肘肛肚育良芒Ａ芋芍見角言谷豆豕貝赤走足身車辛

Ｂ辰迂迆迅迄巡邑邢邪邦那酉釆里防阮

Ｃ阱阪阬並乖乳事些亞享京佯依侍佳使

Ｄ佬供例來侃佰併侈佩佻侖佾侏侑佺兔

Ｅ兒兕兩具其典冽函刻券刷刺到刮制剁

Ｆ劾劻卒協卓卑卦卷卸卹取叔受味呵

A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 咖呸咕咀呻呷咄咒咆呼咐呱呶和咚呢

5 周咋命咎固垃坷坪坩坡坦坤坼夜奉奇

6 奈奄奔妾妻委妹妮姑姆姐姍始姓姊妯

7 妳姒姅孟孤季宗定官宜宙宛尚屈居Ａ屆岷岡岸岩岫岱岳帘帚帖帕帛帑幸

Ｂ庚店府底庖延弦弧弩往征彿彼忝忠忽

Ｃ念忿怏怔怯怵怖怪怕怡性怩怫怛或戕

Ｄ房戾所承拉拌拄抿拂抹拒招披拓拔拋

Ｅ拈抨抽押拐拙拇拍抵拚抱拘拖拗拆抬

Ｆ拎放斧於旺昔易昌昆昂明昀昏昕昊


RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 昇服朋杭枋枕東果杳杷枇枝林杯杰板

5 枉松析杵枚枓杼杪杲欣武歧歿氓氛泣

6 注泳沱泌泥河沽沾沼波沫法泓沸泄油

7 況沮泗泅泱沿治泡泛泊沬泯泜泖泠Ａ炕炎炒炊炙爬爭爸版牧物狀狎狙狗

Ｂ狐玩玨玟玫玥甽疝疙疚的盂盲直知矽

Ｃ社祀祁秉秈空穹竺糾罔羌羋者肺肥肢

Ｄ肱股肫肩肴肪肯臥臾舍芳芝芙芭芽芟

Ｅ芹花芬芥芯芸芣芰芾芷虎虱初表軋迎

Ｆ返近邵邸邱邶采金長門阜陀阿阻附

AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 陂隹雨青非亟亭亮信侵侯便俠俑俏保

5 促侶俘俟俊俗侮俐俄係俚俎俞侷兗冒

6 冑冠剎剃削前剌剋則勇勉勃勁匍南卻

7 厚叛咬哀咨哎哉咸咦咳哇哂咽咪品Ａ哄哈咯咫咱咻咩咧咿囿垂型垠垣垢

Ｂ城垮垓奕契奏奎奐姜姘姿姣姨娃姥姪

Ｃ姚姦威姻孩宣宦室客宥封屎屏屍屋峙

Ｄ峒巷帝帥帟幽庠度建弈弭彥很待徊律

Ｅ徇後徉怒思怠急怎怨恍恰恨恢恆恃恬

Ｆ恫恪恤扁拜挖按拼拭持拮拽指拱拷

AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 拯括拾拴挑挂政故斫施既春昭映昧是

5 星昨昱昤曷柿染柱柔某柬架枯柵柩柯

6 柄柑枴柚查枸柏柞柳枰柙柢柝柒歪殃

7 殆段毒毗氟泉洋洲洪流津洌洱洞洗Ａ活洽派洶洛泵洹洧洸洩洮洵洎洫炫

Ｂ為炳炬炯炭炸炮炤爰牲牯牴狩狠狡玷

Ｃ珊玻玲珍珀玳甚甭畏界畎畋疫疤疥疢

Ｄ疣癸皆皇皈盈盆盃盅省盹相眉看盾盼

Ｅ眇矜砂研砌砍祆祉祈祇禹禺科秒秋穿

Ｆ突竿竽籽紂紅紀紉紇約紆缸美羿耄




RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 耐耍耑耶胖胥胚胃胄背胡胛胎胞胤胝

5 致舢苧范茅苣苛苦茄若茂茉苒苗英茁

6 苜苔苑苞苓苟苯茆虐虹虻虺衍衫要觔

7 計訂訃貞負赴赳趴軍軌述迦迢迪迥Ａ迭迫迤迨郊郎郁郃酋酊重閂限陋陌

Ｂ降面革韋韭音頁風飛食首香乘亳倌倍

Ｃ倣俯倦倥俸倩倖倆值借倚倒們俺倀倔

Ｄ倨俱倡個候倘俳修倭倪俾倫倉兼冤冥

Ｅ冢凍凌准凋剖剜剔剛剝匪卿原厝叟哨

Ｆ唐唁唷哼哥哲唆哺唔哩哭員唉哮哪

AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 哦唧唇哽唏圃圄埂埔埋埃堉夏套奘奚

5 娑娘娜娟娛娓姬娠娣娩娥娌娉孫屘宰

6 害家宴宮宵容宸射屑展屐峭峽峻峪峨

7 峰島崁峴差席師庫庭座弱徒徑徐恙Ａ恣恥恐恕恭恩息悄悟悚悍悔悌悅悖

Ｂ扇拳挈拿捎挾振捕捂捆捏捉挺捐挽挪

Ｃ挫挨捍捌效敉料旁旅時晉晏晃晒晌晅

Ｄ晁書朔朕朗校核案框桓根桂桔栩梳栗

Ｅ桌桑栽柴桐桀格桃株桅栓栘桁殊殉殷

Ｆ氣氧氨氦氤泰浪涕消涇浦浸海浙涓

AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 浬涉浮浚浴浩涌涊浹涅浥涔烊烘烤烙

5 烈烏爹特狼狹狽狸狷玆班琉珮珠珪珞

6 畔畝畜畚留疾病症疲疳疽疼疹痂疸皋

7 皰益盍盎眩真眠眨矩砰砧砸砝破砷Ａ砥砭砠砟砲祕祐祠祟祖神祝祗祚秤

Ｂ秣秧租秦秩秘窄窈站笆笑粉紡紗紋紊

Ｃ素索純紐紕級紜納紙紛缺罟羔翅翁耆

Ｄ耘耕耙耗耽耿胱脂胰脅胭胴脆胸胳脈

Ｅ能脊胼胯臭臬舀舐航舫舨般芻茫荒荔

Ｆ荊茸荐草茵茴荏茲茹茶茗荀茱茨荃


RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 虔蚊蚪蚓蚤蚩蚌蚣蚜衰衷袁袂衽衹記

5 訐討訌訕訊託訓訖訏訑豈豺豹財貢起

6 躬軒軔軏辱送逆迷退迺迴逃追逅迸邕

7 郡郝郢酒配酌釘針釗釜釙閃院陣陡Ａ陛陝除陘陞隻飢馬骨高鬥鬲鬼乾偺

Ｂ偽停假偃偌做偉健偶偎偕偵側偷偏倏

Ｃ偯偭兜冕凰剪副勒務勘動匐匏匙匿區

Ｄ匾參曼商啪啦啄啞啡啃啊唱啖問啕唯

Ｅ啤唸售啜唬啣唳啁啗圈國圉域堅堊堆

Ｆ埠埤基堂堵執培夠奢娶婁婉婦婪婀

B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 娼婢婚婆婊孰寇寅寄寂宿密尉專將屠

5 屜屝崇崆崎崛崖崢崑崩崔崙崤崧崗巢

6 常帶帳帷康庸庶庵庾張強彗彬彩彫得

7 徙從徘御徠徜恿患悉悠您惋悴惦悽Ａ情悻悵惜悼惘惕惆惟悸惚惇戚戛扈

Ｂ掠控捲掖探接捷捧掘措捱掩掉掃掛捫

Ｃ推掄授掙採掬排掏掀捻捩捨捺敝敖救

Ｄ教敗啟敏敘敕敔斜斛斬族旋旌旎晝晚

Ｅ晤晨晦晞曹勗望梁梯梢梓梵桿桶梱梧

Ｆ梗械梃棄梭梆梅梔條梨梟梡梂欲殺

B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 毫毬氫涎涼淳淙液淡淌淤添淺清淇淋

5 涯淑涮淞淹涸混淵淅淒渚涵淚淫淘淪

6 深淮淨淆淄涪淬涿淦烹焉焊烽烯爽牽

7 犁猜猛猖猓猙率琅琊球理現琍瓠瓶Ａ瓷甜產略畦畢異疏痔痕疵痊痍皎盔

Ｂ盒盛眷眾眼眶眸眺硫硃硎祥票祭移窒

Ｃ窕笠笨笛第符笙笞笮粒粗粕絆絃統紮

Ｄ紹紼絀細紳組累終紲紱缽羞羚翌翎習

Ｅ耜聊聆脯脖脣脫脩脰脤舂舵舷舶船莎

Ｆ莞莘荸莢莖莽莫莒莊莓莉莠荷荻荼



RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 莆莧處彪蛇蛀蚶蛄蚵蛆蛋蚱蚯蛉術袞

5 袈被袒袖袍袋覓規訪訝訣訥許設訟訛

6 訢豉豚販責貫貨貪貧赧赦趾趺軛軟這

7 逍通逗連速逝逐逕逞造透逢逖逛途Ａ部郭都酗野釵釦釣釧釭釩閉陪陵陳

Ｂ陸陰陴陶陷陬雀雪雩章竟頂頃魚鳥鹵

Ｃ鹿麥麻傢傍傅備傑傀傖傘傚最凱割剴

Ｄ創剩勞勝勛博厥啻喀喧啼喊喝喘喂喜

Ｅ喪喔喇喋喃喳單喟唾喲喚喻喬喱啾喉

Ｆ喫喙圍堯堪場堤堰報堡堝堠壹壺奠

B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 婷媚婿媒媛媧孳孱寒富寓寐尊尋就嵌

5 嵐崴嵇巽幅帽幀幃幾廊廁廂廄弼彭復

6 循徨惑惡悲悶惠愜愣惺愕惰惻惴慨惱

7 愎惶愉愀愒戟扉掣掌描揀揩揉揆揍Ａ插揣提握揖揭揮捶援揪換摒揚揹敞

Ｂ敦敢散斑斐斯普晰晴晶景暑智晾晷曾

Ｃ替期朝棺棕棠棘棗椅棟棵森棧棹棒棲

Ｄ棣棋棍植椒椎棉棚楮棻款欺欽殘殖殼

Ｅ毯氮氯氬港游湔渡渲湧湊渠渥渣減湛

Ｆ湘渤湖湮渭渦湯渴湍渺測湃渝渾滋

B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 溉渙湎湣湄湲湩湟焙焚焦焰無然煮焜

5 牌犄犀猶猥猴猩琺琪琳琢琥琵琶琴琯

6 琛琦琨甥甦畫番痢痛痣痙痘痞痠登發

7 皖皓皴盜睏短硝硬硯稍稈程稅稀窘Ａ窗窖童竣等策筆筐筒答筍筋筏筑粟

Ｂ粥絞結絨絕紫絮絲絡給絢絰絳善翔翕

Ｃ耋聒肅腕腔腋腑腎脹腆脾腌腓腴舒舜

Ｄ菩萃菸萍菠菅萋菁華菱菴著萊菰萌菌

Ｅ菽菲菊萸萎萄菜萇菔菟虛蛟蛙蛭蛔蛛

Ｆ蛤蛐蛞街裁裂袱覃視註詠評詞証詁



RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 詔詛詐詆訴診訶詖象貂貯貼貳貽賁費

5 賀貴買貶貿貸越超趁跎距跋跚跑跌跛

6 跆軻軸軼辜逮逵週逸進逶鄂郵鄉郾酣

7 酥量鈔鈕鈣鈉鈞鈍鈐鈇鈑閔閏開閑Ａ間閒閎隊階隋陽隅隆隍陲隄雁雅雄

Ｂ集雇雯雲韌項順須飧飪飯飩飲飭馮馭

Ｃ黃黍黑亂傭債傲傳僅傾催傷傻傯僇剿

Ｄ剷剽募勦勤勢勣匯嗟嗨嗓嗦嗎嗜嗇嗑

Ｅ嗣嗤嗯嗚嗡嗅嗆嗥嗉園圓塞塑塘塗塚

Ｆ塔填塌塭塊塢塒塋奧嫁嫉嫌媾媽媼

B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 媳嫂媲嵩嵯幌幹廉廈弒彙徬微愚意慈

5 感想愛惹愁愈慎慌慄慍愾愴愧愍愆愷

6 戡戢搓搾搞搪搭搽搬搏搜搔損搶搖搗

7 搆敬斟新暗暉暇暈暖暄暘暍會榔業Ａ楚楷楠楔極椰概楊楨楫楞楓楹榆楝

Ｂ楣楛歇歲毀殿毓毽溢溯滓溶滂源溝滇

Ｃ滅溥溘溼溺溫滑準溜滄滔溪溧溴煎煙

Ｄ煩煤煉照煜煬煦煌煥煞煆煨煖爺牒猷

Ｅ獅猿猾瑯瑚瑕瑟瑞瑁琿瑙瑛瑜當畸瘀

Ｆ痰瘁痲痱痺痿痴痳盞盟睛睫睦睞督

B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 睹睪睬睜睥睨睢矮碎碰碗碘碌碉硼碑

5 碓硿祺祿禁萬禽稜稚稠稔稟稞窟窠筷

6 節筠筮筧粱粳粵經絹綑綁綏絛置罩罪

7 署義羨群聖聘肆肄腱腰腸腥腮腳腫Ａ腹腺腦舅艇蒂葷落萱葵葦葫葉葬葛

Ｂ萼萵葡董葩葭葆虞虜號蛹蜓蜈蜇蜀蛾

Ｃ蛻蜂蜃蜆蜊衙裟裔裙補裘裝裡裊裕裒

Ｄ覜解詫該詳試詩詰誇詼詣誠話誅詭詢

Ｅ詮詬詹詻訾詨豢貊貉賊資賈賄貲賃賂

Ｆ賅跡跟跨路跳跺跪跤跦躲較載軾輊



RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 辟農運遊道遂達逼違遐遇遏過遍遑逾

5 遁鄒鄗酬酪酩釉鈷鉗鈸鈽鉀鈾鉛鉋鉤

6 鉑鈴鉉鉍鉅鈹鈿鉚閘隘隔隕雍雋雉雊

7 雷電雹零靖靴靶預頑頓頊頒頌飼飴Ａ飽飾馳馱馴髡鳩麂鼎鼓鼠僧僮僥僖

Ｂ僭僚僕像僑僱僎僩兢凳劃劂匱厭嗾嘀

Ｃ嘛嘗嗽嘔嘆嘉嘍嘎嗷嘖嘟嘈嘐嗶團圖

Ｄ塵塾境墓墊塹墅塽壽夥夢夤奪奩嫡嫦

Ｅ嫩嫗嫖嫘嫣孵寞寧寡寥實寨寢寤察對

Ｆ屢嶄嶇幛幣幕幗幔廓廖弊彆彰徹慇

BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 愿態慷慢慣慟慚慘慵截撇摘摔撤摸摟

5 摺摑摧搴摭摻敲斡旗旖暢暨暝榜榨榕

6 槁榮槓構榛榷榻榫榴槐槍榭槌榦槃榣

7 歉歌氳漳演滾漓滴漩漾漠漬漏漂漢Ａ滿滯漆漱漸漲漣漕漫漯澈漪滬漁滲

Ｂ滌滷熔熙煽熊熄熒爾犒犖獄獐瑤瑣瑪

Ｃ瑰瑭甄疑瘧瘍瘋瘉瘓盡監瞄睽睿睡磁

Ｄ碟碧碳碩碣禎福禍種稱窪窩竭端管箕

Ｅ箋筵算箝箔箏箸箇箄粹粽精綻綰綜綽

Ｆ綾綠緊綴網綱綺綢綿綵綸維緒緇綬

BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 罰翠翡翟聞聚肇腐膀膏膈膊腿膂臧臺

5 與舔舞艋蓉蒿蓆蓄蒙蒞蒲蒜蓋蒸蓀蓓

6 蒐蒼蓑蓊蜿蜜蜻蜢蜥蜴蜘蝕蜷蜩裳褂

7 裴裹裸製裨褚裯誦誌語誣認誡誓誤Ａ說誥誨誘誑誚誧豪貍貌賓賑賒赫趙

Ｂ趕跼輔輒輕輓辣遠遘遜遣遙遞遢遝遛

Ｃ鄙鄘鄞酵酸酷酴鉸銀銅銘銖鉻銓銜銨

Ｄ鉼銑閡閨閩閣閥閤隙障際雌雒需靼鞅

Ｅ韶頗領颯颱餃餅餌餉駁骯骰髦魁魂鳴

Ｆ鳶鳳麼鼻齊億儀僻僵價儂儈儉儅凜




RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 劇劈劉劍劊勰厲嘮嘻嘹嘲嘿嘴嘩噓噎

5 噗噴嘶嘯嘰墀墟增墳墜墮墩墦奭嬉嫻

6 嬋嫵嬌嬈寮寬審寫層履嶝嶔幢幟幡廢

7 廚廟廝廣廠彈影德徵慶慧慮慝慕憂Ａ慼慰慫慾憧憐憫憎憬憚憤憔憮戮摩

Ｂ摯摹撞撲撈撐撰撥撓撕撩撒撮播撫撚

Ｃ撬撙撢撳敵敷數暮暫暴暱樣樟槨樁樞

Ｄ標槽模樓樊槳樂樅槭樑歐歎殤毅毆漿

Ｅ潼澄潑潦潔澆潭潛潸潮澎潺潰潤澗潘

Ｆ滕潯潠潟熟熬熱熨牖犛獎獗瑩璋璃

BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 瑾璀畿瘠瘩瘟瘤瘦瘡瘢皚皺盤瞎瞇瞌

5 瞑瞋磋磅確磊碾磕碼磐稿稼穀稽稷稻

6 窯窮箭箱範箴篆篇篁箠篌糊締練緯緻

7 緘緬緝編緣線緞緩綞緙緲緹罵罷羯Ａ翩耦膛膜膝膠膚膘蔗蔽蔚蓮蔬蔭蔓

Ｂ蔑蔣蔡蔔蓬蔥蓿蔆螂蝴蝶蝠蝦蝸蝨蝙

Ｃ蝗蝌蝓衛衝褐複褒褓褕褊誼諒談諄誕

Ｄ請諸課諉諂調誰論諍誶誹諛豌豎豬賠

Ｅ賞賦賤賬賭賢賣賜質賡赭趟趣踫踐踝

Ｆ踢踏踩踟踡踞躺輝輛輟輩輦輪輜輞

BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 輥適遮遨遭遷鄰鄭鄧鄱醇醉醋醃鋅銻

5 銷鋪銬鋤鋁銳銼鋒鋇鋰銲閭閱霄霆震

6 霉靠鞍鞋鞏頡頫頜颳養餓餒餘駝駐駟

7 駛駑駕駒駙骷髮髯鬧魅魄魷魯鴆鴉Ａ鴃麩麾黎墨齒儒儘儔儐儕冀冪凝劑

Ｂ劓勳噙噫噹噩噤噸噪器噥噱噯噬噢噶

Ｃ壁墾壇壅奮嬝嬴學寰導彊憲憑憩憊懍

Ｄ憶憾懊懈戰擅擁擋撻撼據擄擇擂操撿

Ｅ擒擔撾整曆曉暹曄曇暸樽樸樺橙橫橘

Ｆ樹橄橢橡橋橇樵機橈歙歷氅濂澱澡


RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 濃澤濁澧澳激澹澶澦澠澴熾燉燐燒燈

5 燕熹燎燙燜燃燄獨璜璣璘璟璞瓢甌甍

6 瘴瘸瘺盧盥瞠瞞瞟瞥磨磚磬磧禦積穎

7 穆穌穋窺篙簑築篤篛篡篩篦糕糖縊Ａ縑縈縛縣縞縝縉縐罹羲翰翱翮耨膳

Ｂ膩膨臻興艘艙蕊蕙蕈蕨蕩蕃蕉蕭蕪蕞

Ｃ螃螟螞螢融衡褪褲褥褫褡親覦諦諺諫

Ｄ諱謀諜諧諮諾謁謂諷諭諳諶諼豫豭貓

Ｅ賴蹄踱踴蹂踹踵輻輯輸輳辨辦遵遴選

Ｆ遲遼遺鄴醒錠錶鋸錳錯錢鋼錫錄錚

C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 錐錦錡錕錮錙閻隧隨險雕霎霑霖霍霓

5 霏靛靜靦鞘頰頸頻頷頭頹頤餐館餞餛

6 餡餚駭駢駱骸骼髻髭鬨鮑鴕鴣鴦鴨鴒

7 鴛默黔龍龜優償儡儲勵嚎嚀嚐嚅嚇Ａ嚏壕壓壑壎嬰嬪嬤孺尷屨嶼嶺嶽嶸

Ｂ幫彌徽應懂懇懦懋戲戴擎擊擘擠擰擦

Ｃ擬擱擢擭斂斃曙曖檀檔檄檢檜櫛檣橾

Ｄ檗檐檠歜殮毚氈濘濱濟濠濛濤濫濯澀

Ｅ濬濡濩濕濮濰燧營燮燦燥燭燬燴燠爵

Ｆ牆獰獲璩環璦璨癆療癌盪瞳瞪瞰瞬

C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 瞧瞭矯磷磺磴磯礁禧禪穗窿簇簍篾篷

5 簌篠糠糜糞糢糟糙糝縮績繆縷縲繃縫

6 總縱繅繁縴縹繈縵縿縯罄翳翼聱聲聰

7 聯聳臆臃膺臂臀膿膽臉膾臨舉艱薪Ａ薄蕾薜薑薔薯薛薇薨薊虧蟀蟑螳蟒

Ｂ蟆螫螻螺蟈蟋褻褶襄褸褽覬謎謗謙講

Ｃ謊謠謝謄謐豁谿豳賺賽購賸賻趨蹉蹋

Ｄ蹈蹊轄輾轂轅輿避遽還邁邂邀鄹醣醞

Ｅ醜鍍鎂錨鍵鍊鍥鍋錘鍾鍬鍛鍰鍚鍔闊

Ｆ闋闌闈闆隱隸雖霜霞鞠韓顆颶餵騁



RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 駿鮮鮫鮪鮭鴻鴿麋黏點黜黝黛鼾齋叢

5 嚕嚮壙壘嬸彝懣戳擴擲擾攆擺擻擷斷

6 曜朦檳檬櫃檻檸櫂檮檯歟歸殯瀉瀋濾

7 瀆濺瀑瀏燻燼燾燸獷獵璧璿甕癖癘Ａ癒瞽瞿瞻瞼礎禮穡穢穠竄竅簫簧簪

Ｂ簞簣簡糧織繕繞繚繡繒繙罈翹翻職聶

Ｃ臍臏舊藏薩藍藐藉薰薺薹薦蟯蟬蟲蟠

Ｄ覆覲觴謨謹謬謫豐贅蹙蹣蹦蹤蹟蹕軀

Ｅ轉轍邇邃邈醫醬釐鎔鎊鎖鎢鎳鎮鎬鎰

Ｆ鎘鎚鎗闔闖闐闕離雜雙雛雞霤鞣鞦

C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 鞭韹額顏題顎顓颺餾餿餽餮馥騎髁鬃

5 鬆魏魎魍鯊鯉鯽鯈鯀鵑鵝鵠黠鼕鼬儳

6 嚥壞壟壢寵龐廬懲懷懶懵攀攏曠曝櫥

7 櫝櫚櫓瀛瀟瀨瀚瀝瀕瀘爆爍牘犢獸Ａ獺璽瓊瓣疇疆癟癡矇礙禱穫穩簾簿

Ｂ簸簽簷籀繫繭繹繩繪羅繳羶羹羸臘藩

Ｃ藝藪藕藤藥藷蟻蠅蠍蟹蟾襠襟襖襞譁

Ｄ譜識證譚譎譏譆譙贈贊蹼蹲躇蹶蹬蹺

Ｅ蹴轔轎辭邊邋醱醮鏡鏑鏟鏃鏈鏜鏝鏖

Ｆ鏢鏍鏘鏤鏗鏨關隴難霪霧靡韜韻類

C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 願顛颼饅饉騖騙鬍鯨鯧鯖鯛鶉鵡鵲鵪

5 鵬麒麗麓麴勸嚨嚷嚶嚴嚼壤孀孃孽寶

6 巉懸懺攘攔攙曦朧櫬瀾瀰瀲爐獻瓏癢

7 癥礦礪礬礫竇競籌籃籍糯糰辮繽繼Ａ纂罌耀臚艦藻藹蘑藺蘆蘋蘇蘊蠔蠕

Ｂ襤覺觸議譬警譯譟譫贏贍躉躁躅躂醴

Ｃ釋鐘鐃鏽闡霰飄饒饑馨騫騰騷騵鰓鰍

Ｄ鹹麵黨鼯齟齣齡儷儸囁囀囂夔屬巍懼

Ｅ懾攝攜斕曩櫻欄櫺殲灌爛犧瓖瓔癩矓

Ｆ籐纏續羼蘗蘭蘚蠣蠢蠡蠟襪襬覽譴



RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 護譽贓躊躍躋轟辯醺鐮鐳鐵鐺鐸鐲鐫

5 闢霸霹露響顧顥饗驅驃驀騾髏魔魑鰭

6 鰥鶯鶴鷂鶸麝黯鼙齜齦齧儼儻囈囊囉

7 孿巔巒彎懿攤權歡灑灘玀瓤疊癮癬Ａ禳籠籟聾聽臟襲襯觼讀贖贗躑躓轡

Ｂ酈鑄鑑鑒霽霾韃韁顫饕驕驍髒鬚鱉鰱

Ｃ鰾鰻鷓鷗鼴齬齪龔囌巖戀攣攫攪曬欐

Ｄ瓚竊籤籣籥纓纖纔臢蘸蘿蠱變邐邏鑣

Ｅ鑠鑤靨顯饜驚驛驗髓體髑鱔鱗鱖鷥麟

Ｆ黴囑壩攬灞癱癲矗罐羈蠶蠹衢讓讒

C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 讖艷贛釀鑪靂靈靄韆顰驟鬢魘鱟鷹鷺

5 鹼鹽鼇齷齲廳欖灣籬籮蠻觀躡釁鑲鑰

6 顱饞髖鬣黌灤矚讚鑷韉驢驥纜讜躪釅

7 鑽鑾鑼鱷鱸黷豔鑿鸚爨驪鬱鸛鸞籲ＡＢ　　　　　　　　　ヽ

ＣＤヽヾゝゞＥ々〆〇ーぁあぃいぅうぇえぉ

Ｆおかがきぎくぐけげこごさざしじ

C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 すずせぜそぞただちぢっつづてでと

5 どなにぬねのはばぱひびぴふぶぷへ

6 べぺほぼぽまみむめもゃやゅゆょよ

7 らりるれろゎわゐゑをんァアィイＡゥウェエォオカガキギクグケゲコ

Ｂゴサザシジスズセゼソゾタダチヂッ

Ｃツヅテデトドナニヌネノハバパヒビ

Ｄピフブプヘベペホボポマミムメモャ

Ｅヤュユョヨラリルレロヮワヰヱヲン

Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 乂乜凵匚厂万丌乇亍囗兀屮彳丏冇与

5 丮亓仂仉仈冘勼卬厹圠夃夬尐巿旡殳

6 毌气爿丱丼仨仜仩仡仝仚刌匜卌圢圣

7 夗夯宁宄尒尻屴屳帄庀庂忉戉扐氕Ａ氶汃氿氻犮犰玊禸肊阞伎优伬仵伔

Ｂ仱伀价伈伝伂伅伢伓伄仴伒冱刓刉刐

Ｃ劦匢匟卍厊吇囡囟圮圪圴夼妀奼妅奻

Ｄ奾奷奿孖尕尥屼屺屻屾巟幵庄异弚彴

Ｅ忕忔忏扜扞扤扡扦扢扙扠扚扥旯旮朾

Ｆ朹朸朻机朿朼朳氘汆汒汜汏汊汔汋

CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 汌灱牞犴犵玎甪癿穵网艸艼芀艽艿虍

5 襾邙邗邘邛邔阢阤阠阣佖伻佢佉体佤

6 伾佧佒佟佁佘伭伳伿佡冏冹刜刞刡劭

7 劮匉卣卲厎厏吰吷吪呔呅吙吜吥吘Ａ吽呏呁吨吤呇囮囧囥坁坅坌坉坋坒

Ｂ夆奀妦妘妠妗妎妢妐妏妧妡宎宒尨尪

Ｃ岍岏岈岋岉岒岊岆岓岕巠帊帎庋庉庌

Ｄ庈庍弅弝彸彶忒忑忐忭忨忮忳忡忤忣

Ｅ忺忯忷忻怀忴戺抃抌抎抏抔抇扱扻扺

Ｆ扰抁抈扷扽扲扴攷旰旴旳旲旵杅杇



RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 杙杕杌杈杝杍杚杋毐氙氚汸汧汫沄沋

5 沏汱汯汩沚汭沇沕沜汦汳汥汻沎灴灺

6 牣犿犽狃狆狁犺狅玕玗玓玔玒町甹疔

7 疕皁礽耴肕肙肐肒肜芐芏芅芎芑芓Ａ芊芃芄豸迉辿邟邡邥邞邧邠阰阨阯

Ｂ阭丳侘佼侅佽侀侇佶佴侉侄佷佌侗佪

Ｃ侚佹侁佸侐侜侔侞侒侂侕佫佮冞冼冾

Ｄ刵刲刳剆刱劼匊匋匼厒厔咇呿咁咑咂

Ｅ咈呫呺呾呥呬呴呦咍呯呡呠咘呣呧呤

Ｆ囷囹坯坲坭坫坱坰坶垀坵坻坳坴坢

CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 坨坽夌奅妵妺姏姎妲姌姁妶妼姃姖妱

5 妽姀姈妴姇孢孥宓宕屄屇岮岤岠岵岯

6 岨岬岟岣岭岢岪岧岝岥岶岰岦帗帔帙

7 弨弢弣弤彔徂彾彽忞忥怭怦怙怲怋Ａ怴怊怗怳怚怞怬怢怍怐怮怓怑怌怉

Ｂ怜戔戽抭抴拑抾抪抶拊抮抳抯抻抩抰

Ｃ抸攽斨斻昉旼昄昒昈旻昃昋昍昅旽昑

Ｄ昐曶朊枅杬枎枒杶杻枘枆构杴枍枌杺

Ｅ枟枑枙枃杽极杸杹枔欥殀歾毞氝沓泬

Ｆ泫泮泙沶泔沭泧沷泐泂沺泃泆泭泲

CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 泒泝沴沊沝沀泞泀洰泍泇沰泹泏泩泑

5 炔炘炅炓炆炄炑炖炂炚炃牪狖狋狘狉

6 狜狒狔狚狌狑玤玡玭玦玢玠玬玝瓝瓨

7 甿畀甾疌疘皯盳盱盰盵矸矼矹矻矺Ａ矷祂礿秅穸穻竻籵糽耵肏肮肣肸肵

Ｂ肭舠芠苀芫芚芘芛芵芧芮芼芞芺芴芨

Ｃ芡芩苂芤苃芶芢虰虯虭虮豖迒迋迓迍

Ｄ迖迕迗邲邴邯邳邰阹阽阼阺陃俍俅俓

Ｅ侲俉俋俁俔俜俙侻侳俛俇俖侺俀侹俬

Ｆ剄剉勀勂匽卼厗厖厙厘咺咡咭咥哏



RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 哃茍咷咮哖咶哅哆咠呰咼咢咾呲哞咰

5 垵垞垟垤垌垗垝垛垔垘垏垙垥垚垕壴

6 复奓姡姞姮娀姱姝姺姽姼姶姤姲姷姛

7 姩姳姵姠姾姴姭宨屌峐峘峌峗峋峛Ａ峞峚峉峇峊峖峓峔峏峈峆峎峟峸巹

Ｂ帡帢帣帠帤庰庤庢庛庣庥弇弮彖徆怷

Ｃ怹恔恲恞恅恓恇恉恛恌恀恂恟怤恄恘

Ｄ恦恮扂扃拏挍挋拵挎挃拫拹挏挌拸拶

Ｅ挀挓挔拺挕拻拰敁敃斪斿昶昡昲昵昜

Ｆ昦昢昳昫昺昝昴昹昮朏朐柁柲柈枺

CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 柜枻柸柘柀枷柅柫柤柟枵柍枳柷柶柮

5 柣柂枹柎柧柰枲柼柆柭柌枮柦柛柺柉

6 柊柃柪柋欨殂殄殶毖毘毠氠氡洨洴洭

7 洟洼洿洒洊泚洳洄洙洺洚洑洀洝浂Ａ洁洘洷洃洏浀洇洠洬洈洢洉洐炷炟

Ｂ炾炱炰炡炴炵炩牁牉牊牬牰牳牮狊狤

Ｃ狨狫狟狪狦狣玅珌珂珈珅玹玶玵玴珫

Ｄ玿珇玾珃珆玸珋瓬瓮甮畇畈疧疪癹盄

Ｅ眈眃眄眅眊盷盻盺矧矨砆砑砒砅砐砏

Ｆ砎砉砃砓祊祌祋祅祄秕种秏秖秎窀

D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 穾竑笀笁籺籸籹籿粀粁紃紈紁罘羑羍

5 羾耇耎耏耔耷胘胇胠胑胈胂胐胅胣胙

6 胜胊胕胉胏胗胦胍臿舡芔苙苾苹茇苨

7 茀苕茺苫苖苴苬苡苲苵茌苻苶苰苪Ａ苤苠苺苳苭虷虴虼虳衁衎衧衪衩觓

Ｂ訄訇赲迣迡迮迠郱邽邿郕郅邾郇郋郈

Ｃ釔釓陔陏陑陓陊陎倞倅倇倓倢倰倛俵

Ｄ俴倳倷倬俶俷倗倜倠倧倵倯倱倎党冔

Ｅ冓凊凄凅凈凎剡剚剒剞剟剕剢勍匎厞

Ｆ唦哢唗唒哧哳哤唚哿唄唈哫唑唅哱



RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 唊哻哷哸哠唎唃唋圁圂埌堲埕埒垺埆

5 垽垼垸垶垿埇埐垹埁夎奊娙娖娭娮娕

6 娏娗娊娞娳孬宧宭宬尃屖屔峬峿峮峱

7 峷崀峹帩帨庨庮庪庬弳弰彧恝恚恧Ａ恁悢悈悀悒悁悝悃悕悛悗悇悜悎戙

Ｂ扆拲挐捖挬捄捅挶捃揤挹捋捊挼挩捁

Ｃ挴捘捔捙挭捇挳捚捑挸捗捀捈敊敆旆

Ｄ旃旄旂晊晟晇晑朒朓栟栚桉栲栳栻桋

Ｅ桏栖栱栜栵栫栭栯桎桄栴栝栒栔栦栨

Ｆ栮桍栺栥栠欬欯欭欱欴歭肂殈毦毤

D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 毨毣毢毧氥浺浣浤浶洍浡涒浘浢浭浯

5 涑涍淯浿涆浞浧浠涗浰浼浟涂涘洯浨

6 涋浾涀涄洖涃浻浽浵涐烜烓烑烝烋缹

7 烢烗烒烞烠烔烍烅烆烇烚烎烡牂牸Ａ牷牶猀狺狴狾狶狳狻猁珓珙珥珖玼

Ｂ珧珣珩珜珒珛珔珝珚珗珘珨瓞瓟瓴瓵

Ｃ甡畛畟疰痁疻痄痀疿疶疺皊盉眝眛眐

Ｄ眓眒眣眑眕眙眚眢眧砣砬砢砵砯砨砮

Ｅ砫砡砩砳砪砱祔祛祏祜祓祒祑秫秬秠

Ｆ秮秭秪秜秞秝窆窉窅窋窌窊窇竘笐

D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 笄笓笅笏笈笊笎笉笒粄粑粊粌粈粍粅

5 紞紝紑紎紘紖紓紟紒紏紌罜罡罞罠罝

6 罛羖羒翃翂翀耖耾耹胺胲胹胵脁胻脀

7 舁舯舥茳茭荄茙荑茥荖茿荁茦茜茢Ａ荂荎茛茪茈茼荍茖茤茠茷茯茩荇荅

Ｂ荌荓茞茬荋茧荈虓虒蚢蚨蚖蚍蚑蚞蚇

Ｃ蚗蚆蚋蚚蚅蚥蚙蚡蚧蚕蚘蚎蚝蚐蚔衃

Ｄ衄衭衵衶衲袀衱衿衯袃衾衴衼訒豇豗

Ｅ豻貤貣赶赸趵趷趶軑軓迾迵适迿迻逄

Ｆ迼迶郖郠郙郚郣郟郥郘郛郗郜郤酐



RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 酎酏釕釢釚陜陟隼飣髟鬯乿偰偪偡偞

5 偠偓偋偝偲偈偍偁偛偊偢倕偅偟偩偫

6 偣偤偆偀偮偳偗偑凐剫剭剬剮勖勓匭

7 厜啵啶唼啍啐唴唪啑啢唶唵唰啒啅Ａ唌唲啥啎唹啈唭唻啀啋圊圇埻堔埢

Ｂ埶埜埴堀埭埽堈埸堋埳埏堇埮埣埲埥

Ｃ埬埡堎埼堐埧堁堌埱埩埰堍堄奜婠婘

Ｄ婕婧婞娸娵婭婐婟婥婬婓婤婗婃婝婒

Ｅ婄婛婈媎娾婍娹婌婰婩婇婑婖婂婜孲

Ｆ孮寁寀屙崞崋崝崚崠崌崨崍崦崥崏

D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 崰崒崣崟崮帾帴庱庴庹庲庳弶弸徛徖

5 徟悊悐悆悾悰悺惓惔惏惤惙惝惈悱惛

6 悷惊悿惃惍惀挲捥掊掂捽掽掞掭掝掗

7 掫掎捯掇掐据掯捵掜捭掮捼掤挻掟Ａ捸掅掁掑掍捰敓旍晥晡晛晙晜晢朘

Ｂ桹梇梐梜桭桮梮梫楖桯梣梬梩桵桴梲

Ｃ梏桷梒桼桫桲梪梀桱桾梛梖梋梠梉梤

Ｄ桸桻梑梌梊桽欶欳欷欸殑殏殍殎殌氪

Ｅ淀涫涴涳湴涬淩淢涷淶淔渀淈淠淟淖

Ｆ涾淥淜淝淛淴淊涽淭淰涺淕淂淏淉

D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 淐淲淓淽淗淍淣涻烺焍烷焗烴焌烰焄

5 烳焐烼烿焆焓焀烸烶焋焂焎牾牻牼牿

6 猝猗猇猑猘猊猈狿猏猞玈珶珸珵琄琁

7 珽琇琀珺珼珿琌琋珴琈畤畣痎痒痏Ａ痋痌痑痐皏皉盓眹眯眭眱眲眴眳眽

Ｂ眥眻眵硈硒硉硍硊硌砦硅硐祤祧祩祪

Ｃ祣祫祡离秺秸秶秷窏窔窐笵筇笴笥笰

Ｄ笢笤笳笘笪笝笱笫笭笯笲笸笚笣粔粘

Ｅ粖粣紵紽紸紶紺絅紬紩絁絇紾紿絊紻

Ｆ紨罣羕羜羝羛翊翋翍翐翑翇翏翉耟



RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 耞耛聇聃聈脘脥脙脛脭脟脬脞脡脕脧

5 脝脢舑舸舳舺舴舲艴莐莣莨莍荺荳莤

6 荴莏莁莕莙荵莔莩荽莃莌莝莛莪莋荾

7 莥莯莈莗莰荿莦莇莮荶莚虙虖蚿蚷Ａ蛂蛁蛅蚺蚰蛈蚹蚳蚸蛌蚴蚻蚼蛃蚽

Ｂ蚾衒袉袕袨袢袪袚袑袡袟袘袧袙袛袗

Ｃ袤袬袌袓袎覂觖觙觕訰訧訬訞谹谻豜

Ｄ豝豽貥赽赻赹趼跂趹趿跁軘軞軝軜軗

Ｅ軠軡逤逋逑逜逌逡郯郪郰郴郲郳郔郫

Ｆ郬郩酖酘酚酓酕釬釴釱釳釸釤釹釪

D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 釫釷釨釮镺閆閈陼陭陫陱陯隿靪頄飥

5 馗傛傕傔傞傋傣傃傌傎傝偨傜傒傂傇

6 兟凔匒匑厤厧喑喨喥喭啷噅喢喓喈喏

7 喵喁喣喒喤啽喌喦啿喕喡喎圌堩堷Ａ堙堞堧堣堨埵塈堥堜堛堳堿堶堮堹

Ｂ堸堭堬堻奡媯媔媟婺媢媞婸媦婼媥媬

Ｃ媕媮娷媄媊媗媃媋媩婻婽媌媜媏媓媝

Ｄ寪寍寋寔寑寊寎尌尰崷嵃嵫嵁嵋崿崵

Ｅ嵑嵎嵕崳崺嵒崽崱嵙嵂崹嵉崸崼崲崶

Ｆ嵀嵅幄幁彘徦徥徫惉悹惌惢惎惄愔

D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 惲愊愖愅惵愓惸惼惾惁愃愘愝愐惿愄

5 愋扊掔掱掰揎揥揨揯揃撝揳揊揠揶揕

6 揲揵摡揟掾揝揜揄揘揓揂揇揌揋揈揰

7 揗揙攲敧敪敤敜敨敥斌斝斞斮旐旒Ａ晼晬晻暀晱晹晪晲朁椌棓椄棜椪棬

Ｂ棪棱椏棖棷棫棤棶椓椐棳棡椇棌椈楰

Ｃ梴椑棯棆椔棸棐棽棼棨椋椊椗棎棈棝

Ｄ棞棦棴棑椆棔棩椕椥棇欹欻欿欼殔殗

Ｅ殙殕殽毰毲毳氰淼湆湇渟湉溈渼渽湅

Ｆ湢渫渿湁湝湳渜渳湋湀湑渻渃渮湞



RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 湨湜湡渱渨湠湱湫渹渢渰湓湥渧湸湤

5 湷湕湹湒湦渵渶湚焠焞焯烻焮焱焣焥

6 焢焲焟焨焺焛牋牚犈犉犆犅犋猒猋猰

7 猢猱猳猧猲猭猦猣猵猌琮琬琰琫琖Ａ琚琡琭琱琤琣琝琩琠琲瓻甯畯畬痧

Ｂ痚痡痦痝痟痤痗皕皒盚睆睇睄睍睅睊

Ｃ睎睋睌矞矬硠硤硥硜硭硱硪确硰硩硨

Ｄ硞硢祴祳祲祰稂稊稃稌稄窙竦竤筊笻

Ｅ筄筈筌筎筀筘筅粢粞粨粡絘絯絣絓絖

Ｆ絧絪絏絭絜絫絒絔絩絑絟絎缾缿罥

DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 罦羢羠羡翗聑聏聐胾胔腃腊腒腏腇脽

5 腍脺臦臮臷臸臹舄舼舽舿艵茻菏菹萣

6 菀菨萒菧菤菼菶萐菆菈菫菣莿萁菝菥

7 菘菿菡菋菎菖菵菉萉萏菞萑萆菂菳Ａ菕菺菇菑菪萓菃菬菮菄菻菗菢萛菛

Ｂ菾蛘蛢蛦蛓蛣蛚蛪蛝蛫蛜蛬蛩蛗蛨蛑

Ｃ衈衖衕袺裗袹袸裀袾袶袼袷袽袲褁裉

Ｄ覕覘覗觝觚觛詎詍訹詙詀詗詘詄詅詒

Ｅ詈詑詊詌詏豟貁貀貺貾貰貹貵趄趀趉

Ｆ跘跓跍跇跖跜跏跕跙跈跗跅軯軷軺

DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 軹軦軮軥軵軧軨軶軫軱軬軴軩逭逴逯

5 鄆鄬鄄郿郼鄈郹郻鄁鄀鄇鄅鄃酡酤酟

6 酢酠鈁鈊鈥鈃鈚鈦鈏鈌鈀鈒釿釽鈆鈄

7 鈧鈂鈜鈤鈙鈗鈅鈖镻閍閌閐隇陾隈Ａ隉隃隀雂雈雃雱雰靬靰靮頇颩飫鳦

Ｂ黹亃亄亶傽傿僆傮僄僊傴僈僂傰僁傺

Ｃ傱僋僉傶傸凗剺剸剻剼嗃嗛嗌嗐嗋嗊

Ｄ嗝嗀嗔嗄嗩喿嗒喍嗏嗕嗢嗖嗈嗲嗍嗙

Ｅ嗂圔塓塨塤塏塍塉塯塕塎塝塙塥塛堽

Ｆ塣塱壼嫇嫄嫋媺媸媱媵媰媿嫈媻嫆



RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 媷嫀嫊媴媶嫍媹媐寖寘寙尟尳嵱嵣嵊

5 嵥嵲嵬嵞嵨嵧嵢巰幏幎幊幍幋廅廌廆

6 廋廇彀徯徭惷慉慊愫慅愶愲愮慆愯慏

7 愩慀戠酨戣戥戤揅揱揫搐搒搉搠搤Ａ搳摃搟搕搘搹搷搢搣搌搦搰搨摁搵

Ｂ搯搊搚摀搥搧搋揧搛搮搡搎敯斒旓暆

Ｃ暌暕暐暋暊暙暔晸朠楦楟椸楎楢楱椿

Ｄ楅楪椹楂楗楙楺楈楉椵楬椳椽楥棰楸

Ｅ椴楩楀楯楄楶楘楁楴楌椻楋椷楜楏楑

Ｆ椲楒椯楻椼歆歅歃歂歈歁殛嗀毻毼

DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 毹毷毸溛滖滈溏滀溟溓溔溠溱溹滆滒

5 溽滁溞滉溷溰滍溦滏溲溾滃滜滘溙溒

6 溎溍溤溡溿溳滐滊溗溮溣煇煔煒煣煠

7 煁煝煢煲煸煪煡煂煘煃煋煰煟煐煓Ａ煄煍煚牏犍犌犑犐犎猼獂猻猺獀獊

Ｂ獉瑄瑊瑋瑒瑑瑗瑀瑏瑐瑎瑂瑆瑍瑔瓡

Ｃ瓿瓾瓽甝畹畷榃痯瘏瘃痷痾痼痹痸瘐

Ｄ痻痶痭痵痽皙皵盝睕睟睠睒睖睚睩睧

Ｅ睔睙睭矠碇碚碔碏碄碕碅碆碡碃硹碙

Ｆ碀碖硻祼禂祽祹稑稘稙稒稗稕稢稓

DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 稛稐窣窢窞竫筦筤筭筴筩筲筥筳筱筰

5 筡筸筶筣粲粴粯綈綆綀綍絿綅絺綎絻

6 綃絼綌綔綄絽綒罭罫罧罨罬羦羥羧翛

7 翜耡腤腠腷腜腩腛腢腲朡腞腶腧腯Ａ腄腡舝艉艄艀艂艅蓱萿葖葶葹蒏蒍

Ｂ葥葑葀蒆葧萰葍葽葚葙葴葳葝蔇葞萷

Ｃ萺萴葺葃葸萲葅萩菙葋萯葂萭葟葰萹

Ｄ葎葌葒葯蓅蒎萻葇萶萳葨葾葄萫葠葔

Ｅ葮葐蜋蜄蛷蜌蛺蛖蛵蝍蛸蜎蜉蜁蛶蜍

Ｆ蜅裖裋裍裎裞裛裚裌裐覅覛觟觥觤



RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 觡觠觢觜触詶誆詿詡訿詷誂誄詵誃誁

5 詴詺谼豋豊豥豤豦貆貄貅賌赨赩趑趌

6 趎趏趍趓趔趐趒跰跠跬跱跮跐跩跣跢

7 跧跲跫跴輆軿輁輀輅輇輈輂輋遒逿Ａ遄遉逽鄐鄍鄏鄑鄖鄔鄋鄎酮酯鉈鉒

Ｂ鈰鈺鉦鈳鉥鉞銃鈮鉊鉆鉭鉬鉏鉠鉧鉯

Ｃ鈶鉡鉰鈱鉔鉣鉐鉲鉎鉓鉌鉖鈲閟閜閞

Ｄ閛隒隓隑隗雎雺雽雸雵靳靷靸靲頏頍

Ｅ頎颬飶飹馯馲馰馵骭骫魛鳪鳭鳧麀黽

Ｆ僦僔僗僨僳僛僪僝僤僓僬僰僯僣僠

E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 凘劀劁勩勫匰厬嘧嘕嘌嘒嗼嘏嘜嘁嘓

5 嘂嗺嘝嘄嗿嗹墉塼墐墘墆墁塿塴墋塺

6 墇墑墎塶墂墈塻墔墏壾奫嫜嫮嫥嫕嫪

7 嫚嫭嫫嫳嫢嫠嫛嫬嫞嫝嫙嫨嫟孷寠Ａ寣屣嶂嶀嵽嶆嵺嶁嵷嶊嶉嶈嵾嵼嶍

Ｂ嵹嵿幘幙幓廘廑廗廎廜廕廙廒廔彄彃

Ｃ彯徶愬愨慁慞慱慳慒慓慲慬憀慴慔慺

Ｄ慛慥愻慪慡慖戩戧戫搫摍摛摝摴摶摲

Ｅ摳摽摵摦撦摎撂摞摜摋摓摠摐摿搿摬

Ｆ摫摙摥摷敳斠暡暠暟朅朄朢榱榶槉

E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 榠槎榖榰榬榼榑榙榎榧榍榩榾榯榿槄

5 榽榤槔榹槊榚槏榳榓榪榡榞槙榗榐槂

6 榵榥槆歊歍歋殞殟殠毃毄毾滎滵滱漃

7 漥滸漷滻漮漉潎漙漚漧漘漻漒滭漊Ａ漶潳滹滮漭潀漰漼漵滫漇漎潃漅滽

Ｂ滶漹漜滼漺漟漍漞漈漡熇熐熉熀熅熂

Ｃ熏煻熆熁熗牄牓犗犕犓獃獍獑獌瑢瑳

Ｄ瑱瑵瑲瑧瑮甀甂甃畽疐瘖瘈瘌瘕瘑瘊

Ｅ瘔皸瞁睼瞅瞂睮瞀睯睾瞃碲碪碴碭碨

Ｆ硾碫碞碥碠碬碢碤禘禊禋禖禕禔禓



RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 禗禈禒禐稫穊稰稯稨稦窨窫窬竮箈箜

5 箊箑箐箖箍箌箛箎箅箘劄箙箤箂粻粿

6 粼粺綧綷緂綣綪緁緀緅綝緎緄緆緋緌

7 綯綹綖綼綟綦綮綩綡緉罳翢翣翥翞Ａ耤聝聜膉膆膃膇膍膌膋舕蒗蒤蒡蒟

Ｂ蒺蓎蓂蒬蒮蒫蒹蒴蓁蓍蒪蒚蒱蓐蒝蒧

Ｃ蒻蒢蒔蓇蓌蒛蒩蒯蒨蓖蒘蒶蓏蒠蓗蓔

Ｄ蓒蓛蒰蒑虡蜳蜣蜨蝫蝀蜮蜞蜡蜙蜛蝃

Ｅ蜬蝁蜾蝆蜠蜲蜪蜭蜼蜒蜺蜱蜵蝂蜦蜧

Ｆ蜸蜤蜚蜰蜑裷裧裱裲裺裾裮裼裶裻

E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 裰裬裫覝覡覟覞觩觫觨誫誙誋誒誏誖

5 谽豨豩賕賏賗趖踉踂跿踍跽踊踃踇踆

6 踅跾踀踄輐輑輎輍鄣鄜鄠鄢鄟鄝鄚鄤

7 鄡鄛酺酲酹酳銥銤鉶銛鉺銠銔銪銍Ａ銦銚銫鉹銗鉿銣鋮銎銂銕銢鉽銈銡

Ｂ銊銆銌銙銧鉾銇銩銝銋鈭隞隡雿靘靽

Ｃ靺靾鞃鞀鞂靻鞄鞁靿韎韍頖颭颮餂餀

Ｄ餇馝馜駃馹馻馺駂馽駇骱髣髧鬾鬿魠

Ｅ魡魟鳱鳲鳵麧僿儃儰僸儆儇僶僾儋儌

Ｆ僽儊劋劌勱勯噈噂噌嘵噁噊噉噆噘

E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 噚噀嘳嘽嘬嘾嘸嘪嘺圚墫墝墱墠墣墯

5 墬墥墡壿嫿嫴嫽嫷嫶嬃嫸嬂嫹嬁嬇嬅

6 嬏屧嶙嶗嶟嶒嶢嶓嶕嶠嶜嶡嶚嶞幩幝

7 幠幜緳廛廞廡彉徲憋憃慹憱憰憢憉Ａ憛憓憯憭憟憒憪憡憍慦憳戭摮摰撖

Ｂ撠撅撗撜撏撋撊撌撣撟摨撱撘敶敺敹

Ｃ敻斲斳暵暰暩暲暷暪暯樀樆樗槥槸樕

Ｄ槱槤樠槿槬槢樛樝槾樧槲槮樔槷槧橀

Ｅ樈槦槻樍槼槫樉樄樘樥樏槶樦樇槴樖

Ｆ歑殥殣殢殦氁氀毿氂潁漦潾澇濆澒



RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 澍澉澌潢潏澅潚澖潶潬澂潕潲潒潐潗

5 澔澓潝漀潡潫潽潧澐潓澋潩潿澕潣潷

6 潪潻熲熯熛熰熠熚熩熵熝熥熞熤熡熪

7 熜熧熳犘犚獘獒獞獟獠獝獛獡獚獙Ａ獢璇璉璊璆璁瑽璅璈瑼瑹甈甇畾瘥

Ｂ瘞瘙瘝瘜瘣瘚瘨瘛皜皝皞皛瞍瞏瞉瞈

Ｃ磍碻磏磌磑磎磔磈磃磄磉禚禡禠禜禢

Ｄ禛歶稹窲窴窳箷篋箾箬篎箯箹篊箵糅

Ｅ糈糌糋緷緛緪緧緗緡縃緺緦緶緱緰緮

Ｆ緟罶羬羰羭翭翫翪翬翦翨聤聧膣膟

E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 膞膕膢膙膗舖艏艓艒艐艎艑蔤蔻蔏蔀

5 蔩蔎蔉蔍蔟蔊蔧蔜蓻蔫蓺蔈蔌蓴蔪蓲

6 蔕蓷蓫蓳蓼蔒蓪蓩蔖蓾蔨蔝蔮蔂蓽蔞

7 蓶蔱蔦蓧蓨蓰蓯蓹蔘蔠蔰蔋蔙蔯虢Ａ蝖蝣蝤蝷蟡蝳蝘蝔蝛蝒蝡蝚蝑蝞蝭

Ｂ蝪蝐蝎蝟蝝蝯蝬蝺蝮蝜蝥蝏蝻蝵蝢蝧

Ｃ蝩衚褅褌褔褋褗褘褙褆褖褑褎褉覢覤

Ｄ覣觭觰觬諏諆誸諓諑諔諕誻諗誾諀諅

Ｅ諘諃誺誽諙谾豍貏賥賟賙賨賚賝賧趠

Ｆ趜趡趛踠踣踥踤踮踕踛踖踑踙踦踧

E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 踔踒踘踓踜踗踚輬輤輘輚輠輣輖輗遳

5 遰遯遧遫鄯鄫鄩鄪鄲鄦鄮醅醆醊醁醂

6 醄醀鋐鋃鋄鋀鋙銶鋏鋱鋟鋘鋩鋗鋝鋌

7 鋯鋂鋨鋊鋈鋎鋦鋍鋕鋉鋠鋞鋧鋑鋓Ａ銵鋡鋆銴镼閬閫閮閰隤隢雓霅霈霂

Ｂ靚鞊鞎鞈韐韏頞頝頦頩頨頠頛頧颲餈

Ｃ飺餑餔餖餗餕駜駍駏駓駔駎駉駖駘駋

Ｄ駗駌骳髬髫髳髲髱魆魃魧魴魱魦魶魵

Ｅ魰魨魤魬鳼鳺鳽鳿鳷鴇鴀鳹鳻鴈鴅鴄

Ｆ麃黓鼏鼐儜儓儗儚儑凞匴叡噰噠噮



RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 噳噦噣噭噲噞噷圜圛壈墽壉墿墺壂墼

5 壆嬗嬙嬛嬡嬔嬓嬐嬖嬨嬚嬠嬞寯嶬嶱

6 嶩嶧嶵嶰嶮嶪嶨嶲嶭嶯嶴幧幨幦幯廩

7 廧廦廨廥彋徼憝憨憖懅憴懆懁懌憺Ａ憿憸憌擗擖擐擏擉撽撉擃擛擳擙攳

Ｂ敿敼斢曈暾曀曊曋曏暽暻暺曌朣樴橦

Ｃ橉橧樲橨樾橝橭橶橛橑樨橚樻樿橁橪

Ｄ橤橐橏橔橯橩橠樼橞橖橕橍橎橆歕歔

Ｅ歖殧殪殫毈毇氄氃氆澭濋澣濇澼濎濈

Ｆ潞濄澽澞濊澨瀄澥澮澺澬澪濏澿澸

EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 澢濉澫濍澯澲澰燅燂熿熸燖燀燁燋燔

5 燊燇燏熽燘熼燆燚燛犝犞獩獦獧獬獥

6 獫獪瑿璚璠璔璒璕璡甋疀瘯瘭瘱瘽瘳

7 瘼瘵瘲瘰皻盦瞚瞝瞡瞜瞛瞢瞣瞕瞙Ａ瞗磝磩磥磪磞磣磛磡磢磭磟磠禤穄

Ｂ穈穇窶窸窵窱窷篞篣篧篝篕篥篚篨篹

Ｃ篔篪篢篜篫篘篟糒糔糗糐糑縒縡縗縌

Ｄ縟縠縓縎縜縕縚縢縋縏縖縍縔縥縤罃

Ｅ罻罼罺羱翯耪耩聬膱膦膮膹膵膫膰膬

Ｆ膴膲膷膧臲艕艖艗蕖蕅蕫蕍蕓蕡蕘

EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 蕀蕆蕤蕁蕢蕄蕑蕇蕣蔾蕛蕱蕎蕮蕵蕕

5 蕧蕠薌蕦蕝蕔蕥蕬虣虥虤螛螏螗螓螒

6 螈螁螖螘蝹螇螣螅螐螑螝螄螔螜螚螉

7 褞褦褰褭褮褧褱褢褩褣褯褬褟觱諠Ａ諢諲諴諵諝謔諤諟諰諈諞諡諨諿諯

Ｂ諻貑貒貐賵賮賱賰賳赬赮趥趧踳踾踸

Ｃ蹀蹅踶踼踽蹁踰踿躽輶輮輵輲輹輷輴

Ｄ遶遹遻邆郺鄳鄵鄶醓醐醑醍醏錧錞錈

Ｅ錟錆錏鍺錸錼錛錣錒錁鍆錭錎錍鋋錝

Ｆ鋺錥錓鋹鋷錴錂錤鋿錩錹錵錪錔錌



RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 錋鋾錉錀鋻錖閼闍閾閹閺閶閿閵閽隩

5 雔霋霒霐鞙鞗鞔韰韸頵頯頲餤餟餧餩

6 馞駮駬駥駤駰駣駪駩駧骹骿骴骻髶髺

7 髹髷鬳鮀鮅鮇魼魾魻鮂鮓鮒鮐魺鮕Ａ魽鮈鴥鴗鴠鴞鴔鴩鴝鴘鴢鴐鴙鴟麈

Ｂ麆麇麮麭黕黖黺鼒鼽儦儥儢儤儠儩勴

Ｃ嚓嚌嚍嚆嚄嚃噾嚂噿嚁壖壔壏壒嬭嬥

Ｄ嬲嬣嬬嬧嬦嬯嬮孻寱寲嶷幬幪徾徻懃

Ｅ憵憼懧懠懥懤懨懞擯擩擣擫擤擨斁斀

Ｆ斶旚曒檍檖檁檥檉檟檛檡檞檇檓檎

ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 檕檃檨檤檑橿檦檚檅檌檒歛殭氉濌澩

5 濴濔濣濜濭濧濦濞濲濝濢濨燡燱燨燲

6 燤燰燢獳獮獯璗璲璫璐璪璭璱璥璯甐

7 甑甒甏疄癃癈癉癇皤盩瞵瞫瞲瞷瞶Ａ瞴瞱瞨矰磳磽礂磻磼磲礅磹磾礄禫

Ｂ禨穜穛穖穘穔穚窾竀竁簅簏篲簀篿篻

Ｃ簎篴簋篳簂簉簃簁篸篽簆篰篱簐簊糨

Ｄ縭縼繂縳顈縸縪繉繀繇縩繌縰縻縶繄

Ｅ縺罅罿罾罽翴翲耬膻臄臌臊臅臇膼臩

Ｆ艛艚艜薃薀薏薧薕薠薋薣蕻薤薚薞

EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 蕷蕼薉薡蕺蕸蕗薎薖薆薍薙薝薁薢薂

5 薈薅蕹蕶薘薐薟虨螾螪螭蟅螰螬螹螵

6 螼螮蟉蟃蟂蟌螷螯蟄蟊螴螶螿螸螽蟞

7 螲褵褳褼褾襁襒褷襂覭覯覮觲觳謞Ａ謘謖謑謅謋謢謏謒謕謇謍謈謆謜謓

Ｂ謚豏豰豲豱豯貕貔賹赯蹎蹍蹓蹐蹌蹇

Ｃ轃轀邅遾鄸醚醢醛醙醟醡醝醠鎡鎃鎯

Ｄ鍤鍖鍇鍼鍘鍜鍶鍉鍐鍑鍠鍭鎏鍌鍪鍹

Ｅ鍗鍕鍒鍏鍱鍷鍻鍡鍞鍣鍧鎀鍎鍙闇闀

Ｆ闉闃闅閷隮隰隬霠霟霘霝霙鞚鞡鞜



RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 鞞鞝韕韔韱顁顄顊顉顅顃餥餫餬餪餳

5 餲餯餭餱餰馘馣馡騂駺駴駷駹駸駶駻

6 駽駾駼騃骾髾髽鬁髼魈鮚鮨鮞鮛鮦鮡

7 鮥鮤鮆鮢鮠鮯鴳鵁鵧鴶鴮鴯鴱鴸鴰Ａ鵅鵂鵃鴾鴷鵀鴽翵鴭麊麉麍麰黈黚

Ｂ黻黿鼤鼣鼢齔龠儱儭儮嚘嚜嚗嚚嚝嚙

Ｃ奰嬼屩屪巀幭幮懘懟懭懮懱懪懰懫懖

Ｄ懩擿攄擽擸攁攃擼斔旛曚曛曘櫅檹檽

Ｅ櫡櫆檺檶檷櫇檴檭歞毉氋瀇瀌瀍瀁瀅

Ｆ瀔瀎濿濻瀦濼濷瀊爁燿燹爃燽獶

F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 璸瓀璵瓁璾璶璻瓂甔甓癜癤癙癐癓癗

5 癚皦皽盬矂瞺磿礌礓礔礉礐礒礑禭禬

6 穟簜簩簙簠簟簭簝簦簨簢簥簰繜繐繖

7 繣繘繢繟繑繠繗繓羵羳翷翸聵臑臒Ａ臐艟艞薴藆藀藃藂薳薵薽藇藄薿藋

Ｂ藎藈藅薱薶藒蘤薸薷薾虩蟧蟦蟢蟛蟫

Ｃ蟪蟥蟟蟳蟤蟔蟜蟓蟭蟘蟣螤蟗蟙蠁蟴

Ｄ蟨蟝襓襋襏襌襆襐襑襉謪謧謣謳謰謵

Ｅ譇謯謼謾謱謥謷謦謶謮謤謻謽謺豂豵

Ｆ貙貘貗賾贄贂贀蹜蹢蹠蹗蹖蹞蹥蹧

F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 蹛蹚蹡蹝蹩蹔轆轇轈轋鄨鄺鄻鄾醨醥

5 醧醯醪鎵鎌鎒鎷鎛鎝鎉鎧鎎鎪鎞鎦鎕

6 鎈鎙鎟鎍鎱鎑鎲鎤鎨鎴鎣鎥闒闓闑隳

7 雗雚巂雟雘雝霣霢霥鞬鞮鞨鞫鞤鞪Ａ鞢鞥韗韙韖韘韺顐顑顒颸饁餼餺騏

Ｂ騋騉騍騄騑騊騅騇騆髀髜鬈鬄鬅鬩鬵

Ｃ魊魌魋鯇鯆鯃鮿鯁鮵鮸鯓鮶鯄鮹鮽鵜

Ｄ鵓鵏鵊鵛鵋鵙鵖鵌鵗鵒鵔鵟鵘鵚麎麌

Ｅ黟鼁鼀鼖鼥鼫鼪鼩鼨齌齕儴儵劖勷厴

Ｆ嚫嚭嚦嚧嚪嚬壚壝壛夒嬽嬾嬿巃幰



RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 徿懻攇攐攍攉攌攎斄旞旝曞櫧櫠櫌櫑

5 櫙櫋櫟櫜櫐櫫櫏櫍櫞歠殰氌瀙瀧瀠瀖

6 瀫瀡瀢瀣瀩瀗瀤瀜瀪爌爊爇爂爅犥犦

7 犤犣犡瓋瓅璷瓃甖癠矉矊矄矱礝礛Ａ礡礜礗礞禰穧穨簳簼簹簬簻糬糪繶

Ｂ繵繸繰繷繯繺繲繴繨罋罊羃羆羷翽翾

Ｃ聸臗臕艤艡艣藫藱藭藙藡藨藚藗藬藲

Ｄ藸藘藟藣藜藑藰藦藯藞藢蠀蟺蠃蟶蟷

Ｅ蠉蠌蠋蠆蟼蠈蟿蠊蠂襢襚襛襗襡襜襘

Ｆ襝襙覈覷覶觶譐譈譊譀譓譖譔譋譕

F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 譑譂譒譗豃豷豶貚贆贇贉趬趪趭趫蹭

5 蹸蹳蹪蹯蹻軂轒轑轏轐轓辴酀鄿醰醭

6 鏞鏇鏏鏂鏚鏐鏹鏬鏌鏙鎩鏦鏊鏔鏮鏣

7 鏕鏄鏎鏀鏒鏧镽闚闛雡霩霫霬霨霦Ａ鞳鞷鞶韝韞韟顜顙顝顗颿颽颻颾饈

Ｂ饇饃馦馧騚騕騥騝騤騛騢騠騧騣騞騜

Ｃ騔髂鬋鬊鬎鬌鬷鯪鯫鯠鯞鯤鯦鯢鯰鯔

Ｄ鯗鯬鯜鯙鯥鯕鯡鯚鵷鶁鶊鶄鶈鵱鶀鵸

Ｅ鶆鶋鶌鵽鵫鵴鵵鵰鵩鶅鵳鵻鶂鵯鵹鵿

Ｆ鶇鵨麔麑黀黼鼭齀齁齍齖齗齘匷嚲

F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 嚵嚳壣孅巆巇廮廯忀忁懹攗攖攕攓旟

5 曨曣曤櫳櫰櫪櫨櫹櫱櫮櫯瀼瀵瀯瀷瀴

6 瀱灂瀸瀿瀺瀹灀瀻瀳灁爓爔犨獽獼璺

7 皫皪皾盭矌矎矏矍矲礥礣礧礨礤礩Ａ禲穮穬穭竷籉籈籊籇籅糮繻繾纁纀

Ｂ羺翿聹臛臙舋艨艩蘢藿蘁藾蘛蘀藶蘄

Ｃ蘉蘅蘌藽蠙蠐蠑蠗蠓蠖襣襦覹觷譠譪

Ｄ譝譨譣譥譧譭趮躆躈躄轙轖轗轕轘轚

Ｅ邍酃酁醷醵醲醳鐋鐓鏻鐠鐏鐔鏾鐕鐐

Ｆ鐨鐙鐍鏵鐀鏷鐇鐎鐖鐒鏺鐉鏸鐊鏿



RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 鏼鐌鏶鐑鐆闞闠闟霮霯鞹鞻韽韾顠顢

5 顣顟飁飂饐饎饙饌饋饓騲騴騱騬騪騶

6 騩騮騸騭髇髊髆鬐鬒鬑鰋鰈鯷鰅鰒鯸

7 鱀鰇鰎鰆鰗鰔鰉鶟鶙鶤鶝鶒鶘鶐鶛Ａ鶠鶔鶜鶪鶗鶡鶚鶢鶨鶞鶣鶿鶩鶖鶦

Ｂ鶧麙麛麚黥黤黧黦鼰鼮齛齠齞齝齙龑

Ｃ儺儹劘劗囃嚽嚾孈孇巋巏廱懽攛欂櫼

Ｄ欃櫸欀灃灄灊灈灉灅灆爝爚爙獾甗癪

Ｅ矐礭礱礯籔籓糲纊纇纈纋纆纍罍羻耰

Ｆ臝蘘蘪蘦蘟蘣蘜蘙蘧蘮蘡蘠蘩蘞蘥

F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 蠩蠝蠛蠠蠤蠜蠫衊襭襩襮襫觺譹譸譅

5 譺譻贐贔趯躎躌轞轛轝酆酄酅醹鐿鐻

6 鐶鐩鐽鐼鐰鐹鐪鐷鐬鑀鐱闥闤闣霵霺

7 鞿韡顤飉飆飀饘饖騹騽驆驄驂驁騺Ａ騿髍鬕鬗鬘鬖鬺魒鰫鰝鰜鰬鰣鰨鰩

Ｂ鰤鰡鶷鶶鶼鷁鷇鷊鷏鶾鷅鷃鶻鶵鷎鶹

Ｃ鶺鶬鷈鶱鶭鷌鶳鷍鶲鹺麜黫黮黭鼛鼘

Ｄ鼚鼱齎齥齤龒亹囆囅囋奱孋孌巕巑廲

Ｅ攡攠攦攢欋欈欉氍灕灖灗灒爞爟犩獿

Ｆ瓘瓕瓙瓗癭皭礵禴穰穱籗籜籙籛籚

F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 糴糱纑罏羇臞艫蘴蘵蘳蘬蘲蘶蠬蠨蠦

5 蠪蠥襱覿覾觻譾讄讂讆讅譿贕躕躔躚

6 躒躐躖躗轠轢酇鑌鑐鑊鑋鑏鑇鑅鑈鑉

7 鑆霿韣顪顩飋饔饛驎驓驔驌驏驈驊Ａ驉驒驐髐鬙鬫鬻魖魕鱆鱈鰿鱄鰹鰳

Ｂ鱁鰼鰷鰴鰲鰽鰶鷛鷒鷞鷚鷋鷐鷜鷑鷟

Ｃ鷩鷙鷘鷖鷵鷕鷝麶黰鼵鼳鼲齂齫龕龢

Ｄ儽劙壨壧奲孍巘蠯彏戁戃戄攩攥斖曫

Ｅ欑欒欏毊灛灚爢玂玁玃癰矔籧籦纕艬

Ｆ蘺虀蘹蘼蘱蘻蘾蠰蠲蠮蠳襶襴襳觾



RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 讌讎讋讈豅贙躘轤轣醼鑢鑕鑝鑗鑞韄

5 韅頀驖驙鬞鬟鬠鱒鱘鱐鱊鱍鱋鱕鱙鱌

6 鱎鷻鷷鷯鷣鷫鷸鷤鷶鷡鷮鷦鷲鷰鷢鷬

7 鷴鷳鷨鷭黂黐黲黳鼆鼜鼸鼷鼶齃齏Ａ齱齰齮齯囓囍孎屭攭曭曮欓灟灡灝

Ｂ灠爣瓛瓥矕礸禷禶籪纗羉艭虃蠸蠷蠵

Ｃ衋讔讕躞躟躠躝醾醽釂鑫鑨鑩雥靆靃

Ｄ靇韇韥驞髕魙鱣鱧鱦鱢鱞鱠鸂鷾鸇鸃

Ｅ鸆鸅鸀鸁鸉鷿鷽鸄麠鼞齆齴齵齶囔攮

Ｆ斸欘欙欗欚灢爦犪矘矙礹籩籫糶纚

F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 纘纛纙臠臡虆虇虈襹襺襼襻觿讘讙躥

5 躤躣鑮鑭鑯鑱鑳靉顲饟鱨鱮鱭鸋鸍鸐

6 鸏鸒鸑麡黵鼉齇齸齻齺齹圞灦籯蠼趲

7 躦釃鑴鑸鑶鑵驠鱴鱳鱱鱵鸔鸓黶鼊Ａ龤灨灥糷虪蠾蠽蠿讞貜躩軉靋顳顴

Ｂ飌饡馫驤驦驧鬤鸕鸗齈戇欞爧虌躨钂

Ｃ钀钁驩驨鬮鸙爩虋讟钃鱹麷癵驫鱺鸝

Ｄ灩灪麤齾齉龘碁銹裏墻恒粧嫺ＥＦ

FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

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RA8806

Appendix F Font Table - JIS Code

Please refer to the Japanese Kanji font table(RA8806_DS_V12_Font_JISpdf)


2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write

6-1-3 Memory WriteRead

6-1-4 Status Read


6-2-1 Display Resolution

6-2-2 Display Window and Active Window

6-2-3 ComSeg Scan Direction

6-2-4 Idle Time Counter (ITCR)




6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode

6-4-2-1 External Interrupt Mode

6-4-2-2 Polling Mode

6-4-3 Touch Panel Sampling Time Reference Table

6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM


6-10-1 CharacterGraphic Mode


6-10-1-2 Half Size Font


6-10-1-4 Bold and Inverse

6-10-1-5 Two Layer Display

6-10-1-6 Line Gap

6-10-2 Gray Scale Display

6-10-3 Font Size Adjustment and Font Write-Time

6-10-4 Font Vertical Display




6-12 Scroll Function

6-12-1 Horizontal Scrolling

6-12-2 Vertical Scrolling

6-13 Cursor

6-13-1 Cursor Position and Shift


6-13-3 Cursor Blinking

6-13-4 Cursor Width and Height




7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number






RA8806

Update History

Version Date Description

10 March 25 2008 Preliminary Version

11 June 20 2008

1 6-4-3 Touch panel sampling time reference table 2 Add Section 6-15 Eliminating Flicker Mode 3 Update table 8-2 DC characteristic 4 Add Section 8-3 for RA8806 driver IF timing chart 5 Update font table of Appendix D and Appendix E

12 March 2 2009

1 Add the description of Japanese Kanji font version of RA8806-J2 Update Figure 6-38Figure 6-39 PWM Reference Circuits 3 Update the Section 6-10-1-3 for the usage of Chinese font and

Japanese Kanji font



RA8806



2 Feature 6

3 Block Diagram 7














RA8806


















RA8806






RA8806




2 Feature





RA8806

3 Block Diagram


MCU Interface

Oscillator

Registers


PWMController

Display Timing

Generator


X1X2Y1Y2

ZCS1

CS2

ZWR

ZRD RS

INT

BU

SYD

ATA

[70

]ZR

ST MI

DW DB

CLK

_OU

T

512KByteFont ROM

512ByteCGRAM


KIN[70]KOUT[70]

PWM_OUT

XG

XD

System Configure


DDRAM1DDRAM2


RA8806

MPU

HW Set Up

LCD Driver


Touch Panel

LCD Panel

8x8 Key Pad

Xrsquotal

LCD Driver




RA8806

4 Pin Definition

4-1 MPU Interface


DATA[70] IO


ZRD (EN)

I


ZWR (ZRW)

I


RS I



ZCS1 CS2



BUSY O


4-2 Clock Interface






RA8806



ZRST I




Y1 I






CLK_OUT O


DW I


MI I


DB I





RA8806






XCK O


ZDOFF O


LD[70] O


4-5 Power



VDD P




GND GNDP

P Ground





RA8806










01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV






























RA8806

(Continued)











RA8806




7


flag = 1 R

6


= 1

R


R

4-3 NA R






7




0 RW

6


0 RW

5



0 RW

4 Reserved 0 R

3



GB code

0 RW



RA8806

2


0 RW


0 RW


0 RW




0 RW

6



0 RW


0 RW


0 RW

3-2



01 RW


0 RW


0 RW





0 RW

6-4 Reserved 000 R



RA8806

3


0 RW

2


0 RW


0 RW


0 RW




0 RW


0 RW


0 RW


0 R

2


0 RW

1


0 RW

0


0 RW



RA8806



7


0 RW

6



0 RW

5


10010010)

0 RW


0 RW


0 RW


0 RW


0 RW

0 Reserved 0 R



7-4




0000 RW

3-0



0000 RW



RA8806



7




0 RW

6-4









001 RW

3-2



00 RW

1-0


01 RW



RA8806





27h RW




5-0




( 320 8 ) - 1 = 39 = 27h

27h RW





EFh RW



7-0




240 ndash 1 = 239 = EFh

EFh RW



RA8806




00h RW




00h RW



5-0


00h RW



5-0



00h RW




5-0



00h RW



RA8806



7-0


00h RW



7-0


00h RW



7-0


00h RW



7-0





00h RW





RA8806



7-0



In which


XCK_PRD = 1 XCK






00h RW




0 RW


0 RW

5-4


00 RW


0 RW



RA8806

2-0







000 RW




0 RW

6-4 Reserved 000 R

3-2


00 RW

1-0


00 R




00h R





NA RW




RA8806


7-0



NA RW




0 RW

6-4


000 RW

3



0 RW

2-0


000 RW







RA8806






0 RW

6-2 Reserved 00h R

1-0




and REG[C3h]

00 RW




0 RW


0 RW

5-4 Reserved 00 R

3-0


1111 b CLK 32768




0000 RW



RA8806



7-0


00h RW



7-0


00h RW



7




0 RW

6-4 Reserved 000 R

3



0 RW

2



0 RW

1-0


00 RW




RA8806



7-6


00 RW

5-4


00 RW

3-0 Reserved 0000 R


RA8806


6-1 MPU Interface


8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI


6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8














RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6












tc = 1CLK



RA8806


RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA








RA8806


RS

ZCS1

ZWR

ZRD





RS

ZCS1

ZWR

ZRD

DATA[70]



RS

ZCS1

ZWR

ZRD






RA8806



YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806


Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver



F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )


1st line




RA8806





RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7


FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7


DISPO

FF

Y1~Y160


VDD

VSS










XCK



FR Frame Pulse


YD







RA8806








Panel Resolution


DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh





REG[30h]




RA8806








320

240



80


159160

239





RA8806








240

160



012

119120

159



i


RA8806


Table 6-7




(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1


COM239

COM0

COM239







XCLK

LP

T_COM

ITCR COM_SCAN





RA8806




And












Table 6-8






RA8806










show on the screen








REG[12h]



RA8806


6-4 Touch Panel


YU

XL

YDXR

Electrode

X Plate

Y Plate


SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL




RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm



Table 6-10

Operation mode





coordination



RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )















RA8806

(2) Program Example






RA8806




















RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )


( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )




RA8806

(2) Program Example






RA8806











REG[C4h]



REG[0Fh]












RA8806


(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid


i


RA8806

(2) Program Example








RA8806




SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan




RA8806






07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806


87h86h85h84h83h82h81h80h







97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7









KSCR1


REG[A0h]



KSDR0

KSDR1

KSDR2






RA8806













RA8806


(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End


i


RA8806

(2) Program Example





RA8806

2 Hardware Method

(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask


( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806




RA8806

6-6 Clock and Reset



XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK




EXT￠0tWL

tRCL

tWH

tFCL







EXT Φ0


Notes





RA8806


RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW



VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD




UnitMinTypMax





RA8806


6-7 Power



RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC



RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)




RA8806



RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806










REG[00h]



RA8806












Wake-Up Event

INT

t INTST




RA8806




Key-ScanEvent

INT

t INTST








RA8806

RA8806

MCU

DisplayData RAM


InterfaceController

LCDDriver


XCLK

LP

T_COM

ITCR COM_SCAN









RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY






Full Size Font 250






RA8806

6-9 PWM







TH TL







TH TL

TPWM

TPWM




RA8806






RA8806










RA8806

0 1 2 3 4 5 6 7 hellip


1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment







Bit 7 ISO8859 mode



REG[F0h]



RA8806



Table 6-24






RA8806

-81h -C1h


00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h




+20h+40h




-1Fh





RA8806




RA8806










REG[00h]




RA8806




Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND







RA8806







DDRAM2

Gray-Scale Display

DDRAM1

411301210100


3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0








RA8806



















RA8806



Program Example





RA8806














RA8806






1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452



RA8806


0

15

0 7

0 150

7




RAiO


SEG0 SEG319COM0

COM239

RAiO


COM239 COM0SEG0

SEG319




RA8806









RA8806













8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1


9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567







REG[12h]

CURX Bit [40]


REG[60h]


REG[70h]



RA8806

CGRAMCreate Font


be created) (1)




display layer (3)




Note












RA8806




RA8806

Program Example(2)


font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00











REG[12h]





RA8806


CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000


CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813





9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913



00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )




( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

Yes


Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )




Write CMD


DDRAM1 to DDRAM2





RA8806

Program Example(3)





RA8806









RA8806

Program Example(4)











RA8806








REG[03h]






Start




( Set REG[03h][21] = 0 0 )



i


RA8806




RA8806



Start




( Set REG[03h][21] = 0 1 )





RA8806


6-13 Cursor











RA8806







瑞


cursor

CASE 1






RA8806


瑞



cursor

CASE 2

1 Cursor set


1 Cursor set


瑞



cursor

CASE 3


i


RA8806





瑞佑科技









RA8806



RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver


320320






RA8806

320

240DDRAM1

Data

DDRAM2Data240


DDRAM1 DDRAM2





RA8806

DDRAM1 DDRAM2



DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806









REG[01h]




RA8806

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR




LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction





RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low






LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long





RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction




SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle



SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806



7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH


PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68



RA8806








RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1



DBMI

DW


GNDPRSCS2


5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC


RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT



DBMI

VDDPGNDP

LD0


5 10 15 20

25

30

35


GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP




RA8806


E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm


i


RA8806




A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008


θ1 0 -- -- 0 -- --






RA8806




RA8806




A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number



Resolution (Max)


Compliance


(Note 2) ISO-8859-1 ~ 4 Yes


(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)



(Note 2 3) ISO-8859-1 ~ 4 Yes


(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)


ISO-8859-1 ~ 4 Yes


320x240 (Note 1)


Notes










RA8806


















RA8806







Figure 6-30)






ISB 18 21 mA Case2


140 160 μA Case2 -- 05 1 μA Case1










RA8806



LP


tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

























Note






RA8806





RA8806







(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65



RA8806





(Hz) REG[90h]

ITCR Frame Rate


REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253





RA8806



0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806



i


RA8806






RA8806



i


RA8806





RA8806




RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806




RA8806






RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ














RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ







C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ









Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ








FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　




RA8806




2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write


6-1-4 Status Read









6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode




6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM








6-10-1-6 Line Gap










6-13 Cursor








7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number






RA8806



2 Feature 6

3 Block Diagram 7














RA8806


















RA8806






RA8806




2 Feature





RA8806

3 Block Diagram


MCU Interface

Oscillator

Registers


PWMController

Display Timing

Generator


X1X2Y1Y2

ZCS1

CS2

ZWR

ZRD RS

INT

BU

SYD

ATA

[70

]ZR

ST MI

DW DB

CLK

_OU

T

512KByteFont ROM

512ByteCGRAM


KIN[70]KOUT[70]

PWM_OUT

XG

XD

System Configure


DDRAM1DDRAM2


RA8806

MPU

HW Set Up

LCD Driver


Touch Panel

LCD Panel

8x8 Key Pad

Xrsquotal

LCD Driver




RA8806

4 Pin Definition

4-1 MPU Interface


DATA[70] IO


ZRD (EN)

I


ZWR (ZRW)

I


RS I



ZCS1 CS2



BUSY O


4-2 Clock Interface






RA8806



ZRST I




Y1 I






CLK_OUT O


DW I


MI I


DB I





RA8806






XCK O


ZDOFF O


LD[70] O


4-5 Power



VDD P




GND GNDP

P Ground





RA8806










01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV






























RA8806

(Continued)











RA8806




7


flag = 1 R

6


= 1

R


R

4-3 NA R






7




0 RW

6


0 RW

5



0 RW

4 Reserved 0 R

3



GB code

0 RW



RA8806

2


0 RW


0 RW


0 RW




0 RW

6



0 RW


0 RW


0 RW

3-2



01 RW


0 RW


0 RW





0 RW

6-4 Reserved 000 R



RA8806

3


0 RW

2


0 RW


0 RW


0 RW




0 RW


0 RW


0 RW


0 R

2


0 RW

1


0 RW

0


0 RW



RA8806



7


0 RW

6



0 RW

5


10010010)

0 RW


0 RW


0 RW


0 RW


0 RW

0 Reserved 0 R



7-4




0000 RW

3-0



0000 RW



RA8806



7




0 RW

6-4









001 RW

3-2



00 RW

1-0


01 RW



RA8806





27h RW




5-0




( 320 8 ) - 1 = 39 = 27h

27h RW





EFh RW



7-0




240 ndash 1 = 239 = EFh

EFh RW



RA8806




00h RW




00h RW



5-0


00h RW



5-0



00h RW




5-0



00h RW



RA8806



7-0


00h RW



7-0


00h RW



7-0


00h RW



7-0





00h RW





RA8806



7-0



In which


XCK_PRD = 1 XCK






00h RW




0 RW


0 RW

5-4


00 RW


0 RW



RA8806

2-0







000 RW




0 RW

6-4 Reserved 000 R

3-2


00 RW

1-0


00 R




00h R





NA RW




RA8806


7-0



NA RW




0 RW

6-4


000 RW

3



0 RW

2-0


000 RW







RA8806






0 RW

6-2 Reserved 00h R

1-0




and REG[C3h]

00 RW




0 RW


0 RW

5-4 Reserved 00 R

3-0


1111 b CLK 32768




0000 RW



RA8806



7-0


00h RW



7-0


00h RW



7




0 RW

6-4 Reserved 000 R

3



0 RW

2



0 RW

1-0


00 RW




RA8806



7-6


00 RW

5-4


00 RW

3-0 Reserved 0000 R


RA8806


6-1 MPU Interface


8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI


6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8














RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6












tc = 1CLK



RA8806


RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA








RA8806


RS

ZCS1

ZWR

ZRD





RS

ZCS1

ZWR

ZRD

DATA[70]



RS

ZCS1

ZWR

ZRD






RA8806



YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806


Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver



F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )


1st line




RA8806





RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7


FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7


DISPO

FF

Y1~Y160


VDD

VSS










XCK



FR Frame Pulse


YD







RA8806








Panel Resolution


DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh





REG[30h]




RA8806








320

240



80


159160

239





RA8806








240

160



012

119120

159



i


RA8806


Table 6-7




(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1


COM239

COM0

COM239







XCLK

LP

T_COM

ITCR COM_SCAN





RA8806




And












Table 6-8






RA8806










show on the screen








REG[12h]



RA8806


6-4 Touch Panel


YU

XL

YDXR

Electrode

X Plate

Y Plate


SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL




RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm



Table 6-10

Operation mode





coordination



RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )















RA8806

(2) Program Example






RA8806




















RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )


( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )




RA8806

(2) Program Example






RA8806











REG[C4h]



REG[0Fh]












RA8806


(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid


i


RA8806

(2) Program Example








RA8806




SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan




RA8806






07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806


87h86h85h84h83h82h81h80h







97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7









KSCR1


REG[A0h]



KSDR0

KSDR1

KSDR2






RA8806













RA8806


(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End


i


RA8806

(2) Program Example





RA8806

2 Hardware Method

(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask


( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806




RA8806

6-6 Clock and Reset



XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK




EXT￠0tWL

tRCL

tWH

tFCL







EXT Φ0


Notes





RA8806


RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW



VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD




UnitMinTypMax





RA8806


6-7 Power



RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC



RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)




RA8806



RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806










REG[00h]



RA8806












Wake-Up Event

INT

t INTST




RA8806




Key-ScanEvent

INT

t INTST








RA8806

RA8806

MCU

DisplayData RAM


InterfaceController

LCDDriver


XCLK

LP

T_COM

ITCR COM_SCAN









RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY






Full Size Font 250






RA8806

6-9 PWM







TH TL







TH TL

TPWM

TPWM




RA8806






RA8806










RA8806

0 1 2 3 4 5 6 7 hellip


1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment







Bit 7 ISO8859 mode



REG[F0h]



RA8806



Table 6-24






RA8806

-81h -C1h


00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h




+20h+40h




-1Fh





RA8806




RA8806










REG[00h]




RA8806




Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND







RA8806







DDRAM2

Gray-Scale Display

DDRAM1

411301210100


3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0








RA8806



















RA8806



Program Example





RA8806














RA8806






1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452



RA8806


0

15

0 7

0 150

7




RAiO


SEG0 SEG319COM0

COM239

RAiO


COM239 COM0SEG0

SEG319




RA8806









RA8806













8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1


9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567







REG[12h]

CURX Bit [40]


REG[60h]


REG[70h]



RA8806

CGRAMCreate Font


be created) (1)




display layer (3)




Note












RA8806




RA8806

Program Example(2)


font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00











REG[12h]





RA8806


CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000


CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813





9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913



00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )




( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

Yes


Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )




Write CMD


DDRAM1 to DDRAM2





RA8806

Program Example(3)





RA8806









RA8806

Program Example(4)











RA8806








REG[03h]






Start




( Set REG[03h][21] = 0 0 )



i


RA8806




RA8806



Start




( Set REG[03h][21] = 0 1 )





RA8806


6-13 Cursor











RA8806







瑞


cursor

CASE 1






RA8806


瑞



cursor

CASE 2

1 Cursor set


1 Cursor set


瑞



cursor

CASE 3


i


RA8806





瑞佑科技









RA8806



RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver


320320






RA8806

320

240DDRAM1

Data

DDRAM2Data240


DDRAM1 DDRAM2





RA8806

DDRAM1 DDRAM2



DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806









REG[01h]




RA8806

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR




LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction





RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low






LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long





RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction




SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle



SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806



7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH


PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68



RA8806








RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1



DBMI

DW


GNDPRSCS2


5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC


RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT



DBMI

VDDPGNDP

LD0


5 10 15 20

25

30

35


GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP




RA8806


E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm


i


RA8806




A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008


θ1 0 -- -- 0 -- --






RA8806




RA8806




A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number



Resolution (Max)


Compliance


(Note 2) ISO-8859-1 ~ 4 Yes


(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)



(Note 2 3) ISO-8859-1 ~ 4 Yes


(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)


ISO-8859-1 ~ 4 Yes


320x240 (Note 1)


Notes










RA8806


















RA8806







Figure 6-30)






ISB 18 21 mA Case2


140 160 μA Case2 -- 05 1 μA Case1










RA8806



LP


tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

























Note






RA8806





RA8806







(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65



RA8806





(Hz) REG[90h]

ITCR Frame Rate


REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253





RA8806



0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806



i


RA8806






RA8806



i


RA8806





RA8806




RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



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RA8806



RA8806



RA8806



RA8806



RA8806




RA8806






RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ














RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ







C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ









Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ








FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　




RA8806




2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write


6-1-4 Status Read









6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode




6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM








6-10-1-6 Line Gap










6-13 Cursor








7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number






RA8806


















RA8806






RA8806




2 Feature





RA8806

3 Block Diagram


MCU Interface

Oscillator

Registers


PWMController

Display Timing

Generator


X1X2Y1Y2

ZCS1

CS2

ZWR

ZRD RS

INT

BU

SYD

ATA

[70

]ZR

ST MI

DW DB

CLK

_OU

T

512KByteFont ROM

512ByteCGRAM


KIN[70]KOUT[70]

PWM_OUT

XG

XD

System Configure


DDRAM1DDRAM2


RA8806

MPU

HW Set Up

LCD Driver


Touch Panel

LCD Panel

8x8 Key Pad

Xrsquotal

LCD Driver




RA8806

4 Pin Definition

4-1 MPU Interface


DATA[70] IO


ZRD (EN)

I


ZWR (ZRW)

I


RS I



ZCS1 CS2



BUSY O


4-2 Clock Interface






RA8806



ZRST I




Y1 I






CLK_OUT O


DW I


MI I


DB I





RA8806






XCK O


ZDOFF O


LD[70] O


4-5 Power



VDD P




GND GNDP

P Ground





RA8806










01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV






























RA8806

(Continued)











RA8806




7


flag = 1 R

6


= 1

R


R

4-3 NA R






7




0 RW

6


0 RW

5



0 RW

4 Reserved 0 R

3



GB code

0 RW



RA8806

2


0 RW


0 RW


0 RW




0 RW

6



0 RW


0 RW


0 RW

3-2



01 RW


0 RW


0 RW





0 RW

6-4 Reserved 000 R



RA8806

3


0 RW

2


0 RW


0 RW


0 RW




0 RW


0 RW


0 RW


0 R

2


0 RW

1


0 RW

0


0 RW



RA8806



7


0 RW

6



0 RW

5


10010010)

0 RW


0 RW


0 RW


0 RW


0 RW

0 Reserved 0 R



7-4




0000 RW

3-0



0000 RW



RA8806



7




0 RW

6-4









001 RW

3-2



00 RW

1-0


01 RW



RA8806





27h RW




5-0




( 320 8 ) - 1 = 39 = 27h

27h RW





EFh RW



7-0




240 ndash 1 = 239 = EFh

EFh RW



RA8806




00h RW




00h RW



5-0


00h RW



5-0



00h RW




5-0



00h RW



RA8806



7-0


00h RW



7-0


00h RW



7-0


00h RW



7-0





00h RW





RA8806



7-0



In which


XCK_PRD = 1 XCK






00h RW




0 RW


0 RW

5-4


00 RW


0 RW



RA8806

2-0







000 RW




0 RW

6-4 Reserved 000 R

3-2


00 RW

1-0


00 R




00h R





NA RW




RA8806


7-0



NA RW




0 RW

6-4


000 RW

3



0 RW

2-0


000 RW







RA8806






0 RW

6-2 Reserved 00h R

1-0




and REG[C3h]

00 RW




0 RW


0 RW

5-4 Reserved 00 R

3-0


1111 b CLK 32768




0000 RW



RA8806



7-0


00h RW



7-0


00h RW



7




0 RW

6-4 Reserved 000 R

3



0 RW

2



0 RW

1-0


00 RW




RA8806



7-6


00 RW

5-4


00 RW

3-0 Reserved 0000 R


RA8806


6-1 MPU Interface


8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI


6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8














RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6












tc = 1CLK



RA8806


RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA








RA8806


RS

ZCS1

ZWR

ZRD





RS

ZCS1

ZWR

ZRD

DATA[70]



RS

ZCS1

ZWR

ZRD






RA8806



YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806


Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver



F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )


1st line




RA8806





RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7


FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7


DISPO

FF

Y1~Y160


VDD

VSS










XCK



FR Frame Pulse


YD







RA8806








Panel Resolution


DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh





REG[30h]




RA8806








320

240



80


159160

239





RA8806








240

160



012

119120

159



i


RA8806


Table 6-7




(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1


COM239

COM0

COM239







XCLK

LP

T_COM

ITCR COM_SCAN





RA8806




And












Table 6-8






RA8806










show on the screen








REG[12h]



RA8806


6-4 Touch Panel


YU

XL

YDXR

Electrode

X Plate

Y Plate


SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL




RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm



Table 6-10

Operation mode





coordination



RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )















RA8806

(2) Program Example






RA8806




















RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )


( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )




RA8806

(2) Program Example






RA8806











REG[C4h]



REG[0Fh]












RA8806


(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid


i


RA8806

(2) Program Example








RA8806




SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan




RA8806






07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806


87h86h85h84h83h82h81h80h







97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7









KSCR1


REG[A0h]



KSDR0

KSDR1

KSDR2






RA8806













RA8806


(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End


i


RA8806

(2) Program Example





RA8806

2 Hardware Method

(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask


( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806




RA8806

6-6 Clock and Reset



XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK




EXT￠0tWL

tRCL

tWH

tFCL







EXT Φ0


Notes





RA8806


RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW



VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD




UnitMinTypMax





RA8806


6-7 Power



RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC



RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)




RA8806



RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806










REG[00h]



RA8806












Wake-Up Event

INT

t INTST




RA8806




Key-ScanEvent

INT

t INTST








RA8806

RA8806

MCU

DisplayData RAM


InterfaceController

LCDDriver


XCLK

LP

T_COM

ITCR COM_SCAN









RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY






Full Size Font 250






RA8806

6-9 PWM







TH TL







TH TL

TPWM

TPWM




RA8806






RA8806










RA8806

0 1 2 3 4 5 6 7 hellip


1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment







Bit 7 ISO8859 mode



REG[F0h]



RA8806



Table 6-24






RA8806

-81h -C1h


00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h




+20h+40h




-1Fh





RA8806




RA8806










REG[00h]




RA8806




Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND







RA8806







DDRAM2

Gray-Scale Display

DDRAM1

411301210100


3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0








RA8806



















RA8806



Program Example





RA8806














RA8806






1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452



RA8806


0

15

0 7

0 150

7




RAiO


SEG0 SEG319COM0

COM239

RAiO


COM239 COM0SEG0

SEG319




RA8806









RA8806













8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1


9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567







REG[12h]

CURX Bit [40]


REG[60h]


REG[70h]



RA8806

CGRAMCreate Font


be created) (1)




display layer (3)




Note












RA8806




RA8806

Program Example(2)


font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00











REG[12h]





RA8806


CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000


CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813





9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913



00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )




( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

Yes


Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )




Write CMD


DDRAM1 to DDRAM2





RA8806

Program Example(3)





RA8806









RA8806

Program Example(4)











RA8806








REG[03h]






Start




( Set REG[03h][21] = 0 0 )



i


RA8806




RA8806



Start




( Set REG[03h][21] = 0 1 )





RA8806


6-13 Cursor











RA8806







瑞


cursor

CASE 1






RA8806


瑞



cursor

CASE 2

1 Cursor set


1 Cursor set


瑞



cursor

CASE 3


i


RA8806





瑞佑科技









RA8806



RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver


320320






RA8806

320

240DDRAM1

Data

DDRAM2Data240


DDRAM1 DDRAM2





RA8806

DDRAM1 DDRAM2



DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806









REG[01h]




RA8806

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR




LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction





RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low






LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long





RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction




SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle



SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806



7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH


PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68



RA8806








RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1



DBMI

DW


GNDPRSCS2


5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC


RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT



DBMI

VDDPGNDP

LD0


5 10 15 20

25

30

35


GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP




RA8806


E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm


i


RA8806




A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008


θ1 0 -- -- 0 -- --






RA8806




RA8806




A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number



Resolution (Max)


Compliance


(Note 2) ISO-8859-1 ~ 4 Yes


(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)



(Note 2 3) ISO-8859-1 ~ 4 Yes


(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)


ISO-8859-1 ~ 4 Yes


320x240 (Note 1)


Notes










RA8806


















RA8806







Figure 6-30)






ISB 18 21 mA Case2


140 160 μA Case2 -- 05 1 μA Case1










RA8806



LP


tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

























Note






RA8806





RA8806







(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65



RA8806





(Hz) REG[90h]

ITCR Frame Rate


REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253





RA8806



0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806



i


RA8806






RA8806



i


RA8806





RA8806




RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806




RA8806






RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ














RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ







C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ









Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ








FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　




RA8806




2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write


6-1-4 Status Read









6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode




6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM








6-10-1-6 Line Gap










6-13 Cursor








7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number






RA8806






RA8806




2 Feature





RA8806

3 Block Diagram


MCU Interface

Oscillator

Registers


PWMController

Display Timing

Generator


X1X2Y1Y2

ZCS1

CS2

ZWR

ZRD RS

INT

BU

SYD

ATA

[70

]ZR

ST MI

DW DB

CLK

_OU

T

512KByteFont ROM

512ByteCGRAM


KIN[70]KOUT[70]

PWM_OUT

XG

XD

System Configure


DDRAM1DDRAM2


RA8806

MPU

HW Set Up

LCD Driver


Touch Panel

LCD Panel

8x8 Key Pad

Xrsquotal

LCD Driver




RA8806

4 Pin Definition

4-1 MPU Interface


DATA[70] IO


ZRD (EN)

I


ZWR (ZRW)

I


RS I



ZCS1 CS2



BUSY O


4-2 Clock Interface






RA8806



ZRST I




Y1 I






CLK_OUT O


DW I


MI I


DB I





RA8806






XCK O


ZDOFF O


LD[70] O


4-5 Power



VDD P




GND GNDP

P Ground





RA8806










01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV






























RA8806

(Continued)











RA8806




7


flag = 1 R

6


= 1

R


R

4-3 NA R






7




0 RW

6


0 RW

5



0 RW

4 Reserved 0 R

3



GB code

0 RW



RA8806

2


0 RW


0 RW


0 RW




0 RW

6



0 RW


0 RW


0 RW

3-2



01 RW


0 RW


0 RW





0 RW

6-4 Reserved 000 R



RA8806

3


0 RW

2


0 RW


0 RW


0 RW




0 RW


0 RW


0 RW


0 R

2


0 RW

1


0 RW

0


0 RW



RA8806



7


0 RW

6



0 RW

5


10010010)

0 RW


0 RW


0 RW


0 RW


0 RW

0 Reserved 0 R



7-4




0000 RW

3-0



0000 RW



RA8806



7




0 RW

6-4









001 RW

3-2



00 RW

1-0


01 RW



RA8806





27h RW




5-0




( 320 8 ) - 1 = 39 = 27h

27h RW





EFh RW



7-0




240 ndash 1 = 239 = EFh

EFh RW



RA8806




00h RW




00h RW



5-0


00h RW



5-0



00h RW




5-0



00h RW



RA8806



7-0


00h RW



7-0


00h RW



7-0


00h RW



7-0





00h RW





RA8806



7-0



In which


XCK_PRD = 1 XCK






00h RW




0 RW


0 RW

5-4


00 RW


0 RW



RA8806

2-0







000 RW




0 RW

6-4 Reserved 000 R

3-2


00 RW

1-0


00 R




00h R





NA RW




RA8806


7-0



NA RW




0 RW

6-4


000 RW

3



0 RW

2-0


000 RW







RA8806






0 RW

6-2 Reserved 00h R

1-0




and REG[C3h]

00 RW




0 RW


0 RW

5-4 Reserved 00 R

3-0


1111 b CLK 32768




0000 RW



RA8806



7-0


00h RW



7-0


00h RW



7




0 RW

6-4 Reserved 000 R

3



0 RW

2



0 RW

1-0


00 RW




RA8806



7-6


00 RW

5-4


00 RW

3-0 Reserved 0000 R


RA8806


6-1 MPU Interface


8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI


6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8














RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6












tc = 1CLK



RA8806


RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA








RA8806


RS

ZCS1

ZWR

ZRD





RS

ZCS1

ZWR

ZRD

DATA[70]



RS

ZCS1

ZWR

ZRD






RA8806



YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806


Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver



F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )


1st line




RA8806





RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7


FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7


DISPO

FF

Y1~Y160


VDD

VSS










XCK



FR Frame Pulse


YD







RA8806








Panel Resolution


DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh





REG[30h]




RA8806








320

240



80


159160

239





RA8806








240

160



012

119120

159



i


RA8806


Table 6-7




(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1


COM239

COM0

COM239







XCLK

LP

T_COM

ITCR COM_SCAN





RA8806




And












Table 6-8






RA8806










show on the screen








REG[12h]



RA8806


6-4 Touch Panel


YU

XL

YDXR

Electrode

X Plate

Y Plate


SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL




RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm



Table 6-10

Operation mode





coordination



RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )















RA8806

(2) Program Example






RA8806




















RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )


( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )




RA8806

(2) Program Example






RA8806











REG[C4h]



REG[0Fh]












RA8806


(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid


i


RA8806

(2) Program Example








RA8806




SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan




RA8806






07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806


87h86h85h84h83h82h81h80h







97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7









KSCR1


REG[A0h]



KSDR0

KSDR1

KSDR2






RA8806













RA8806


(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End


i


RA8806

(2) Program Example





RA8806

2 Hardware Method

(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask


( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806




RA8806

6-6 Clock and Reset



XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK




EXT￠0tWL

tRCL

tWH

tFCL







EXT Φ0


Notes





RA8806


RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW



VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD




UnitMinTypMax





RA8806


6-7 Power



RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC



RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)




RA8806



RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806










REG[00h]



RA8806












Wake-Up Event

INT

t INTST




RA8806




Key-ScanEvent

INT

t INTST








RA8806

RA8806

MCU

DisplayData RAM


InterfaceController

LCDDriver


XCLK

LP

T_COM

ITCR COM_SCAN









RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY






Full Size Font 250






RA8806

6-9 PWM







TH TL







TH TL

TPWM

TPWM




RA8806






RA8806










RA8806

0 1 2 3 4 5 6 7 hellip


1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment







Bit 7 ISO8859 mode



REG[F0h]



RA8806



Table 6-24






RA8806

-81h -C1h


00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h




+20h+40h




-1Fh





RA8806




RA8806










REG[00h]




RA8806




Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND







RA8806







DDRAM2

Gray-Scale Display

DDRAM1

411301210100


3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0








RA8806



















RA8806



Program Example





RA8806














RA8806






1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452



RA8806


0

15

0 7

0 150

7




RAiO


SEG0 SEG319COM0

COM239

RAiO


COM239 COM0SEG0

SEG319




RA8806









RA8806













8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1


9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567







REG[12h]

CURX Bit [40]


REG[60h]


REG[70h]



RA8806

CGRAMCreate Font


be created) (1)




display layer (3)




Note












RA8806




RA8806

Program Example(2)


font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00











REG[12h]





RA8806


CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000


CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813





9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913



00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )




( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

Yes


Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )




Write CMD


DDRAM1 to DDRAM2





RA8806

Program Example(3)





RA8806









RA8806

Program Example(4)











RA8806








REG[03h]






Start




( Set REG[03h][21] = 0 0 )



i


RA8806




RA8806



Start




( Set REG[03h][21] = 0 1 )





RA8806


6-13 Cursor











RA8806







瑞


cursor

CASE 1






RA8806


瑞



cursor

CASE 2

1 Cursor set


1 Cursor set


瑞



cursor

CASE 3


i


RA8806





瑞佑科技









RA8806



RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver


320320






RA8806

320

240DDRAM1

Data

DDRAM2Data240


DDRAM1 DDRAM2





RA8806

DDRAM1 DDRAM2



DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806









REG[01h]




RA8806

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR




LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction





RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low






LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long





RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction




SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle



SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806



7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH


PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68



RA8806








RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1



DBMI

DW


GNDPRSCS2


5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC


RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT



DBMI

VDDPGNDP

LD0


5 10 15 20

25

30

35


GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP




RA8806


E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm


i


RA8806




A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008


θ1 0 -- -- 0 -- --






RA8806




RA8806




A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number



Resolution (Max)


Compliance


(Note 2) ISO-8859-1 ~ 4 Yes


(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)



(Note 2 3) ISO-8859-1 ~ 4 Yes


(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)


ISO-8859-1 ~ 4 Yes


320x240 (Note 1)


Notes










RA8806


















RA8806







Figure 6-30)






ISB 18 21 mA Case2


140 160 μA Case2 -- 05 1 μA Case1










RA8806



LP


tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

























Note






RA8806





RA8806







(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65



RA8806





(Hz) REG[90h]

ITCR Frame Rate


REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253





RA8806



0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806



i


RA8806






RA8806



i


RA8806





RA8806




RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806




RA8806






RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ














RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ







C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ









Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ








FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　




RA8806




2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write


6-1-4 Status Read









6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode




6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM








6-10-1-6 Line Gap










6-13 Cursor








7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number







RA8806




2 Feature





RA8806

3 Block Diagram


MCU Interface

Oscillator

Registers


PWMController

Display Timing

Generator


X1X2Y1Y2

ZCS1

CS2

ZWR

ZRD RS

INT

BU

SYD

ATA

[70

]ZR

ST MI

DW DB

CLK

_OU

T

512KByteFont ROM

512ByteCGRAM


KIN[70]KOUT[70]

PWM_OUT

XG

XD

System Configure


DDRAM1DDRAM2


RA8806

MPU

HW Set Up

LCD Driver


Touch Panel

LCD Panel

8x8 Key Pad

Xrsquotal

LCD Driver




RA8806

4 Pin Definition

4-1 MPU Interface


DATA[70] IO


ZRD (EN)

I


ZWR (ZRW)

I


RS I



ZCS1 CS2



BUSY O


4-2 Clock Interface






RA8806



ZRST I




Y1 I






CLK_OUT O


DW I


MI I


DB I





RA8806






XCK O


ZDOFF O


LD[70] O


4-5 Power



VDD P




GND GNDP

P Ground





RA8806










01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV






























RA8806

(Continued)











RA8806




7


flag = 1 R

6


= 1

R


R

4-3 NA R






7




0 RW

6


0 RW

5



0 RW

4 Reserved 0 R

3



GB code

0 RW



RA8806

2


0 RW


0 RW


0 RW




0 RW

6



0 RW


0 RW


0 RW

3-2



01 RW


0 RW


0 RW





0 RW

6-4 Reserved 000 R



RA8806

3


0 RW

2


0 RW


0 RW


0 RW




0 RW


0 RW


0 RW


0 R

2


0 RW

1


0 RW

0


0 RW



RA8806



7


0 RW

6



0 RW

5


10010010)

0 RW


0 RW


0 RW


0 RW


0 RW

0 Reserved 0 R



7-4




0000 RW

3-0



0000 RW



RA8806



7




0 RW

6-4









001 RW

3-2



00 RW

1-0


01 RW



RA8806





27h RW




5-0




( 320 8 ) - 1 = 39 = 27h

27h RW





EFh RW



7-0




240 ndash 1 = 239 = EFh

EFh RW



RA8806




00h RW




00h RW



5-0


00h RW



5-0



00h RW




5-0



00h RW



RA8806



7-0


00h RW



7-0


00h RW



7-0


00h RW



7-0





00h RW





RA8806



7-0



In which


XCK_PRD = 1 XCK






00h RW




0 RW


0 RW

5-4


00 RW


0 RW



RA8806

2-0







000 RW




0 RW

6-4 Reserved 000 R

3-2


00 RW

1-0


00 R




00h R





NA RW




RA8806


7-0



NA RW




0 RW

6-4


000 RW

3



0 RW

2-0


000 RW







RA8806






0 RW

6-2 Reserved 00h R

1-0




and REG[C3h]

00 RW




0 RW


0 RW

5-4 Reserved 00 R

3-0


1111 b CLK 32768




0000 RW



RA8806



7-0


00h RW



7-0


00h RW



7




0 RW

6-4 Reserved 000 R

3



0 RW

2



0 RW

1-0


00 RW




RA8806



7-6


00 RW

5-4


00 RW

3-0 Reserved 0000 R


RA8806


6-1 MPU Interface


8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI


6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8














RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6












tc = 1CLK



RA8806


RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA








RA8806


RS

ZCS1

ZWR

ZRD





RS

ZCS1

ZWR

ZRD

DATA[70]



RS

ZCS1

ZWR

ZRD






RA8806



YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806


Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver



F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )


1st line




RA8806





RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7


FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7


DISPO

FF

Y1~Y160


VDD

VSS










XCK



FR Frame Pulse


YD







RA8806








Panel Resolution


DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh





REG[30h]




RA8806








320

240



80


159160

239





RA8806








240

160



012

119120

159



i


RA8806


Table 6-7




(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1


COM239

COM0

COM239







XCLK

LP

T_COM

ITCR COM_SCAN





RA8806




And












Table 6-8






RA8806










show on the screen








REG[12h]



RA8806


6-4 Touch Panel


YU

XL

YDXR

Electrode

X Plate

Y Plate


SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL




RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm



Table 6-10

Operation mode





coordination



RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )















RA8806

(2) Program Example






RA8806




















RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )


( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )




RA8806

(2) Program Example






RA8806











REG[C4h]



REG[0Fh]












RA8806


(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid


i


RA8806

(2) Program Example








RA8806




SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan




RA8806






07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806


87h86h85h84h83h82h81h80h







97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7









KSCR1


REG[A0h]



KSDR0

KSDR1

KSDR2






RA8806













RA8806


(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End


i


RA8806

(2) Program Example





RA8806

2 Hardware Method

(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask


( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806




RA8806

6-6 Clock and Reset



XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK




EXT￠0tWL

tRCL

tWH

tFCL







EXT Φ0


Notes





RA8806


RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW



VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD




UnitMinTypMax





RA8806


6-7 Power



RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC



RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)




RA8806



RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806










REG[00h]



RA8806












Wake-Up Event

INT

t INTST




RA8806




Key-ScanEvent

INT

t INTST








RA8806

RA8806

MCU

DisplayData RAM


InterfaceController

LCDDriver


XCLK

LP

T_COM

ITCR COM_SCAN









RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY






Full Size Font 250






RA8806

6-9 PWM







TH TL







TH TL

TPWM

TPWM




RA8806






RA8806










RA8806

0 1 2 3 4 5 6 7 hellip


1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment







Bit 7 ISO8859 mode



REG[F0h]



RA8806



Table 6-24






RA8806

-81h -C1h


00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h




+20h+40h




-1Fh





RA8806




RA8806










REG[00h]




RA8806




Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND







RA8806







DDRAM2

Gray-Scale Display

DDRAM1

411301210100


3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0








RA8806



















RA8806



Program Example





RA8806














RA8806






1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452



RA8806


0

15

0 7

0 150

7




RAiO


SEG0 SEG319COM0

COM239

RAiO


COM239 COM0SEG0

SEG319




RA8806









RA8806













8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1


9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567







REG[12h]

CURX Bit [40]


REG[60h]


REG[70h]



RA8806

CGRAMCreate Font


be created) (1)




display layer (3)




Note












RA8806




RA8806

Program Example(2)


font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00











REG[12h]





RA8806


CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000


CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813





9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913



00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )




( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

Yes


Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )




Write CMD


DDRAM1 to DDRAM2





RA8806

Program Example(3)





RA8806









RA8806

Program Example(4)











RA8806








REG[03h]






Start




( Set REG[03h][21] = 0 0 )



i


RA8806




RA8806



Start




( Set REG[03h][21] = 0 1 )





RA8806


6-13 Cursor











RA8806







瑞


cursor

CASE 1






RA8806


瑞



cursor

CASE 2

1 Cursor set


1 Cursor set


瑞



cursor

CASE 3


i


RA8806





瑞佑科技









RA8806



RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver


320320






RA8806

320

240DDRAM1

Data

DDRAM2Data240


DDRAM1 DDRAM2





RA8806

DDRAM1 DDRAM2



DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806









REG[01h]




RA8806

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR




LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction





RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low






LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long





RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction




SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle



SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806



7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH


PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68



RA8806








RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1



DBMI

DW


GNDPRSCS2


5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC


RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT



DBMI

VDDPGNDP

LD0


5 10 15 20

25

30

35


GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP




RA8806


E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm


i


RA8806




A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008


θ1 0 -- -- 0 -- --






RA8806




RA8806




A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number



Resolution (Max)


Compliance


(Note 2) ISO-8859-1 ~ 4 Yes


(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)



(Note 2 3) ISO-8859-1 ~ 4 Yes


(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)


ISO-8859-1 ~ 4 Yes


320x240 (Note 1)


Notes










RA8806


















RA8806







Figure 6-30)






ISB 18 21 mA Case2


140 160 μA Case2 -- 05 1 μA Case1










RA8806



LP


tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

























Note






RA8806





RA8806







(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65



RA8806





(Hz) REG[90h]

ITCR Frame Rate


REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253





RA8806



0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806



i


RA8806






RA8806



i


RA8806





RA8806




RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806




RA8806






RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ














RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ







C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ









Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ








FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　




RA8806




2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write


6-1-4 Status Read









6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode




6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM








6-10-1-6 Line Gap










6-13 Cursor








7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number






RA8806

3 Block Diagram


MCU Interface

Oscillator

Registers


PWMController

Display Timing

Generator


X1X2Y1Y2

ZCS1

CS2

ZWR

ZRD RS

INT

BU

SYD

ATA

[70

]ZR

ST MI

DW DB

CLK

_OU

T

512KByteFont ROM

512ByteCGRAM


KIN[70]KOUT[70]

PWM_OUT

XG

XD

System Configure


DDRAM1DDRAM2


RA8806

MPU

HW Set Up

LCD Driver


Touch Panel

LCD Panel

8x8 Key Pad

Xrsquotal

LCD Driver




RA8806

4 Pin Definition

4-1 MPU Interface


DATA[70] IO


ZRD (EN)

I


ZWR (ZRW)

I


RS I



ZCS1 CS2



BUSY O


4-2 Clock Interface






RA8806



ZRST I




Y1 I






CLK_OUT O


DW I


MI I


DB I





RA8806






XCK O


ZDOFF O


LD[70] O


4-5 Power



VDD P




GND GNDP

P Ground





RA8806










01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV






























RA8806

(Continued)











RA8806




7


flag = 1 R

6


= 1

R


R

4-3 NA R






7




0 RW

6


0 RW

5



0 RW

4 Reserved 0 R

3



GB code

0 RW



RA8806

2


0 RW


0 RW


0 RW




0 RW

6



0 RW


0 RW


0 RW

3-2



01 RW


0 RW


0 RW





0 RW

6-4 Reserved 000 R



RA8806

3


0 RW

2


0 RW


0 RW


0 RW




0 RW


0 RW


0 RW


0 R

2


0 RW

1


0 RW

0


0 RW



RA8806



7


0 RW

6



0 RW

5


10010010)

0 RW


0 RW


0 RW


0 RW


0 RW

0 Reserved 0 R



7-4




0000 RW

3-0



0000 RW



RA8806



7




0 RW

6-4









001 RW

3-2



00 RW

1-0


01 RW



RA8806





27h RW




5-0




( 320 8 ) - 1 = 39 = 27h

27h RW





EFh RW



7-0




240 ndash 1 = 239 = EFh

EFh RW



RA8806




00h RW




00h RW



5-0


00h RW



5-0



00h RW




5-0



00h RW



RA8806



7-0


00h RW



7-0


00h RW



7-0


00h RW



7-0





00h RW





RA8806



7-0



In which


XCK_PRD = 1 XCK






00h RW




0 RW


0 RW

5-4


00 RW


0 RW



RA8806

2-0







000 RW




0 RW

6-4 Reserved 000 R

3-2


00 RW

1-0


00 R




00h R





NA RW




RA8806


7-0



NA RW




0 RW

6-4


000 RW

3



0 RW

2-0


000 RW







RA8806






0 RW

6-2 Reserved 00h R

1-0




and REG[C3h]

00 RW




0 RW


0 RW

5-4 Reserved 00 R

3-0


1111 b CLK 32768




0000 RW



RA8806



7-0


00h RW



7-0


00h RW



7




0 RW

6-4 Reserved 000 R

3



0 RW

2



0 RW

1-0


00 RW




RA8806



7-6


00 RW

5-4


00 RW

3-0 Reserved 0000 R


RA8806


6-1 MPU Interface


8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI


6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8














RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6












tc = 1CLK



RA8806


RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA








RA8806


RS

ZCS1

ZWR

ZRD





RS

ZCS1

ZWR

ZRD

DATA[70]



RS

ZCS1

ZWR

ZRD






RA8806



YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806


Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver



F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )


1st line




RA8806





RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7


FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7


DISPO

FF

Y1~Y160


VDD

VSS










XCK



FR Frame Pulse


YD







RA8806








Panel Resolution


DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh





REG[30h]




RA8806








320

240



80


159160

239





RA8806








240

160



012

119120

159



i


RA8806


Table 6-7




(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1


COM239

COM0

COM239







XCLK

LP

T_COM

ITCR COM_SCAN





RA8806




And












Table 6-8






RA8806










show on the screen








REG[12h]



RA8806


6-4 Touch Panel


YU

XL

YDXR

Electrode

X Plate

Y Plate


SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL




RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm



Table 6-10

Operation mode





coordination



RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )















RA8806

(2) Program Example






RA8806




















RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )


( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )




RA8806

(2) Program Example






RA8806











REG[C4h]



REG[0Fh]












RA8806


(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid


i


RA8806

(2) Program Example








RA8806




SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan




RA8806






07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806


87h86h85h84h83h82h81h80h







97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7









KSCR1


REG[A0h]



KSDR0

KSDR1

KSDR2






RA8806













RA8806


(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End


i


RA8806

(2) Program Example





RA8806

2 Hardware Method

(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask


( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806




RA8806

6-6 Clock and Reset



XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK




EXT￠0tWL

tRCL

tWH

tFCL







EXT Φ0


Notes





RA8806


RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW



VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD




UnitMinTypMax





RA8806


6-7 Power



RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC



RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)




RA8806



RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806










REG[00h]



RA8806












Wake-Up Event

INT

t INTST




RA8806




Key-ScanEvent

INT

t INTST








RA8806

RA8806

MCU

DisplayData RAM


InterfaceController

LCDDriver


XCLK

LP

T_COM

ITCR COM_SCAN









RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY






Full Size Font 250






RA8806

6-9 PWM







TH TL







TH TL

TPWM

TPWM




RA8806






RA8806










RA8806

0 1 2 3 4 5 6 7 hellip


1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment







Bit 7 ISO8859 mode



REG[F0h]



RA8806



Table 6-24






RA8806

-81h -C1h


00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h




+20h+40h




-1Fh





RA8806




RA8806










REG[00h]




RA8806




Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND







RA8806







DDRAM2

Gray-Scale Display

DDRAM1

411301210100


3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0








RA8806



















RA8806



Program Example





RA8806














RA8806






1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452



RA8806


0

15

0 7

0 150

7




RAiO


SEG0 SEG319COM0

COM239

RAiO


COM239 COM0SEG0

SEG319




RA8806









RA8806













8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1


9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567







REG[12h]

CURX Bit [40]


REG[60h]


REG[70h]



RA8806

CGRAMCreate Font


be created) (1)




display layer (3)




Note












RA8806




RA8806

Program Example(2)


font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00











REG[12h]





RA8806


CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000


CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813





9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913



00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )




( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

Yes


Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )




Write CMD


DDRAM1 to DDRAM2





RA8806

Program Example(3)





RA8806









RA8806

Program Example(4)











RA8806








REG[03h]






Start




( Set REG[03h][21] = 0 0 )



i


RA8806




RA8806



Start




( Set REG[03h][21] = 0 1 )





RA8806


6-13 Cursor











RA8806







瑞


cursor

CASE 1






RA8806


瑞



cursor

CASE 2

1 Cursor set


1 Cursor set


瑞



cursor

CASE 3


i


RA8806





瑞佑科技









RA8806



RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver


320320






RA8806

320

240DDRAM1

Data

DDRAM2Data240


DDRAM1 DDRAM2





RA8806

DDRAM1 DDRAM2



DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806









REG[01h]




RA8806

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR




LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction





RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low






LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long





RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction




SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle



SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806



7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH


PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68



RA8806








RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1



DBMI

DW


GNDPRSCS2


5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC


RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT



DBMI

VDDPGNDP

LD0


5 10 15 20

25

30

35


GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP




RA8806


E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm


i


RA8806




A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008


θ1 0 -- -- 0 -- --






RA8806




RA8806




A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number



Resolution (Max)


Compliance


(Note 2) ISO-8859-1 ~ 4 Yes


(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)



(Note 2 3) ISO-8859-1 ~ 4 Yes


(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)


ISO-8859-1 ~ 4 Yes


320x240 (Note 1)


Notes










RA8806


















RA8806







Figure 6-30)






ISB 18 21 mA Case2


140 160 μA Case2 -- 05 1 μA Case1










RA8806



LP


tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

























Note






RA8806





RA8806







(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65



RA8806





(Hz) REG[90h]

ITCR Frame Rate


REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253





RA8806



0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806



i


RA8806






RA8806



i


RA8806





RA8806




RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806




RA8806






RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ














RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ







C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ









Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ








FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　




RA8806




2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write


6-1-4 Status Read









6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode




6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM








6-10-1-6 Line Gap










6-13 Cursor








7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number






RA8806

4 Pin Definition

4-1 MPU Interface


DATA[70] IO


ZRD (EN)

I


ZWR (ZRW)

I


RS I



ZCS1 CS2



BUSY O


4-2 Clock Interface






RA8806



ZRST I




Y1 I






CLK_OUT O


DW I


MI I


DB I





RA8806






XCK O


ZDOFF O


LD[70] O


4-5 Power



VDD P




GND GNDP

P Ground





RA8806










01h MISC NO_

FLICKER CLKO_SEL

BUSY_ LEV






























RA8806

(Continued)











RA8806




7


flag = 1 R

6


= 1

R


R

4-3 NA R






7




0 RW

6


0 RW

5



0 RW

4 Reserved 0 R

3



GB code

0 RW



RA8806

2


0 RW


0 RW


0 RW




0 RW

6



0 RW


0 RW


0 RW

3-2



01 RW


0 RW


0 RW





0 RW

6-4 Reserved 000 R



RA8806

3


0 RW

2


0 RW


0 RW


0 RW




0 RW


0 RW


0 RW


0 R

2


0 RW

1


0 RW

0


0 RW



RA8806



7


0 RW

6



0 RW

5


10010010)

0 RW


0 RW


0 RW


0 RW


0 RW

0 Reserved 0 R



7-4




0000 RW

3-0



0000 RW



RA8806



7




0 RW

6-4









001 RW

3-2



00 RW

1-0


01 RW



RA8806





27h RW




5-0




( 320 8 ) - 1 = 39 = 27h

27h RW





EFh RW



7-0




240 ndash 1 = 239 = EFh

EFh RW



RA8806




00h RW




00h RW



5-0


00h RW



5-0



00h RW




5-0



00h RW



RA8806



7-0


00h RW



7-0


00h RW



7-0


00h RW



7-0





00h RW





RA8806



7-0



In which


XCK_PRD = 1 XCK






00h RW




0 RW


0 RW

5-4


00 RW


0 RW



RA8806

2-0







000 RW




0 RW

6-4 Reserved 000 R

3-2


00 RW

1-0


00 R




00h R





NA RW




RA8806


7-0



NA RW




0 RW

6-4


000 RW

3



0 RW

2-0


000 RW







RA8806






0 RW

6-2 Reserved 00h R

1-0




and REG[C3h]

00 RW




0 RW


0 RW

5-4 Reserved 00 R

3-0


1111 b CLK 32768




0000 RW



RA8806



7-0


00h RW



7-0


00h RW



7




0 RW

6-4 Reserved 000 R

3



0 RW

2



0 RW

1-0


00 RW




RA8806



7-6


00 RW

5-4


00 RW

3-0 Reserved 0000 R


RA8806


6-1 MPU Interface


8080MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

ZRD

ZWR

ZRST

A0

A1-A7

IORQ

D0-D3(D0 -D7)

RD

WR

RES

MI


6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD

6800MPU RA8806

Decoder

RS

ZCS1

CS2

DATA0-3(DATA0-7)

EN

ZRW

ZRST

A0

A1-A7

VMA

D0-3(D0-D7)

EN

RW

RES

MI

VDD




RA8806

RSZCS1CS2

ZWRZRD

DATA(Write)

DATA(Read)

tCYC8

tCC8

tAH8

tDH8

tACC8

tDS8

tAS8

tOH8














RA8806

RSZRWZCS1CS2

EN

DATA(Write)

DATA(Read)

tCYC6

tCC6

tAH6

tDH6

tACC6

tDS6

tAS6

tOH6












tc = 1CLK



RA8806


RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA

RS

ZCS1

ZWR

ZRD

DATA[70] REG DATA








RA8806


RS

ZCS1

ZWR

ZRD





RS

ZCS1

ZWR

ZRD

DATA[70]



RS

ZCS1

ZWR

ZRD






RA8806



YD

FR

LP

ZDOFF

XCK

LD[70]

RA8806


Common Signals

Segment Signals

FLM

M

LP

DISPOFF

CP

D[70]

LCD Driver



F R

Y D

LP

X C K

F R

Y D

LP

X C K

LD(D a ta )


1st line




RA8806





RA8806

FR

YD

LP

ZDOFF

XCK

LD[70]

RA8806

FR

LP

DISPOFF

XCK

EIO1

MD

SC

LR

EIO2

DI0~DI7


FRLP

XCK

EIO1

MD

SC

LR

EIO2

DI0~D

I7


DISPO

FF

Y1~Y160


VDD

VSS










XCK



FR Frame Pulse


YD







RA8806








Panel Resolution


DWWR REG[31h]

DWHR

16080 160 80 13h 4Fh

160128 160 128 13h 7Fh

160160 160 160 13h 9Fh

24064 240 64 1Dh 3Fh

240128 240 128 1Dh 7Fh

240160 240 160 1Dh 9Fh

320240 320 240 27h EFh





REG[30h]




RA8806








320

240



80


159160

239





RA8806








240

160



012

119120

159



i


RA8806


Table 6-7




(1) SDIR = 0

SEG0 SEG319

(2) SDIR = 1


COM239

COM0

COM239







XCLK

LP

T_COM

ITCR COM_SCAN





RA8806




And












Table 6-8






RA8806










show on the screen








REG[12h]



RA8806


6-4 Touch Panel


YU

XL

YDXR

Electrode

X Plate

Y Plate


SW2

SW3

SW0 SW1

VDD

GND

Resistor -Y

Resistor -X

VDDXR

YD

YU

XL




RA8806

001μF x 4

RA8806

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

VDD

39Kohm

001μF x 4

RA8806

X1

X2

Y1

Y2

X1

X2

Y1

Y2

Touch Panel

XR

XL

YU

YD

Touch Panel

XR

XL

YU

YD

VDD

39Kohm



Table 6-10

Operation mode





coordination



RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Auto Mode

( REG[C4h] B7 = 0 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )















RA8806

(2) Program Example






RA8806




















RA8806


Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Other Functions

ISR

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Ext INT Event

ISR Termination

1

0Set Manual Mode

( REG[C4h] B7 = 1 )

Enable TP INT Mask

( REG[0Fh] B4 = 1 )

Check INT Status

( REG[0Fh] B0 = )

Clear TP INT Status

( REG[0Fh] B0 = 0 )


( REG[C4h][10] = 01 )

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )




RA8806

(2) Program Example






RA8806











REG[C4h]



REG[0Fh]












RA8806


(1) Flowchart

Start

Enable Touch Panel

( REG[C0h] B7 = 1 )

Read X Y-axis

( Read REG[C1h]

REG[C2h] REG[C3h] )

Execute Function

Set Auto Mode

( REG[C4h] B7 = 1 )

Clear TP INT Status

( REG[0Fh] B0 = 0 )

0 Check TP Event

( REG[0Fh] B3 = )

validCheck TP Event

100 times


( REG[C4h][10] = 01 )

Other Function

Latch X Data

( REG[C4h][10] = 10 )

Latch Y Data

( REG[C4h][10] = 11 )

Delay enough time

Delay enough time

1

invalid


i


RA8806

(2) Program Example








RA8806




SYSTEM_CLK

REG[C0h] [20] 4M 6M 8M 10M 12M

000 000 000 000 000 000

001 000 000 000 000 000

010 000 000 000 000 000

011 001 001 000 000 000

100 010 010 001 001 001

101 011 011 010 010 010

110 100 100 011 011 011

111 101 101 100 100 100



RA8806

6-5 Key-Scan




RA8806






07h06h05h04h03h02h01h00h

77h76h75h74h73h72h71h70h

67h66h65h64h63h62h61h60h

57h56h55h54h53h52h51h50h

47h46h45h44h43h42h41h40h

37h36h35h34h33h32h31h30h

27h26h25h24h23h22h21h20h

17h16h15h14h13h12h11h10h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7



RA8806


87h86h85h84h83h82h81h80h







97h96h95h94h93h92h91h90h

ROW

0 1 2 3 4 5 6 7

COL

0

1

2

3

4

5

6

7









KSCR1


REG[A0h]



KSDR0

KSDR1

KSDR2






RA8806













RA8806


(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Clear KS Status

( REG[0Fh] B1 = 0 )

0 Check KS Status

( REG[0Fh] B1 = )

1

End


i


RA8806

(2) Program Example





RA8806

2 Hardware Method

(1) Flowchart

Start


( REG[A0h] B7 = 1 )

Other Functions

ISR

Read Key Code

( Read REG[A2h]

REG[A3h] REG[A4h] )

Execute Function

Other INT Function

Ext INT Event

ISR Termination

1

0Enable KS INT Mask


( REG[0Fh] B1 = )

Clear KS Status

( REG[0Fh] B0 = 0 )


i


RA8806




RA8806

6-6 Clock and Reset



XG

XD

RA8806

(4~12MHz)

15pF

15pF

Xrsquotal

XG

XD

RA8806

(4~12MHz)

CLK




EXT￠0tWL

tRCL

tWH

tFCL







EXT Φ0


Notes





RA8806


RA8806

ZRST

RA8806

ZRST

VDD

100KΩ

From MCU

(1) (2)

01uF

1uF

(Option)SW



VDD

ZRSTtRST

tRHtRS08VDD

Reset Complete

02VDD

08VDD




UnitMinTypMax





RA8806


6-7 Power



RA8806

VDDP

VDDVDDH

AVDD

GNDP

GND

AGND

Core

5V 3V

ADC



RA8806

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

33V

047uH

10u 01u 01u 01u

047uH

VDD

GND IO

MCU33V

(Option)

(Option)




RA8806



RA8806MCU5V

i

VDDP

VDD

VDDH

AVDD

MCU IF

GNDP

GND

AGND

5V

VDD

GNDIO

047uH

10u 01u 1u 01u 01u

~3V

(Option)



RA8806










REG[00h]



RA8806












Wake-Up Event

INT

t INTST




RA8806




Key-ScanEvent

INT

t INTST








RA8806

RA8806

MCU

DisplayData RAM


InterfaceController

LCDDriver


XCLK

LP

T_COM

ITCR COM_SCAN









RA8806

RS ZCS1

ZWR

DATA[70]

BUSY

t BST

(Write)

t BUSY






Full Size Font 250






RA8806

6-9 PWM







TH TL







TH TL

TPWM

TPWM




RA8806






RA8806










RA8806

0 1 2 3 4 5 6 7 hellip


1 1 1 0 0 1 1 0D7 D6 D5 D4 D3 D2 D1 D0 　

Segment







Bit 7 ISO8859 mode



REG[F0h]



RA8806



Table 6-24






RA8806

-81h -C1h


00h ～ 2Eh

-01h

40h ～ 7Eh 80h ～ 9Eh

40h ～ 9Dh

9Fh ～ FCh

-7Eh

N=0 N=1

左移1 bit + N

00h ～ 5Dh

+21h




+20h+40h




-1Fh





RA8806




RA8806










REG[00h]




RA8806




Controller

Controller

Controller

Controller

1

2

3

4

DDRAM1 DDRAM2

Controller

Controller

Controller

roller

Visible Display

OR

NOR

XOR

AND







RA8806







DDRAM2

Gray-Scale Display

DDRAM1

411301210100


3a 3b2a 2b 1a 1b0a 0b

3a 3b2a 2b 1a 1b0a 0b

7a 7b6a 6b 5a 5b 4a 4b

7a 7b 6a 6b 5a 5b 4a 4b

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0








RA8806



















RA8806



Program Example





RA8806














RA8806






1 x 1 12 132

2 x 2 36 396

3 x 3 76 836

4 x 4 132 1452



RA8806


0

15

0 7

0 150

7




RAiO


SEG0 SEG319COM0

COM239

RAiO


COM239 COM0SEG0

SEG319




RA8806









RA8806













8F1F

9F0F

8F1E

15

8F1D

9F0E

8F1C

14

8F1B

9F0D

8F1A

13

9F0B

8F16

11

8F15

9F0A

8F14

10

8F13

9F09

8F12

9

8F11

9F08

8F10

8

8F19

9F0C

8F18

12

8F17Half-Size

Full-Size

FontCode

8F0F

9F07

8F0E

7

9F00

8F00

0

9F02

8F04

2

9F04

8F08

4

9F03

8F06

3

8F0D8F0B8F098F058F01

9F01

8F02

1


9F069F05Full-Size

65Font

Code



RA8806

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

0001

0010

0011

0100

0101

0110

0111

0000

1001

1010

1011

1100

1101

1110

1111

1000

4 3 2 1 056 12357 0467 4 3 2 1 0567







REG[12h]

CURX Bit [40]


REG[60h]


REG[70h]



RA8806

CGRAMCreate Font


be created) (1)




display layer (3)




Note












RA8806




RA8806

Program Example(2)


font_data[] = 00 82 44 28 FE 10 10 10 FE 10 10 38 54 92 10 00











REG[12h]





RA8806


CURX

8001 8002 8026 8027

8100 8101 8102 8126 8127

8200 8201 8202 8226 8227

8300 8301 8302 8326 8327

8400 8401 8402 8426 8427

8500 8501 8502 8526 8527

8700 8701 8702 8726 8727

8800 8801 8802 8826 8827

8A00 8A01 8A02 8A26 8A27

8B00 8B01 8B02 8B26 8B27

8C00 8C01 8C02 8C26 8C27

8D00 8D01 8D02 8D26 8D27

8600 8601 8602 8626 8627

8900 8901 8902 8926 8927

8E278E00 8E01 8E02 8E26

CURY0 1 2 26 27

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 26 27

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

8000


CURX

9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 90139000 9001 9002 9003 9004 9005 9006 9007 9008 9009 900A 900B 900C 900D 900E 900F 9010 9011 9012 9013

9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 91139100 9101 9102 9103 9104 9105 9106 9107 9108 9109 910A 910B 910C 910D 910E 910F 9110 9111 9112 9113

9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 92139200 9201 9202 9203 9204 9205 9206 9207 9208 9209 920A 920B 920C 920D 920E 920F 9210 9211 9212 9213

9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 93139300 9301 9302 9303 9304 9305 9306 9307 9308 9309 930A 930B 930C 930D 930E 930F 9310 9311 9312 9313

9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 94139400 9401 9402 9403 9404 9405 9406 9407 9408 9409 940A 940B 940C 940D 940E 940F 9410 9411 9412 9413

9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 95139500 9501 9502 9503 9504 9505 9506 9507 9508 9509 950A 950B 950C 950D 950E 950F 9510 9511 9512 9513

9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 97139700 9701 9702 9703 9704 9705 9706 9707 9708 9709 970A 970B 970C 970D 970E 970F 9710 9711 9712 9713

9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 98139800 9801 9802 9803 9804 9805 9806 9807 9808 9809 980A 980B 980C 980D 980E 980F 9810 9811 9812 9813





9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 96139600 9601 9602 9603 9604 9605 9606 9607 9608 9609 960A 960B 960C 960D 960E 960F 9610 9611 9612 9613

9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 99139900 9901 9902 9903 9904 9905 9906 9907 9908 9909 990A 990B 990C 990D 990E 990F 9910 9911 9912 9913



00

10

20

30

40

50

60

70

80

90

A0

B0

C0

D0

E0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14



RA8806

Start

Access DDRAM1

( REG[12h] [10] = 0 1 )

Yes

N0

Show DDRAM2

( REG[12h] [64] = 010 )

Write 16 bytes data

Set Graphic Mode

( REG[00h] B3 = 0 )




( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

X add 1

(Set REG[60h])


( Set REG[60h][70h] )


Y add 1

(Set REG[70h])

Yes


Access Page2

( REG[12h] [10] = 1 0 )

Set Text Mode

( REG[00h] B3 = 1 )




Write CMD


DDRAM1 to DDRAM2





RA8806

Program Example(3)





RA8806









RA8806

Program Example(4)











RA8806








REG[03h]






Start




( Set REG[03h][21] = 0 0 )



i


RA8806




RA8806



Start




( Set REG[03h][21] = 0 1 )





RA8806


6-13 Cursor











RA8806







瑞


cursor

CASE 1






RA8806


瑞



cursor

CASE 2

1 Cursor set


1 Cursor set


瑞



cursor

CASE 3


i


RA8806





瑞佑科技









RA8806



RA8806LCD Panel

Max 320x240

Normal Mode

ComSeg Signals

LCD Driver

RA8806

LCD Panel

Max 640x240or

Max 320x480

Extension Mod

ComSeg Signals

LCD Driver


320320






RA8806

320

240DDRAM1

Data

DDRAM2Data240


DDRAM1 DDRAM2





RA8806

DDRAM1 DDRAM2



DDRAM1

DDRAM2


DDRAM1

DDRAM2




RA8806









REG[01h]




RA8806

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Start


Memory access cycle

low

high

Start


Memory access cycle

low

high

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR




LP

XCLK

SCAN_BUSY

MPU cycle



Confliction

LP

XCLK

SCAN_BUSY

MPU cycle



Confliction





RA8806

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low

Start

Check status bit-6

(SCAN BUSY)

Check status bit-6

(SCAN BUSY)

high

high

low

Memory access cycle

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



low






LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction

MPU cycle too long





RA8806

LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction


LP

XCLK

SCAN_BUSY

MPU cycle

ITCR



Confliction




SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle


SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration





Read Status cycle



SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






SCAN_BUSY

RD

ZWR

Tcyc Tcyc

ITCR duration






i


RA8806



7-1 Bonding Pad

CLK

_OU

T

ZRS

TX

GX

DD

ATA

7D

ATA

6D

ATA

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0ZR

DZW

RV

DD

PG

ND

P

CS

2R

S

X1Y1X2Y2AVDDAGND

INTBUSYVDDH


PWM_OUTPWM_OUT

TES

TITE

STM

D

ZCS1

VDD

RA8806 Logo

KIN

0K

IN1

KIN

2K

IN3

KIN

4K

IN5

KIN

6K

IN7

KO

UT0

KO

UT1

KO

UT2

KO

UT3

KO

UT4

KO

UT5

KO

UT6

KO

UT7 DB MI

DW

VD

DP

RA8806

282726252423222120

19181716151413121110

987654321

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68



RA8806








RA8806


7-3 Pin Assignment

RAiORA8806L2N-T

TM

08XX-N

Pin 1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CLK

_OU

T

VDD

PG

ND

P

NC

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT

ZCS1



DBMI

DW


GNDPRSCS2


5 10 15 20 25 30

35

40

45

50556065707580

85

90

95

100

NC


RAiORA8806T1N-S

TM

08XX-N

Pin 1

KIN

0N

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CC

LK_O

UT

LD1

LD2

LD3

ZDO

FFXC

KYD LP FR

GN

DVD

DVD

DH

BU

SY INT

AG

ND

AVD

D Y2 X2 Y1 X1PW

M_O

UT



DBMI

VDDPGNDP

LD0


5 10 15 20

25

30

35


GNDPRSCS2ZCS1

45505560

65

70

75

80

VDDP




RA8806


E1E

D1 D

e

bRA

iOTM

RA

8806L2N-ST

08xx-N

Pin-1 Index

Seating Plane

Detail A010mm

θ1

θ2

θ3θ

LL1

Gauge Plane

R2

A2 A

R1

A1

C

Detail A

025

mm


i


RA8806




A -- -- 160 -- -- 0063

A1 005 -- 015 0002 -- 0006

A2 135 140 145 0053 0055 0057

b 022 03 033 0009 0012 0013

c 009 -- 016 0004 -- 0006

e 065 BSC 0026 BSC

D 2200 BSC 0866 BSC

D1 2000 BSC 0787 BSC

E 1600 BSC 0630 BSC

E1 1400 BSC 0551 BSC

L 045 060 075 0018 0024 0030

L1 100 Ref 0039 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008


θ1 0 -- -- 0 -- --






RA8806




RA8806




A -- -- 120 -- -- 0047

A1 005 010 015 0002 0004 0006

A2 095 100 105 0037 0039 0041

b 013 018 023 0005 0007 0009

b1 013 016 019 0005 0006 0007

c 009 -- 020 0004 -- 0008

c1 009 0127 016 0004 0005 0006

e 040 BSC 0016 BSC

D 1190 1200 1210 0469 0472 0476

D1 990 1000 1010 0390 0394 0398

E 1190 1200 1210 0469 0472 0476

E1 990 1000 1010 0390 0394 0398

L 045 060 075 0018 0024 0030

L1 100 Ref 0040 Ref

R1 008 -- -- 0003 -- --

R2 008 -- 020 0003 -- 0008




RA8806

7-5 Part Number



Resolution (Max)


Compliance


(Note 2) ISO-8859-1 ~ 4 Yes


(Note 2) ISO-8859-1 ~ 4 Yes

RA8806L2N-J

LQFP-100 (20x14)



(Note 2 3) ISO-8859-1 ~ 4 Yes


(Note 2 3) ISO-8859-1 ~ 4 Yes

RA8806T1N-J

TQFP-80 (10x10)


ISO-8859-1 ~ 4 Yes


320x240 (Note 1)


Notes










RA8806


















RA8806







Figure 6-30)






ISB 18 21 mA Case2


140 160 μA Case2 -- 05 1 μA Case1










RA8806



LP


tWLPH

tWCK

XCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

LPLP


tWLPH

tWCK

XCKXCK

tWCKLtWCKH

tDS tDH

tWCKH

ITCR

tLD

tSL

tLS

tLH

























Note






RA8806





RA8806







(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR 320 240 4 55 72 55 -- 55 -- 320 240 4 60 59 60 -- 60 -- 320 240 4 65 48 65 -- 65 -- 320 240 4 70 39 70 -- 70 -- 320 240 4 75 31 75 -- 75 -- 320 240 6 55 147 55 34 55 -- 320 240 6 60 128 60 24 60 -- 320 240 6 65 112 65 16 65 -- 320 240 6 70 99 70 9 70 -- 320 240 6 75 87 75 3 75 -- 320 240 8 55 223 55 72 55 -- 320 240 8 60 198 60 59 60 -- 320 240 8 65 176 65 48 65 -- 320 240 8 70 158 70 39 70 -- 320 240 8 75 142 75 31 75 -- 320 240 10 55 -- 55 109 55 15 320 240 10 60 -- 60 94 60 7 320 240 10 65 241 65 80 65 -- 320 240 10 70 218 70 69 70 -- 320 240 10 75 198 75 59 75 -- 320 240 12 55 -- 55 147 55 34 320 240 12 60 -- 60 128 60 24 320 240 12 65 -- 65 112 65 16 320 240 12 70 -- 70 99 70 9 320 240 12 75 253 75 87 75 3 240 160 4 55 167 55 54 55 -- 240 160 4 60 148 60 44 60 -- 240 160 4 65 132 65 36 65 -- 240 160 4 70 119 70 29 70 -- 240 160 4 75 107 75 23 75 -- 240 160 6 55 -- 55 110 55 25 240 160 6 60 -- 60 96 60 18 240 160 6 65 228 65 84 65 12 240 160 6 70 208 70 74 70 7 240 160 6 75 190 75 65 75 3 240 160 8 55 -- 55 167 55 54 240 160 8 60 -- 60 148 60 44 240 160 8 65 -- 65 132 65 36 240 160 8 70 -- 70 119 70 29 240 160 8 75 -- 75 107 75 23 240 160 10 55 -- 55 224 55 82 240 160 10 60 -- 60 200 60 70 240 160 10 65 -- 65 180 65 60 240 160 10 70 -- 70 163 70 52 240 160 10 75 -- 75 148 75 44 240 160 12 55 -- 55 -- 55 110 240 160 12 60 -- 60 253 60 96 240 160 12 65 -- 65 228 65 84 240 160 12 70 -- 70 208 70 74 240 160 12 75 -- 75 190 75 65



RA8806





(Hz) REG[90h]

ITCR Frame Rate


REG[90h]ITCR

160 160 4 55 187 55 74 55 17 160 160 4 60 168 60 64 60 12 160 160 4 65 152 65 56 65 8 160 160 4 70 139 70 49 70 5 160 160 4 75 127 75 43 75 2 160 160 6 55 -- 55 130 55 45 160 160 6 60 -- 60 116 60 38 160 160 6 65 248 65 104 65 32 160 160 6 70 228 70 94 70 27 160 160 6 75 210 75 85 75 23 160 160 8 55 -- 55 187 55 74 160 160 8 60 -- 60 168 60 64 160 160 8 65 -- 65 152 65 56 160 160 8 70 -- 70 139 70 49 160 160 8 75 -- 75 127 75 43 160 160 10 55 -- 55 244 55 102 160 160 10 60 -- 60 220 60 90 160 160 10 65 -- 65 200 65 80 160 160 10 70 -- 70 183 70 72 160 160 10 75 -- 75 168 75 64 160 160 12 55 -- 55 -- 55 130 160 160 12 60 -- 60 -- 60 116 160 160 12 65 -- 65 248 65 104 160 160 12 70 -- 70 228 70 94 160 160 12 75 -- 75 210 75 85 160 128 4 55 244 55 102 55 31 160 128 4 60 220 60 90 60 25 160 128 4 65 200 65 80 65 20 160 128 4 70 183 70 72 70 16 160 128 4 75 168 75 64 75 12 160 128 6 55 -- 55 173 55 67 160 128 6 60 -- 60 155 60 58 160 128 6 65 -- 65 140 65 50 160 128 6 70 -- 70 127 70 44 160 128 6 75 -- 75 116 75 38 160 128 8 55 -- 55 244 55 102 160 128 8 60 -- 60 220 60 90 160 128 8 65 -- 65 200 65 80 160 128 8 70 -- 70 183 70 72 160 128 8 75 -- 75 168 75 64 160 128 10 55 -- 55 -- 55 138 160 128 10 60 -- 60 -- 60 123 160 128 10 65 -- 65 -- 65 110 160 128 10 70 -- 70 239 70 100 160 128 10 75 -- 75 220 75 90 160 128 12 55 -- 55 -- 55 173 160 128 12 60 -- 60 -- 60 155 160 128 12 65 -- 65 -- 65 140 160 128 12 70 -- 70 -- 70 127 160 128 12 75 -- 75 -- 75 116



RA8806






(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR Frame Rate

(Hz) REG[90h]

ITCR

240 128 4 55 224 55 82 55 11 240 128 4 60 200 60 70 60 5 240 128 4 65 180 65 60 65 -- 240 128 4 70 163 70 52 70 -- 240 128 4 75 148 75 44 75 -- 240 128 6 55 -- 55 153 55 47 240 128 6 60 -- 60 135 60 38 240 128 6 65 -- 65 120 65 30 240 128 6 70 -- 70 107 70 24 240 128 6 75 253 75 96 75 18 240 128 8 55 -- 55 224 55 82 240 128 8 60 -- 60 200 60 70 240 128 8 65 -- 65 180 65 60 240 128 8 70 -- 70 163 70 52 240 128 8 75 -- 75 148 75 44 240 128 10 55 -- 55 -- 55 118 240 128 10 60 -- 60 -- 60 103 240 128 10 65 -- 65 240 65 90 240 128 10 70 -- 70 219 70 80 240 128 10 75 -- 75 200 75 70 240 128 12 55 -- 55 -- 55 153 240 128 12 60 -- 60 -- 60 135 240 128 12 65 -- 65 -- 65 120 240 128 12 70 -- 70 -- 70 107 240 128 12 75 -- 75 253 75 96 240 64 4 55 -- 55 224 55 82 240 64 4 60 -- 60 200 60 70 240 64 4 65 -- 65 180 65 60 240 64 4 70 -- 70 163 70 52 240 64 4 75 -- 75 148 75 44 240 64 6 55 -- 55 -- 55 153 240 64 6 60 -- 60 -- 60 135 240 64 6 65 -- 65 -- 65 120 240 64 6 70 -- 70 -- 70 107 240 64 6 75 -- 75 253 75 96 240 64 8 55 -- 55 -- 55 224 240 64 8 60 -- 60 -- 60 200 240 64 8 65 -- 65 -- 65 180 240 64 8 70 -- 70 -- 70 163 240 64 8 75 -- 75 -- 75 148 240 64 10 55 -- 55 -- 55 -- 240 64 10 60 -- 60 -- 60 -- 240 64 10 65 -- 65 -- 65 240 240 64 10 70 -- 70 -- 70 219 240 64 10 75 -- 75 -- 75 200 240 64 12 55 -- 55 -- 55 -- 240 64 12 60 -- 60 -- 60 -- 240 64 12 65 -- 65 -- 65 -- 240 64 12 70 -- 70 -- 70 -- 240 64 12 75 -- 75 -- 75 253





RA8806



0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL




RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

HL

i


RA8806


0 1 2 3 4 5 6 7 8 9 A B C D E F

0

1

2

34

5

6

78

9

A

B

C

D

E

F

HL




RA8806



i


RA8806






RA8806



i


RA8806





RA8806




RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806



RA8806




RA8806






RA8806

A4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ














RA8806

A7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










A9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

AA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

AD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










AF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

B0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










B8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

B9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ













RA8806

BC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










BE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ











RA8806

BF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

C5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










C6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ







C7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ









Ｆヴヵヶ



RA8806

C8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 5 6 7 Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　Ｄ　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

C9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

CE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










CF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

D7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










D9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

DD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










DF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










E8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

E9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










ED 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










EE 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

EF 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F0 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F1 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F2 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F3 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F4 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F5 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F6 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F7 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ












RA8806

F8 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ










F9 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ








FA 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　



RA8806

FB 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FC 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　

FD 0 1 2 3 4 5 6 7 8 9 ＡＢＣＤＥＦ

4 　　　　　　　　　　　　　　　　

5 　　　　　　　　　　　　　　　　

6 　　　　　　　　　　　　　　　　

7 　　　　　　　　　　　　　　　Ａ　　　　　　　　　　　　　　　

Ｂ　　　　　　　　　　　　　　　　

Ｃ　　　　　　　　　　　　　　　　

Ｄ　　　　　　　　　　　　　　　　

Ｅ　　　　　　　　　　　　　　　　

Ｆ　　　　　　　　　　　　　　　




RA8806




2 Feature

3 Block Diagram

4 Pin Definition

4-1 MPU Interface

4-2 Clock Interface



4-5 Power





6-1 MPU Interface

6-1-1 MPU Type

6-1-2 Command Write


6-1-4 Status Read









6-4 Touch Panel

6-4-1 Auto Mode

6-4-2 Manual Mode




6-5 Key-Scan

6-6 Clock and Reset

6-6-1 OSC Circuit


6-6-3 Reset

6-7 Power




6-7-4 Sleep Mode


6-8-1 Interrupt

6-8-2 Busy

6-9 PWM








6-10-1-6 Line Gap










6-13 Cursor








7-1 Bonding Pad


7-3 Pin Assignment


A

A

7-5 Part Number





raio ra8806mar 02, 2009 · (zrw) i . write/read-write . when mpu i/f is 8080 series, this pin...

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