Job Paper Ramesh Raju Navan

Electrical Engineering Department IIT Bombay

Professional Objective

Research and development in the area of fabrication, characterization and Simulation of advance MOS transistors and process integration technology. Interested in early exploration of advanced technologies and systems.

Areas of Interest

CMOS/VLSI Technology, Organic/Polymer Electronics, Design and Simulation of Devices, Novel material characterization and Device Structures.

Title of PhD Thesis: ASIC Design using Organic Thin Film Transistor

Introduction

The field of low-cost organic electronics is a relatively new topic of research in the

domain of semiconductor technology. Activities started in the 1980s by demonstrating organic

field effect transistors (OFETs) which make use of special organic compounds for the

semiconducting channel instead of crystalline silicon. These OFETs cannot compete with

silicon-based transistors regarding switching speed or packing density but provide prospects of

considerably reducing fabrication costs, large-area manufacturing (i.e. direct application of

electronic structures onto large substrates), or implementing mechanically flexible integrated

circuits. These advantages generate applications of OFETs where fabrication costs or flexibility

are more important than e.g. switching speed of the transistors. One example is the

implementation of extremely low-cost radio-frequency identification (RFID) tags. Fabrication

costs below one Cent would e.g. boost application of RFID devices as price tags in supermarkets.

Owing to their complex fabrication, silicon-based RFID tags cannot reach this price target.

Currently, low-cost organic electronics is in the early stages of development and

optimization of devices and processes. Various materials and fabrication processes are

continuously tested and optimized. Circuit simulation is an important part in this process as it

provides insight into the performance potential of existing or hypothetical OFET generations in

OFET based circuits. In the course of circuit simulation, devices are modeled and the electrical

performance of typical application circuits is analyzed. Employing circuit simulation in the

process of optimizing devices consists of numerous iterations of modeling devices, simulating

application circuits, and extracting performance figures from simulation results. Therefore,

efficient methods of modeling OFET devices and analyzing OFET-based circuits by use of

circuit simulation are needed in order to automate the analysis process as much as possible.

Scientific Contribution of PhD Thesis Work

Progress in the simulation-based circuit analysis of organic transistors could be made in

this work. Second, a novel methodology for extracting device parameters has been developed.

The transistor characteristics drain-current (ID) vs. drain-source voltage (VDS) are inspected. A

novel device simulation technique was developed for organic TFTs. ISE-TCAD was used by

replacing device parameters for Silicon with that of Pentacene. An acceptable match was

observed in simulated and measured characteristics of the devices by tuning the device

parameters. The results obtained from device simulation procedure were thus used to generate

the LUTs for the organic devices which were used for circuit simulation.

Patterned gate p-type OTFTs with HfOx as high-k gate dielectric materials were

fabricated for circuit applications, which showed low operating voltages (-4V). All p-type

organic inverters composed of enhancement mode load and driver were fabricated which operate

at a low operating (0 to 4V) and bias voltages (VDD = 4V). Another approach for simulation was

to extract spice parameters of OTFTs with the PSO algorithm. This was done for both Pentacene

and P3HT based devices.

Figure OTFT structure in Bottom Gate Bottom contact configuration with patterned gate (Al)

Figure Output (IDS-VDS), transfer IDS-VGS (triangles) and IDS

1/2 -VGS (solid line) characteristics of a typical fabricated OTFT with HfOx as gate dielectric

(W/L=15200µm /20µm)

Figure Measured vs. Simulated IDS− VDS characteristics for OTFTs fabricated (Data scaled to width W=1μm)

Figure DC transfer characteristics and Transient response of the simulated all p-type enhancement mode organic inverter for VDD= 5.0 V. Inset shows the schematic of Inverter.

Several methods of surface improvement were tried and compared with each other. A

novel procedure for OTS deposition was theorized and verified experimentally to be correct.

OTS deposition on silicon dioxide was found to give the highest mobilities among all the

methods tried of 0.26 cm2/Vs.

We also demonstrated the fabrication of ZnO/P3HT nanocomposite transistors. A

comparative picture was presented between these composite based and pristine P3HT transistors.

Our results indicate a tenfold mobility enhancement in the composite transistors compared to

pristine ones, without any significant deterioration in threshold voltage or on-off current ratio.

However, there is still scope for further improvement in terms of better dispersion of ZnO

nanostructures and the possibility of obtaining higher on-off current ratios.

Figure Cross sectional view of the P3HT/ZnO nanocomposite based bottom contact organic filed effect transistor. Transfer (IDS-VGS) characteristics comparison for different concentration of ZnO nanorods in P3HT/ZnO nanocomposite where VGS is varied from 10 to -40V & VDS = -40V

The use of metallated porphyrin SAM for the tuning of the threshold voltage of pentacene

based OTFTs has been studied. The Id-Vg curves showed that porphyrin SAMs having different

central metal atoms are responsible for the change in the threshold voltage values of the

corresponding OTFTs. The formation of SAM was confirmed by the UV-Vis spectroscopy.

We have also demonstrated a low voltage organic field effect transistor with a

photopatternable nanoparticle (BT) SU-8 composite with a dielectric constant in the range of 14.

The material is a good candidate for all-polymer FETs as its implementation does not require

expensive deposition techniques, the process is large area compatible and the gate dielectric

easily photopatternable. The BT concentration in SU-8 is optimized from the dielectric constant

and the leakage current point of view. We have demonstrated excellent OFET performance at a

BT wt% of 0.88 which gives a dielectric constant of around 14. At this BT concentration, the

SU-8 composite is still photopatternable. With higher BT concentration, the surface roughness

increases which increases the leakage current and degrades the mobility. This work therefore

establishes a promising photopatternable high-k dielectric process for fabrication of OFETs and

circuits through a solution processing method.

Figure Capacitance verses frequency plots for different concentration of BT nanoparticles

blended into the SU-8 dielectric films and Dependence of resistivity and dielectric constant on BT wt% and Cross-section of Organic Inverter

A new compact OTFT-based ADC using only p-type transistors, fabricated in the same

process, is designed and simulated using LUT-based approach in SEQUEL circuit simulator, the

LUT data is obtained from fabricated pentacene-based OTFTs using sputtered SiO2 as a gate

dielectric and source/drain contacts made of gold. The LUT simulation approach is validated at

the circuit level using the measurements taken on fabricated OTFT-based inverter. The ADC

circuit is designed using proposed 4-transistor architecture to control the switching voltage of a

differential inverter. Though the designed ADC is aimed for high voltage levels of around tenths

of volts its operation was limited to 5V due to increased leakage of Pentacene-based organic

transistors at high voltages.

Figure Block diagram of the ADC circuit synthesized using the voltage divider

and the differential inverter circuit

Figure (a) Differential inverter circuit using four P-type transistors. (b) LUT-based simulation results of the switching characteristic of the inverter for higher values of VIN, the output voltage tends to the

threshold voltage of M2 i.e. around 2.3V.

Figure (a) Cascade circuit of a differential and simple inverter for each single bit of ADC (b) Simulation results of the ADC

Research and Development Expertise

Working in Microelectronics and Nanotechnology lab of Department of Electrical Engineering, at Indian Institute of Technology, Bombay, INDIA and also did internship at Nanyang Technological University, Singapore (25thFeb to 30th May, 2008), I have exposure in semiconductor processing, characterization & simulation. Specifically, I have worked on the following aspects as part of my Ph.D. Lithography Oxidation, Depositions, Metallization All chemical etching, cleaning and safety procedures for the Device fabrication Electrical characterization Device Physics based analysis of fabricated MOS devices and Organic Field Effect

Transistors (OFETs). Process & Device simulation using ISE-TCAD Circuit simulation using simulators like SPICE, SEQUEL.