What is memory?

A term for a device that enables the computer to retain (store) information.

What are the types of memory?

Volatile memory (Random Access Memory/RAM; Cache Memory; Virtual Memory)- Contents of memory are erased when power supply is turned off. Also called Temporary storage.

Nonvolatile memory(Read Only Memory/ROM; Flash Memory)- Contents of memory are not erased when power is turned off. Also called Permanent storage.

Random Access Memory (RAM) Technology• Why do computer

designers need to know about RAM technology?– Processor performance is

usually limited by memory bandwidth

– As IC densities increase, lots of memory will fit on processor chip

• Tailor on-chip memory to specific needs

- Instruction cache

- Data cache

- Write buffer

• What makes RAM different from a bunch of flip-flops?– Density: RAM is much

denser

Memory SpeedUnit one billionth of a second ( nanosecond)

DRAM: 50-100nsSRAM: 10-50nsROM: 50-250ns

Main Memory Background•Random Access Memory (vs. Serial Access Memory)•Different flavors at different levels

–Physical Makeup (CMOS, DRAM)–Low Level Architectures (FPM,EDO,BEDO,SDRAM)

•Cache uses SRAM: Static Random Access Memory–No refresh (6 transistors/bit vs. 1 transistor

Size: DRAM/SRAM 4-8, Cost/Cycle time: SRAM/DRAM 8-16

•Main Memory is DRAM: Dynamic Random Access Memory–Dynamic since needs to be refreshedperiodically (8 ms, 1% time)–Addresses divided into 2 halves (Memory as a 2D matrix):

»RAS or Row Access Strobe»CASor Column Access Strobe

Timing Diagram Conventions

Input Signal Output Signal

Must be steady Will be steady high or lowhigh or low

High-to-low Will be changing fromchanges permitted high-to-low during

designated interval

Low-to high Will be changing fromchanges permitted low-to-high during

designated interval

Don't-Care State changing

(Does not apply) Centerline represents high impedance (off) state

RAM Timing

Simplified Read TimingSimplified Read Timing

Simplified Write TimingSimplified Write Timing

WE

CS

Address

Data Out Data Out

Valid Address

Access Time

Input Data

Valid Address

Data In

Address

WE

CS

Memory Cycle Time

Access Time

The time it takes for new data to be ready to appear at

the output

Access Time

The time it takes for new data to be ready to appear at

the output

The most important parameterof the clock is the duration of a cycle,tCYC.

The Clock Cycle

The old address is removedin clock state S0 and theaddress bus floated

Valid Address

Initially, in stateS0 the addressbus contains theold address

In state S1 a newaddress becomesvalid for the remainderof the memory access

Address Bus

tCLAV

Valid Address

We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted

When AS* is active-low it indicates that the address is valid

We now look at the timing of the clock, the address, and the address strobe

AS* goes active low afterthe address has become validAS* goes inactive

high before the addresschanges

AS* goes low in clockstate S2

The data strobe, is assertedat the same time as AS*in a read cycle

The timing of DS* in a read cycle is the same as the address strobe, AS*

Data from the memoryappears near the end ofthe read cycle

The earliest time at which the memory canbegin to access data is measured from the pointat which the address is first valid

Data from the memory is latched intothe 68000 by the falling edge of theclock in state S6.

Data must be validtDICL seconds beforethe falling edge of S6

We know that the time between theaddress valid and data valid is tacc

The address becomesvalid tCLAV seconds afterthe falling edge of S0

From the fallingedge of S0 to thefalling edge of S6:

•the address becomes valid•the data is accessed•the data is captured

3 tcyc = tCLAV + tacc + tDICL