Rapid Test and Development System forIon Chip Traps

R. Graham, J. Wright, S. Chen, S. Nelson, G. Shu, B.B. Blinov

University of Washington, Seattle, USA This work is funded by IARPA under the MUSIQC project.

Abstract

Planar ion chip traps are good quantum computer candidates because DC control electrodes placed within hundreds of microns of the trapping region allow finecontrol over multiple trapped ions simultaneously. Recently fabricated chips include mounted optical cavities, fabricated mirrors for photon collection and printedmicrowave coils for driving hyperfine transitions. In order to facilitate easily mounting and frequently upgrading these traps, we have designed a UHV-compatibleprinted circuit board that connects CPGA-100 socket chip trap carriers to four DB-25 vacuum feedthroughs. The board incorporates low-pass filters on the DCcontrol pins approximately 1 cm from the chip to quickly route capacitive RF pickup to ground. The board is installed in a custom UHV chamber and the DCelectrodes are controlled with a custom low cost DAC solution. We have reached UHV pressures with the assembled system without significant problems, and arecurrently attempting to trap Barium ions.

Introduction

Trapped ions are a promising candidate building block for a quantumcomputer. One of the most promising trap designs is the planar ion trap,fabricated on a chip using semiconductor fabrication techniques [1]. Thebasic design of these traps puts an ion in a trapping region around 70 µmabove the chip surface formed by an RF electric field. The ion is lasercooled with beams passing just above the surface and the position iscontrolled by adjusting DC voltages on electrodes on the trap surface. Thisallows multiple trapping regions to be defined and ions to be shuttledaround the chip.

An example CPGA-100 packaged linearchip trap made by Sandia (left) and aSEM image of the same trap (right)[2,3].

Chamber Design

Traditionally building an ion trap in a vacuum system involves wirewrapping and spot welding to make electrical connections. While thesetechniques are compatible with the Ultra High Vacuum (UHV)environment, they do not scale well to chip traps which might require over100 connections to be made. In addition to being tedious and error prone,large numbers of point to point connections can cause problems withoptical access and molecular flow.

We have designed a trap chamber with all vacuum compatible parts using aprinted circuit board (PCB) to hold the chip carrier. This is shown inexploded view below. The goal of this work has been to realize a system inwhich we can rapidly test different traps and try new ideas. The PCBapproach has secondary benefits, for example it has allowed us to installon-board integrated low pass filters very near to the DC control electrodeson the chip trap which accommodates excellent filtering of the RF trappingfields.

Exploded view of trap chamber

I A recessed viewport allowsimaging optics to be placedvery close to the chip.

I A 6-inch spherical octagonprovides optical access forthe laser beams.

I The chip carrier is held in a100-Pin CPGA PolyetherEther Ketone (PEEK)socket

I The PCB is made from aRogers ceramic-filled PTFEboard laminate with a goldsurface.

I Four PEEK 25-pin D-Subconnectors are used tosupport the PCB and routeDC signals. Only the RFelectrodes requirewire-wrapped connectionsvia a separate feed-through.

I A custom bottom flange isused to mount thefeedthroughs.

Optical access

Efficient collection of fluorescence light from the ion and good imaging isimportant, initially for trapping and ultimately for robust qubit statedetection and for generating remote entanglement [3].

We are now using a recessed top viewport which allows us to place amicroscope objective very close to the ion, achieving a numerical apertureof 0.28. In the future we plan to switch to a bellows mounted customrecessed viewport. This will hold a custom optic mated with the viewportto achieve near diffraction limited imaging of the ion.

DC Potential Control

Because of the large number of DC electrodes which must be controlled,using off-the-shelf equipment quickly becomes cumbersome and expensive.

We have designed a low cost (around $300) custom electrode controlsystem around three AD5372 digital to analog converters. These parts haveproven quite capable, allowing us to control 96 electrodes over a 20 V rangeto within 0.3 mV at an update rate of 2.4 µs/channel with the ability tosimultaneously update multiple channels.

DC potential control board

Conclusion

I After operating two systems of this design for nearly a year, we have foundthem reliable and easy to assemble. Traps can be swapped out andmodifications made in a few hours. After a couple of days of bakingfollowed by titanium sublimation pumping we can achieve a stable pressurearound 10−11 Torr.

I The signals applied to the DC electrodes are clean, with an overallattenuation of the 16 MHz RF signal of around -66 dB.

I The AD5372 chips form a convenient solution for controlling the DCvoltages and are suitable for setting up trapping regions and shuttlingoperations.

References

[1] D. Kielpinski, C. Monroe, and D. J. Wineland, Nature 417, 709 (2002)

[2] D Stick, K M Fortier, R Haltli, C Highstrete, D L Moehring, C Tigges, M G Blain, “Demonstration of a

microfabricated surface electrode ion trap” Physics arXiv:1008.0990v2 (2010)

[3] M. G. Blain, S. A. Kemme, D. L. Stick, C. P. Tigges, A. A. Cruz-Cabrera, A. R. Ellis, L. Fang, K. M.

Fortier, W. L. Gordy, R. A. Haltli, C. Highstrete, T. L Lindgren, D. L. Moehring, C. Y. Nakakura, M. E.

Smith, J. E. Stevens, J. R. Wendt, J. J. Hudgens, “Microfabricated Surface Ion Traps for Quantum

Computation”, poster presented at annual SQUINT meeting, 2011

[4] G. Shu, C-K. Chou, N. Kurz, M.R. Dietrich, B.B. Blinov, “Efficient fluorescence collection and ion

imaging with the ‘tack’ ion trap,“ J. Opt. Soc. Am. B 28, 2865-2870 (2011)

http://depts.washington.edu/qcomp/pdfs/squint2012-rdg.pdf rdgraham@uw.edu