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RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FPL September 5-7, 2011

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RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FPL September 5-7, 2011. Why Build Your Own Tools Anyway?. Proof of concept in their own right - PowerPoint PPT Presentation

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Page 1: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip LundriganBrent Nelson and Brad Hutchings

FPLSeptember 5-7, 2011

Page 2: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Why Build Your Own Tools Anyway?

• Proof of concept in their own right– Hypothetical architectures may not account

for all real-world factors• Targeting real chips important

• The field needs wild and crazy ideas– The vendors don’t have all the answers!

• That requires custom CAD tools

2

Page 3: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

The Challenge

• Building custom physical CAD Tools for commercial FPGAs == difficult– Closed, proprietary

device databases– Unsupported

interfaces• Architectural nuances

complicate things…

3

Page 4: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Motivation #1: Rapid Prototyping

tool runtime

qual

ity o

f res

ult (

QO

R)

hoursminutesseconds

Page 5: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Motivation #1: Rapid Prototyping

tool runtime

qual

ity o

f res

ult (

QO

R)

hoursminutesseconds

Commercial toolsfocus here…

Page 6: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Motivation #1: Rapid Prototyping

tool runtime

qual

ity o

f res

ult (

QO

R)

hoursminutesseconds

Commercial toolsfocus here…

For rapid prototyping and implementation we would like tools which focus here…

Page 7: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Motivation #2: Reliability

• SEU mitigation using TMR– Selective duplication tools– Single-bit TMR failures in routing

• Half-latch detection– Weak keeper tie-offs susceptible to SEUs

• Need a way to do post-PAR analysis• Need a way to do post-PAR modifications

7

Page 8: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDL: A Physical Database for Xilinx

• A textual design database representation– For Xilinx designs

• Available for many years

8

Xilinxmap

Xilinx

par –p(route only)

Xilinx

par –r(place only)

.NCD .NCD .NCD

Xilinxxdl

Xilinxxdl

Xilinxxdl

.XDL.XDL.XDL

BYURapidSmith Tools

Xilinx bitgen

.BIT

Custom CAD Tools

Page 9: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

#1: XDL as a Design Representation

9

• xdl –ncd2xdl design– Converts NCD to XDL

• xdl –xdl2ncd design– Converts XDL back to NCD

• Can inject own CAD tools at any point in the flow or bypass it entirely

• Must convert back to NCD for bitgen

Xilinxmap

Xilinx

par –p(route only)

Xilinx

par –r(place only)

.NCD .NCD .NCD

Xilinxxdl

Xilinxxdl

Xilinxxdl

.XDL.XDL.XDL

BYURapidSmith Tools

Xilinx bitgen

.BIT

Custom CAD Tools

Page 10: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

#2: XDLRC as a Device Description

• xdl -report -pips -all_conns partName– Dumps textual description of specific device

as a .xdlrc file– Details everything you need to write placers

and routers (except timing data)

10

Page 11: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Challenges of XDLRC Device Descriptions

• They are massive!– Up to 73GB of text for one device!– Difficult for tools to directly operate on XDLRC

• They are missing some information– Primitive sites that support more than 1 type– Pin name mappings missing for some sites– Result: placement/routing inefficiencies occur

• RapidSmith solves these problems

11

Page 12: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

SOME TERMINOLOGY

12

Page 13: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

A Familiar View of the Fabric…

13

Page 14: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

A Familiar View of the Fabric…

14

Page 15: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

A Familiar View of the Fabric…

15

L_TERMINT

L_TERMINT

L_TERMINT

INT_SO

INT_SO

INT_SO

INT

INT

INT

INT

INT

INT

INT

INT

INT

CLB

CLB

CLB

CLB

CLB

CLB

IOIS

IOIS

IOIS

Page 16: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDLRC Abstraction – 2D Tile Array

16

Page 17: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDLRC Abstraction - Tiles

17

HCLK_X1Y39

INT_X2Y37

CLB_X2Y37DSP_X10Y32

BRAM_X5Y32

Page 18: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDLRC Abstraction – Primitive Sites

18

INT_X2Y37Contains:TIEOFF_X2Y37

CLB_X2Y37Contains:SLICE_X3Y75SLICE_X3Y74SLICE_X2Y75SLICE_X2Y74

BRAM_X5Y32Contains:RAMB16_X0Y8FIFO16_X0Y8

DSP_X10Y32Contains:DSP48_X0Y17DSP48_X0Y16

Page 19: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDL EXAMPLES

19

Page 20: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDL Example

20

inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91 ,cfg " BXINV::BX BYINV::#OFF ... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4)) ... YUSED::#OFF ";

...

net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , ;

Page 21: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDL Example

21

inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91 ,cfg " BXINV::BX BYINV::#OFF ... F:inst23lut0:#LUT:D=((~A1*A3)+(A1*A2)) G:inst23lut1:#LUT:D=((~A1*A3)+(A1*A4)) ... YUSED::#OFF ";

...

net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2 , pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT , pip INT_X31Y53 OMUX_S3 -> IMUX_B18 , pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3 , ;

Page 22: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDL Module Example

22

module "mux" "inst23" , cfg " _SYSTEM_MACRO::FALSE "; port "mux5i_0_inport" "inst31" "F4"; port "mux5i_1_inport" "inst33" "F2";... inst "inst23" "SLICEL",placed CLB_X13Y45 SLICE_X18Y91 ,

cfg " BXINV::BX BYINV::#OFF ... YUSED::#OFF ";

... net "shiftResult4" , cfg " ", inpin "inst4" G3 , outpin "inst5" YQ , pip CLB_X31Y53 IMUX_B18_INT -> G3_PINWIRE2 , pip CLB_X31Y54 YQ_PINWIRE2 -> SECONDARY_LOGIC_OUTS6_INT , pip INT_X31Y53 OMUX_S3 -> IMUX_B18 , pip INT_X31Y54 SECONDARY_LOGIC_OUTS6 -> OMUX3 , ;endmodule "mux";

Page 23: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

THE RAPIDSMITH TOOL SUITE

23

Page 24: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith

24

XDLFile

RapidSmith

XDLFile

Page 25: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith

25

XDLFile

RapidSmith

XDLFile

Internal GraphRepresenation Ja

va API

Page 26: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith

26

XDLFile

RapidSmith

XDLFile

Java AP

IInternal GraphRepresenation

CustomCad Tools

( create, place,route, modify

circuits )

Page 27: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Abstractions

28

XDL XDLRC

Page 28: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

XDLRC Device File Creation

• Three major strategies to reduce XDLRC information size:– Aggressive wire and object reuse– Careful pruning of unnecessary wires– Customized serialization and compression

• XDLRC size compression of >10,000X • Device files load in just a few seconds or

less

29

Page 29: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Device Files Performance

30

Xilinx Part Name

XDLRC Report Size

RapidSmith File Size

Memory Footprint

Load Time From Disk

Virtex 4 LX200 10.0 GB 1.01 MB 61 MB 602 ms

Virtex 5 LX330 12.5 GB 1.07 MB 69 MB 622 ms

Virtex 6 CX240T

8.5 GB 0.94 MB 35 MB 460 ms

Virtex 6 LX760 22.8 GB 1.76 MB 77 MB 1.07 s

Virtex 7 855T 32.0 GB 2.63 MB 115 MB 1.41 s

Virtex 7 2000T 73.6 GB 5.96 MB 301 MB 3.34 s

Page 30: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

7 EXAMPLES OF RAPIDSMITH USE AND CAPABILITIES

31

Page 31: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Example #1: Random Placer

32

public class RandomPlacer{ public static void main(String[] args){ // Create and load a design Design design = new Design(args[0]); Random rng = new Random(0); // Create random number generator // Place all unplaced instances for(Instance i : design.getInstances()){

if(i.isPlaced()) continue; PrimitiveSite[] sites =

design.getDevice().getAllCompatibleSites(i.getType()); int idx = rng.nextInt(sites.length); int watchDog = 0; // Find a free primitive site while(design.isPrimitiveSiteUsed(sites[idx])){

if(++idx > sites.length) idx = 0; if(++watchDog > sites.length)

System.out.println("Placement failed.");}i.place(sites[idx]);

} // Save the placed design design.saveXDLFile(args[1]); }}

Page 32: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Example #2: Placing a Module

33

// Load XDL file (parses XDL, populated design object)Design design = new Design("moduleContainingDesign.xdl");// Get the 1024-FFT module definition by nameModule fft = design.getModule("fft1024");// Create an instance of the FFT module called "f0"ModuleInstance mi = design.createModuleInstance("f0", fft);//Find all compatible sites with the anchorPrimitiveType type = mi.getAnchor().getType();PrimitiveSite[] sites = design.getDevice().getAllCompatibleSites(type);int i = 0;while(!mi.place(sites[i++], design.getDevice())){ if(i >= sites.length) error(mi.getName()+ " has no valid placement!");}

Page 33: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Example #3: VCC/GND Handling

• GND/VCC supplied in two ways:– LUTs configured to drive ‘1’ or ‘0’– TIEOFF primitives in every switch box

• Supplied GND / VCC posts

• Router must partition nets into neighborhoods to use local static sources– RapidSmith includes a StaticSourceHandler

class with a variety of methods to provide this functionality

34

Page 34: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Example #4: HMFlow

35

.mdl

HMCache

Generic HMG

Design Parser & Mapper

Design Stitcher

XDL Hard MacroPlacer

XDLRouter

.xdl

INPUT DESIGNS

HARD MACRO SOURCES

PLACED & ROUTED XDL

• Rapid compilation approach using hard macros

• Built on top of RapidSmith

Part of CHREC research project

Demonstrated > 50X reduction in tool flow time

Page 35: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Example #5: Device Browser

36

Page 36: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Example #6: Design Explorer

37

Page 37: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith Example #7: Custom Hard Macro Placer

38

Page 38: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

39

RapidSmith Example #7: Timing Visualizer

Page 39: RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Conclusion

• RapidSmith– Provides XDL-based infrastructure– Designed to aid in the construction of custom CAD tools

• Flexible– Custom CAD flow

• HMFlow for Hard Macro-Based Design– Custom individual steps in the flow

• Placer or router– Post Xilinx flow circuit modifications

• Reliability modifications– Post Xilinx flow circuit analysis

• Timing visualization• Available open source:

– http://rapidsmith.sourceforge.net

40

http://rapidsmith.sourceforge.net/
http://rapidsmith.sourceforge.net/

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