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Software Defined Radio Engineering

Day 1:

12/4/2014 John Reyland, PhD

• SDR Introduction • SDR Approaches:

• Software Communications Architecture (SCA) • NASA STRS • GNU Radio and Simulink

• SDR Advantage/Disadvantage • Digital Modulation for SDR

Day 2:

Day 4:

• RF Channels • Channel Equalization • Multiple Access Techniques • Source and Channel Coding

• Analog Signal Processing

Stop me and ask!!!!

1

Day 3:

• Digital Signal Processing

Software Defined Radio Engineering

Basic High Level Structure of a Software Defined Radio:

12/4/2014 John Reyland, PhD 2

Software Defined Radio Engineering Two broad categories of what is called software defined radio:

12/4/2014 John Reyland, PhD 3

Open-source Configuration Design: Enables control and reconfiguration defined by Software Communication Architecture (SCA) specification or other configuration spec such as Open Base Station Architecture Initiative (OBSAI). Example: SCA or STRS complaint radios , OBSAI compliant cellular base station components Business motivation: Radio hardware becomes a commodity as many vendors design to the same standard. This saves money for large users like government and wireless operators because they can program the same hardware to meet new applications.

Proprietary Configuration Design: Mechanism for control and configuration is the intellectual property of the radio manufacturer. Reconfiguration is limited by the user interface and not generally expandable after purchase. Example: Multimode cellular handset, software controlled amateur radio. These might be called “Switch Defined Radio” Business motivation: Radio flexibility appeals to users who need a specific set of fixed signal choices. Future waveforms may not be supportable however this may not be a concern at the time of purchase.

SDR Major Standards, SCA and STRS

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. Software Communications Architecture (SCA) motivation 2. SCA basic concepts 3. SCA comparison with other SDR approaches 4. SCA simplifications 5. Space Telecommunication Radio System (STRS) motivation 6. STRS basic concepts 7. STRS hardware 8. STRS basic software structure 9. STRS applications

4

Software Communications Architecture (SCA)

A goal of SCA is, from [S2a]:

“Provide for the portability of applications between different SCA compliant implementations.”

SCA seeks to save time and money by enabling deployment of SCA compliant waveform applications on radio hardware manufactured by various companies.

12/4/2014 © John Reyland, PhD 5

Software Communications Architecture (SCA)

The SCA “Big picture”, the framework that sets up applications

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Space Telecommunications Radio System (STRS)

12/4/2014 John Reyland, PhD

Is SCA suitable for space flight radio reconfiguration? Space communication can have different constraints: • Space flight radios tend to use

slightly older more “time proven” technology – thus computational resources and memory may be limited .

• Deep space missions can extend

over many years - the ability to reconfigure a waveform after deployment can have significant advantages for data collection.

7

Space Telecommunications Radio System (STRS)

12/4/2014 John Reyland, PhD

http://spaceflightsystems.grc.nasa.gov/SOPO/SCO/SCaNTestbed/

8

NASA’s SCAN SDR test bed mounted externally on the truss of the International Space Station

SDR Architectures

12/4/2014 John Reyland, PhD 9

Learning Objectives:

1. Typical SDR signal processing components 2. Fundamental architectures and interfaces 3. Analog vs. Digital IF sample Distribution 4. FPGA dynamic partial reconfiguration for SDR 5. DSP vs. FPGA reconfiguration

SDR Architectures

SDR digital processing generally follows this structure:

12/4/2014 © John Reyland, PhD

Throughput here means, “How fast can the next value be entered”

See [D38]

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ASIC, FPGA FPGA, DSP DSP, GPP

SDR Architectures

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Define IF (intermediate frequency) as the desired signal center frequency at the ADC output. Generally this means complex baseband samples centered at ~0 Hz (0 Hz IF means the sample rate only has to accommodate the signal bandwidth). We can decouple SDR from the radio front end using distributed digital IF

The channelizer uses DSP techniques to filter and subsample the IF streams to provide only the BW needed.

SDR Architectures

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DSSS and FEC packet processing using alternate FPGA DR frames:

GNU Radio and Simulink

12/4/2014 John Reyland, PhD

Learning Objectives:

1. GNU Radio basics 2. GNU Radio strengths and weakness 3. Simulink basics 4. VHDL coder, Xilinx System Generator, Altera DSP Builder 5. Simulink extensions, how they affect FPGA development

13

GNU Radio and Simulink

12/4/2014 John Reyland, PhD

Overview and comparison of two popular block diagram oriented tools for building SDRs

“Software Defined” here means a set of blocks can be arranged in a block diagram editor (BDE) any number of ways to implement any radio within the capabilities of the RF front end hardware. Notice the difference with SCA, which depends on an arrangement of files. Both approaches require a skilled developer to expand the radio repertoire.

Advantages Disadvantages

GNU Radio

Free and open source, accessible to hobby users.

Runs under Linux, only limited support for Windows. Data flow between blocks can make recursive flow graphs a problem. Does not seem to support VHDL code generation, application is limited to running on PC.

Simulink Runs under both Linux and Windows. Not event driven. Runs sample by sample or fame by frame, timing is tightly controlled so that recursions around blocks are predictable. Block diagrams directly translate to VHDL, facilities product design in a commercial setting.

Expensive, requires multiple toolboxes with multiple licenses

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GNU Radio and Simulink

12/4/2014 John Reyland, PhD

Data path architecture: sample data is continuously flowed between blocks (i.e. streamed)

Sample rate at ADC matters, must match signal bandwidth

Sample rate at DAC is important, must match signal bandwidth

Throughput of signal processing matters. How fast can I enter the next data? Processing can be paced with “Throttle” block. Throttling prevents the simulation from using 100% CPU time.

15

Event driven architecture: Event 1 = DSP process 1 has number of samples ready to output Event 1 trigger = Ready to send Event 1 reaction = DSP process 2 reads samples into FIFO (How many? Consider tradeoff between sample count, efficiency and latency)

GNU Radio and Simulink

12/4/2014 John Reyland, PhD

Simulink VHDL code generation example

Key concept: Simulink BDE, VHDL, and FPGA logic are “Bit and cycle true”

Notice the very precise fixed point attribute (FPA) “sfix24_en12”, a twos complement fixed point signed number with 24 total bits and 12 factional bits. FPA can be different for every signal to minimize use of FPGA resources. This is a departure from the words and bytes of processor based computing.

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SDR Disadvantage/Advantage

12/4/2014 John Reyland, PhD

Learning Objectives:

1. SDR basic advantages, disadvantages 2. Adaptive coding and modulation basics 3. Evolution to cognitive radio

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SDR Advantages

12/4/2014 John Reyland, PhD

SDR Future Proofing (avoiding hardware obsolesce): There are two ways to avoid hardware obsolesce: • Facilitate software reconfiguration of existing hardware

For example SCA XML configuration file sets or STRS XSLT configuration files. This is part of the SCA rational, an expensive hardware platform can have a long life cycle if it can be reconfigured for waveforms that are designed in years to come.

• Modularize hardware so that only part of the radio hardware needs to be upgraded STRS and Open Base Station Architecture Initiative (OBSAI) attempt to future proof hardware by isolating certain modules behind well defined interfaces.

A well defined universally accepted HID can eventually make this STRS module into a commodity. Note that the HID specifies both electrical and mechanical characteristics so that modules from different suppliers can be compatible.

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SDR Advantages

12/4/2014 John Reyland, PhD

SDR Makes Possible Adaptive Coding and Modulation (ACM):

2

0

1 sPC WLog

WN

W = Channel bandwidth limit (Hz) C = Input data rate, not including coding (bits/second) Ps = Signal power (watts) N0 = Noise power spectral density (watts/Hz) R = Actual channel data rate R<C for arbitrarily low error rate

“Given a discrete memoryless channel [i.e. each signal symbol is perturbed by Gaussian noise independently of the noise effects on all other symbols] with capacity C bits per second, and an information source with rate R bits per second, where R<C, there exists a code such that the output of the source can be transmitted over the channel with an arbitrarily small probability of error.”

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SDR Advantages

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SDR Advantages

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• Cognitive Radio does not necessarily depend on SDR. • CR can be implemented with or without the ultimate software defined radio (e.g SCA). • CR and SDR can have separate technology roadmaps.

From [H5]

SDR Modulation Types

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. Linear modulation basics: BPSK, QPSK, MSK, OFDM 2. Peak to Average Power 3. Raised Cosine Filtering 4. Error Vector Magnitude (EVM) 5. IEEE 802.11a for wireless LANs 6. PSK coding for Doppler mitigation 7. Nonlinear modulation basics: FSK, GMSK 8. GMSK precoding

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SDR Modulation Types

12/4/2014 © John Reyland, PhD 23

MSK Demodulator

SDR Modulation Types

12/4/2014 © John Reyland, PhD

OFDM starts by converting high speed symbols indexed by n at rate 1/Ts

Into parallel blocks indexed by k at rate 1/T = 1/MTs

In this example, M=4

Symbols enter at rate Fs = 1/Ts

Symbols go into frequency domain bins. Symbols on separate frequency domain channels now exit at Fs . Each block is an OFDM “symbol” at block rate Fs/M

24

FDM with channel spacing at the symbol rate

SDR Modulation Types

12/4/2014 © John Reyland, PhD

Here is the output spectrum showing orthogonal channels spaced 1/MTs apart. Note that sampling is at the original symbol rate: Fs = 1/Ts

0 0 0 0

0 /2 /2

0 2

0 /2

(4 ) (4 ) (4 1) (4 2) (4 3)

(4 1) (4 ) (4 1) (4 2) (4 3)

(4 2) (4 ) (4 1) (4 2) (4 3)

(4 3) (4 ) (4 1) (4 2) (4

j j j j

j j j j

j j j j

j j j

s k b k e b k e b k e b k e

s k b k e b k e b k e b k e

s k b k e b k e b k e b k e

s k b k e b k e b k e b k

/23) je

Important: Four time domain symbols in results in four samples out The four samples out are four samples/symbol on 4 different orthogonal channels

25

RF Propagation Channels

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. Line of Sight Propagation 2. Diffraction, Reflection 3. Slow and Fast Fading 4. Channel coherence time and bandwidth 5. Fade Margin 6. Diversity 7. Rake Receiver 8. Multiple Input, Multiple Output (MIMO) channels 9. Doppler characterization

26

RF Propagation Channels

12/4/2014 © John Reyland, PhD

Diffraction, reflection, scattering all contribute to various kinds of fading, for example small scale multipath fading

Multipath: Multiple paths from transmitter to receiver. Small receiver or reflector movements can cause variations in received signal power

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RF Propagation Channels

12/4/2014 © John Reyland, PhD

2

2

2 2

2

2

22

average excess delayk k

kavg

k

k

k k

kavg

k

k

t avg avg

a t

ta

a t

ta

t t

t = RMS Delay Spread

1 1

50 5coh

t t

B

Coherence Bandwidth

For fixed receiver and reflectors, RMS delay spread and coherence BW, describe the channel time dispersion

See [R2], page 160

28

RF Propagation Channels

12/4/2014 © John Reyland, PhD 29

As the receiver moves, the multipath delay profile changes:

From Matlab channel visualization tool: http://www.mathworks.com/help/comm/ug/channel-visualization.html

RF Propagation Channels

12/4/2014 © John Reyland, PhD

At constant velocity v, car takes seconds to travel between points A and B. Assume transmitter is far enough away that can be considered constant

30

Doppler spectrum is another important moving receiver concept:

2 2 cosL v t

t

cos1

2d

vf

t

For a constant velocity, a constant Doppler shift results:

Channel Equalization Techniques

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. Intersymbol Interference 2. Linear LMS Equalizers 3. Dispersion Directed Equalizer 4. Fractionally Spaced Equalizer 5. Decision Feedback Equalizer 6. OFDM Frequency Domain Equalizer 7. Group Delay Compensators

31

Channel Equalization Techniques

To repair Intersymbol Interference (ISI), we can use a tapped delay line (TDL) equalizer

12/4/2014 © John Reyland, PhD 32

Channel Equalization Techniques

Orthogonally principle: Error vector of the optimal estimator is at a right angle to the estimation. The optimal solution satisfies the orthogonally principle.

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1 11 21

1

2 21 22

2

3 31 32

ˆˆ

ˆ

d h hc

d Hc d h hc

d h h

Point is the closest point in the column space of H to the true solution d. The closest

point will have to be perpendicular to d

Channel Equalization Techniques

12/4/2014 © John Reyland, PhD 34

A decision feedback nonlinear adaptive equalizer:

See [E1] and [E2]

Channel Equalization Techniques

Fsym = NOFDM Tsample = OFDM symbol rate

MF Fsym = Frequency domain spacing, Hertz

Bcoh = RF channel coherence bandwidth

NOFDM = Number of OFDM channels

Tsample = Sample rate of each input signal

12/4/2014 © John Reyland, PhD

RMS Delay Spread

1

F sym coh

coh

M F B

B

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Multiple Access Techniques

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. Overview of multiple access 2. Code division 3. Time division 4. Wireless sensor networks 5. Frequency division 6. Space division and beamforming

36

Multiple Access Techniques

12/4/2014 © John Reyland, PhD

IEEE 802.15.4 defines the TDMA physical layer for Wireless Sensor Networks (WSN):

Contention slots: Remotes randomly pick a slot, listen for activity and then transmit a reservation request. This type of random access is called Carrier Sense Multiple Access (CSMA). Collisions between remote signals are possible Contention free slots: Network coordinator has assigned a slot for exclusive use of a remote. Assignment is communicated to all remotes through the beacon.

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Multiple Access Techniques

12/4/2014 © John Reyland, PhD 38

0 = extra distance the wavefront must travel to antenna element E1 L2= extra distance the wavefront must travel to antenna element E2 L2+L3 = extra distance the wavefront must travel to antenna element E3 For a given carrier frequency f and speed of light C, extra distance corresponds to phase shift in radians, for example: Element receivers compensate this phase to create a main lobe at any angle

3 2 32 f C L L

Basic idea behind smart antenna beamforming:

Source and Channel Coding

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. Source coding basics 2. Entropy 3. Sampling 4. Companding 5. Channel coding basics 6. Pulse Code Modulation (PCM) 7. Shannon-Hartley theorem 8. Block and convolutional coding and decoding 9. Turbo coding and decoding 10. Trellis coding

39

Source and Channel Coding

The maximum a posteriori (MAP) log likelihood ratio:

12/4/2014 © John Reyland, PhD

1 1 1

0 0 0

| |log log log

| |

col col row

MAP ML AP ML EXT

p S r p r S p SL L L L L

p S r p r S p S

Turbo Decoder diagram for this example:

40

Source and Channel Coding Log likelihood ratio of modulo two addition of two soft decisions (see [C21]):

12/4/2014 © John Reyland, PhD

0 1 0 1 0 1 0 1min ,L r r L r L r sign L r sign L r L r L r

This addition rule is used to combine data and parity into extrinsic information Extrinsic means extra, or indirect, information derived from the decoding process

41

Source and Channel Coding

12/4/2014 © John Reyland, PhD

Column extrinsic information can be feedback to row decoder for a new iteration

42

Analog Signal Processing

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. RF Amplifier Review 2. RF Mixer Review 3. RF Filter Review 4. Frequency Planning 5. Non-zero IF Receiver Design 6. Complex Signal Representation 7. Zero IF Receiver Design 8. ADC Interfacing 9. ADC Dynamic Range 10. SigmaDelta and One Bit ADC s 11. Automatic Gain Control 12. Noise 13. SDR RF Switching Technology 14. Charge Domain Sampling 15. SDR Transmitters

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Analog Signal Processing

12/4/2014 © John Reyland, PhD

802.11g signal is 20 MHz wide OFDM. We sample 60 MHz IF at Fs = 80 MHz So far, the preselector has provided the only bandpass filtering Not good enough, too much aliasing! This will hurt receiver performance with a complicated signal like OFDM

44

Analog Signal Processing

12/4/2014 © John Reyland, PhD

Noise: Another critical receiver characteristic

k = Boltzman constant = 1.38e-23 Joules/Kelvin = (Watt*Sec)/Kelvin = (Watts per 1 Hz)/Kevin

0 KelvinN kT

A very sensitive power meter will measure a noise power proportional to the physical temperature of the resistor

The temperature must be measured using the Kelvin scale, where 0 Kelvin corresponds to “absolute zero”, the temperature at which all thermal motion ceases (as defined in thermodynamics). To get noise power spectral density, we use a conversion factor:

Temperature is a measure of the molecular average kinetic energy Joules is a measure of energy. Energy is integrated power (watts * seconds, for constant power). One Hz of frequency (1 cycle/second) corresponds to one second of time (1 second/cycle)

45

Analog Signal Processing

12/4/2014 © John Reyland, PhD

ADC dynamic range details for one in-band signal:

10

max

20log 8FS

ADC

VdB

V

Minimum SNR required by the modulation type:

Signal power must be backed off by peak to average power ratio (PAPR). For OFDM:

minRe 1020log ADC

q

NoiseFloorADC

VSNR

V

Note: ADC driver amplifier must also have sufficient dynamic range

46

Analog Signal Processing

12/4/2014 © John Reyland, PhD 47

ADC

Example: x(t) = +2 Vref = +4

Analog Signal Processing

12/4/2014 © John Reyland, PhD

ADC performance is critical for Software Defined Radio:

UMTS Advanced Wireless Service (AWS) Uplink specifies both GSM and WCDMA channels

A basestation SDR designed for both receives in-band WCDMA or multiple in-band GSM signals

48

Digital Signal Processing

12/4/2014 © John Reyland, PhD

Learning Objectives:

1. Receiver Preamble Processing 2. Quadrature Down Conversion and Filtering 3. Multiple Signal Downconversion 4. CIC Filters 5. Digital Modem Design Overview 6. Automatic Gain Control 7. Resampling 8. Symbol Timing for QPSK and Higher Order QAM 9. Matched Filtering for Linear Modulations 10. Carrier Estimation 11. Decision Feedback Equalization 12. FIR and IRR Parallelization for High Speed Processing

49

Digital Signal Processing

12/4/2014 © John Reyland, PhD

Another example is the IEEE 802.11 preamble

50

Bk blocks are 16 sample identical known sequences. A delay and correlate technique provides initial packet detection:

From [D39]

Digital Signal Processing

We will organize the SDR DSP discussion around the receiver architecture below:

12/4/2014 © John Reyland, PhD

Symbol time tracking, equalization and carrier tracking are jointly estimated and don’t interact much with each other. This is an important feature of this design. This setup is suitable for many linear modulations in common use today: • Nonlinear demodulation would replace equalizer with phase discriminator and

also probably not have carrier tracking • CDMA would required additional code synchronization circuits • OFDM would require an FFT to separate subcarriers

51

Digital Signal Processing

12/4/2014 © John Reyland, PhD

Let’s take another look at digital receiver color coded sampling rates: • FS = ADC sampling rate. FS is related to signal bandwidth, not baud rate. • FS/K = Complex baseband sample rate, K = 2 or 4 to reduce processing load • MFsym = Fixed number of samples/symbol. Often M = 2, 4 or 8. • Fsym = One sample/symbol. Final subsampling before decoding payload data.

Generally there is no integer relation between FS and Fsym, also FS/K > MFsym. The FIFO effects a transition between real time and non-real time processing A DSP receiver is basically a complicated downsampler!

52

Digital Signal Processing

A popular filter and decimate circuit is the cascaded integrator comb (CIC) filter

12/4/2014 © John Reyland, PhD

2 24

1 1

1 1 1 1

1

1 1 1

1 2 3

1 1( ) 1

( ) 1 1

1 1 1 1

1

1 1 1

1

z zu z z

x z z z

z z jz jz

z

z jz jz

z z z

1

4

( ) 1

( ) 1

( )1

( )

w z

x z z

u zz

w z

53

Digital Signal Processing DTTL and Gardner are good for antipodal signaling such as BPSK, QPSK. For higher order QAM, we use band edge timing [D34, D32, D12]:

12/4/2014 © John Reyland, PhD

Timing

Reference

Generator

Advantages: • Works with timing tone, not dependent on baseband symbols crossing zero • Timing tone approaches are generally independent of carrier tracking convergence • Tracks symbol period and also finds best symbol sample • Works with closed or open loop symbol timing Disadvantage: Requires a lot of DSP resources

54

Digital Signal Processing

12/4/2014 © John Reyland, PhD

Timing

Reference

Generator

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2-120

-100

-80

-60

-40

-20

0

Normalized Frequency fT

Avera

ge P

ow

er

QAM Received Power Spectrum +/-Fsym shifted, Excess BW = 0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

30

40

50

Normalized Frequency fT

Avera

ge P

ow

er

Fsym/2 Resonator Outputs, Excess BW = 0.5

A closer look at some of the frequency domain signals that generate the timing tone. . All these signals are complex. The imaginary part of the symbol rate sampled timing tone is proportional to: = symbol sampling error, T = symbol time See [D37], chapter 14, for proof

Timing tone spectrum is magenta

2sin

T

55

Digital Signal Processing

12/4/2014 © John Reyland, PhD

Finally, we can convert this equation into a parallelized second order IIR filter: 1 1 1

0 1 0 1 0 0( 1) ( ) ( ) ( 1)Y n B BY n B A X n B A X n

See [D14], [D15] for the original derivation

56