RC4 Stream Cipher algorithm for Wi-Fi Security

BY

K.P.RAKESH (08621A0487) K.HARI (08621A0489)

INTERNAL GUIDE K. SATHISH

INTRODUCTION

The aim of this project is to provide security to the streaming data.

It is very important to secure networked continuous media from potential threats such as hackers, eavesdroppers, etc.

The applications for streaming are endless. Streaming can be delivered as a complete video package of linear programming, as a subscription service, or as pay-per-view (PPV).

Steps involved in desinging a system

To design any system in VLSI, then one should undergo two steps

Front End Step In VLSI, Front End Steps include Block Diagram, Coding, Compilation and simulation.Back End Step

In VLSI, Back End Steps include Synthesis, Placing and Routing, Timing Verification

Design Flow :

Coding CompilationSimulation/Verifiaction

SynthesisFitting/

Placing and RoutingTiming

Verification

Hierarchy/Block Diagram

Front End Steps

Back End Steps

CRYPTOGRAPHY:-

Cryptography means “security”.

Various types of keys for security are:-

1. Private key

Ex: Atm

2. Public key

Ex: credit card

3. Authentication key

Ex: Aadhar card

CIPHER:

Cipher means “data”.

Ciphers are of two types:

1. Block Cipher : The different algorithms in Block cipher

are DES , AES etc.

2. Stream Cipher : The different algorithms in stream cipher

are WEP , RC4 etc.

History Of RC :-

The RC algorithms are a set of symmetric key encryption algorithms invented by Ron Rivest.

The "RC" may stand for either Rivest's cipher or, more informally, Ron's code.

• RC1 was never published

• RC2 was a 64-bit block cipher developed in 1987.

• RC3 was broken before ever being used.

• RC4 is the world's most widely used stream cipher.

RC4 uses a variable length key from 1 to 256 bytes to initialize a 256-byte array.

The project deals with the Design of RC4 stream cipher for wireless LAN Security.

The RC4 stream cipher works in two phases. The key setup phase and the pseudorandom key stream generator phase. Both phases must be performed for every new key.

The primary functions are generation of 256-bytes key data from variable key length (6 to 16 bytes), initialization of the key setup, swapping of 256-bytes between two blocks of 256 bytes (to randomize the bytes).

BLOCK DIAGRAM

State Machine Control :

State Machine controller is a device which controls the other devices used in the circuit.

The operations of various circuits depends on the SMC of the circuit.

The Output of State Machine Control is given to every block of the circuit.

ENCRYPTION

Converting the defined format data into undefined format data by using XOR operation.

EX: msg - 0 1 1 0 1 0 0 0 1 key - 1 0 1 1 0 1 1 0 1

Cipher = 1 1 0 1 1 1 1 0 0 DECRYPTION

Converting the undefined format data into defined format data by using XOR operation.

EX: cipher - 1 1 0 1 1 1 1 0 0 key - 1 0 1 1 0 1 1 0 1

msg = 0 1 1 0 1 0 0 0 1

Tools Used :

Verilog language is developed basically on two languages

90% of ‘C’ language

10% of English & Pascal

To design our project we are mainly using two tools namely,

Active HDL

XILINX

Active-HDL (ALDEC): Active-HDL is an integrated environment EDA tool designed for development of VHDL, Verilog, EDIF, state, block diagram, Simulation (wave form) models and design of Synthesizable IP-Cores.

Xilinx ISE: Integrated Software Environment (ISE) enables to quickly Design, Simulation of HDL source, Synthesis of HDL based RTL design and FPGA Implementation (Placing, routing ,mapping) and Bit Stream generation.

Applications:

Widely used in the transport layer & secure socket layer protocol.

Used in WI-FI protected access & all kinds of wireless communication.

Used in AOCE, secure SQL and TKIP (temporal key integrity protocol).

THANK YOU