READING AND WRITING FLASH MEMOR Y

USING DELTA SIGMA MODULATION

by

J~nnirerTaylor

A thesis

submitted In partial fulfillment

of the requirements for the degree of

Master of Science In Electrical Engineering

Boise State University

November 2004

•

TIle Ihesls prcstnled by Jennifer Taylor entilled Readmg and Wrning Flash

Memory using Della SIgma Modulauon is hereby approved:

~rJL R. Jacob Hater Advisor

. MigLoo Committee Member

Dale

fit: k f?~ //-/..:>-01 n R. Pelion Dale'

Dean. Graduale College

TABLE OF CONTENTS

LISTOFTABLES ........................................................................... IV

LIST OF FIGURES ............ .................................................................. V

CHAPTER ONE: INTRODUCTION TO FLASH MEMORY AND SENSING .. .

1.1 Flash Ce ll SlruclUre and Operation ........ . ............ .. .......... .. ..... . . I

1.2 Flash Memory Sense Amplifier.; ...... ...... . .. .... ..... ......... .... ....... 7

CHAPTER TWO: THE BASICS OF ANALOG TO DIGITAL CONVERSION AND

..u: MODULATION . ..... .. . . ... .. ............... ...... ... .... ... . .. .. . ... . .............. 11

2. 1 Analog to Digital Con"<' rsion ................ ....... ......... .. ................... 11

2.2 ..u: Noise Shaping Modulator.; .. ... ...... ....... ....... ..... .... ............ IS

CHAPTER THREE: dL SENSE AMPLU' lER DES IGN AND OPERA HON .. ... . 2 1

3. I Sense Amplifier Block Diagram ............................... . ...... . .. 2 1

3.2 Sense Amplifier Circuit Design ... 23

3.2. 1. Integralor .. ..... ..... .............. ........ .... . . ...... ......... ... 23

3.2.2. Analog to Digital Converter . . ................ .............. .. 25

3.2.3. Dig;talto Analog Converter (~edback Circuit ) ... .. ... 27

3.3 Sense Ampl ifier Operallon .. . ................ . .. .... . ........ .. .... .... . 28

3.3.1. Sense Amplifier Operation ............... ... . .. ...... ..... . .... 28

3.3.2. Sense Amplifier Si mulaliOfis ......................... . ........... . 29

3.3.3. Noise Simulations .................................................... 33

CHAPTER FOUR: US ING THE..u: SENSE AMPUFIER FOR PROGRAMMING 38

4.1 Conventional Flash Cell Programming ....... ............. ....... ... ............. 38

4.2 Flash Cell Programming with At Modular.ion ... ..... ...... ...... ...... . .. 42

O IAPTER FIVE: CONCLUS IONS ...... . .. .. ..... ........ ......... . . ............. ... 46

REFERENCES ... ... .... ....... ... ............. .................... . .................. .. .......... 47

APPENDLX ....... ................. ........................................................... .... 49

'"

I •

1

Table 3.1

Table 3.2

Table 3.3

Table 304

Table 4. I

LIST OF TABLES

61: sense amp operation for varying cdl currents ........................... 32

AI: Sense amp outputs for "white nOise" simulation ....................... 34

SprCE results with simulated Voo and ground bounce .. .. .. .............. 35

SPICE si muJation results for billine capacitl ve coupling . .. .. .......... .. 37

Example of possible programming conditions for NAND nash cell

With dI: methodology ........................... ......... ...... . . .... 44

Figure Ll

Figure J.2

Figure U

Figure 1.4

Figu re l.S

Figure 1.6

Figure 1.7

Figure 1.8

Figure 1.9

Figure 1.10

Figure 1.11

~igurt'! 1.1 2

Figure 2.!

Figure 2.2

Figure 2.3

Figure 2.4

Figure 2.5

Figure 2.6

Figure 2.7

Figure 2.8

Figure 2.9

Figure 3. 1

Figure 3.2

Figure 3.3

Figure 3.4

LIST OF FIGURES

Rasll Memory Celt C ross-Section and SCM:matlc ..... .... .. . .. . .. 2

Programmed and Erased Rash Memory Celts .......... ... ................... )

Rash Cell Oxide Capacitances .. .. . . . .. .. ...... .. ... .. ... ..................... 3

Flash Cellumlcr Rcad Conditions . . . . . . . . ..... ... . . .... ...... 4

R ash Cell los Curvcs ... ... .. . .... .. . ...... . ....... ....... ..... ... . ... 5

Rash Ccll Current Variallon over T ime ..... ...... . . . ....... . .... . .. . ......... 5

NOR Architecturc . ... ... .. . ...... ...... .. ........ .. . . . . . .. . ...... ... ..... .. . ... 6

NAND Architecture .. . ... . ..... . ...... ..... ....... .... . ........... . ......... 7

DifFcrentlal Amp Sensmg SCM:me .......................... _ .. . 8

Example Sense Amplifier ........... . ..... .... _ .. _ .. .... ........ .. ....... . 9

Latch Sensing Schcme ... ............ . ............... _. _ .......... . 10

Actual Cell Curren t versus Average Current obtained by

AI: Modulation . .. . .... . ... . . .... _ .. ' _. ......... ......... ... .. ...... . _ . _. _... . 10

Block Diagram of Analog to Dlgual Conversion Process

Example input signal varying between 0 and I .024V

.... . ... II

Example Output of Sample & lIold . ...... ... ......... .

12

" Example Quantization Error .... _ .. _ .. _... ... . ...... .. . .. . .. ....... . . . ___ ." 14

Model of AOC Process ........ ........... . .. ................ ..... 14

First order lowpass At modulator ......... ...... ....... .

Typical mput and omput SIgnals of a II.t modulator __ ...... _ . .. .. ... .

16

16

Quantizat ion Noise Spectral Density .......... . ............... . ......... ..... 18

Modulation Noi se: Spectral Density .......... .......... ... ... .................. . ..... 19

Block Diagram of At Sensing CircUIt ." _, ,, __ . .... ... ... .. .............. .. . ........ 22

Transistor Level Diagram of AE Sensmg Cill:uL! ............ .. . ____ 23

SPICE simulation showing comparator s witchl11g point ...... 25

Voltage atthc output of first comparator stage ..... . .... .. .......... 26

Figure 3.5 Voltage at the output of second comparnlor stage .......................... 26

Figure 3.6 VolLage at the: output of third and final comparator stage ..... ............. 27

Figure 3.7 SPICE simulations of circuit optrntion with varying nash cell cum:nts. 30

Figure 3.g Number of times feedback is enabled versus nash cell current .......... 31

Figure 3.9 Current consumption during scnsing operation ............................ J2

Figure 3.10 Rash cell currents modeled as sinUSOidal signals . ........ ....... ..... . .. 34

figure 3. 11 Simulations of VOl) and ground bounce ... ... ... .......... ....... . .. 34

Figure 3. 12 Modi ficahon to circUi t to simulate bitlinc capacitive coupling ..... 35

Figure 3. 13 +200mV noise source: charge is added to the bitlmc when fccdback

is not enabled ....... .. ...................................... . . ....... .. 36

Figure 3. 14 -200mV noise source: charge is removed from the bithne faster than

Figure 4 .1

Figure 4.2

Figure 4.3

Figure 4.4

Figure 4.5

expected with 1 J.lA nash cell current .................. .

CHE programming of a flash cell ........... . ... .. ............. .

Fowler-Nordheim programming of a nash cell ................ .

Rash IV curves demonstrating 4 states per cell ............ .

Method to program NAND flash cell .... nh IlE modulation

. ..... 37

.•.•. 39

. ., .. 41

.... 43

Block d iagram of 6:1: programming operation ....... ... ............... ..... 45

+

CHAPTER ONE

lNTROOUCfION TO fLASH MEMORY AND SENSING

The state of a nash memory cell, whether it is a logic high or low, is determined

by sensing the current through the cell./ 1-3) Today's common design practice is to

convert the current to a voltage and then use a differential ampltfier or latch to detenmlle

whether the nash memory cell has been programmed or erased_! 1-9) The dtfferent,a)

amplifier or latch scheme for data sensing has a major shoncoming; il is sensitive to

process vanatlons and noise, demanding wide threshold voltage margms between the

programmed atJd erased memory cell statcs. As a result, programming and crase times

arc long, and it is difficult to store more than one bit of dat~ per memory cell./IO]

ThIS thesis presents a new and Improved sense amplifier desIgn based on delta

sigma modulatIon. Flash cell current is converted from analog to digital using a o ne-bit

..u: modulator. The dcl[.JI sigma modulator cancels out noise and outputs an accurate

measurement of average cell current. The data conversion circuitry is SImple and less

sensitive to noise and process variations, WIth less margin required bclw"en programmed

and erased StatC5. This new design approach leads 10 boih more precise sensing and more

economical memory chips.

1.1 flash Cell SlnJcture and Operation

One cell of a nash memory array consists of a Single n-<:hannd trnnsistor with

two polysihcon galC5 stacked on lop of each other. The !KllIom gate. which is called the

1

2 floating galc, is completely surrounded by dielectrics. Tllis dietecmc insulation gives lhe

floaling gale the ability \0 store charge. The bottom d,electric is silicon dioxide, and IS

called the [unltel ox ide. Between the two poly gates is an imer/evel dieloctric consisling

of an o~ide-nitride-o)(idc sandwich. The drain junction is intentionally abrupt to

facilitate the programming operaliOfl, wtuch lypically OCCllrs through hOi camer inJcctlon.

The source jUllction is mlcnllonally graded to suppress band-tcrband tunneling wllidl

might occur dunng the Fowler·Nordhcim crase operation. 'The cross-section and

schematic of a single flash cell are illustrated in Figure 1.1.

Conlrol Gate

InlCr Uvel Q1Kk (ONO)

F!o'Uftl GILe

T""""IOxlde

o

G -11

5

Figure 1.1. Rash Memory Cell Cross-Section (left) and Schematic {right}

Electrons can be stored 011 the floatmg gale by a programming operat1On. and

they can be removed from the gate by an erase operation. Programming and erase are

accompl ished by applying voltages to the control gale. source, substrate. and drain. TItc

state of thc flash cell (programmed or erased) is defined by whether or nOllhe floating

gate contains electmns. A programmed cell contaHlS electrons on the floatmg gate. and

an erased cell does nOl contai n electrons, as IIlustlllled in Figure 1.2_r 1-3)

]

Programmed cell Erased cell

le-e-c-I

:;J c: :;J c: Figure] .2. Programmed and Erased Flash Memory Cells.

Figure 1.3 illustrates tile oXide capacitances associated Wilh the flash cell .

Assurnmg the capacitances of the tunnel oxide and the mtcrpoly dielectric are roughly

equivalent and equal 10 c... the total capacitance from the gate to tile substrate will be

C,.fl (due 10 the two c.. in parallel). The lhrc.o;hold voltage of a single flash cell can be

detennined by the foUowing equation:

(Ll)

where $"" is the contac t potential between the bulk and lhe gate poly. $w is the

electrostatic potential of the pol ype substmte, Ot.o is the charge contained III ttle channel

region. and C""f1 is the gate 10 substrate capacitance.( III

Floaung G.te

Tunnel O .. de

Figure 1.3. Flash Cell Oxide Capacltll.lICCS

When e!eclron$ are stored on [he noming gate. the threshold voltage is Increased

with the trapped charge (Q""'rl). as Indicated in equar.ion 1.2:

..2.L 'l..w Vrn.o;_=-41_-2<fJR>+2 o ( C + C ) . - ( 1.2)

TIllS d ifference In threshold vollage is LISe<! [0 de!cnnlllC' whether a nash cdt is

programmed or erased.! 11 J

A flash cell IS read by applYing approximately 5V [0 the contml gale, I V to the

drain, OV to the source and substrale. and measuring the current from dram to source.

TIle read operation is illustrated in Figure 1.4. An erased cell's threshold voltage is

designed [0 be less than the 5V applied to the conlrol gale dunng a read. Therefore.

under read conditions, an e~d cell will tum on and will draw current from drain to

SOUI'CC. In eontra.o;t, the ele<:trons ao;lded to [he flOatHlS gale of a programmed cell cause

its threshold voltage to be greater than the 5V read voltage. When a programmed cell is

read, the .;:elliS turned off. and no current flows from drain 10 sourI:C. Figure 1.5 5hows

I ypical los CUr "CS of an erased bu and a programmed bit.] I ·J.I ] I

G, d I

N+ Soun:c

5V I

COfltrol Gate

f1o.11mg Gate

IV I

lds C N+ Drain

p. Sub5lral.:

Figure 1.4. Flash Cell under Read Condilion5.

4

Flash Cell Current

"""

-5V Read Voltage Ha~h Gale Voltage

Figure 1.5. Flash Cell los Curves.

Figure [.6 contains an eumple of lhe nash cdl curren! over time. The cell

curren! varies due to Injected noise, including capacitive coupling from adjacent circult~

and VOl) Or ground Ouciuarions. As a resuh of [he Inherent variation In nash cell CUITCnt.

the margin between programmed nnd erased Siaies must be surficientJy large In order 10

pre'em a sensmg error. llIe [r,arg'" between lhe erased cell's and the programmed celrs

threShold "ollages is typically 2V or higher. r 12J

CeJl Current

1 Wide Margtn

j

time

Figure 1.6. Flash Cdl Cum:n! Variation over Time

5

Flash cells are arranged in a NOR memory array by columns and rows. The

comrol gales arc: CQnnecled through wordlines, and the draIns are connected through

bitlines. All of tile r.ources are connected together. 11Je sense amplifiers exist althe

bollom of each billinc. When a flash cell IS !t:ad, appropriate voltages are applied to its

word linc and billinc, while the other wordJines am! bitlirteS remain al ground. 11le flash

cell bemg read will supply current on liS billme if it IS erased, and will supply no current

if it is programmed, The sense ampl ifier then dcte<:\s the current on the billine and

compares il 10 a ~nown level to decide .... hether the cell is programmed or erased.! J-3[

A NAND memory array lias a similar architecture, with the exception Ihal each

flash cell IS not connected d'coctly 10 a hIllin<:, so the flash cell currem must be passed

through other flash cells to gel to the billirIC. As a result. III a NAND array, a very h.igh

pass voltage IS applied to all word lines except the cell under test's wordline. The cell

under test's wordhne receives a read voltage that will tum on an erilliCd cell but WIll nOi

tum on a programmed ceiL If the cell is erased, current will now through. all cells and be

detected by the sense amp. If !he cell IS programmed, no curren! will now.[ I ! J The:

NOR and NAND arch.ite(;tures are illustrated In Figures] .7 and] .8.

(I"h ...

r

r

(I"Ii"" ;+1

Word" ...

FigufC ].7. NOR Architecture.

6

7

Bltline

Stlp{\ I

Wordlln~ II

Wordhn~ II

Wordlln~ II

I s.,n.~ Amphfl~t J

Figure 1.8. NAND Arch,ICl;IUrc.

1.2 Flash t\-'Iemory Sense AmplUiers

Common &ense amplifiers (01' NOR nastl memory ctlips are s'ngle-ellded senslIlg

schemes that compare Ihe potenlial difference betwccn a vOllage genera\ed by the nash

cell currell! and a n:fen:llce vollage Ihrough the use of a dl fferenllal amphficr /I _5.6_9 J

The basic d ifferential amplifier design is iJ!uslraied in Figure 1.9. Once lhe SENSE signal

is enabled, lhe di ffcrcll!ial amplifier compares the flash billine vollage 10 a reference

voltage. If lhe flash buhne vOllage is lugher than the re ference voltage. Ihe DATA OUT

signal will be pulled 10 a logic high. If the flash bullllc voltage is lowerlhan lhe

reference vollage. DATA OUT will be pulled 10 a logic low.

8<thnt I I Brftrcoct

Figure 1.9. Differentia! Amp Sensing Scheme

One example of a sense amplifier based on J differenllal amplifier .sensing

scheme is Illustrated in Figure I. ]0. This sense amplifier uses parasItiC cap:W::l!ancc to

;megralf ,he difference between the flash cell current and a reference current. The

reference current i~ generated (mlH anOlher flash cell that has ils threshold voltage

programmed to a voltage level in between lhe fully programmed and fully erased Slales.

The paraSitic capacitance"s voltage IS Ihen compared to a reference voltage by a

differential amplific[.[9]

This type of sense amp is open-loop and makes its decision at a Sct point In lime.

As previously discussed, the flash cell current varies over [!fne due to Injected noise.

The reference cell's current w,ll also vary over lime. The accuracy orlhis sense

amplifier will be affeeted by mally factors illcluding ~he amOlJIl~ of noise affecting ~he

cell llIId refercnce currents. and the s!;;l1sitivity, gal n, offset, and noise I mmunity of the

•

.

9 differenuaJ amplifier. S'nce Ihis sense amp is based on analog currents and voltages, the

circuit elements must be very precise. Further, the amounl of margi ll between the

expected fl85h ceil currents and reference current must be suffictently large to prevent

senstng errors.

Dummy Column Decoder

---II '"

v ;

v

T Cr~='''":-::--_ Cell

Column Decoder

---II C,II

Figure 1.10. Example Sense Amplifier /9J

The commonly used sense amp tn NAND architectures consists of a basic lalch.

as ilIuslraled in Figure l.tl. During Ihe SCt-Up for Ihe sense. lite SENSE RESET signat is

asserted and pulls lite left side of the latch to a logic low. Once the SE,'IISE signal is

asserted. if the NAND cell umkr lest is erased, current will flow and discharge lite flash

cell's bllJtne, causing tile Stale oflhe latch 10 flip.[6J This type of sensing scheme is also

open loop, making '\s decision at an isolated potnl in lime. The sense amp must be

10 desigoed wilh v~ry good noise lnununHy [0 prev"m injected "oise from causing the latch

10 incorrectly flip sllItes and result In a sens ing error.

""'1 [

B i lljn~

Figure LJ L Latch Sensing Scheme.

The remalllder of this thesis discusses Ihe use of .... ~ modulalJon to measure a

flash cell current Tile ft.l: modutatiOl1 cancels ol,lllhc nOIse causing cell current

fluctuatIons and provides a measurement of Ihe average cell current. as depIcted in

Figure 1. 12. Use of toE modulat1On In the sense amp alleviates the need for high

precIsion cI rcuitry thaI is necessary to provide noise immUnity and accurate analog

comparisons In conventional sense amplifiers.

'-Act .... Coil Currrn, 00'0" bm<

L/'v.1-~7-r--A---br'"~ ·\~V-" A ..... 0." .. , obwr>ed by dI: Modultllon

rigurc 1.12. Actual eel! Current versus Average Current obtamed by 6.1: Modulal1on

"

CHAPTER TWO

TIlE BASICS OF ANALOG TO DIGITAL CONVERSION AND.1.l: MODULATION

The ~I]si ng operation in a nash memory array is essentially an analog to digital

conversion. The nash cell current is analog; it is continuous in time and may vary

slightly over the sensing period. A scnse amplifier must tocli convert (IuS analog signal

into a digital '0' or '/' (ao erused Stale or a programmed slate). This c hapler reviews the

basics of analog to diglla] conversion IUld 111: modu lation.

2.1 Analog 10 I>igitaJ ConHrsion

T he block diagram In Figure 2. 1 Illustrates lhe analog to digital oollvcrsion

process. and FIgures 2.2~2.4 comain plOIS of the signals along each point In Ih,s block

diagram. The ADC process cons ists of a sample and hold block to sample lhe signal and

prevent it from f1ucm3lmg whde Ihe conversIon is laking place, and then the. actual

analog [0 digi1al oonvener.[13.1 4 ]

InpUI Signal Sample " HoJd Ana"" 10 I);rill' OUIPUI Si naJ

c-.~"...-

Figure 2.1. Block DIagram of Analog 10 DigItal COnversion Process

Tile plot III Figure 2.2 shows the analog Inpu1 signal (flash crll current) 1hat will

be cOIlvened 10 a dlgi1al signal. For ease of simula1ions. the flash cell currell! can be

12 conve"~d to a voltage pnar \0 the analog \0 digital conversion. The Input signal soould

not vary ~igni ficantly; however for the purposes of this discussion we wi ll assume the

analog signal varies between 0 and I.024V in a sinusoidal function. The value of I,024V

is purposely cOOsen (0 correspond to a IO·bit digital representation.

. - .... " - -'.

, . --,-

"

••. IO--:U~;--'~;--'f=~-'+';cc~~ r. JOO. ""'. HO . . ...... .

". o

Figure 2.2. Example input signal varying between 0 and L024 V.

The plot in t-igure 2,] shows the signal after passing through the sample and hold

block. The sample and hold allows the signal 10 change only at periodic intervals

OOtTeSponding \0 a clock signal. Changes in the input when tile clock signal is OfF are

ignored (because the signal is held) •

• "

"

"

... 1 --.I,~~'S--'f..-o.l.f.:. :..- '" • ,.. • 'u • '.. • • .. . ". •

Figure 2 .3. Example Output of Sample & Ilo[d.

" Til<: AOC block then converts the stalic input SIgnal 11110 a digItal representation,

or an Integer value betwccn 0 and 1023 for each sampled sig"al as indicated by tile nat

portions in Figure 2.), This digital conversion results in an error called tho: quanlil.lJtlon

error. As a specific example, analog signals of 0.5001 V and O.5O().tV will both be

represented by the digital signal of 500. The difference, or resolution, belYreen 0.5001 V

and O.5004V ,slost in this conversion.

Any digital represemation can have a maximum error of +/- \I'i LSB (Least

Significant Bil). which is half the distance between adjacent quantIzation levels. For a

IO-bit digital signal with 1.024 V range. tile quamiution levels reside .001 V apart. and

toc maxImum error can be .OOO5V. Thus, tbe digital signa! consists of lhe origUiul

analog signal plus (he quantization error. The plolln Figure 2.4 shows the quantization

errof fOf Ihi~ eumple. Quantization error normally will be while. or rarldom. noise. [n

thiS case. the quantizallon error has a distinct panem due 10 the input signal being a

sinusoidal waveform. The quantization error can be reduced by IIlcrcasing tile number of

bJls In Ihe digital !>ample. For example. a 12-bll digital signal with the same I.024V

range will result In a maximum error of JX)()125V versus an error of .OOO5V with a 10-

bit dig!!al signal.

.!

l4

.'

Figure 2.4. Example Quantization Error.

The analog to digital conversion process can be modeled as the summation of the

input signal and tile quantIzation noise. This is illustrated in Figure 2.5

Quantizalilln Error

Input Signal OUlput Sigtlal + )--"===~

Analog Digi tal

Figure 2.5. Model of ADC Process.

Analog \0 Digital Converlers are typically characterized oy their Signal 10 Noise

Ratio (SNR). SNR is a measure of how well the COl1verler passes tile input signal willie

surpressmg the quantization noise. Contimllng our example WIth an input sinusoidal

signal. tile SNR is expressed as:

SNR,.;...\ = 20'log VVJIi

,'-v:;;:rJi2 (2.1)

\

For OUr example. the SNR of our Sillusoidal signal with a 10·bll digital representation

can be calculated as :

SNR = 20. 10g n.SI2Y f 2 '" 62dB -- 0.001 V I 12 (2.2)

Another commonly referred to characlcri5lic of a data convener is the number of

effective bits. defined as:

SNR ..... _ 1.76

6.02 (2.3)

This equallon would be: applied when the SNR is measured, instead of calculated as HI

the above diSCussIon

2.2 £u; Noise Shaping Modul"tors

Quami1,allon error IS not lhe only error imroduced imo lilt: signal during tile

analog to dlgnal process. In a real circuLI. 11K: analog [0 digital conversion accurncy will

be affected by lhe gan). offsel, and linearity of the CQnvencr. AckhuonaJiy. 'lOlse from

adjacent circuit blocks may cause some amount of periodic corruption \0 the input signal.

To overcome the possibility of an mcorrecl digital output, eilher Ihe analog to digila!

converter mUSI be designed wilh a high degree of precisiOll. or allcmalive!y a noisc.

shapillg dma cOllverter. such as [he Il.r CO!lvener. may be used.

The simpiesl & modulator is Ihe first-order !owpass modulator, shown III Figure

2.6_ The inpul is an analog. CQntinuous signal. <1I1d the output is a discrete·t ime, blllary

signal. Example Inpul <1I1d output signals are shown in Figure 1.7.

"

" ADC

nCq:nolOr , Dpul (I) • · OutpUt (z)

-¢ "., + · • I·z' · · · · · . '--~.---.-- .. ...

DAC

Figure 2.6. fi rst order I()w~ 4r modulator

• . .. •

I .1 • • I

• • --?J • • ·

• • • • • • • • • • .. - ••

• -'-' • • T • • •

• • • • • -• _ ..... J.. ----.-- ... - · ... " • • • • • • • • • .. - -

Flpre2..7 . T}-ptcaI mput and <lUll'll! $.IgnUs of • .u: modulalor

.

17

From Figure 2.6, we can discuss the operation of the .1.:1: modulator. The circun

calculates !he dl (ference between tile i"PUi signal and the delayed OOIPUI signal, and

integrates this difference. TI1e output o f the lnlcgralion is the n fed 10 a summer where it

is added togethu with quantization noise from the ADC. The OUtput of the summer is

the output signal. The result is Iha1 the O11tPUI tracks the average value of the inpul.

From the diagram in Figure 2.6, lhe following equalJons can be wrinen:

j ln(d - Out(,)] • .....c...... + Ek) ~ Oul(t) I-t I

T his shows th.allhe output signal consists of:

• the input signal delayed by one clock cycle

• the quantization noise (error) di fferenti:ued,

(2.4)

(2.5)

- - - - _Cn."'.,differentialian aUhe-'luantiz.aliMl'lOiK acts 10 push the quantization nOIse to hIgher

frequencies. This is why.u: modulation is also often referred to as noise-shap"'g. The

effect is a reduction oC quantiution nOlSC in one frequency band at the expense of the

remaining frequencies .

As discussed in section 2.1, the quanttuuon nOtSC for a ttnK:-varying input signal

,s random, and thereCore ,ts voltage s[JCctrum is flat. The noise voltage spectral denSIty

can be calculated as

(2.6)

18

where V UH is [hoe voltage difference tIe/wecn adjacem qURmiz31ion levels. and r, is rile

sampling frnquency. A graphical reprcscntalion of [he quantlzallon noise spectral

density is shown in Figure 2.8.

r, r 2

Figure 28- Quantization NOIse Spectral Density

The differentiation of the quanliZalion noise is ca lled the modulation ooise. and

can be calculated as:

Modulation NOlsc '" (I - 7, ') • V Qt

" ( I _ c -j10(III.I) • (2.7)

The power spec tral density of the modulation noise can be wrilten as:

:2 0 (1-coS2:1 f l , 12', (2.8)

A graphical representation of the modulation IIOlse spectral density is sllow" In figure

2.9, Comparing Figures 2.8 and 2_9, we can see Ihaltlle noise is pushed to higher

frequcncles, similarly tu toe ;lI!: I'rocc::s~eU Ihrougll" highrass filler

•

Modulation Noise

2V~B

.fI21,

r, 2

r

Figure 2.9. Modulution Noise Spectral Densny

Al frequencies approaching DC, the modulation noise is reduced!O zero. This is

ideal for Ihe case of a flash SC[lSC amplifier. because the Inpul signal 10 be digih7-ed is

expected 10 be a DC signal.

11le noise value of V l.SH I m iii applicable only for [he specific case of a lUoe.

varymg inpul signal wilh random quantization noise in continuous opel1l1ion. Chap!.er 3

d,SCUS5C5 the use of a.o.I: m<Xiulalor wilh a single bit OUlput to Sense a flash cell current

In the simple dE modulator dcslgn proposed in chapler J. tile quantization noise, or

mInimum re5Olulion. will be Vsw:;1 K. where K is the number of clock cycles, which IS

also (he number of data samples coUC(;ted.

1lJc SNR of lhe single bil OUtput dE modulator used in a sensing operation can

then be written as

SNR "'"20 . log -,S';"fr","I~ Signal' K (2.9)

19

20

Suppose the /lot modulator mak.,.. a d~c;sion afl~r 500 clock cycles, or aller 500 data

poilUS have been collected. The SNR will then be

SNR * 20 . log Signal '" 20 · log (500):: 54dB Signal f K

(2.IO)

In order to gel a relative comparison of performance between the Single bit oUlput61:

modulator willi conventional ADCs. we can calculate Number of Effe<:live Bits 10 see

thal wilh only one bit. the simple l!.1: modulator is able to achieve a similar SNR value as

a morc compleJO AOC with a digital ompul of over 8 bits!

Ndl " SNR n"", - 1.76 = 8.7 bits

6.02 (2.11)

An additional advantage of the single bit output 1'01: modulator IS lhal the analog

to digital conversion is inherently linear. Smce there are only twO possible output codes

with a onc-bit converter (' I" and '0 '), the two analog vohages representing these output

codes w,ll always iiI a stnughl lim:. In a multI-bit converter, lillCarily can be a concern

and an additional source of error. [13.14]

CHAPTER THREE

61: SENSE AMPLIFIER DESIGN AND OPERAT ION

(n thIS chapler. the design of a sense amplifier for nash memory uSing AI:

modulatioll is discussed. A very simple topology is pn:scnled [0 illustrate how the ... 1:

noise shaping can compensate for an nnprecise compar.llor. In cOl1tra.o;ltO the lICCuralC

sensing Cin:Ults needed without noise shaping. The cin:ui[ open'ltion is explained, ilI1d

several slmuialloll5 are perfonned 10 demonstrate the sense amp's capabi lity in the

presence of vmoos noise sources.

3, 1 Sense Amplifier 81{>C k Diagram

21

A block diagram of tile sense amplifier circUli is shown helow in Figure 3. 1 As

discussed;n chapter two, a ... 1: noise modulauolliopology consists of an integrator. an

analog \0 digital converter. and a digllalto analog converter. For this sensing cirCUli. the

IOtegnuor is implemented as a capacitor. the ADC is implemented as a simple clocked

~ompaT1ltor, and the DAC is Implemented as a current source and swit~h controlled by

the output of the ADC.

1 (I)

[ E(5) I

l Analog 10 Dtgilal Connrttr

Inltgnlor

•...... -..... --_ ..... -...... ..... . : : , ' , '

+ )-----f~·:·~ .. : .. :·r_·: .. ~·t'-----+i--_;=:j

, •

.•••••••••• 1

, , v,. eLK

, .... -.-...... -................ -~

,---.. -.----.-------.. ~ , ' , , • • ,

, • , • •

From Fi~ 3.1. the following cquallom can bcdcm-ed:

,--I m+E(5): 1 '" ~

~+E(I).a...(I+:C)

l. • ...1.L. + E(5} • 2£... .. sC+1 sC+1

(31 )

(3.2)

(3.3)

Thus as upteled. the output orlhe.:1I §CtISC amp. J.... is cquivaienl lo tbc desired cell

current subJccted \0 a lowpass filter. oombmed with the quantization l1()isc subjected 10 a

hlghpMI filter,

~\ -------------------------.

23

3.2 Sen5e Amplifier Circuil Design

A simple lransistor-le~eI implementation for !he blod ;: di agram of Figure 3.1

IS shown below in Figure 3.2.

Source

Feedback

Clock

~

To Counter

-II ,.11

Figure 3.2. Transistor Le~el Diagram of 6L Sensing Circuit

3.2.1. Integrator

The integrator consists simply of the blthne capacitance of the !lash memory

array. While the bltline capacitance of a memory array will vary depending on cell

de.~ign. process technology. and number of cells per column, the billine capacitance is

assumed to be SpF for this design. This capacitance is initially charged up to a reference

~oltage ofO.SV. which is chosen to be close to the switclling point of tile clocked

compar~or. Thc bitline capacitance does not need to be pre-charged. as the L\L sensing

eircuit itself can charge up the bit line capacitance to tile comparator switching poinl;

however. this would add some delay to the sensing operation.

Al the beginning of the sense, thc flash cell CUl'n'nl will begll! 10 d,5(:harge the:

buhnc ~,tance unulthc .'01bgc at Ihal node ruches the s .... nching POInt oCtile

~oc Qnor:; the romparalor switches. the feedbad" circuli (d\5CU.ued in I1'l(Ke

detall In sechOfl 3.2.3) will supply SUrrK:MenI current (0 cause the billillC capatlW'lCe 10

c/wsC bal:k up to a voltage Ic,"el abo,'c lhecompanuor swnchuig pOl1'II. EJopeded

discharge IJIJ1C$ (M .. few nub cell current valu£s are!ihown below, by salVin&:

.1.&._ ~v, 7

c... - T

WIth c.... '" SpF. and t. V .... ,. O"V (complete discharge) .

... Discharge Time

I,A 2_5~

30flA 8]lIs

.. '" 42ns

(H)

24

In ordr:r 10 avoid completely discharging the buline capacitance (and losmg the benefit of

Ive"'g'"! over ume),lhe Ctl'CUII canoot be allowed to discharge for more than 42..s In

one dod: cycle, foc I. maximum nash cell CUm"f\1 of 6(4lA For thl$ design •• IOO~1Hz

doek is chosen. giving Ova" JOns of margin. While the disclwgc raI£ of tile capKilOf

setS the nummum clock frequency, tbcre IS no IirrulllllOll for- mnilTlLlm clock frequency_

II is wonh nounS U\3l the YOllage on thc bitlLIJc. and coru.equently the voltage

applied 10 1"'= dIain of the flash cell, will vary over time as the capac'lU)Ce charf:!:s Lip

and dischilfgel> around the comparator $WnchHlg poinL ThIS Will cause the nash cell

curnm 10 nuc;1Uale Slightly. Thll> IS nOl a problem since the avtrage value of the bllime

.

" ~lliII>Cc will be a conSl ...... :and we tue seeking to Iktermme the ~pondlRg

avenge value of the nash cell current.

l ,U Analog to DitiW Con~mcr

T'he docked eomparalOf COI\SlSlS or~ ,nVaterS and IWo~"'.u:hes. llus SIITlpk

prcclSl: for the AI: ooue shapmslO .. orL. The eompznlorcaIJ oeeu>onaJly make ""ron,

The NMOS and PMOS switches arc: sixcd as 1001llld 2Ql1 resp«lIvely. The

InnJistOB In the mvencrs are. Sl~ as 10110 NMOS and 1fJIIO PMOS These Inn!islon

an: made slightly long In on:Ier to keep power oonsumpllon lower. TIle comparator'S

de<:iSIOTi pOint will correspond to the switching point of the first inverter In thl.~ design.

the SWitching point IS approXimately O.SV, as shown in the SPICE simulalloo In Figure

3.3 below

•• .. , ,Output,

•• • ",_ J. •• 'DD t: ...,. 1 • • i. ,···

"" Figure 3.3. SPICE simulation showing compal1llor SWltchmg pDlnL

-

" The 1"'0 s .... ,tches controlled by CLOCK act logether 10 WI'VC as an edge-

sufflcicnl gam 10 te.'>IOR thE output Signal 10 full ... oIlag1:; Ic~·els. Figures 3.4-36 show the

vQ{tage al'tcr u ch mverter stage oftbe oompanIOf As un be seen. the output 113$

ruched faIrly c lean logic Ie,'cts by the final mve1ter .

.. 1110 •.

0.0 o ,

0.0

.... -

•• 0

OO'\,--~~c;.-~~~~~ i -, •• , _. _" .... WI

..... oS

Figure 3.4 VoI.tage !llihe output of firsl c::amparalOl" sllIge

0 -0,.-, , 0 --- -'" ,

• • -...

0 0 , ... - .. .. 0 0

! ! • 0 "--- --

0 0 ,. 0 •• 0 -0 o. 0 •• 0 .. - ~

Figure 3.5. Voltage at the output of second comparator Slage.

•

• ---_ .. ......... -_ ., .... .. __ .... ... -- ..... .

I a .••

___ i ------- ......•. -• • lOa , lDD •

, --- -- ' .. _.

laD 0 ~

.00 D

figure 3.6. Vol tllge allhe output of third and final comparator stage.

3.2.3. Digital \0 Analog Converter (Feedback Circuit)

The fudbad: circuit consists of a nash cell for Ihe CUrTent source, and a lrallsiswr

controlled by lhe output of the clocked comparator. Wocn tlie sensing IS initialed, the

current source is disconnected and the nash cell being sensed causes lhe blliine

r;:apacilance 10 discharge. Once the bi tline capacitance voltage 1'l:1lChe.s tile switching

poim of the doded comparator. the feedback SWI[ch is enabled and Ihe feedback current

is cOllnecled \0 the bitlitle capaci tance. causing illO charge back up to a voltage level

higher than the CQmparalQr switchmg point . Thus the feedback current must be selected

at a level at lust as high as the highest flash cell cum:nt e)(pected. For thiS design. a

feedback: cum:nt of 6O~A is 5C1~ted. IIIld the expected flash cell current values will

range from O~A 10 -50~A. The precise value of this cum:nl IS nOtlmponanl. nor is il

important to be consistent across a wafer.

-

For ~~in! 5impli<:I\)'. a nuh celt IS used In tlus de5ign ((I{" II", fccd'-:k

currenl. Tlus flash «:11 would need to be el'&&Cd 10 lhe desll~ Ie\cl dunng wafer probe:

\estlllg. Another choice for feedback cumnl would be. 5Wttc:hal eapKltor A S .... llebal

ea~lIor would result III lower po'o"er. but m{U11'CS 1""0 OOIHI\WappIIIgdock Signals

<",hlCh are 00l OlherNise ~uua!). and may aI50 ~ui~ ,rKTCHCd '.youl.U:L

3.3 Sense Amplirler OPf'ration

),3.1. Sense: Amphfter Ope@hOO

In this desIgn, the sense amplifier ,$ elocl.cd al IOOMHl.. Thus. every IOns, thcu:

tS a constant amount of ch.lrge removed from the b,tline capacitance due to the current

frorn lhe nash cell being sensed. n,is charge can be calculated by:

Q .. , == k.ou T (3.S)

For example. Qt.. for a cell drawHl' lO..,A of current IS 300fC when T .. 1011 &.

The rate at whIch charp 1$ added 10 the bttlinc ca~ltantC by the: f~dback

current IS no! con!iUll1t dunllg each .. lad: cyc:l ... "nee the f«<ibKk current Is ~mes

enabled ilI1d somettmes disabled. If the bllhne tapKlI;mCe voltage IS leu than !he

swtlclung point of !be comp¥alor, lhc:n!he r ....... bacl CII'I:\l1I WIll be enmlcd and.

feedbact cum:0I .... ill be added to !he brtlme capac,tanee for one dod. c)'tlc. If th:

btlline eapaetWlce vollllge tJ; grealef than the SWItching paim of!he cornpantor. then tiE

rccdbiLct cirru.tt Villi be disabled, and the nash cell current will conlHlUC to dtscharge!he

billine capacitance. A deciSIon is nude agal1W the companttor SWItching point cnry

cloct cycle (every IOns). If N IS the l(Hai number of clod;: c~1c$ used In the. sense. and

.

M IS the ntlmber of L"I>C.'.he feedback cu ...... nt il cnabl""-. lIEn the charCC added ",> (he

QI , I (3.6)

If the Circuli IS openring properly. the ,venge feedback current will equallhc flam cdl

CUrTaIL. 50 .. 'e can wnte;

M N

. T '" Q.,. .. Ie... • T (3.7)

(38)

(3.9)

Usmg the above equations. we ~a" M'C that the minimum ~, vBIU<lLhat can be

<;ensed. and the minimum reSOlution. corresponds to M=I (one high output code dunng

t~ entire ~sing time). For this design. lhe 5t:nSlng time .. as seLected as 5 ..... ~. and the

rcedback currenl is 6OvA- Thus the mmimum ~Iuhon is:

I 500' 6O!u\ = In.A (3.10)

3J,2 Sense Amplifier Simo1MIOBS

Sunulauons for It.: design In Fipre 3.2 we«. pcrlormed wllb SPICE Womg SOnm

BSIM4 models and a VUl>wpply vollaseof I.OV. n.c appendix COOIaIRS the nctlm

useifi()generate the slmulatlOiIS contamed In IbIS chapter.

•

The first set of simulatIOns show the bitline capacitance vol1age (vi) alld the

OUlplll of the comparator (VOlll) for several different flash cell current values. As seen in

Figure 3.7 below. when tile bitline capacitance voltage drops below approximately O.SV,

the comparator output is enabled, and the bitline capacitance charges back up to a value

above the comparator SWitching poim. 1bc higher the flash cell currem, the faslcr the

bitlin" capacitance discharges. and the more often the feedback current must be enabled

to maintain the constant -O.~V bitline capacllaflCC voltage. For the case of OIlA nash

ce ll current, the bitline capacitance does not discharge within the sensing time. and

therefore the feedback circuit is never enabled.

ken - Qy.A

.. - .. .- • ... • •• • V,~ , •• • ,. •

V • • -• • • ,. •

bll =3QuA

. - .,

. , .. , ..

-_. • ;-

-• -• ,,- •

--

,.. . _. ".

T" "

~-.!

1·

• • • • •

... .

•

kn _ ISuA

• - 0>

,

• ,

• ,

.. "

. , ..

- -' ,

! , ." •

j.-

"'-

, .. ."

,....,'~ r

"'w tb-H W7'!Hb' !

. , ..... " .• , ••• ,,- '"~ . • • Figure 3.7. SPICE simulations of circuit operation wllh varymg flash cell currents.

-

Additional simulations were perfonm:d wilh varying flash cell currents OuI to

5COJns w obtain the graph in Figure 3.8. The relationship between the number of times

the comparator is enabled and the flash cell current is linear.

,. ,~

• ~ 150 , ' ,,, , i" , •

• .. " ./

V

Sense Amp OperatIon

./ ./

./ /'

" .... k C .. , c~.,....,t ( .... )

./

./

Figure 3.8. Number of times feedback is enabled versus flash cdl current

Table 3.1 contains the simulated cell currents, resulting number of compar.llor

pulses, and calculated cell currents based on the formula:

(J.ll)

The error can be deereased by increasing the sensing time.

Table 3.1 ~ SCMe amp oper.ation ror varymg cell currents.

CdlC""'-' " ' S ' ted' I"IoMos c:.k*alftl CeI CoorrtDl (." 1 r ........ I.A)

0 , 0 0

, " " " , " ., "

" u, n ,

" '" " 0

" '" '" " " '" ." " " "" '" " " no ..

lbe current coosumed by thLS sen5C amphfier WIl$ sLmulated at around 10j.1A

plot is consumed by the comparator ~nd d oes nOl. rnclttdc thecon~tant flash ce ll curren1

or.he reedbac:l ~n1

•• ..

Figure 3.9. Current consumption during sensmg opcl1ltion.

3.),) Noise Simulations

3,3,),1 While Noi.~

33

To demonstrate the cffecllveneu of the dI noise shaping In thiS sense amphfier.

SPICE sunulatLOns were pcrfOfllled w"h the addihon of noi~y signals, The firs! case

mve5l1g3u:d IS the In.tectioo of wh,te thennal and ",ckeT noue. from surroundIng CIrl:UU~,

For the purposes of modeling In SPICE. Ihls ooise was Simulated by setting the flasb cell

current 10 a Sinusoidal ,ignal umead of a DC value. Because tho: average of a sinusoidal

SIgnal equals zero. II is easy 10 predict that the..u: scnse amplifier will func;lion very well

under while noise conditions. since the sense amphfier fUllctions by averaging the nash

cell currenl over the entire sensing lime.

Slmulallon, ... ere performed wllb SinUSOIdal flash. cdl cUIT(':nlS rangmg from OuA

10 tWLce the In,ended DC value at 100M!!?, as LlluS\rnled in FIgure), to, TIllS amount of

nolSC is obViously much more severe than wou1d occur In a nash memory ell'CUII. bul

demonstrates the sense amplifier's capabllny to filler out nmdom noise. Table 3.2

Ineludes the simulauoo results for two differem currents; in both cases. the error

produced by the sinUSOidal nOise is Icss thall 1j.tA A simllnr IlOISC source applied 10 a

current being sensed with a differential amplifier or latch would cause 3 sensing error.

unless lhere was so much margin btull In between the prog~mmcd and erased StateS that

the d,ff amp Of latch would not be iocom:ttly flipped.

--,--, .. .0

, .. .. " . -.. .I V--,!'o-'--+..,'L-!!,-~,---! i, .... .. . .., N. ' ... "0LL!~:7L-i~fo-'-;! i. lO' .. . .. . H. , ... ,,- .. ". •

Figure 3.10. Flash cell currents modeled as sinusoidal signals (12p.A and 30p.A peak·peak)

Table 3.2. dI: Sense amp OUlputs for "while noise" simulation_

34

<All Cunni ... , Sirnul.,'" , ........

'" C ..... I.' ... CUrfUI

7 .•• .0. Cur .. n. wi ........ ...,....

6 SuA ISuA .J·15uA '" IHuA

3,3.3,2 Vooagd Ground Bounce

AnoliJercornmon noise signal affecting sense amplifier operat ion IS Vpp and

ground bounce. This nOIse condllion was simulated by adding a 20mV 10 50mV

lOOMliz sinusoidal signal 10 the Vooand ground sign3ls. as shown," Figure 3. II

o -- o --.. -., ..

" o

"

"'~;O--;;'--',,";-'--;; i. ,,,. '"' .... ,oo .... , ,,- N

Figure 3.11. Simulations of Vooand ground bounce.

31 The sense amplifier performed ve ry well with 50mV Voo and ground OOoncc, (l>

the n:sulll; in table 3.3 demonstrate, The 50rnV lIoise added between l00-300nA nOIse 10

the signal , which is certainly acceptable even if the desired resolution is on the order of a

3-4 ).lA.

Table 3.3. SPICE results with simulmed Voo and groond bounce:.

3,3,)) H,llinc Capacitive Coupling

A third comlllQn wurce of noise IS capacitive coupling of the hi!lmc This was

simulated by brieny connecting the bitline 10 a "noisc" source during the sense. The

modified c:;ircu il used for the simulations is shown," Figure 3.12.

Noise source, 300mV to 700mV

Enabled afte r 1000ns j for 50ns I

-il C,II

Figure 3.12. Modification to circuit to simulate bill ine capacitive coupl ing.

The Simulations in Figures 3.13 and 3.14 show the results of addmg a posItive

and neg3uve nOise source to the bitl ine. For the fil'§t ease. the po,itive noise source

causes the bitlillC to be recharged even though the feedback was not enabled. For the

second case. the negative noise source causes tile bitlinc to briefly discharge fa.~ter than

expected for the flash cell CUITCnl. If the sense amplifier was designed with a differential

amplifier or a latch. a significant nOise jump in the signal could eause the sense amp to

output an inoom:c\ result. Ilowever wllh the llol: sensing methodology. the error will

average out over time. Improved aceurney can be obtained with longer sensing lime!>.

rigures 3. 11 and 3.12 il lustrale IIIe CircUits behavior with the simulated capacitive

couphng. and Table 3.4 conlallls tile results for 50mV and 200mV nOise sources wilh a

5).15 se llse. The 50mV noise SO\Irce results in pTllCtlca!ly no difference to Ihe calculated

currcm,

I S .......••... - .-.' -,_ .. _._ .. _._ .. _ .. _,. _. , , , , , , , , ,

1 0 . . ....•..•.... , ---, _.- ............. _.

-" .. .... ~ ...... . -- ........ ................. .. ............. .

t ....

Figure 3.\3. +200mV noise source: charge is add"d to the bitline when feedback is not enabled.

"

• -vi

, ... -.- .. , ..... .,.... ........ "'-

1 0 ..•

"f+-H+~

.. , ...... '1, ...... . o • -/'0 S

._-. . ........... -........ --..• 10 15 2.

6

f

Figure).14. ·200mV OOI;.e $OU~: charge 1$ removed from Ihe bit line faster Ihan eltpeclCd wllh luA nash cell currenl

Table 3.4 . SPICE Simulation rewh5 for bithne capacitive coupllllg.

NoW " ~ o . """.

,,",Oun.

'" '" '" ,~

'"'

Siraubfal • !\aha ~c......

" , ... " , ... .. 1.7,""

" ,,~

" 22uA

37

38

CHAPTER FOUR

USlNG T HE 11I: SENSE AMPLIFIER FOR PROGRAMMING

In chapler three, the design of a sense ampllfiu using AI: noise shaping was

discussed. The t.r sense amplifier with a l00MHz clocl and 5~ sensing lime was

shown to reasonably sense nash cell cUlTcms with an accuracy of less than 2-3~A. even

under white nOlsc. Voolground bounce and bitline capactive coupling condit ions. While

this dcgrt'Xl of accuracy is illlerest;lIg. il is 1101 bcneficiallO use willi modem nash

memory arrays due to the wide threshold voltage separallon between programmed and

erased bils thaI IS commonly implemented. ThiS chapter di.o;cusses implementallon of

.1!: senSing in nash memory programming. in order \0 lake adva11lage of the h.igh degree

of resolution obtainable.

4.1 Con\'{~nlional Flash. Cell Programming

Rash cells may be programmed through either Fowler-Nordheim wllrlChng or

channel hoi Carner (CHE) injection. CHE programming is Iyplcatty used fOl" NOR nash

architeclure, and 15 achieved by applying a high vollage to both Ihe control gale

(wordhne) and the dfllin (bilhne). The source and the substrale are grounded. The Iligh

vollage on Ille comrol gate and drain causes a higll cllannel current to now between dram

and source, and also causes a channd field Ihat generates Ilot electrons. The vollage on

the comrol gate IS coupled onto the noatlOg gate, allraeting oot electrons 10 tile !1oating

" gale. High l'OII'gc pul.K:S oolhe onkr of I. re .... l1S att. applied to the cell. and in bdv...en

c.ach pulse lhe celllJ rad against I. Sd current le~c:1. l1Jc diagram In Fi~ 4 I

ilILWlaId thIS pro&nmming mdbod..l2.J.ISI

N+ Source

N-""""

IOV I

~=::C~=W::'::"'='='=:I I ROlling Gale I

-;;; 'r e- N-+-Dnlm

P·SubRBte

Figure 4. I. CitE provamnllng of I. nash cell

archilCCture). I hIgh voltage 1$ applied to the COI'llrol gatc: (wordlmc) .... Iu<:h coopk.s a

high voltage onlO the floating gau,_ The b,lllI1c, SOU~. lUld 5ubSlralc are lied 10 ground.

Similarly to CHE programmillg. the high voltagc: is applied 10 Ihe: cell In pulses; lIo\o.eH~r

the durauOll is lyPlcally several hundred ).IS, whIch IS aI Iea!l one: order of magnitude

larger lhan fOC" CHE progmrumng [11.16[ FowIn-Non1helm prognmming IS iJluslraied

in Figure 41.

----------------------------.....

Fllat

N+ Source: ) N· 50\1rce

20V I

COfltrol Gate

Rooting Gal(:

e-\.

p- Substrate

G1nd

N+ Ora'n

Figure 4.2. Fowler-Nordheim programming of a flash cell.

In both cases. high voltages an: applied 10 the cell for a SCI period of lime (one

pulse), and then the cell IS compared agam<! a verify level. If the programmed cell's

current IS greater Ihan the reference current. the cell has nOi been programmed

sufficiently and another pulse will be applied. If the programmed cell's currem is Jess

than the reference current, the program operation is ceased and successful. Generally.

the same sense amplifier circuLlry used for a cell read is used during lhe Verification step.

except Wilh a different reference current.

Due 10 the inherent Imprecision of traditIonal sense amp circui try . the flash cells

lICe programmed and erased such tl131Ihen: is a wide mru-gill between the programmed

and erased current levels. Fore~ampJc. a typical NOR nash memory cell is programmed

to a threshold voltage greater than 6V, and er2Sed to a threshold voltage less than 4V,[ 12[

This may re5uh in a programmed/erased current differential of 30llA or higllcr. This

margin is necessary so thaI the read sense amp makes eorr...::1 deciSions . FUrlllcr. since

.

this much margill is used, the accu racy orthe programmed a"d erased currenlS IS lint

precisely controlled. As long as the programmed level i~ at least as low as the

appropriate reference curren!. it is considered goud enough.

III order to reduce costs, several nash manufacturers arc using a mulli-Ievel cell

technology. which stores more than one bit's worth of data In one ceU.[6,7.10.12) For

eumple, a two-bn per cell techllology will contain four vollage levels correspondllIg to

00, 01, 10, and II codes, Instead of just two voltage levels corrcspondrng to a 0 or I code,

In order to accomplish this. vohage ranges are establIShed for each digital code. as shown

in Figure 4.3.

Flash Cell Cum:n!

" " " 00

Flash Gale Vollage

Figure 4.3. Flash IV curves demonstrating 4 states per cell

In order to use II multi-level cell technology, the nash cell currenl~ must be

controlled mure precisely. 1lle distances between reference currents for a two-bit per

cell technology may approach IO)lA, versus tile 30)lA or more differential thal. can exiSl

with a one-bit per et:11 technology. Typically tIM: cell's charge is more accurately

controlled during programmmg by limiting the gate voltage to lower level. while

" prosr.uJUTling t .... hi~rum:nl stales. and by using smaller pulse .... ldths and lIS a ~II

SeYCnll'$SUI:S arne wnh thIS prognmrrung IIIClbodoIosY rOf mulll·Ic.~1 ocU

Wd!nologtes. Tht smaller pulse ... 1!Itb. and ITIOI'e frequent "Wroes leads 10 a longer

progmrurung ume: •• ,htch "'""Y Of flUIy DOt be: ICCq)I.abIe 10 CUSlOInI:B.. The 1lWXI"

between each prognmmrd tulTml le"eI musI still be IIIlgI! mough to fICCOmmodMc the

rtSOIultOn possIble with the !.ClUe :unp. ",hlCh hoots the numberorbllJ!hat can be

Implemented percdl Further. SInce lhe cells are programmed until they reach a sec

current le\'cl, and the actual cell Clltrcnl is not accurately mO'UIOfW. the re.su lt may be

thlll the: cell's eLi"","! is on the edge between IWO logic slales. and there IS ~H1u .. lly no

margIn For charge gaIn or los~ dunng field lise.

4.2 ~'h,sh Cell J>ro,,:namming with iI.I Modulation

dunng the flll!ih programming opt:faliOIlS In order 10 ehtrunalc many of the problcnu

discussed In the !l"" ',ous ~IOII This mnhodolor;y would be IIk$ sueeessful In !he

use 0( NAND f1~ where the prograttlffilng umes an: s'imrlCanliy )onget than the

sensing umes - typu:ally x.'en! hulldred .,.s orprogr.vnmmg tune, versu.s leu than 5)'S

ror. Knse ",uhm I 1 ·'2~ R'SOJuuon.[ 161 An .mpicIDrnlallOll of'llI15 Idea I5lhow"n In

Fizure 4.4 The conlroller ... 111 consist of wme type or counter or filler to convcn the 6!

moduworOUtputlO a cell cumnl value. and IoJie that swtlclle$ lbe output between

+ZOV and OV depcndm!; on whether 01" nOl the; pre.netennlllW cell cum:nl le,'('1 has blXn

reached.

43 Assuming rhe nash cell IS erased pnor to commencement of the programnllng

operation. the cell will be drawing a hIgh current ( for eJ(llmple, 6OJ.lA). Al ,he beginning

of the programming operation, llu: controller output will be high (+20V) \0 enable

programmmg. As the +20V is applied to the nash cell's wordline, the cell's tltrcsllold

voltage will Increase and the current will drop. The current is continu()U5Jy monitored by

tile AI: modulator. Once the cutrell! reaches the pre·delermillCd level (forexarnple.

30IlA). the com roller's output will go low (OY) and the programming operation 1"111

cease.

• 20V or OV I':J'iJ I Cont roller II Flash (eli

~;i~'~'~M~od~"~I'~'O~'~~~ Digital output Current input

J Figure 4.4 . Method 10 program NAND nash cell with AI: modulation

As shown In chapler 3, the AI: sense amplifier with a 5~ sensing lime can • measure a current's val ue to within a few)-LA. For the currem referclICe of 601lA, StUCCn

suites ean be defined with41lA distance between each state. This would allow a four bit

per cell technology - twice as dense as the two bit per cell arrays which are commonly

used in the industry. Further, only one current reference is required for programming all

.. Sixteen Slates; ""Jlh uadmon .... muill-levcl cell programming lechn,q~ lift~n currenl

rcf"uiCU would be mjUlred.

current. the amy cells could be pmuammed 10 a ll'lO"''' vallie Instead of JUS! 1I-1thm a

w1Odow. The cell currenl value could be .... ell comrollcd by adJustmg culler the ~oltages

af1(Vor pulse duT1l.UOflS during each programming operation based on how fill aloog the

cell has bee!) programmed. For cllnrnple, III the "as.;: of Fowler Nordheim tunneling.

there could be three different Coodl1lOns for programmms: large, medIUm. and small, as

~nbed In Table 4 I

Tllble <S •. E.lample of possibk programrrunS coodillO<lS

for NAND Rash cell ""m dI methodoklu

The smull progr3mrnmg pulses would be defined such thai virtually no over-

progl1lmnUIIg occurs, Shifling from IMge 10 slnall programming pulses would not be

possible wltI! sl.atld:utl passlfail ven(ICaIiOl1 l&alllst a rcfneocc current. JUICe thechip's

staU: mactune would have no WlI)' of know'"I'" .... hat pomt the small prognrnnung

pulses should be,m. In onIa 10 tula JrnaII..-tndow """h 5taJKbrd prognmmmg. all of

d!. scnslng and enabhng the poMibilny to .shift from largr to sm;tll pul~. ~

4S programming operat ion w,U be: mucli more lime efficient. This methodology is show n In

Figure 4.5.

SIlO,., "",chin. appl;'" 1_'1<, ...... ium, .......... U pul_ de~""ing .......... mu<h furtMc nil nteCb ... be prog .. mmtd

Figure 4 .5. Block diagram of AI: programmmg operation.

The same method can be used 10 pragnu" a NOR nash cdl. However, the NOR

cell programming with hOI: canier injection is accomplished much more quick.ly-

typicalLy on the order o f severn] )is. For best resolutIOn ""Iii a NOR archile<;lUre. the

C(lntrollcr should limit its OUtput high pulses 10 one 8 to IOV pulse evel)' 5",s, to aVOid

over-progranuning.

CHAPTER FIVE

CONCLUSIONS

Sense amplifier.; for nash memory arrays arc commonly based on differential

amplifier.; or latches. These circuits have several shortcomings including susceptIbility

to nOIse. causing incorrect senses of the memory cell state. To Improve noise Immumty.

a new sense amplifier has been designed using 61: noIse modulation.

The new scnse amplifier conSIsts simply of three inverter.;. three switches. and a

reference curren! source. The simple topology IIlcrea.'ieS manufacturabilllY case. yet due

to liS nOIse sliaping ability. It can detect a current WIth approx imately lIlA resolution.

The new sense amp can wilhstand V,>dground bounce of over 50mV and signal noise of

over 200mV. The CIrcUli can also be used during progT1llllmlllg to achieve hIgher

densities 31 low cost by storing four b,ts of data per memory cell.

REFERENCES

[I I Betty Pnncc, Semico.uJuCIQf Mtmorits, John Wiley & SOllS Lid, 2001, ISBN 0-471 -92465-2.

12] William D. Brown and Joe E. Brewer, Nom'Qlalllc SemiconduC/(Jf Memory Technology, IEEE Prcss, 1998. ISBN 0-7803-1173-6.

131 Intcl Flash Memory Articles. IV/ull is Flash Memory?, October 2002. <http://www,jntel.eomldc.,igniOcomp/lirticle<l298312.!!df>

14 J A.A.M. Amill. "Deslgn and analysis or a high-spud sense amplifier for single­transistor Ilonvolmi Ie memory cells:' lEE Proceedings. April 1993. PI'. 117-122.

[5] S. Atsuml et al.. "A Channel-Erasing LS-V-Only 32-Mb NOR Flash EEPROM with a Bnllne Di rect Sensing Scheme."' IEEE Journal of Solid-Smle CirculIS, Nov. 2000. pp. 1648-1654.

(6] T. Choet al.. "A Dual-Mode NAND Flash Memory: I-Gb MuhiJevel and Hlgh­Performance 512-Mb Single-Level Modc!; ," IEEE 10urnal of Solid-State Circuits, Nov. 2001, Pl" 1700-1706.

(71 M. Ohkawa et ai. , "A 98 rnm2 Ole SIZC 3.3-V 64-Mb Flash Memory with FN­NOR Type Four-Levd Celi:' IEEE Journal of Solid-Slate Circuits, Nov. 1996, pp.1584-1589

[8] G. Torelli. A. ManSlrelta. R. Gastaldl , and P. Rolandi . "Mixed serial-parallel sensing scheme for a 64-Mbi! 4-blueell factory-programmed OTP.ROM." Microelectronics Joumal30. 1999. pp. 875-886.

/9] J. Bell. J. Bruce, B Blalock, P. Stubberud. "CMOS current mode nash analog 10 digital convener", Proc. IEEE Midwest Symposium on Circuils and Systems 2001, vol. J •• Augusl 2001. Pl'. 272·275.

/IOJ A. Modelh. A. Manslreua, and G. Torelli. "Basic Feasibility Constr.unt5 for Multilevel CHE-Programmed Flash Memories," lEEE TransactIOns on Electronic Devices, Vol. 48. No.9. Scpt 2001. pp. 2032-2042.

(" I R. Jacob Baker. HalTY W. L,. and David E Boyce. CMOS: Circuillk.<isn. l..tIyow. and Simulation, Wiley-IEEE. 1998. [SUN 0-1803·3416-1.

[121 Intel Technology Journal, Inul SlralaFlash Memory T~cfulOlog)' Overview, Q4 '97. .:::hup:/fwww.inlel.comldesignlflasMsf/overview.pdf>

[13] R. Jacob Baker. CMOS Mix.ed·Signal Circuil D~sign. Wiley-IEEE, 2002. ISBN 0-47 1·22754-4.

[141 Sleven W. Smith. The St'ien/ist and Engineer's Guide 10 Digital Signal Processing. California Technical Publishing. 1997. ISBN 0-9660176-3-3.

r IS] lmel S!ra!aFlash Memory Dalashee!s. July 2004, <hl!p:llwww.inlel.cQmlde.signlflcQmp/llaJashIYZ9Q667 .hlm>

[16] Samsung NAND Flash Memory Dalashe<:ts. May 2004. <hnp:llwww.samslIng.comIPnxillctslScmiconductorlAashIN ANDI2GbitJK9F2G 08UOMlds_~flg{}8uOm_revQ6.pdf>

APPENDIX

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