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Physics Procedia 37 ( 2012 ) 1413 – 1420
1875-3892 © 2012 Published by Elsevier B.V. Selection and/or peer review under responsibility of the organizing committee for TIPP 11. doi: 10.1016/j.phpro.2012.03.742
TIPP 2011 - Technology and Instrumentation in Particle Physics 2011
Readout Electronics for Hyper Suprime-Cam
Hironao Miyatakea, Hiroaki Aiharaa, Hiroki Fujimoria, Sogo Mineoa, SatoshiMiyazakib, Hidehiko Nakayab, Tomohisa Uchidac
aDepartment of Physics, University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo, 113-0033, JapanbNational Astronomical Observatory of Japan, 2-21-1, Osawa, Mitaka, Tokyo 181-8588, JapancHigh Energy Accelerator Research Organization, 1-1 Oho, Tsukuba, Ibaraki 305-0801, Japan
Abstract
Hyper Suprime-Cam (HSC) is a 1 Giga pixel CCD camera for a wide-field galaxy survey at the Subaru 8-m Telescope.
It will be mounted on the prime focus of the Subaru Telescope and is scheduled to receive its first light in 2012. The
primary science is to conduct a weak lensing survey over ∼ 2,000 square degrees. The HSC has a 1.5-degree-diameter
field of view, 7 times larger than that of its predecessor Suprime-Cam. It consists of a large corrector lens system and
a focal plane equipped with 116 pieces of 2k x 4k fully depleted CCDs. Combined with the superb image quality and
large aperture of the Subaru telescope, the survey using HSC can cover a cosmological volume and reach the limiting
magnitude of at least one magnitude fainter than the other surveys conducted using 4-m class telescopes. The readout
electronics of the HSC consist of two parts: one is the analog front-end electronics (FEE) and the other is the digital
back-end electronics (BEE). The FEE is placed in a vacuum dewar together with the CCDs, and processes the analog
CCD signal into 16-bit digital data. The BEE is small and light enough to be integrated into the camera unit, and employs
three links of Gigabit Ethernet to readout a 2.3-GByte single exposure within 10 seconds at fast readout operation. The
readout noise from the electronics is smaller than that from CCDs.
c© 2011 Elsevier BV. Selection and/or peer-review under responsibility of the organizing committee for TIPP 2011.
Keywords: dark energy, CCD camera, readout electronics
1. Introduction
Hyper Suprime-Cam (HSC) is the next generation wide-filed camera to be mounted on the prime focus of
Subaru Telescope [1][2]. The HSC has a 1.5-degree-diameter field of view, which is 7 times larger than that
of its predecessor Suprime-Cam [3]. To cover the large field of view, 116 pieces of 2k x 4k fully depleted
CCDs are employed. The total number of pixels amounts to 1 Giga pixels. Among the 8∼10-m class
telescopes built in this decade, the big advantage of the Subaru Telescope is prime focus and superb image.
The combination of the HSC and Subaru Telescope realizes deep, wide and high quality observations.
The primary science driver of the HSC is the weak lensing survey over ∼ 2000 square degrees to put a
constraint on the nature of dark energy. To achieve this survey with practical observation time, a wide field
of view is necessary. The superb image of the HSC will help to reduce systematic errors of weak lensing
measurement. We plan the deep survey in a limiting magnitude ∼ 26 in i’-band, which enable us to explore
the nature of dark energy of early universe around redshift z ∼ 1. These are the unique points from other
Available online at www.sciencedirect.com
© 2012 Published by Elsevier B.V. Selection and/or peer review under responsibility of the organizing committee for TIPP 11. Open access under CC BY-NC-ND license.
Open access under CC BY-NC-ND license.
1414 Hironao Miyatake et al. / Physics Procedia 37 ( 2012 ) 1413 – 1420
Wide field corrector
Dewar
Focal plane
Front-end electronics
Back-end electronicsis installed in this space
Filter exchanger
Fig. 1. Cross section of the HSC. Fig. 2. Focal plane of the HSC.
weak lensing surveys which will be carried out in this decade, such as the Dark Energy Survey (DES) [4]
and Panoramic Survey Telescope & Rapid Response System (Pan-STARRS) [5].
The electronics of the HSC is divided into two parts: one is the analog front-end electronics (FEE), and
the other is the digital back end electronics (BEE). The requirement of the readout electronics is as follows.
First, a single exposure whose amount of data is as large as ∼2.3 GBytes should be read out within 10 second
at fast readout operation. Second, the noise caused by the electronics should be lower than the noise from a
CCD (∼4e−).
We describe the overview of the HSC and its readout electronics in section 2. The brief description of
the FEE is written in section 3, and the detail design of the BEE is written in section 4. Then in section 5
the noise measurement of the electronics is described.
2. Overview of Hyper-Suprime Cam and Readout Electronics
The cross section of the HSC is shown in Fig. 1. The height of HSC is about 3 m. The light focused
by 8-m primary mirror goes through wide field corrector [6], which consists of 7 lenses and placed in lens
barrel shown as a red part in Fig. 1, and a filter placed in between the last lens and focal plane. Filters are
stored in the filter exchanger when they are not used. We plan to use 5 broad band filters and several narrow
band filters. The broadband filters consist of g’, r’, i’, z’ from Sloan Digital Sky Survey system and one
more red band Y at ∼ 1μm. CCDs are placed on the focal plane that is inside of dewar and actively cooled
down to about -100 degrees Celsius to suppress dark current.
Fig.2 shows the focal plane of the HSC. We employ 116 CCDs. Among these CCDs, 112 CCDs are
used for scientific purpose1, while 4 CCDs are used for telescope guiding. The CCDs are manufactured by
Hamamatsu Photonics K.K. [7] whose dimension is 2k pixels x 4k pixels. Each CCD has 4 outputs. The
CCD is fully depleted so that it has high sensitivity around longer wavelength; quantum efficiency of the
CCD is about twice as that of CCDs formerly used in Suprime-Cam manufactured by MIT/LL [7]. Thus the
HSC can observe high redshift objects at high efficiency.
The 112 science CCDs are read out in 2 channels, while the 4 guide CCDs are read out in 1 channel.
Fig. 3 shows the readout system of a single channel for science CCDs. Following the readout trigger signal
1Actually 8 CCDs out of the 112 CCDs are used for auto focus. However, we include these auto-focus CCDs into the science CCDs
since they are read out together by the same channel.
Hironao Miyatake et al. / Physics Procedia 37 ( 2012 ) 1413 – 1420 1415
FEE BEE DAQSystem
56 CCDs*
16-bit serial data56 LVDS pairs*
1 OpticalGigabit Ethernet*
Analog image data
* numbers shown here is for a single channel for science CCDs
Fig. 3. Schematics of readout electronics.
from the DAQ system, the BEE generates readout signal. The FEE drives the readout signal and controls
the CCDs. Then the analog signal is sent from the CCD and processed and digitized into 16 bit by the FEE,
which is then sent to the BEE through LVDS signal pairs as 16-bit serial data. The BEE sends the data
to DAQ system through the Gigabit optical Ethernet. We note that the number of the LVDS signal which
corresponds to that of CCDs connected to the FEE, i.e. 56 pairs for a single channel for science CCDs and 4
pairs for a channel for guide CCDs, is reduced to just a single Ethernet connection per channel by the BEE.
The FEE is placed in the dewar together with the CCDs [6], while the BEE is placed outside of the dewar
as shown in Fig. 1.
3. Front-end Electronics
The FEE has analog circuits to process CCDs signals which consist of clock drivers, digital to analog
converters (DAC), pre-amps, correlated double sampling (CDS) circuits, and analog to digital converters
(ADC). The clock drivers are used to drive CCD control signals generated by the BEE. An image signal
from an output of CCD first comes into the pre-amp and is amplified by ∼3 folds. After a proper offset
generated by the DAC is added, the image signal is processed in the CDS to eliminate kTC noise. The
image signal is digitized into 16 bits by the ADC. 4 outputs from a single CCD are multiplexed here, and
then sent to the BEE through a single LVDS pair.
Fig. 4 shows the picture of FEE boards attached to a dewar frame. Since the FEE is installed into the
dewar, it is necessary to exhaust its heat outside of dewar. The FEE board has an aluminum core PCB, which
enables heat to go out through the PCB, dewar frame, and dewar wall as shown in Fig. 4.
For details on the FEE, please refer to [8] and [9].
4. Back-end Electronics
The BEE issues readout clocks following commands from the DAQ system, grabs image data from the
FEE, and send them to DAQ system through a single Gigabit Ethernet connection. The Gigabit Ethernet
is employed to satisfy the requirement of readout speed. Other requirements for the BEE are as follows.
First, the noise caused by the BEE should not be major source of readout noise. The detail of the noise
measurement is described in section 5. Second, the BEE should be small since it is integrated into the
camera unit, and its power consumption should be low to prevent heat emitted by the BEE from affecting
the light path.
Fig. 5 shows a picture of the BEE which is used for a single channel of readout. The single box of
BEE is designed as 3U Euro-card system with 7 slots (153 mm x 180 mm x 130 mm). In total, three boxes
are integrated into the camera unit. The power consumption of the BEE is ∼10 W. The BEE consists of 5
components: backend power (BPW), Gigabit Ethernet SiTCP CMC board for astronomy (GESiCA) [10],
backend GESiCA interface (BGI), backend clock transmission (BCT), and backend data acquisition (BDA).
1416 Hironao Miyatake et al. / Physics Procedia 37 ( 2012 ) 1413 – 1420
CCD connector
FEE
Dewar frame
Heat to dewar wall
Fig. 4. FEE boards attached to dewar frames.
BPW
GESiCA/BGI
BDA
BCT
Fig. 5. Picture of BEE. Details of each components (BPW, GESiCA, BGI, BCT, and BDA) are explained in the text.
Hironao Miyatake et al. / Physics Procedia 37 ( 2012 ) 1413 – 1420 1417
NetworkProcessor(SiTCP)
ClockSequencer
DRAMController
LineDriver
Serial-parallelConverter
Frame Grabber(DDR2-SDRAM)
Single Optical Gigabit Ethernetconnection to DAQ sysmtem *
CCD/ FEEcontrol signal
Data from CCD56 LVDS pairs *
* numbers shown here is for a single channel for sincece CCDs
16-bitparallel
BCTBCT
BDA
GESiCA/BGI
Fig. 6. Schematics of BEE.
The BPW manages power for the FEE and CCDs. An external power is supplied to the BPW, and then after
checking the voltages and currents the BPW distributes the power. The BGI is used for the interface between
GESiCA, BCT, and BDA to convert signal levels. The details for other modules are described below.
Fig. 6 shows a schematics of the BEE relevant to readout process. GESiCA, BGI, BCT, and BDA
are related to readout. GESiCA employs 1000BASE-SX [11] for the Gigabit Ethernet link. SiTCP [12] is
used for a network processor, which is implemented on an FPGA on GESiCA. In General, the Ethernet is
controlled by software with a standard OS. In this case a powerful CPU and hardware is required to control
it at rates close to gigabit, and thus the power consumption would be of the order of several tens of watts
and the size and weight would be large. On the other hand, SiTCP adopts essential controls of the Ethernet
and can be implemented on a single FPGA, which helps to reduce power consumption, size, and weight.
We would like to note that SiTCP has been used in various experiments, such as a DAQ system for Super-
Kamiokande [13] and a readout electronics for gas electron multiplier detectors [14], thanks to its low power
consumption and its handy protocol.
Once the command for readout is sent from the DAQ system via the Ethernet, SiTCP interprets it and
sends a trigger signal to clock sequencer. Following the command from the DAQ system, the clock se-
quencer issues readout clock. The readout clock goes out of GESiCA/BGI and is driven by line drivers
inside of the BCT, and then sent to the CCDs and FEE.
To satisfy the requirement for the readout time, the BEE reads out CCDs in parallel. The BEE for a
single channel receives image data from the FEE through 56 LVDS pairs. Each LVDS pair is used for
sending 16-bit serial data from each CCD. The BDA multiplexes the serial data from each CCD into 16-bit
parallel data. The parallel data is then sent into GESiCA/BGI and stored in frame grabber. We employed a
2-GB Double-Data-Rate2 Synchronous Dynamic Random Access Memory (DDR2-SDRAM) as the frame
grabber that is large enough to store whole image data. The data is then read from the frame grabber and sent
to SiTCP. Finally the data is sent to the DAQ system through the Gigabit Ethernet. Thanks to the parallel
CCD readout and the Gigabit Ethernet, the BEE achieved 9.4 s for reading out whole image data.
For further details on the BEE, please refer to [15].
1418 Hironao Miyatake et al. / Physics Procedia 37 ( 2012 ) 1413 – 1420
Pre-Amp
DAC
CDS ADC
FEE
GND
Readout clock from BEE
Output to BEE
Integration period: 2usDC to mimic CCD signal level
Fig. 7. Setup of noise measurement.
5. Noise Measurement
In general, noise of CCD image data consists of Poisson noise and readout noise. The former noise is
inevitable since this noise originates from statistical uncertainty of photons coming into CCD pixels. The
latter noise can be caused by the CCDs, FEE and BEE. In bright region Poisson noise becomes dominant,
and therefore the readout noise is hidden; The readout noise does matter in dark region. In this section, we
investigate how the FEE and BEE contribute to the readout noise in the dark region.
The readout noise from CCDs are expected to be ∼4 e− at normal readout operation (20 s for reading
out all CCDs) [7]. Thus the noise from the FEE and BEE is required to be lower than ∼4 e−. Although the
BEE is entirely digital part, the BEE can cause noise through jitter of the readout clock to control the CDS
in FEE. The noise from the FEE and BEE , Nelectronics, is expected to have a following dependency on output
voltage of the FEE:
Nelectronics =
√N2
intrinsic+(V̄2
out,reset + V̄2out,signal
) (ΔTT
)2, (1)
where Nintrinsic is noise that is constant over the range of the voltage, V̄out,reset and V̄out,signal are the mean of
reset part and signal part of the output voltage of FEE, respectively, T is an integration period in the CDS
which is determined by the readout clock from the BEE, and ΔT is the jitter of the integration period.
We measured the readout noise as shown in Fig. 7. To mimic CCD signal, we tied input of the FEE
pre-amp FEE to GND, and a DC level generated by the DAC was injected to the CDS. The voltage level
of the DAC can be changed from outside. The integration period of the CDS is fixed to that for normal
operation mode; 2 μs.
The result of the noise measurement is shown in Fig. 8. The horizontal axis is the mean output voltage
obtained by averaging the output of the FEE ADC (in ADU units), whereas the vertical axis is noise, i.e.,
standard deviation of the output. The lower horizontal axis and left vertical axis are in units of ADU, and
the upper horizontal axis and right vertical axis are in equivalent noise charge. We used a conversion factor
of 3 e−/ADU which is a design value of the system [9]. We obtained the constant component of readout
noise and the jitter of the CDS control signal by fitting equation 1 to the data:
Nintrinsic = 2.644 ± 0.005 e− (2)
ΔTT
= 22.80 ± 0.04 ppm. (3)
Hironao Miyatake et al. / Physics Procedia 37 ( 2012 ) 1413 – 1420 1419
Fig. 8. Result of noise measurement.
Note that V̄out,reset and V̄out,signal used here are the same since we use constant DC signal as the input signal to
the CDS. The constant component mainly comes from quantization noise of the ADC in FEE. From these
values, noise from the jitter in the dark region is estimated as
Njitter(@V = 1000ADU) = 0.10 e−. (4)
Here we assumed an offset corresponding to 1000 ADU is added so that there are only a few electrons from
a CCD. Thus we conclude that the readout noise from the electronics is much smaller than that from CCD.
Among the noise from electronics, the noise from the FEE is dominant, and that from the BEE is much
smaller, which means that the BEE is not the major source of the readout noise.
6. Summary
The HSC is the next generation wide-field camera which will be mounted at the prime focus of Subaru
Telescope. To attain 1.5-degree-diameter field of view, 116 pieces of 2k x 4k CCDs are employed. The HSC
will enable us to carry out the unique galaxy survey since it realizes wide and deep imaging with superb
seeing condition. The HSC will see its first light in 2012, and is expected to begin the survey from 2013 to
explore the nature of dark energy.
We have developed readout electronics for the HSC, which consists of the FEE, the analog part of the
electronics to process CCD signals, and the BEE, the digital part to control the FEE and CCDs and send
data from the FEE to the DAQ system. In this paper, we described details on the BEE. The size of the
BEE is 153 mm x 180 mm x 130 mm, which consists of 7 slots of Euro-card system. It realizes low power
consumption (∼10 W), while achieving fast readout (9.4 s for reading out all CCDs), thanks to the parallel
CCD readout and SiTCP. The noise of the readout electronics is smaller than that from the CCDs, arising
mainly from the FEE, whereas the noise contribution by the BEE is ∼20 times smaller than the FEE.
1420 Hironao Miyatake et al. / Physics Procedia 37 ( 2012 ) 1413 – 1420
Acknowledgement
This work is supported by Grant-in-Aid for Scientific Research of Japan Society for the Promotion of
Science (JSPS).
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