ready for future computing? - all-electronics

Ready For Future Computing?

Levent Akyil

Software and Services Group

Copyright© 2012, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners.

This decade we will create and extend computing technology

to connect and enrich the lives of every person on earth

Intel’s Vision

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Solutions and Tools - Tools and Problems

“The solution of important problems may be delayed because the requisite tools are not perceived. Or the availability of certain tools may lead to an awareness of problems, important or not, that can be solved with their help.” Tjalling Charles Koopmans, Three Essays on the State of Economic Science, Vol III, p 170 (1957) Picture source: http://en.wikipedia.org/wiki/File:Tjalling_Koopmans.jpg

http://en.wikipedia.org/wiki/File:Tjalling_Koopmans.jpg

http://en.wikipedia.org/wiki/File:Tjalling_Koopmans.jpg


More Devices

>15 Billion

Connected Devices

1. IDC “Server Workloads Forecast” 2009. 2.IDC “The Internet Reaches Late Adolescence” Dec 2009, extrapolation by Intel for 2015 2.ECG “Worldwide Device Estimates Year 2020 - Intel One Smart Network Work” forecast 3. Source: http://www.cisco.com/assets/cdc_content_elements/networking_solutions/service_provider/visual_networking_ip_traffic_chart.html extrapolated to 2015

More Users

>1 Billion new

users in Internet

More Data

>1 Zettabyte of

Internet Traffic 3

Computing in 2015?

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Internet expansion and increasing volume of

Connected Devices define new requirements

http://www.cisco.com/assets/cdc_content_elements/networking_solutions/service_provider/visual_networking_ip_traffic_chart.html

http://www.cisco.com/assets/cdc_content_elements/networking_solutions/service_provider/visual_networking_ip_traffic_chart.html


Computing in 2020? (Source: IDC Directions 2010, March 2010, ICT Outlook forecast)

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Need for Connected and Intelligent Software

Can we provide seamless user experience?

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Need for Computing Power

Source: http://atlas.ch/photos/events-simulated-black-hole.html

A new view of a black hole event. ATLAS collision events. In some theories, microscopic black holes may be produced in particle collisions that occur when very-high-energy cosmic rays hit particles in our atmosphere. Photo #: black-hole-event-wide

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http://atlas.ch/photos/events-simulated-black-hole.html









Highly Parallel Applications

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Can compute tame the beast of massive, unstructured, dynamic datasets to enable real-time simulation and analytics?

http://physbam.stanford.edu/~fedkiw/animations/bag_pull.avi


Intel® Software Development Products

Intel platforms

Key hardware

features and

capabilities

Software Developers

Tools for

developers + =

Performance

Productivity

Quality

Future Ready

We transform computing experience by providing software and tools

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Key Pillars of Software Development Intel® Parallel Studio XE

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Performance

Optimizing for

performance and scalable

solutions

Productivity

Error detection

and performance

tuning

Quality, Security

Static and Dynamic analysis

tools

Scalable Parallelism

Parallel programming

models

for today

and future architectures


Highly Parallel Computing: Optimized Hardware + Software Development

Intel® MIC Architecture Co-processor ideal for

highly parallel computing applications

Develop with Intel Tools for Intel® Xeon® today, Scale your software investment to Future Intel® Many Integrated Core Products

Intel® Xeon® processors are designed for

intelligent performance and smart energy

efficiency

Common tools and

programming models

Architecturally aware Tools

supporting standards

based C/C++ and FORTRAN

programming

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More cores. Wider vectors. Co-Processors. Tools need to access all three dimensions to deliver performance

Images do not reflect actual die sizes

Intel® Xeon®

processor

64-bit

Intel® Xeon®

processor

5100 series

Intel® Xeon®

processor

5500 series

Intel® Xeon®

processor

5600 series

Intel® Xeon®

processor code-named

Sandy Bridge

Intel® Xeon®


Ivy Bridge

Intel® Xeon®


Haswell

Intel® MIC co-processor

code-named

Knights Ferry

Intel® MIC co-processor

code-named

Knights Corner

Core(s) 1 2 4 6 8 32 >50

Threads 2 2 8 12 16 128 >200

SIMD Width 128 128 128 128 256 256 256 512 512

SSE2 SSSE3 SSE4.2 SSE4.2 AVX AVX AVX2 FMA3

Software challenge: Develop scalable software

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Intel® Architecture Programming

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Intel® Xeon®

processor family

Intel® Xeon ®

processor

Intel® MIC architecture

co-processor

Single Source

Compilers and Runtimes

Common Areas with Intel® Xeon®

processors

C, C++, Fortran compilers

Intel developer tools and libraries

Coding and optimization techniques

Ecosystem support

Eliminates Need for Dual Programming Architecture


Intel® Parallel and Cluster Studio XE best choice for C/C++/Fortran development tools

Performance


Productivity

Quality

1 Evans Data Corp. North American Development Survey 2011 Volume I

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Key Pillars of Software Development Performance

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Performance

Optimizing for


solutions



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Performance

Optimizing for


solutions



Performance

Optimizing for


solutions

For an Intel processor, LAPACK Performance Intel MKL compared with ATLAS* open source solution

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Performance

Optimizing for


solutions

MPI Latency: 768 Processes / 64 Nodes on Intel processors running Linux* 64 Intel® MPI Library vs. alternative MPI libraries

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Tune cross-node MPI

Visualize MPI behavior

Evaluate MPI load balancing

Find communication hotspots

Tune single node parallelism

Visualize thread behavior

Evaluate thread load balancing

Find thread sync. bottlenecks

Intel®

Trace Analyzer and Collector

Intel®

VTune™ Amplifier XE

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“I know how to make 4 horses pull a cart - I don't know how to make

1024 chickens do it.”

Enrico Clementi Pioneer in computational techniques for quantum chemistry and Molecular dynamics

Picture source: http://www.webalice.it/enrico.clementi/

http://www.webalice.it/enrico.clementi/

http://www.webalice.it/enrico.clementi/


Key Pillars of Software Development Scalable Parallelism

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models

for today


Concurrent Containers Common idioms for concurrent access

- a scalable alternative serial container

with a lock around it

Miscellaneous Thread-safe timers

Generic Parallel Algorithms Efficient scalable way to exploit the power

of multi-core without having to start

from scratch

Task scheduler The engine that empowers parallel

algorithms that employs task-stealing

to maximize concurrency

Synchronization Primitives

User-level and OS wrappers for

mutual exclusion, ranging from atomic

operations to several flavors of

mutexes and condition variables

Memory Allocation Per-thread scalable memory manager and false-sharing free allocators

Threads OS API wrappers

Thread Local Storage

Scalable implementation of thread-local

data that supports infinite number of TLS

Intel® Threading Building Blocks



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models

for today


Intel® Threading Building Blocks



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models

for today


Intel® Cilk™ Plus

cilk_for (int i=0; i<n; ++i) {

Foo(a[i]);

}

int fib(int n)

{

if (n <= 2)

return n;

else {

int x,y;

x = fib(n-1);

y = fib(n-2);

return x+y;

}

}

int fib(int n)

{

if (n <= 2)

return n;

else {

int x,y;

x = cilk_spawn fib(n-1);

y = fib(n-2);

cilk_sync;

return x+y;

}

}

Turn serial code

Into parallel code

Parallel loops made easy

Open specification at

cilkplus.org



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models

for today



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Programmer's Drinking Song (sung to the tune of “100 Bottles of Beer”:

99 little bugs in the code, 99 bugs in the code, fix one bug, compile it again, 101 little bugs in the code. 101 little bugs in the code....

(Repeat until BUGS = 0)

-- Anonymous


Key Pillars of Software Development Productivity, Quality, Security

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Productivity

Quality

Security

Error detection

and Performance

tuning

Size and complexity of applications are greater,

organizations facing more application defects,

vulnerabilities and costs

Reworking defects 40%-50% of total project effort*

Effective analysis tools to find coding defects and vulnerabilities during the development lifecycle

Reduce time, effort, and

cost required to find and repair coding defects and security vulnerabilities,

prior to deploying software

Increase developer productivity and

proficiencies in delivering application reliability &

integrity

Find errors earlier when they are less expensive to fix

Correctness tools in development cycle, increase ROI by 12%-21%

Cost Factors – Square Project Analysis

CERT: U.S. Computer Emergency Readiness Team, and Carnegie Mellon CyLab NIST: National Institute of Standards & Technology : Square Project Results



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Productivity

Quality

Security

Error detection

and Performance

tuning

Memory Errors Threading Errors Security Errors

• Invalid Accesses • Memory Leaks • Uninitialized Memory

Accesses

• Races • Deadlocks • Cross Stack References

• Buffer overflows and underflows

• Incorrect pointer usage • Over 250 error types…

Jean Kypreos

Advanced Video Processing Team Manager

Envivio

"Having such a tool this early in the development stage frees the

validation from trivial bug reports and gives our engineers the

opportunity to code more efficiently from the very beginning of the

product cycle."

Intel® Inspector XE – Find errors



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Productivity

Quality

Security

Error detection

and Performance

tuning

Spending Time? Wasting Time? Waiting Too Long?

• Focus tuning on functions

taking time

• See call stacks

• See time on source

• See cache misses on your

source

• See functions sorted by

# of cache misses

• See locks by wait time

• Red/Green for CPU

utilization during wait

Claire Cates

Principal Developer, SAS Institute Inc.

We improved the performance of the latest run 3 fold.

We wouldn't have found the problem without something

like Intel® VTune™ Amplifier XE.

Intel® VTune™ Amplifier XE – Find bottlenecks



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Productivity

Quality

Security

Error detection

and Performance

tuning

Automated MPI Correctness Checking


Driving Future Insight

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Intel: Full Engagement on Delivery of Technical Compute Workload Optimization

Ecosystem Collaboration

Products and Technology

Research Community

Standards Based Solution Optimization and Delivery

Optimize Intel® Solutions to Address Emerging Workloads

Identify Computing’s Role in Scientific and Research Challenges

Accelerate Time to Insight

Intel Xeon, MIC, Common Tools &

Compilers

Top 500 Exascale Insight


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An Insatiable Need For Computing

Based on current technology, scaling today’s systems to an exaflop level would consume more than a gigawatt

of power - roughly the output of Hoover Dam

Picture source: http://en.wikipedia.org/wiki/Hoover_Dam

Source: The Opportunities and Challenges of Exascale Computing, http://science.energy.gov/~/media/ascr/ascac/pdf/reports/Exascale_subcommittee_report.pdf


Accelerating the Path to Exascale

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Intel’s Exascale Commitment Reaching Exascale by 2018 through combination of

Intel MIC-based products and Intel Xeon processors

Exascale requires >100X performance of today at only 2x the power of today‘s #1 system

Intel® Many Integrated Core (Intel® MIC) Architecture

One programming model democratizes usage and avoids costly detours

Performance & Programmability

Knights Ferry Software Development Platform


Intel: Shattering Barriers More than one sustained TeraFlop/sec

ASCI Red: 1 TeraFlop/sec December 1996

1996 First System 1 TF/s Sustained

(with 2/3 system built… 7264 Intel® Pentium Pro processors)

OS: Cougar 72 Cabinets

Knights Corner: 1 TeraFlop/sec November 2011

2011 First Chip 1 TF/s Sustained One 22nm Chip

OS: Linux* One PCI express slot

Source and Photo: http://en.wikipedia.org/wiki/ASCI_Red

* Full system 1.3 TeraFlop/sec, later upgraded to 3.1 TeraFlops/sec with 9298 Intel® Pentium II Xeon processors

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http://en.wikipedia.org/wiki/File:ASCI-red.jpg


Intel & HPC

Strong Research Partnerships

Universities

Government

Industry

World Class Research in HPC

* Other names, logos and brands may be claimed as the property of others.

Delivering Breakthrough

Technologies to Fuel Innovation

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End-users Are Excited Too!

“Moving a code to MIC might involve sitting down and adding a couple lines of directives that takes a few minutes. Moving a code to a GPU is a project“ (4/21/11)

Dan Stanzione, Deputy Director at TACC

“The CERN openlab team was able to migrate

a complex C++ parallel benchmark to the

Intel MIC software development platform in

just a few days.”

“By just utilizing standard programming on both Intel® Xeon processor and Intel® MIC architecture based platforms, the performance met multi-threading scalability expectations and we observed near-theoretical linear performance scaling with the number of threads.”

Programming models are the key to harness the computational power of massively parallel devices. Obviously, Intel has realized this trend and substantially supports open standards and invests in innovative programming models. LRZ and TUM are using Intel hard- and software for many years and know the tool chain by heart.

MIC Execution: Straightforward. First version within a few hours, optimized version took 2 days

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Intel Exascale Labs - Europe

ExaScale Computing

Research Center, Paris

Performance and scalability of

Exascale applications

Exascale Cluster Lab

Jülich

Exascale cluster scalability

and reliability

Space weather prediction

Architectural simulation and visualization

Numerical kernels

Exascience Lab

Leuven

Scalable Run Time System

Exascale tools

New algorithms

Intel -BSC Exascale Lab, Barcelona

Strong commitment to advance computing leading edge: Intel collaborating with HPC community & European researchers 4 labs in Europe, Exascale computing is the central topic

Signed Collaboration agreement

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http://www.google.fr/imgres?imgurl=http://www2.iap.fr/users/riazuelo/img/logoCEA.JPG&imgrefurl=http://www2.iap.fr/users/riazuelo/index.html&h=213&w=217&sz=7&tbnid=e0g5b27UZQ9I_M::&tbnh=105&tbnw=107&prev=/images?q=logo+CEA&hl=fr&usg=__ZEHCoO_aADKuKHtZjYRNDlTUGE8=&ei=zuUDSvSlMuONjAfQi43ZBA&sa=X&oi=image_result&resnum=3&ct=image


Optimize and extend

• Program for multicore processors today

• Versatile Intel® Architecture scales forward for continued relevancy and accessibility

• Best way to prepare for Intel® MIC Architecture

• Compatible models and tools make parallel programming accessible to all

C++ and FORTRAN developers

on Windows®* and Linux*

High performance, cross platform apps

Evaluate today

http://software.intel.com/en-us/intel-sdp-home/

C++ and FORTRAN developers

on Windows* and Linux*

High performance MPI clusters

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Summary

• Efficient handling of connected, intelligent, massive, unstructured, and dynamic data is key to meeting the growing computational needs and software expectation of today and future

• Intel® Software Development Products provide key pillars of today’s and future software development

• Productivity,

• Quality,

• Performance

• and Scalable Parallelism

“The solution of important problems may be delayed

because the requisite tools are not perceived.” Tjalling Charles Koopmans, Three Essays on the State of Economic Science, Vol III, p 170 (1957)


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Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, reference www.intel.com/software/products.

Copyright © , Intel Corporation. All rights reserved. Intel, the Intel logo, Xeon, Core, VTune, and Cilk are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others.

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