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Reap What You Sow:Reap What You Sow:Spare Cells for PostSpare Cells for Post--Silicon Silicon Metal FixMetal Fix
KaiKai--hui Changhui Chang††
Igor MarkovIgor Markov††‡‡
Valeria Valeria BertaccoBertacco††
†University of Michigan at Ann Arbor
Apr. 15, 2008
‡National TaiwanUniversity
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Current Design Challenges
� Due to looming design complexity, more bugsescape pre-silicon verification
� Post-silicon validation and debugging are responsible for 35% of a chip’s time to market
Pre-silicon Post-silicon
180nm
130nm > 28% of TTM !
90nm > 35% of TTM ?
~ 17% ofTTM
2
for 35% of a chip’s time to market
� High-profile bug escapes
� Pentium – FDIV bug
� AMD Phenom L3 cache bug
� Decreased time to market shortens verification time → more bugs in silicon
� Post-silicon fix is growing in importance
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Dramatic Increase in Mask Costs
� Mask cost is increasingdramatically� $3M/set at 65nm node
Mask cost trends [ITRS’05]
3
0
2
4
6
8
80 70 65 57 50 45Technology node (nm)
Mas
k co
st (
$mil
lion
) Current node:
$3M/set
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Dramatic Increase in Mask Costs
� Mask cost is increasingdramatically� $3M/set at 65nm node
� Transistor masks are most expensive⇒ Reuse can reduce cost
4
⇒ Reuse can reduce cost� Only metal layers can
be changed ⇒⇒⇒⇒ metal fix
� Metal fix can be accomplished by� Respin of the chip
� Focused Ion Beam (FIB) modifications of wires
� No transistor can be changed in metal fix
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Traditional Fix vs. Metal Fix
If an XOR gate is preplaced on the chip, it can be used
to fix the error by reconnecting the wires
5
Functional error:AND should be
XORTraditional techniques fix the problem by replacing the AND with XOR, but it requires remanufacturing
of the whole chip
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Spare-Cell Insertion Problem
� To enable metal fix, spare cells
need to be preplaced on the silicon die
� A spare cell is an unconnected cell
� Spare cell selection and placement impact metal fix quality
Poor spare-cell selection requires
Although spare-cell insertionis an important problem,
metal fix quality
6
XOR
NAND
NOR
INV
NOR
XOR
NAND
NOR
NOR
NAND
XOR
NOR
NOR
NOR
NOR
XOR replaced by NAND
High-quality fix with small perturbation to
the silicon die
Poor spare-cell placement requires
long wires
several cellsis an important problem,
no definitive solutions have been published
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Why is Spare-Cell Insertion Difficult?
� Predict post-silicon bugs is difficult
� Given a known bug, determining the best cells for the fix is easy
� However, post-silicon bugs cannot be known in advancein advance
� Need to considering both logical and physical information
� Can be challenging because spare cells are disconnected from the netlist
� Most existing logic synthesis and physical design tools cannot be utilized
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Our Contributions
� Connect cell-type selection problem to logic synthesis – SimSynth
� Measures heterogeneity among signals
� Addresses cell density problem
Handle spare-cell placement using � Handle spare-cell placement using physical design methods
� A novel spare-cell insertion methodology
� Considers both logical and physical aspects
� Covers both cell selection and placement
� First empirical study for spare-cell insertion8
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Outline
� Spare-cell selection: SymSynth
� Based on logic simulation – fast
� Adaptive to the needs of different design regions
� Spare-cell placement: UniSpare
� Reduces impact of spare cells on circuit performance
� Provides better metal fix quality
� Our spare-cell insertion methodology
� Experimental results
� Conclusions
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Spare-Cell Selection: SimSynth
� Goal: identify more useful cell types
� Based on the following observations
� Bugs discovered post-silicon are often subtle bugssubtle bugs
� To fix the bugs, the functionality of the circuit is only changed slightly
� Cells that can generate signals close to existing ones are more useful
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SimSynth Example
� Simulate input patterns to generate signatures
� A bit in the signature is the simulation value of an input vector
� It is the signal’s partial truth-table
� Try each cell type and measure the rate to successfully replicate a signaturereplicate a signature
11
g1
01
1101
g2
00
01
1111
01 10
Succeed
Fail
Cell types with higher success rates are more useful
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SimSynth Analysis
� Signatures are partial truth tables
� Allows cells to generate different functions
� More input patterns � more accurate truth tables
� Used when smaller function changes are expected
� Fewer patterns allows more significant changes� Fewer patterns allows more significant changes
� Measures heterogeneity of the circuit
� Low success rate � signal heterogeneity is high
� Generating useful signals requires more spare cells
� Needs higher spare-cell density
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Spare-Cell Placement
� PostSpare
� Spare cells scattered after placement
� ClusterSpare� Cell islands uniformly distributed before placement
� UniSpare (new)� UniSpare (new)
� Cells uniformly distributed before placement
13PostSpare ClusterSpare UniSpare
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Our Spare-Cell Insertion Methodology
Selection of spare cell types
and density(SimSynth)
CircuitSpare-cell types and
density
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Placementmethod
selection Spare-cellenriched
layout
Placementmethod
Cell insertionand placementExpected
bug density,metal fix
technique
Trade-off amongimpact to circuit delay,
wirelength andmetal fix quality
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Previous Work
No publications, only patents!No empirical evaluations
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No empirical evaluations(bug data are usually confidential)
For details please see the paper
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Empirical Evaluation
Benchmark Description Cell count
Alpha_IF Instruction fetch unit of Alpha 1205
Alpha_ID Instruction decode unit of Alpha 11806
Alpha_EX Instruction execution unit of Alpha 20903
� Benchmarks
Alpha_EX Instruction execution unit of Alpha 20903
Alpha_MEM Memory stage of Alpha 363
Alpha Alpha CPU full chip 30212
MRISC MiniRISC CPU 4359
Hold_logic Part of picoJava IU control 67
EXE_ECL Part of OpenSparc EXU control 2083
MD5 MD5 encryption/decryption core 9181
DES_perf DES encryption/decryption core 100776
16(Alpha is from Bug UnderGround project in Michigan)
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Cell-Type Selection
0.3
0.35
0.4
� Different circuit requires different types of cells
� INV, AND, OR, NAND, NOR are more useful
17
0
0.05
0.1
0.15
0.2
0.25
0.3
Alpha_IF Alpha_ID Alpha_EX Alpha_MEM Alpha MRISC Hold_logic EXU_ECL MD5 DES_perf
INV AND OR XOR NAND NOR MUX2
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Spare-Cell Density
� Resynthesize subcircuits using spare cells
� Measure the number of cells used
� Lower success rate requires more spare cells
6
7
0.35
0.4
18
0
1
2
3
4
5
6
Alpha_IF Alpha_ID Alpha_EX Alpha
Av
era
ge
nu
mb
er
of
spa
re c
ell
s u
sed
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Alpha_IF Alpha_ID Alpha_EX Alpha
INV AND OR XOR
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Cell-Type Selection
� Comparison to previous work
� Ours has 23% and 4% smaller delay increase
� Wirelength increase is approximately the same
125%
19
95%
100%
105%
110%
115%
120%
Delay Wirelength
Yee Giles Ours
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103%
104%
105%
Spare-Cell Placement
� Impact on delay and wirelength before metal fix
96%
97%
98%
99%
100%
101%
102%
Delay Wirelength
PostSpare ClusterSpare UniSpare (new)20
PostSpare ClusterSpare UniSpare
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Spare-Cell Placement
� Impact on delay and wirelength after metal fix
120%
125%
21
90%
95%
100%
105%
110%
115%
Delay Wirelength
PostSpare ClusterSpare UniSpare (new)
PostSpare ClusterSpare UniSpare
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Spare-Cell Placement
� Impact on number of metal segments affected
140
150
22
70
80
90
100
110
120
130
140
Metal segments affected
PostSpare ClusterSpare UniSpare (new)
PostSpare ClusterSpare UniSpare
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Summary
� Spare cell selection
� Use SimSynth to determine cell types and density
� Spare cell placement
� PostSpareMinimal impact on circuit performance, worst metal fix quality� Minimal impact on circuit performance, worst metal fix quality
� ClusterSpare
� Minimal number of affected metal segments
� Larger impact on circuit delay
� UniSpare
� Minimal delay increase
� Balance between impact to the circuit and metal-fix quality
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Insights and Contributions
� Cell-type selection: a logic synthesis problem
� A new technique – SimSynth
� Selects different spare cells for different designs
� Can also estimate required spare-cell density
� Cell placement: a physical design problem
XOR
NAND
NOR
NOR
NAND
� Trade-off among delay/wirelength increase, affected metal segments and circuit performance
� UniSpare provides the best balance between impact to the circuit and metal-fix quality
� A new spare-cell selection & insertion methodology
� Considers both logical and physical information
� First empirical analysis of spare-cell insertion
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NAND
NOR
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Backup Slides
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Spare-Cell Placement
300
350
400
450
500
Nu
mb
er
of
me
tal
seg
me
nts
aff
ect
ed
26
0
50
100
150
200
250
0 5 10 15 20
Nu
mb
er
of
me
tal
seg
me
nts
aff
ect
ed
Number of cells used during metal fix
PostSpare
ClusterSpare
UniSpare
Linear (PostSpare)
Linear (ClusterSpare)
Linear (UniSpare)
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Spare-Cell Placement
100.15%
100.20%
100.25%
Ch
an
ge
in
ro
ute
d w
ire
len
gth
27
99.95%
100.00%
100.05%
100.10%
0 5 10 15 20
Ch
an
ge
in
ro
ute
d w
ire
len
gth
Number of cells used during metal fix
PostSpare
ClusterSpare
UniSpare
Linear (PostSpare)
Linear (ClusterSpare)
Linear (UniSpare)
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Previous Work
� Spare-cell insertion method depends on expected bug rate and nature of bugs
� May vary from design to design
� Confidential – most work published as patents
Selection of spare-cell types� Selection of spare-cell types
� Most-commonly used cell [Yee’97]
� Basic gates (NAND, NOR, INV…) [Lee’97,Giles’03]
� Configurable logic [Payne’99, Wong’01, Schadt’02,
Bingert’03, Or-Bach’04]
� Complex structures [Chaisemartin’03, Vergnes’04]
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Previous Work
� Insertion of spare cells
� Scattered after design placement [Yee’97, Payne’99]
� Scattered uniformly before design placement [Schadt’02]
� Floorplaned with the design
� Scattered uniformly before design placement [Bingert’03]� Scattered uniformly before design placement [Bingert’03]
� Scattered after design placement [Brazell’06]
� Placed closer to potentially buggy region [Lee’97, Vergnes’04]
� Drawbacks
� Lacks analytical and empirical evaluation
� The same method is applied throughout the design� Cannot address different needs from different design regions
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