reason (ist-2000-30193) first annual report workpackage 03

Annual Review MeetingLviv, Ukraine, February 14-15, 2003

REASON (IST-2000-30193)First Annual Report

Workpackage 03

Raimund UbarTallinn Technical University

[email protected]

Annual Review Meeting, Lviv, Ukraine, February 14-15, 2003

Goals

WP3 is devoted to – training in design for testability of SoC, and – developing research skills and creativity

by

– development of • Courses (Task 3.1), • Tools (Task 3,2), • laboratory research scenarios (Task 3.3), and

– dissemination of new methods and tools in tutorials, workshops and seminars (Task 3.4)


Participants

• WP leader CR3: TTU (Estonia) 17,4 + + + +• CO1: WUT (Poland) 0.2 + +• CR4: VSTU (Russia) 1.1 + +• CR6: FEI STU (Slovakia) 0.2 +• CR8: TUI (Germany) 2.0 +• CR12: TUE (Netherlands) 0• CR13: IISAS (Slovakia) 4.3 + + + +• CR14: TUS (Bulgaria) 3.8 + +• CR15: LPU (Ukraine) +• CR17: TULC (Czech Republik) 4.8 + + + +• CR18: KTU (Lithuania) 8.0 + +• CR19: BSU (Belarus) 4.4 + + + +

Efforts Task1 Task2 Task3 Task4


New Courses in 2002

International events (3):

Task 3.1. Course materials Task 3.4 Training Actions

A Acronym Name Partner A Event/Organizer Place/Date No A/B (%)

2 TTU_CODIGIT Digital Testing TTU 7 Summer school (E)/ TU Darmstadt

Darmstadt, Aug. 26-30

10 56/44

4 TTU_TUTDFTAT SOC Analog Test

VSTU, FEISTU WUT

2 Tutorial (E)/ TTU

Tallinn, Oct. 7-9

34 18/66

5 TTU_TUTDFTDIT SOC Digital Test

TUL, VUT, IISAS

3 Tutorial (E)/ TTU

Tallinn. Oct. 7-9

11 30/70

Action 2 – in 2003 will be repeated in Germany, Estonia and twice in SwedenActions 4,5 – in 2003 will be repeated in Ukraine (twice), Czech Rep. and Slovakia


New Courses in 2002

Local events (6):

Task 3.1. Course materials Task 3.4 Training Actions

A Acronym Name Partner A Event/Organizer Place/Date No A/B (%)

1 TULC_WSATPGCS ATPG TULC 1 Workshop, TULC (CZ)

Liberec, June 26

7 0/5

9 BSU_COLTDTIC Test and DFT of LSI BSU 13 Course with labs. BSU

Minsk 01.09-30.11

22 71/29

6 IISAS_DETBIST Test Gener. and BIST

IISAS 8 Course with lab, IISAS (S,CZ)

Bratislava, Nov. 12

TULC_TWBIS BIST TULC 6 Tutorial and WS TULC (E)

Liberec, Nov

42 34/62

7 TUS_DESTESTSYS CHIP

DFT of SOC TUS 4 Tutorial, TUS (B,E)

Sofia, Dec. 10

10 40/50

TUS_TESTDIGCIR Testing and DFT of DC

TUS 5 Workshop, TUS (B,E)

Sofia, Dec 11-13

16 14/64


Tool development in 2003A Acronym Tool Partner Status P/M 1 Specification of tools All D3.1

Tools for defect oriented testing

2 TTU_DOFSIM Defect-oriented functional fault simulator TTU 3.0 3 TTU_MAFFAD Tool for mapping functional faults to defects TTU Prototype 1,5 4 TTU_DOFGEN Defect-oriented test generator TTU 3.0 5 IISAS_DEFGEN

_GA Genetic algorithm based defect-oriented test generator

IISAS Prototype 2.0

6 LPU_FIESTA Cell-oriented defect analysis tool LPU 7,7

Tools for BIST analysis

7 TTU_SIMBIST BIST simulator TTU Prototype 3,0 8 TTU_HYBCAN Hybrid BIST cost analysis tool TTU 1,5 9 TULC_PGO SW tools for test generation and BIST TULC

Tools for high-level test generation

15 TTU_VHDLDD VHDL_DD converter TTU 5.0 16 KTU_ISGA Test generator for testing algorithms KTU 22.0


Tool development in 2003A Acronym Tool Partner Status P/M

Tools for design error diagnosis (prototype tools)

10 TTU_DERRIN Design error insertion tool TTU Prototype 0,5 11 TTU_PREDIA Prediagnostic tool for design error diagnosis TTU Prototype 1,0 12 TTU_TVECIN Interactive user interface for incerting manual

test vectors TTU Prototype 1.0

13 TTU_ECRDCR Encryption/decryption tool for emulating design errors

TTU Prototype 0,5

14 TTU_COMLIB Common library for binding diagnostic programs

TTU Prototype 0,5

Tools for testing analog circuits

17 VSTU_TeDiAC Tool for test and diagnostics of analog circuits

VSTU 4,8

18 BSU_TGAFSC Tools for test generation and analysis for functional switching

BSU 10.0

19 TULC_BSEDU SW and HW for Boundary Scan demonstration

TULC

20 TULC_RAS Tool for insertion random access scan cells TULC


Goals Revisited

• Design and Test of SOC: complexity, multiplicity of concepts, methods, algorithms and tools

• It is crucial – to develop in students and engineers creativity, skills of critical

thinking, problem solving and decision making, – to give them experience of developing new knowledge through

experimental or theoretical research in labs

• To support this goal, a new conception of teaching research will be developed and shared between partners


Goals Revisited

• To find solutions for problems - will be the task of the laboratory research

• The students should not be asked – to carry out boring measurements, – to press simply on buttons for getting results as a confirmation of

what they already know

• Instead, – they have at their disposal a set of tools,

– they have to plan and carry out experiments to find answers for questions and complex problems


Rethinking the Task 3.2

• Task 3.1. Courses

• Task 3.2. Teaching, training and research environment• Internet based “living pictures” for training (WP8)

– Education applets– Learning (training) applets

• Tool development for SW based research (WP3)– Interfaces for joint use of tools

• Educhip for HW based research (WP9)

• Task 3.3. Research scenarios• Task 3.4. Dissemination (tutorials, workshops, courses)


Cooperation in Tool DevelopmentDefect-Oriented Test

• TTU: Defect-oriented ATPG and Fault Simulator• IISAS: Genetic algorithms based defect-oriented ATPG • LPU/WUT: Cell-oriented Defect/Fault Analysis

BIST• TTU: BIST Quality Analysis• TULC: Tools for test generation and BIST• TTU: Hybrid BIST Cost Optimization

High-Level ATPG• TTU: Hierarchical ATPG• KTU: Test Generation for testing algorithms

Other new tools:• BSU: Test Generation and Analysis for Functional Switching• TTU: Tools for Fault/Design Error Diagnosis • VSTU: Test and Diagnosis of Analog Circuits


Diagnostic software Turbo-Tester

Test Generation

BIST Simulation

Methods:DeterministicRandomGenetic

Methods:BILBOCSTPStore/Generate

Design Test

Levels:GateMacro

Fault Simulation

Methods:Single faultParallelDeductive

Fault Table

Fault models:Stuck-at-faultsStuck-opensDelay faults

Test Optimization

Fault Diagnosis

Fault Location

Lab Research Env. - 1


Lab Research Env. - 2

SA

CSTP

RTPG

Manual patterns

Pseudorandom

testpatterns

Stored test

patterns

FSim

SAF

TPG

Delay

TPG

Defect

TPG

FaultTable

ADDER FB

DEFSIM

Working modes:BILBOCSTPStore & GenerateFunctional BISTBroadcasting BIST


.

ROM. . .

SoC

Core

Co

ntro

ller

• Combining – on-line generated pseudo-

random patterns – with pre-generated and stored

test patterns

• Problems :– To find the best characteristics

for test generator (PRPG)

– To find the best level of mixing pseudo-random test and stored test as the tradeoff between memory cost and testing time

Hybrid BIST:

CORE UNDER TEST

Response Analyzer

Test Generator

Example: Research Scenario


Cooperation in Research Teaching

Existing cooperation• Defect-Oriented Test: IISAS, TTU, WUT, (LPU)• Logic Level Test: TTU, TUI (Internet based)• Hierarchical Test: TTU, TUI (Internet based)• EduCHIP based: IISAS, TTU, TULC, WUT

Potential cooperation• BIST: TULC, TTU• Boundary Scan: IISAS, TTU, TUI, TULC (Internet based)

Other activities:• TTU: Fault/Design Error Diagnosis• TTU: Hybrid BIST• VSTU: Test and Diagnosis of Analog Circuits• BSU: Genetic Algorithms for VLSI testing• KTU: Testing of algorithms


New Courses in 2002In progress (4):

Task 3.1. Course materials Task 3.4 Training Actions (planned)

A Acronym Name Partner A Event/Organizer Place/Date 3 TTUCODEFT Design for

testability and fault tolerance

TTU Tutorial/TULC Tutorial/TTU Tutorial/FEISTU Jalta/Harkov RTI

Liberec/June Tallinn/Mai Bratislava/September September

8 IISAS_DEFTPG Defect-oriented test pattern generation

IISAS Tutorial/TULC Tutorial/ FEISTU

Liberec/June Bratislava/September

9 AGBOT A textbook on testing

TULC, IISAS, WUT, TTU

TUE_TUTDFTDT Fault diagnosis methods in digital circuits

TUE 11 Tutorial Cancelled


Events planned for 2003International events (9):

Task 3.4 Training Actions (planned)

A Acronym Name Partner Event/Organizer Place/Date 8 TTU_SYVATE

System validation and test

TTU Master course/ Jönköping Univ.

Jönköping/ January 20 – March 1

9 TTU_TUTDFTDIT Repeated

Advanced test methods

IISAS,FEISTU WUT, TTU

Tutorial/LPU Lviv/February 17

12 VSTU_ATUTOR Repeated

Test and diagnosis of analog circuits

VSTU Tutorial/LPU Slavsk/February 19

26 TTU_SYVATE Repeated

System validation and test

TTU Training course/ Linköping Univ.

Linköping/ March 19_21

14 TULC_TED Repeated

Defect-oriented testing of SOC

IISAS, WUT, TULC, TTU

Tutorial/TULC Liberec/June

15 TULC_TDTF - IC-DFT

Design for Testability

TULC Tutorial/TULC Liberec/June

16 TTU_CODIGIT Repeated

Digital Testing TTU Summer School/ TU Darmstadt

Darmstadt/August


Defect-oriented testing of SOC


Tutorial/FEISTU Bratislava/September

18 Tools for defect-oriented test


Hands-on train. session/ FEISTU

Bratislava/September


Advanced test methods

TULC WUT, TTU

Tutorial/Charkow RTI

Jalta/September


Events planned for 2003Local events:

Task 3.4 Training Actions (planned)

A Acronym Name Partner Event/Organizer Place/Date 20 Deterministic Test and

BIST IISAS Course/IISAS Bratislava/February

21 Deterministic Test and BIST

IISAS Course/IISAS Bratislava/April

11 Testing of SOC TTU Tutorial/TTU Tallinn/Mai 22 22 Testing and DFT of digital

circuits TUS + other Workhop/TUS Sofia/November

23 Testing and DFT of digital circuits

TUS + other Tutorial/TUS Sofia/November

24 TULC_TOD IC design tools practice for DFT

TULC Hands-on session/TULC

Liberec

25 Introduction to electronic devices testing and DFT for SMEs

VSTU Workshop/VSTU Vladimir


Main achievemetns• Co-operation between partners with the goal to develop

new courses and laboratory tools resulted in intensive joint research with several joint publications

• For better coordination of the work in WP3, three WP3 meetings were organized in Brno, Tallinn and Bratislava

• Two joint tutorials on Digital/Analog Test were carried out in Tallinn with involving the partners FEISTU, IISAS, TTU, TULC, VSTU, and WUT

• Both had a great success, attended, by 25/34 participants • The tutorials will be repeated in 2003 twice in Ukraine, in Czech

Republik, Slovakia and partly also in Germany and twice in Sweden


Main achievemetns• To increase the synergy of the whole project, tight links

were created between 3 WPs - WP3 and • WP8 - to create a basis for distance learning, and

• WP9 - to improve the HW based experimental research teaching

• Based on the intensive cooperation (IISAS, TTU, TULC, WUT) the conception of Task 3.2 of tool development was extended with the goal to develop an advanced research training environment involving

• new low-cost tools, • advanced distance learning technologies and • educational HW based laboratory basis (using EduChip)

• Based on this environment, new research training scenarios will be developed during the second/third project years


Main problems• Overlaps in proposed courses, tutorials and other events.

This makes coordination of this WP more difficult • Partners are looking for ways of better coordination of the

work• Examples:

– Action AGBOT to better motivate the cooperation – Developing jointly research training environment as the result of

cooperation between WP3, WP8 and WP9– For joining efforts in developing new research scenarios based on

this environment, new links and interfaces between partners’ tools should be created


• We have to look for more intensive cooperative activities, local actions are less important– Joint courses, tutorials– Joint tool environments– Joint research scenarios

• Defect oriented test (WUT, IISAS, TTU)• Hybrid BIST (WUT, IISAS, TTU)• Design for testability (TTU, TULC), etc.

– Joint materials: AGBOT• The goal for 2003: Hands-on lab courses for partners with

partner tools are the way to cooperation and to creation of joint research scenarios

Concluding Remarks


Thank you

reason (ist-2000-30193) first annual report workpackage 03

Documents

ttu estonia

tools task

pgosw tools

tool development

defect oriented testing2ttu

prediaprediagnostic

tulc czliberec

seminars task