recent developments in electrical metrology

8/4/2019 Recent Developments in Electrical Metrology

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Recent Developments in Electrical Metrology

for MOS Fabrication

Gate Engineering

Channel Engineering

Source-Drain Extension Engineering

George A. Brown

SEMATECH

Mark C. Benjamin

Solid State Measurements,Inc.


2/25

Gate EngineeringGeorge A. Brown

SEMATECH


3/25

3Slide 050309002

Introduction Gate Dielectrics

Brief Roadmap Review Traditional Gate Dielectric Electrical Metrology

Measurements, analysis, and limi tations

Improved Methods and Recent Developments

Critical C-V measurement parameters High frequency

Low series resistance test structures

Adequate area resolution

UHFCAP structure Multi-frequency C-V, D- characteristics Interface State (Dit) Measurement: charge pumping

In-line C-V Measurements

Summary


4/254Slide 050309002

ITRS Roadmap for High Performance Gate Dielectrics (2004 update)

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

2003 2005 2007 2009 2011 2013 2015 2017

Calendar Year

Jg(A/cm2)

01

2

3

45

6

7

89

10

11

1213

14

EOT(A)

Jg,simulated

(oxynitride)

Jg,limit

EOT

Beyond this point of cross over,

oxynitride is incapable of meeting the

limit (Jg,limit) on gate leakage current

density

Scaling beyond 1 nm, 103A/cm2 is almost upon us!


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5Slide 050309002

Evolution of gate dielectric electrical metrology

ParameterTraditional

MeasurementTechnique

TraditionalAnalysis

Technique

Shortcomings forAdvanced Devices

ImprovedMeasurement

Technique

Improved AnalysisTechnique

Oxidethickness, CET

100 kHz/1 MHzMOS C-V

ClassicalPoisson's Law

Models

C-V distortion from highgate leakage

Low-Rs teststructures, UHF

C-V

Multi-elementequivalent circuits

Oxidethickness, EOT

100 kHz/1 MHzMOS C-V

ClassicalPoisson's Law

Models

Failure to account forquantum confinement,

poly depletion

Schrodinger solversfor EOT

Interface StateDensity, Dit

Quasi-static C-VClassical

Poisson's LawModels

Gate leakagedominates quasi-static

data

Charge pumpingBrew's Dit

Pulse level, rise timeto separate bulktrapping from Dit

Oxide Charge

Tgrapping

MOS C-V

HysteresisVfb

inaccurate, poorly

defined for high-k

Pulsed transient

Id-Vg

Pulse rise time

analysis

New methodologies must be developed to deal with the characteristics of

radically scaled gate dielectric stacks.


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6Slide 050309002

Measurement of 0.5 nm EOT Gate Stacks with High Leakage

High leakage gate stacks are modeled as parallel

RC equivalent circuits.

To resolve the capacitance, use of higherfrequencies will reduce the capacit ive impedance,

making that element dominate the parallel

resistance/conductance. But this only works if there is negligible parasitic

series resistance in the test structure. Use of

higher frequencies if series resistance is presentonly makes the capacitive impedance of interest

negligible in comparison with Rs.

Gp Cp

Q = Cp/Gp

Gp Cp

Rs

Requirements for EOT Measurement of High Leakage


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7Slide 050309002

Requirements for EOT Measurement of High LeakageGate Stacks

1. Capacitor test structure design with minimum seriesresistance.

Topside electrical contact to the capacitor substrate is

required to eliminate the wafer chuck from themeasurement circuit.

2. Use of measurement frequencies high enough to reduce the

effect of the parallel conductance of the gate stack.Dissipation factor must be reduced sufficiently to permit

accurate measurements.

3. Geometric resolution of the test structure effective area must

be adequate to assure accurate and precise definition of EOT.


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8Slide 050309002

1-Port Philips UHF MOSCAP Design

Designed for low series resistance

Uses 3-point (G-S-G) UHF probe head

720 - 1.0x2.6 m capacitor elements Right and left ground pads connect p-well to

S/D.

active poly


9/25

9Slide 050309002

Multi-Frequency MIS C-V Measurements on the Philips UHF MOSCAP

UHF Capacitor Test Structure: High Frequency C-V Performance

0.0E+00

5.0E-12

1.0E-11

1.5E-11

2.0E-11

2.5E-11

3.0E-11

3.5E-11

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Gate Voltage [V]

Capac

itance

[F]

f = 100 kHzf = 1 MHz

f = 2 MHz

f = 5 MHz

f = 10 MHz

f = 20 MHz

f = 50 MHz

f = 100 MHz

CVC model

Lot-wafer 3052109-18: 40 cycles HfO2; HF-NH3 preclean

CVC Model ParametersEOT = 7.35

Nsurf = 9.7E17 /ccVfb = -0.252 V

RMS fit error = +/-0.8%

A(eff) for EOT fit = 8.74x10-6 cm2

0.0E+00

5.0E-12

1.0E-11

1.5E-11

2.0E-11

-2 -1 0 1 2

Voltage [V]

Capac

itan

ce

[F] 100KHz

1MHz

4MHz10MHz20MHz50MHz100MHz

3090511-01

2 nm SiO2 TiN gate electrode 0.7 nm EOT HfO2 poly gate

Effective Area = 8.7x10-6 cm2

Measurement: Agilent 4294A Precision Impedance Analyzer IV Probe mode

Frequency-invariant C-V data can be obtained in wafer form on 2 nm SiO2films with properly designed test structures.

Some frequency dispersion is seen on more highly scaled high-k devices.

Three element Equivalent Circuit Parameter Analysis from Dissipation


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10Slide 050309002

Three-element Equivalent Circuit Parameter Analysis from Dissipation

Factor-Frequency Characteristics

Dissipation Factor vs. Frequency PlotLot-wafer 3073102-07: STI HfSiO

0.01

0.1

1

10

1.0E+05 1.0E+06 1.0E+07 1.0E+08

Frequency [Hz]

Dissipation

Factorat-2V

D-f dataRo = 1.4E4 ohms

Rs = 18.4 ohms

D = 1/RoCo D = RsCo

ooo

s

ooo

oso

CRR

R

CRC

GRGD

1)1(

1)1(+=

+=

For low frequencies, D ~ 1/f:

In the high frequency limit, D ~ f:

osCRD =

Extraction of Ro, Rs from

D- PlotsEOT = 17.2

Go= 1/Ro Co

Rs


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11Slide 050309002

Dit: Comparison of Charge Pumping Techniques

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.510

9

1010

1011

1012 nFET W/L=10/1mTH75-2072317 #08

Vpeak

= 1.2V

Vbase = 1.0V Vbase

= -1.0V

Nit

[#/cycle*cm

2]

Vbase

[V] or Vpeak

[V]

1MHz Nit

100kHz Nit10kHz Nit

Fixed Amplitude,

Variable Base ChargePumping

Fixed Base, Variable Amplitude Charge

Pumping (into accumulation) Fixed Base, VariableAmplitude Charge Pumping

(into inversion)

These techniques provide

alternative ways to

characterize traps and

trapping processes in

high-k films.

Information on energyand depth distribution of

the traps may be obtainedfrom these curves.

3.5 nm HfSiO / polySi


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12Slide 050309002

EM-probe Description

Straycapacitancecompensatedvia software

Tip Shaft

~35 um

~300 um

InterfaceLayerassociatedwith tipcontact

~10 to 20

200um

Small contact area provides superior

performance for ultra-thin dielectrics

AFM Indicates

No SurfaceDamage

2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED


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13Slide 050309002

In-line Measurement of CET/EOT with EM-probe

y = 1.388x - 3.3638

R2 = 0.9898

0

5

10

15

20

25

30

335

0 5 10 15 20

nMOS EOT (A)

EM-

ga

teCET(Ang.)

OxynitrideThermal OxideOxynitride

25

Device-correlatable CET/EOT measurements can be made in-line

for real-time process control down to ~1 nm.


14/25

Channel Engineering

SDE Engineering

Mark C. BenjaminSolid State Measurements, Inc.


15/25

15Slide 050309002

Relationship Between Dose and NSURF

N

W

C

V

NSURF = Average Dopant Density within WEQ

NSURF

WEQ WMAX

Equilibrium Dose = EQD = N(w)dw from the surface to WEQ

= NSURFWEQ = SQRT(2kSSL,INVNSURF/q)2005 Solid State Measurements, Inc. ALL RIGHTS RESERVED


16/25

16Slide 050309002

EM-gate Equilibrium CV Comparison

SSM-6100 EM-probe CV versus Implant Dose

0

1

2

3

4

5

6

-3 -1 1 3 5

Vg(V)

C(

pF)

Slot 1 1E11 cm-2Slot 3 2E11 cm-2

Slot 5 5E11 cm-2

Slot 7 1E12 cm-2

Slot 9 1E13 cm-2Slot 11 5E13 cm-2

Slot 13 8E13 cm-2

Slot 15 1E14 cm-2



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17Slide 050309002

Sensitivity: Nsurf versus Implant Dose

SSM-6100 Nsurf Sensitivity Comparison

1.00E+15

1.00E+16

1.00E+17

1.00E+18

1.00E+19

1.00E+11 1.00E+12 1.00E+13 1.00E+14

Implant Dose (cm-2)

Nsurf

(cm-3

)



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18Slide 050309002

Major Device and Materials Issues with USJ S/D Structures

Sheet Resistance (RS)

Surface Carrier Density(N

SURF

)

Junction Depth (XJ)

Carrier Density ProfileShape

Junction Leakage Sensitive to Implant EOR Damage

Goal: Increase Electrically Active N

and Decrease W Ideal BOX Profile!!

W

N

Ideal

Actual

EORDe

fec

ts

NMAX

XJ


4 C ti l EM P b


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19Slide 050309002

4pp: Conventional vs EM-Probe

Semiconductor Substrate

USL

Force

Sheet Resistance = R S = CF(V/I)

I IV

1 2 3 4

s

Conventional Four Point Probe

dSemiconductor Substrate

USL

Force

Sheet Resistance = R S

I IV

1 2 3 4


USL

Force

S

I IV

1 2 3 4

s

Conventional Four Point Probe


USL

Force

I IV

1 2 3 4

EM-probe Four Point Probe

s

dSemiconductor Substrate

USL

Force

I IV

1 2 3 4

EM-

s

d

= CF(V/I)Sheet Resistance = R S



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20Slide 050309002

EM-probe Description

Stray

capacitancecompensatedvia software

Tip Shaft

~35 um

~300 um

InterfaceLayerassociatedwith tipcontact

~10 to 20

200um

Small contact area provides superiorperformance for ultra-thin dielectrics

AFM IndicatesNo Surface

Damage

EM Probe CV and IV: Non penetrating


21/25

21Slide 050309002

EM-Probe CV and IV: Non-penetrating

EM-Probe CV and IV is used extensively to measure dielectricswith thicknesses less than 1 nm.

-1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2

Gate Voltage (V)

0

10

20

30

40

C(pF)

EM-gate Short Term Repeatability Test8 Angstrom SiON Wafer

Mean = 9.83 Ang.Sigma = 0.051 Ang.

-12 -10 -8 -6 -4 -2 0

Vg(V)

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

I(A)

EM-gate IV: Thin OxidesStepped Voltage IV, Step Delay = 1000 msec

90 Ang. (Slot 7)30 Ang. (Slot 24)10 Ang. (Slot 25)

TOX = 90 Ang.

TOX=30Ang.

TOX=10Ang.~ 4 to 5 Orders of Magnitude Difference


Basic Principle of Four Point Probe (4pp) Method for R


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22Slide 050309002

Basic Principle of Four Point Probe (4pp) Method for RS

IA

VM

Voltmeter: Requires High ZIN, low

Input Offset Current

+ + - -

t

Resistivity = = [qp]-1 = RArea/lRArea/l P-type

Resistance = VM/IA

Sheet Resistance = /t = CF(VM/IA); = [q N(x)dx]-1

For Probes located far from Edge of Circular Sample, CF = 4.532

Semi-Infinite Slab

Defined StructureL

W RS = (V/I)/(L/W) , Units /Square

xJ

To eliminate Contact Resistance, Kelvin or Transmission Line(TLM)Structures are Used

Irvins Curves

1

2


C ti l EM P b 4 R C 1 P USJ St t


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23Slide 050309002

Conventional versus EM-Probe 4pp RS Case 1: P+ USJ Structures

10

100

1000

10000

100000

#1-1 #1-2 #1-3 #1-4 #1-5 #1-6

Rs

(Ohms

/square

)

Conventional 4pp

EM-gate 4pp

16 nm

45 nm

15 nm

45 nm45 nm

28 nm

Rs vs xj Comparison

0

0.2

0.4

0.6

0.8

11.2

0 200 400 600xj (Ang.)

Ratio(Method/EM-Probe)

Conventional 4pp

VPS

Hg Probe 4pp


R N Correlation: General Considerations


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RS NSURF Correlation: General Considerations

Correlation Depends on Activation and xJ

N

W W

N

Xj ~ Constant,Diffusionless

Nsurf Increasing;Higher Activation Nsurf ~ Constant

Xj increasing

Good Rs Nsurf Correlation Poor Rs Nsurf Correlation


Summary


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Summary

Gate Engineering requires new measurement and analysistechniques

Channel engineering requires new measurement techniques for in-

line metrology Equilibrium Nsurf extends usefulness

Source-Drain Extensions (USJ) require new measurement

techniques Junction leakage requires thought -> Nsurf ?


recent developments in electrical metrology

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