recent progress and emerging technologies of spintronics

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RECENT PROGRESS AND EMERGING TECHNOLOGIES OF SPINTRONICS DEVICE FOR VLSI 1- Spintronics basics 2- MRAM 3- Logic-In-Memory 4- Emerging concepts

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RECENT PROGRESS AND EMERGING TECHNOLOGIES OF SPINTRONICS DEVICE FOR VLSI

1- Spintronics basics

2- MRAM

3- Logic-In-Memory

4- Emerging concepts

MAGNETISM BASICS

AtomicMoment

Exchange Interactions

-JexSi.Sj

MacroscopicMagnetization

Lattice coupling+ shape anisotropy

Magneticanisotropy

• Intrinsic logic system (2 states)

• Non volatile• Size-independent

… as long as ΔE>kBT

Permanent magnetSpin moment

Electrons have a charge and a spin

Ferromagnetic

Antiferromagnetic

Orbital moment + Spin moment+ Spin-Orbit

L

J = L + SS=+1/2 or -1/2Eas

yax

is

ΔE=KuV

SPIN TRANSPORT

Exchange interaction Band splitting

Spin polarized current in and exiting magnetic layers

Giant MagnetoResistance (GMR)

In metals, if spin flip marginal Scattering proportional to

available DOS just above EF

Mobility (conductance) asymmetry

J

Sustained until spin-flippingdiffusion event

ρ depends on relative orientation of spin current and local M

ThickPolarizer

q Incoming e-

Transmitted (filtered) e-(spin↑)

Reflected e- (spin↓)

y

x

zTransfer of angular momentum = STT

Precession Damping Spin torque (ST)

)()()()()( PMMbPMM

Ma

dtMdM

MHM

dtMd

S

J

S

J

Seff

rrrrrr

rrrr

×−××+×+×−=θγθγαγ

Extended Gilbert equation :

If spin torque > damping torque Switching

If spin torque < damping torque No switching

SPIN TRANSFER TORQUE (STT)

Magnetization (Resistance) Current « Magnetoresistance »(Spin) Current Magnetization « Spin Transfer Torque »

H = -4 Oe

8,7

8,8

8,9

9

9,1

-8 -4 0 4 8I(mA)

R(o

hms)

H = -4 Oe

8,7

8,8

8,9

9

9,1

-8 -4 0 4 8I(mA)

R(o

hms)

I = -0.4 mA

8,7

8,8

8,9

9

9,1

-400 -200 0 200 400H(Oe)

R(o

hms)

I = -0.4 mA

8,7

8,8

8,9

9

9,1

-400 -200 0 200 400H(Oe)

R(o

hms)

eVEF

0EF

F1 F2

Insulator

EF

Parallel state

Ferro 1

Ferro 2

Insulator

EF

Antiparallel state

)()( 21 FF EnEn ×∝σ

↑↑

↑↑↑↓ −=

RRR

TMR

H

R

SPINTRONICS BUILDING BLOCK : THE MTJ

Low R

High R

Tunnel Magneto-Resistance

Magnetic Tunnel Junction

MRAM BUILDING BLOCK : THE MTJ

Al 2O 3

Co/Ru/CoFeCoFe/Fe

Amorphous : Incoherent tunneling

of various Bloch states

Crystalline: Specific wave

functionsoverlap

T.Kawahara, Hitachi

Base electrode

Seed layer

Pinning layer

Tunnel barrier

Capping layer

Spin injection layer

Thermal barrier

Etch stop layer

Contact to select transistor+ diffusion barrier

Ta(5) or NiFeCr(10) : Promotes texture of critical layers

PtMn(20) : AF layer sets direction of reference layer

CoFeB(2) / Ru(0.8)/CoFe(2) : SAF, immune to external fields

MgO (1.1) : Defines cell R & TMR

Reference layer

NiFe(3) / CoFe(2) : Stores data (2 stable states)

Storage layer

Protects MTJ during process

Top ElectrodeComplex but mastered for volume manufacturing

(1 millions heads/day since 5+ years !)

MRAM BUILDING BLOCK : THE MTJ

MTJ MANUFACTURING

TMR read head

GMR/TMR SENSORS

External Field Magnetization Resistance

Position sensors(earth field) Disk drive heads

(media bits stray field)

R(H)H

R

H

“1”

“0”

“1”

“0”- - - -Free

Pinned

H = Field from media

PM PM

I I

+ + + + + + + + + + + + + + +

+ + + + + + + + + + + + + + +

- - - - - - - - - - - - - - -

Vout

φEasy axis

H

Peripheral (CMOS) circuit not integratedSingle element devicesVolume manufacturing on Si or AlTiC wafersSub-‘’30nm’’ technology

“1” “0”

Rlow Rhigh

MAGNETIC RANDOM ACCESS MEMORIES

Magnetization state Logic memory state

0 100 200 300 400 500 600 700 800 900 100010

-6

10-5

10-4

10-3

10-2

10-1

100

Resistance

Nor

mal

ised

Cou

nt

0 100 200 300 400 500 600 700 800 900 100010

-6

10-5

10-4

10-3

10-2

10-1

100

10-1

100

Resistance

Nor

mal

ised

Cou

nt

Rmin Rmax

>25σ

Figure of merit is not ΔR, but ΔR/σΔR/σ >25 for functional device,

>40 for production-worthy processWW distribution 1σ need to be < 1%

Address

Data out (Rhigh)

Data ref

Data out (Rlow)

Address

Data out (Rhigh)

Data ref

Data out (Rlow)

WHY MRAM ?

Although not the best in each category, MRAM isthe only memory which scores everywhere

Fast, non-volatile, infinite endurance memory

+ moderate power (no HV), rad-hard, easy to embedd

Thermal Assist« TAS » or « TAMRAM »

Hx

Hy

Field-only« Toggle »

Spin Transfer Torque« STT » or « SPRAM »

Established technology1.5M units shipped4.5M forecasted in 2011Infinite endurance

PerpendicularPlanar

Freescale 4Mb (2006)

THERE ARE MANY MRAM !

STT-TASField-TAS

Fully scalable(stability / retention to <20nm)Multibit possibleLimited array efficiency(layout + large field drivers)

Lowest write current(<100µA, scales with shrink)Minimal cell / array size(~15F², soon not Xtor limited)Low sensitivity to field disturbBeware of stability(retention at small feature size)Combine Combine bothboth !!

1Mb Field-TAS (2011)

Scalability beyond 90 nm ?(Write power increase )

LATEST DEMO CHIPS

Use exchange biased bilayer to “lock” the stored data (high stability)

Heat the cell above to “unlock” the data

Analogous to Heat Assisted Recording in HDD (write at elevated T, store at RT)

TAS MRAM PRINCIPLE

Exchangebias

Lock Unlock

Step 1: Heat cell by flowingcurrent through transistor

R

H

HHexex

Ih = 0Isw = 0

T = ambient temperature

00

R

HIh > 0Isw > 0

T > blocking temperature

Step 2: Switch magnetization by a magnetic field or STT torque

Step 3: Cool undermagnetic field or STT torque

T = ambient temperature

R

HHHexex

Ih = 0Isw = 0

11

TAS write sequence

TAS-Field MTJ stackRxA from 30Ωµm² to 10Ωµm²TMR up to 130%Cell size 50nm (circular)

-200 -100 0 100 200

2000

2500

3000

3500

4000

4500

5000

R(O

hm)

H(Oe)00 -100 0 100 200

H(Oe)

OFFOFF

OFFOFF

Initial state

Final state

Current density @ 10ns Jc = 2.4 106 A/cm²KV/kBT > 100 at 32nm feature size (AR=1)

PtMn

IrMn

STT + TAS PROOF OF CONCEPT

Voltage (V)

Pul

sew

idth

(ns)

10 20 30 40 50 60 70 80 90100

101

102

103

104

technology feature size F(nm)

ppm

fail

rate

10yr ppm fail rate in 32M array, 10 years life (calculated)

CoFeBAR=2

SAF AR=2

TbFeCoAR=1

Co/Pt AR=1

TASAR=1

10 20 30 40 50 60 70 80 90100

101

102

103

104

technology feature size F(nm)

ppm

fail

rate

10yr ppm fail rate in 32M array, 10 years life (calculated)

CoFeBAR=2

SAF AR=2

TbFeCoAR=1

Co/Pt AR=1

TASAR=1

0,0 0,5 1,0 1,5 2,0 2,50

20

40

60

80

100

Sw

itchi

ng ra

te (%

)

Current density (x106A/cm2)

P to AP AP to P

Current pulses 10ns

Perpendicular polarizer (Pt/[Co/Pt]n/Co/Cu/Co)

Metallic spacer (Cu)

Metallic spacer (Cu)

Free layer (NiFe3/Co0.5nm)

In-plane analyzer (Co/IrMn)

IDC

HReal-time

dynamic test

Res

ista

nce

(Ω) Switching

No switching

ΔR

HOW FAST CAN MRAM BE ?

Heat Field

Δt = 14ns (fuse adjustable)

Heat Field

Δt = 14ns (fuse adjustable)

Write cycle 35nsChip level

H.Liu et al, APL97, 242510 (2010)

0.0 0.5 1.0 1.5 2.0 2.5 3.00.0

0.5

1.0

P->APAP->P

Prob

abili

ty

δ (ns)

STT Precessional switching

Switching transient ~ 200 psSwitching time < 1ns (deterministic) Expected Write cycle ~2-3 ns

Field MRAM

Switching transient ~ 1 nsSwitching time 5-10 ns (thermally activated) Product Write cycle ~30 ns

Von Neuman SoC

SiSiLogicLogic CMOS memoryCMOS memory

Large Si footprint, long interconnects Delay, capacitive loss, complex layout, heat

“Janus” SoC

SiSiLogicLogic

MTJsMTJs

Minimal Si footprint, short interconnects Faster, simpler layout, reduced dynamic power

(MAGNETIC) LOGIC-IN-MEMORY

Logic-in-memory concept (introduced in 1969)Storage elements are distributed over the logic planeNon volatility directly inside the logic circuit

Non volatile memoryNo leakage Static power off

Reduced wire count Minimal dynamic power, delayOptimal layout

Need NV, fast, infinite endurance, CMOS compatible memory !

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- Infinite endurance (>1016 for field write)High speed (1-30ns)

- Cell R adjustable, from Ω‘s to MΩ’sMatch with CMOS (~ kΩ)

- Cell is variable resistance driven by low voltageuse as standard library IP

- Can be deposited on any substrate‘’end-of-back-end » » process (above-IC)no impact on logic processonly 3 add-masks

Magneticelement level

CMOS logiclevel

MTJ-BASED LOGIC CIRCUITS

MRAM process well establishedFear for contamination (slowly) vanishingSeveral fabs now enabled with 200/300mm lines

Front-end contamination under controlLow-T BE process (250°C) compatible with Cu

interconnect processEtch still « tricky » IBE vs. RIE ?

High-Speed compact model Electrical behavior of MTJ written by field, STT and with/without thermal assistance.

SPECTRE (5.0) compatible (CADENCE platform analog solver).

MTJ ELECTRICAL COMPACT MODEL

SMTJ model

BSIM3v3 model

Simulation of a TAS-MRAM

R-SRAM ©

(MAGNETIC) NV-LOGIC CIRCUITS

– NV-Full Adder• One input is made non-volatile (instant startup,

security)• Drastic static consumption reduction• Footprint reduction

– Demonstrator : CMOS 0.18µm, – MTJs size: 200X100nm²

Hitachi + Tohoku UniversityS.Matsunaga et al, Applied Physics Express, vol. 1, 2008.

Magnetic LUT

Magnetic Flip-flop

Visite Altis - 15/10/2010 21

REPROGRAMABLE (MAGNETIC) LOGIC

# LUT 4 1444# TILES 361 (19x19)# Sequential elements 1444# of MTJs 187 720# of Transistors 9. 106

Silicon Area 21mm2

MRAM Reconfiguration TileEnergy

9 nJ

MRAM RestorationTile Energy

25,5 pJ

Clock Frequency 100 MHzFull configuration time 72us + 93K Clock

cyclesTile reconfiguration 200ns + 260 Clock

cycles# Input/Output 76 Input / 76

Output

# LUT 4 1444# TILES 361 (19x19)# Sequential elements 1444# of MTJs 187 720# of Transistors 9. 106

Silicon Area 21mm2

MRAM Reconfiguration TileEnergy

9 nJ

MRAM RestorationTile Energy

25,5 pJ

Clock Frequency 100 MHzFull configuration time 72us + 93K Clock

cyclesTile reconfiguration 200ns + 260 Clock

cycles# Input/Output 76 Input / 76

Output

mtile

4504 um

4504

um

4504 um

4504

um

• Increasing interest for MRAM for stand-alone, embedded memories or “logic-in-memory”

• Spintronics brings non volatility to CMOS circuits for low-power, normally-off electronics

• Manufacturing technology mature enough with pure-play foundries entering the game

• Design environment “ready-to-use” as standard library tools

(INTERMEDIATE) CONCLUSION

0

2000

4000

6000

8000

1 104

1998 2000 2002 2004 2006 2008 2010 2012

Nb

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+bre

vets

Année

www.scirus.com Mot clé: "MRAM"

Nb

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r yea

r on

MR

AM

WHAT’S NEXT ?

Courtesy Sam Bader

SPIN TRANSFER OSCILLATORS (STO)

VCO

Mixer

Antenna

fsig fsig-fmixfsig±fmix S(t)Antenafilter

Low f filter

Frequencysynthetizer

Reference

C

LResonator

B

R0Attenuated Resonator

Auto-OscillatorComp.energy losses

B

-Rs

VCO STO

Spin Transfer

Damping

Precession

C

LResonator

B

R0Attenuated Resonator

B

B

R0Attenuated Resonator

Auto-OscillatorComp.energy losses

B

-Rs

B

-Rs

B

-Rs

VCO STO

Spin Transfer

Damping

Precession

Spin TorqueSpin TorqueSpin TorqueSpin Torque

DampingDampingDampingDamping

Heff

M

Heff

M

Can spintonics-based device replace VCOs in a transceiver chain ?

If damping = STT Self-sustained precessionOscillations of R

Resonnance frequency 1-40 GHzTunable by current and/or field

Radio-opportunism

CuPEL

CuCo

IrMn

Pt/(Co/Pt)5

CuPEL

CuCo

IrMn

Pt/(Co/Pt)5

LETI/DCIS

RF in+OSCILLATOR MGO

Bias T

Source de courant

Ampli

IDC

DC + AC AC

Pointe RFAnalyseur de Phase

HHSPINAMP

RF in-

IpolOscSpin 4Kohms

4Kohms

GND

Pointes DC

Pointes DC

PointesRF

Substrat silicium

STO Amp.

LETI/DCIS

RF in+OSCILLATOR MGO

Bias T

Source de courant

Ampli

IDC

DC + AC AC

Pointe RFAnalyseur de Phase

HHHHHHSPINAMP

RF in-

IpolOscSpin 4Kohms

4Kohms

GND

Pointes DC

Pointes DC

PointesRF

Substrat silicium

SPINAMP

RF in-

IpolOscSpin 4Kohms

4Kohms

GND

Pointes DC

Pointes DC

PointesRF

Substrat silicium

4Kohms

4Kohms

GND

Pointes DC

Pointes DC

PointesRF

Substrat silicium

STO Amp.

Freq

uenc

yTime (ns)

500 1000

7.5

7.6

7.7

0

Phase Noise

SPIN TRANSFER OSCILLATORS (STO)

SPIN TRANSFER DOMAIN WALL MOTION

“Race Track Memory”MRAM & logic devices

In Domain Wall, local “magnetic” pressure induced by STT DW motion

Magnetic shift register

0 1 2 30

100

200

300

400

DW

vel

ocity

(m/s

)Current density (x 1012 A/m2)

Nature Materials Vol.9,pp.230–234 (2010)

Best STT value

Rashba-induced DW motion in ultra-thin Pt/Co/Al2O3 layers

NEW MATERIALS : HEUSLER ALLOYS

E

D↑(E) D↓(E)

EF

Jex

E

D↑(E) D↓(E)

EF

Jex

Use « half »-metals (Heusler alloys)

∞→−

=par

parantipar

RRR

TMR

Integration of half-metals couldopen the door for spin switches

Active logic devices

L.Hueso, N.D. Mathur, A.Fert et al, Nature 445, 410, 2007

The long quest for a spin transistor …Problems:• No efficient spin injection from FM into SC• Short spin lifetime in SC• No magnetic SC at RT

GrapheneSpintronics

I2I2I1

I1

M1 M2

sJJ,

TOWARDS PURE SPIN LOGIC ?

Extremly long lifetime + Efficient spin injection

SPIN-ONLY CURRENTS

Charge Current

SpinImbalance

Spin-Hall

Charge current Spin « current »

Inverse Spin-Hall

Spin current Charge current

Spin Current

Spin Current

Charge current

Spin current w/o charge currentWould allow full functionnality with

no heating / power dissipation !

V

Spin injection into graphene

Wei Kan et al (R. K. Kawakami's group), PRL 105, 167202 (2010).B. Dlubak et al, (A. Fert's group) Appl. Phys. Lett. 97, 092502 (2010)

(FINAL) CONCLUSION

Important “cultural” gap between magnetics and microelectronics communities Most MRAM players have HDD experience (e.g. magnetics “culture”)“Mutual education” mandatory to move towards adoption of spintronics in VLSI

Do not be afraid of magnetism and magnetic materials !

0

2000

4000

6000

8000

1 104

1998 2000 2002 2004 2006 2008 2010 2012

Nb

publ

icat

ions

+bre

vets

Année

www.scirus.com Mot clé: "MRAM"

Nb

publ

i+pa

tent

spe

r yea

r on

MR

AM

• Increasing interest for MRAM for stand-alone, embedded memories or “logic-in-memory”

• Spintronics brings non volatility to CMOS circuits for low-power, normally-off electronics

• Manufacturing technology mature enough with pure-play foundries entering the game

• Design environment “ready-to-use” as standard library tools

• Huge development potential