reconfigurable fast fourier transform

8/6/2019 Reconfigurable Fast Fourier Transform

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RECONFIGURABLE FAST

FOURIER TRANSFORM


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Overview

Introduction

FFT Algorithms

Radix Algorithm

Winograd Fourier Transform algorithm

Rader's FFT Algorithm Winograd Algorithm

Reconfigurable Architecture For FFT

Description of the architecture

Architecture of a Twiddle block

Architecture of a WFTA/Radix module

Description of the Module architecture Reconfiguration of the architecture

Advantages

Conclusion

References


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Introduction

The reconfigurable architecture allows more possibilities in the choice of

the FFT size.

Used mainly in digital terrestrial television broadcasting (DTTB)

Two algorithms (Radix algorithm and Winograd Fourier Transform

Algorithm (WFTA)).

Reconfigurable FFT IP deal with different sizes.

2048, 4096, 8192 and even 3780 points used in different television

standards.


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Introduction

multiplicity ofstandards constitutes a critical point in terms ofreceivers' compatibility

to develop a multi standard receiver

solution

1) implementingvarious IPblocks,each associated toaunique

standard.

2) buildingcustomized hardware that mayreconfigureitself.

3) makeuseofreconfigurableFFT algorithmswhich arewell

extended fortheRadixalgorithm


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FFT Algorithms

FFT algorithmsaregenerallyimplemented

according to twomajorapproaches.

theradixand

theWinograd algorithms.


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Radixalgorithm

DiscreteFourierTransform(DFT) isgiven as

toreduce thecomplexity theRadix2algorithm is

presented.

Thecomputation of theFFT ofsizeN=2m is

performedin severalstages. Each stagecomputes2m - 1DFT ofsize2


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Winograd Fourier Transformalgorithm

Combines the Raders index mapping and Winograds

short convolution algorithm.

Winograd algorithm, factorizes ZN 1 into

cyclotomic polynomials .

Winograd can be used to obtain minimal

multiplication FFT


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Rader'sFFT algorithm

FFT algorithm that computes the DFT ofprime sizes by re-expressing the

DFT as a cyclic convolution.

Algorithm

1. Dft:

2. IfNis a prime number, there exists a generatorgsuch that n =gq (modN)

for any non-zero index n and for a unique q in 0,...,N2

3. Similarly k=gp (modN) for any non-zero index kand for a uniquep in

0,...,N2.


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Rader'sFFT algorithm

4) compute the DC component with

5) Rewriting we get

The final summation, above, is precisely a cyclic

convolution of the two sequences aq and bq of

lengthN1 (q = 0,...,N2)


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WINOGRADALGORITHM

based on the Chinese Remaindertheorem(CRT).

CRT:

Its possible to uniquely determine a nonnegative

integer given only its remainder with respect to the

given moduli.


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WINOGRADALGORITHM

Algorithm:h(p) - filter coefficients and

x(p) - data sequence

1. Choose a polynomial m(p) and factor it into k+1

relatively prime polynomials.ie m(p) = m(0)(p)

m(1)(p) ............ m(k)(p)

2. Let

Use the Euclidean GCD algorithm to solve


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WINOGRAD ALGORITHM

3.Compute:

4.Compute5.Compute


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ReconfigurableArchitecture For Fast Fourier

Transform

3780-pointsFFT maybedecomposedinN= 7 x 5 x4

x 3 x 3 x 3 steps.

It canbeimplementedusingWFTA7,WFTA5,

WFTA4andWFTA3 algorithms


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ReconfigurableArchitecture


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Description of thearchitecture

The proposed architecture is divided into six stages.

In each stage, a module implementing a part of the FFT computation

is connected to one memory symbol input and one memory symbol

output.

Twiddle blocks are also implemented at each stage ofcomputation.

The input and output buffers are used to respectively store the time

domain and frequency domain samples. TheNcomplex samples corresponding to an OFDM symbol in time

domain are stored in the input buffer.


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Description of thearchitecture

Each complex sample is coded into 32 bits (16 bits

forthe real part and 16 bits forthe imaginary part).

In the same way, the last connected output memory

ofa module becomes the new input memory for the

next module or becomes the output buffer for the laststage.


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Architectureofa Twiddleblock

Composedofamemory

containing the twiddle factors

andofacomplexmultiplier

Multipliersmakeuseof four

realmultipliersandof two

realadders


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ArchitectureofaWFTA/Radixmodule


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Description of the Module architecture

Each module is composed of three parts.

First part aims to compute additions,

Second per forms multiplications by a

coefficient

last adder stage generates the output results


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Reconfiguration of the architecture

The reconfiguration needs concern the mapping of the data

flow in the structure and the configuration of the different

modules in a WFTA or Radix mode.

For the first point, a memory address controller is used to

control all the Symbol memories in read/write modes.

The reconfiguration of a module is performed by controlling

the different registers, multiplexers and the coefficient memory

addresses


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Advantages

It can be used to implement ofmulti standard

receiver

Less complexity. High throughput.

Allows the implementation of different

algorithms.


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Conclusion

An original reconfigurable architecture allowing

to deal with different sizes ofFFT particularly the

3780 points FFT is presented.

Uses several algorithm and rapidly switch from

one configuration to another.

Use a structure that guarantees a high throughput.


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References

[1] Florent Camarda, Jean-Christophe Prevotet, Fabienne Nouvel,Implementation of a Reconfigurable Fast Fourier Transform Application toDigital Terrestrial Television Broadcasting, in Proc. IEEE, Nov. 2009, pp.353-358.

[2]Keshab K. Parhi,VLSI DigitalSignal ProcessingSystems,2nd ed.,Chap 8,pp

237-244,Wiley Indiapvt.ltd,2008

[3] European Telecommunications Standards Institute, "DVB-T ; framingstructure, channel coding and modulation for DTV," ETSI," Standard, Nov2004.

[4] Association of Radio Industries and Businesses, "Integrated Services DigitalBroadcasting Terrestrial (ISDB-T); specification on channel coding,framing structure and modulation," Tech. Rep., May 2001.

[5] "Framing structure, channel coding and modulation for digital televisionterrestrial broadcasting," Chinese national standard," GB-20600, 2006.


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References

[6] M. Liu, M. Crussiere, J.-F. Helard, and O. P. Pasquero, "Analysis andperformance comparison of DVB -T and DTMB systems for terrestrialdigital TV," in Proc. IEEE, Nov. 2008, pp.1399-1404.

[7] Xilinx, "Fast Fourier Transform v6.0," Tech. Rep., Sep.2008.

[8] Altera, "FFT mega core function user guide," Tech. Rep., Mar. 2009

[9] C.-H. L. J.-C. Kuo, C.-H. WEN and A.-Y. Wu, "Vlsi design of a variable lengthFFT/IFFT processor for OFDM-based communication systems."

[10] Z.-X. Yang, Y.-P. Hu, C.-Y. Pan, and L. Yang, "Design of a 3780-point IFFTprocessor for TDS-OFDM," in Proc. IEEE, vol.48, 2002, pp. 57-61

[11] J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation ofcomplex fourier series," in Proc. Math. Comp., 1965, pp. 297-301.

[12] S. Winograd, "On computing the discrete fourier transform," in Proc.Math. Comp., Jan.1978, pp.175-199


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reconfigurable fast fourier transform

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