IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 12, DECEMBER 2002 713

RecordQ Symmetrical Inductors for 10-GHzLC-VCOs in 0.18-�m Gate-Length CMOS

L. F. Tiemeijer, R. J. Havens, N. Pavlovic, and D. M. W. Leenaerts

Abstract—We report a single-loop inductor suitable for inte-gration in a differential voltage-controlled oscillator (LC-VCO)with 0.6-nH inductance and record quality factors of 18 at 10 GHzand 20 at 15 GHz fabricated in an industrial CMOS processon a 10 cm substrate. A new lumped element model whichaccurately describes the inductor performance without the needfor frequency-dependent elements is presented. During the courseof this work, we found that a patterned ground shield significantlyimproves the inductor performance at these frequencies, but onlywhen the polysilicon bars are connected from the center of theinductor.

Index Terms—CMOS inductors, integrated circuits (ICs),on-wafer microwave measurements, voltage-controlled oscillator(LC-VCO).

I. INTRODUCTION

I NTEGRATED inductors are a key component for radiofrequency (RF) circuits such as low-noise amplifiers,

voltage-controlled oscillators (LC-VCOs), filters, andimpedance matching networks. In a standard CMOS processwith a multilevel interconnect providing a total aluminumthicknesses of 2 m, a quality factor of 15 at 2 GHz [1]is feasible for a 4-turn 5-nH spiral inductor. For smallerinductance values, better values of up to 24 for a 1.4-nH coilhave been obtained in similar processes [2]. So far, literatureon the performance of inductors designed to operate at higherfrequencies has been sparse. This letter represents the first re-port on the performance of an integrated symmetrical inductorsuitable for a differential LC-VCO operating at 10 GHz [3].Application areas for such a VCO are in the lower noise bandof satellite tuners and synthesizers for WLAN transceivers suchas IEEE802.11a and ETSI HIPERLAN/2.

At 10 GHz, substrate losses are more pronounced than atlower frequencies. Although Eddy currents are still negligiblewhen the substrate resistivity is at least 10cm, the currents in-duced in the substrate by the capacitance between the coil andthe substrate dissipate energy and reduce the maximum achiev-able . These capacitive substrate currents are shunted when ahighly conductive ground shield is inserted between the coil andthe substrate. This significantly increases theof the capaci-tance to ground at the expense of a somewhat reduced resonancefrequency. To prevent excessive Eddy currents in these groundshields they need to be patterned [4], [5]. We demonstrate that

Manuscript received July 9, 2002; revised September 12, 2002. This work wassupported by Philips Semiconductors. The review of this letter was arranged byEditor S. Kawamura.

The authors are with Philips Research Laboratories, NL–5656 AA Eind-hoven, The Netherlands (e-mail: luuk.tiemeijer@philips.com).

Digital Object Identifier 10.1109/LED.2002.805740

Fig. 1. Chip photograph of the on-wafer inductor test-structure in two-portground-signal-ground configuration. The four ground pads are connected in thebottom metal layer and to the (dark-gray) patterned ground shield beneath theentire inductor structure. “Open” and “short” dummy structures [7], [8] are usedto de-embed the bondpad and interconnect parasitics.

Fig. 2. Schematic of the polysilicon patterned ground shield used beneath theentire inductor structure. The polysilicon bars are either connected from thecenter using the solid metal 1 cross, or from the perimeter using the dashedopen-ended metal 1 ring.

the conventional patterning scheme [4] may seriously degradethe inductor quality factor, and present a better layout which al-lowed us to realize a record quality factor of 20 at 15 GHz for astandard 0.18-m gate-length CMOS process.

II. I NDUCTOR LAYOUT

For the inductor required for a 10-GHz LC-VCO, an induc-tance below 1 nH is sufficient [3]. An inductance in this range iseasily realized by a single-loop inductor. Due to its symmetry,

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714 IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 12, DECEMBER 2002

Fig. 3. Inductor quality factor versus frequency for single-ended operation.The effect of the CGS and a PGS on the quality factor of a 0.6-nH 10-GHzinductor is clear.

this layout is well suited for a differential VCO, and a center tapcan be easily added. The inductors of this study were fabricatedin the 5-metal layer version of an industrial CMOS process witha minimum gate-length of 0.18m and a 10 cm substrate resis-tivity. To reduce the inductor series resistance, the metal layers 3(0.5 m Al), 4 (0.5 m Al), and 5 (0.9 m Al) are connected inparallel using a large amount of vias. This provides an inductortrack sheet resistance of 18 m/square. A chip photograph ofa sample inductor test-structure suitable for probing with GSGRF-probes [6] is shown in Fig. 1. For integrated inductors ofthis type, the quality factor , defined as the ratio between thereal and imaginary parts of its impedance, is usually not veryhigh. One has to compromise between increasing the inductorsize to reduce its series resistance, and reducing size to obtaina self-resonance frequency sufficiently high for the applicationand providing margin for an acceptable VCO tuning range. Forthe inductors reported here, an outer radius of 170m and atrack width of 30 m was chosen. This provided an inductanceof 0.6 nH. To improve the , two patterned ground shields con-sisting of titanium silicidized polysilicon bars of 1m widthand 1 m spacing in an approximate radial pattern, as shown inFig. 2, were tested. The bars are either connected together in thecenter [5] using two crossing metal 1 strips or contacted fromthe outer perimeter using an open metal 1 ring [4].

III. RESULTS

Two-port -parameter measurements were made in the100 MHz to 40 GHz range using an HP8510C NetworkAnalyzer and Cascade Microtech coplanar GSG RF-probes.

-parameters measured on separate “open” and “short” dummystructures were used to extract a lumped element networkfor the interconnect and bondpad parasitics. In this way, thedistributed nature of the interconnect from bondpads to theinductor was modeled correctly, and could be accounted forduring de-embedding [7]. For frequencies up to 5 GHz, wherethe distributed nature of the interconnect parasitics is irrelevant,

Fig. 4. Inductor quality factor versus frequency for differential operation. Theeffect of the CGS and a PGS on the quality factor of a 0.6-nH, 10-GHz inductoris clear.

this de-embedding procedure yielded the same results asthe conventional open-short approach [8]. Fig. 3 shows thesingle-ended quality factor , which is obtained when oneinductor terminal is connected to ground, versus frequency.is given by the usual definition

(1)

It is seen that compared to the reference inductor without shield,the conventional perimeter grounded shield (PGS) reduces theinductor resonance frequency, without any improvement in

-factor. Only the center grounded shield (CGS) performs asexpected and increases the peakfrom 10 to 12 by reducingthe equivalent series resistance of the parasitic capacitances.Since the inductor will be used in differential mode in a VCO,we need to evaluate the differential quality factor

(2)

where

(3)

represents the inductor impedance under differential excitation[9], which minimizes the impact of the capacitance to the shieldand substrate. Fig. 4 shows that a record quality factorcloseto 20 is achieved at 15 GHz, while at the target frequency of10 GHz, a of 18 is available. Without shield, the drops to14 and the resonance frequency increases from 30 to 50 GHz.At 10 GHz, the record of 18 drops to 4 when a PGS accordingto [4] is used instead of the CGS. This is due to the fact that, inthe latter case, a strong magnetic coupling exists between the in-ductor loop and the open metal ring connecting to the perimeterof the ground shield. At high frequency, the voltage inducedover the open end of this metal ring will be close to that overthe inductor because there is a one-to-one transformation ratio

TIEMEIJERet al.: RECORD SYMMETRICAL INDUCTORS FOR 10-GHz LC-VCOs 715

Fig. 5. Topology of T-model used for the single-loop inductor. Theextracted values of the (frequency independent) resistances, inductances, andcapacitances are given in ohms, picohenris, and femtofarads, respectively.

between the two. Due to the high capacitance of the metal ringand the polysilicon patterned ground shield to the substrate, thiswill induce a considerable current in the substrate immediatelybelow the open end of the metal ring. The observation that forthe PGC the peak quality factors for single-ended and differen-tial operation are almost identical supports our conjecture thatthe losses for this inductor are caused by Eddy currents in theshield.

IV. SIMULATION MODEL

For circuit simulation it is required to map the frequency-de-pendent inductor impedance on a lumped element circuit.Pi-type models are frequently used for this [10]. However, aT-type topology, as shown in Fig. 5, is more suitable for asymmetrical inductor with a central node. Since in differentialoperations no RF current flows between the central node andthe shield node, the circuit connecting these nodes can be asimple lossy capacitance. The resistance seen in series with theinductor increases with frequency due to the skin effect. Thecommon practice [10] to capture this by a phenomenologicalexpression where the resistance increases with the square rootof the frequency is not compatible with the transient simula-tions required to optimize VCO design. This apparent increasein series resistance, however, is driven by the tendency of thecurrent to follow the path of least impedance, which is thepath of least resistance at low frequency and the path of leastinductance at high frequency. This behavior can be modeledwith high accuracy by a third-order distributed L/R network,as shown in Fig. 5. Compared to using only a frequency-de-pendent resistance, this approach has the added advantage thatthe decrease in inductance with frequency is also correctly

described. The values of the frequency independent resistances,inductances, and capacitances were extracted by least squarecurve fitting to the inductor measurements. As can be seen inFigs. 3 and 4, a single lumped element model is capable ofproperly describing the frequency-dependence of the qualityfactor for both single-ended and differential operations.

V. CONCLUSION

A single-loop inductor suitable for integration in a differentialLC-VCO with 0.6-nH inductance and record quality factorsof 18 at 10 GHz and 20 at 15 GHz fabricated in an industrialCMOS process on a 10cm substrate has been reported. Anew lumped element model which accurately describes theinductor performance without the need for frequency-dependentelements is presented. During the course of this work, wefound that a patterned ground shield significantly improves theinductor performance at these frequencies, but only when thepolysilicon bars are connected from the center of the inductor.

ACKNOWLEDGMENT

The authors wish to thank Philips Semiconductors for pro-viding the silicon for this study.

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