redefining the power benchmark
TRANSCRIPT
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Redefining the Power Benchmark
A tmel Wh i t e Paper
Author:
Espen Kragnes, Product Marketing Manager for Flash Microcontrollers and
Andreas Eieland, Sr. Product Marketing Manager for Flash Microcontrollers
AbstractThiswhitepaperdiscussestheneedforlowpowerinhighperformanceMCUs;itlooksathowthisultra
lowpoweroperationisachievedwhilemaintainingthehighperformanceandfeaturesneededinlow
powerapplicationswhile,importantly,explainingwhyengineersneedtomakethemselvesawareofthe
tradeoffsandoptimizationsdifferentIDMsmustmakeinordertoachievelowpower.
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Introduct ion
Powerconsumptionisnowahighpriorityateverystageintheentiremicroelectronicssupplychain.No
phaseisimmunetothedemandforbettercontroloverpowerconsumption.Itcanoftenbeseenpurelyasenduserpressure,buttheneedtoreducepowerdissipationatthetransistorlevelhasbeen
occupyingengineersmindsforalotlongerthanthebatterylifeofportableequipment.Beforeitwas
comprehensivelyaddressed,powerdissipationwasthreateningtolimittransistorintegrationand
therebystalltheprogressofintegratedcircuitdesign.
Theneedforengineerstoefficientlybalancethepowerbudget,however,remainsandcontinuesto
impostsignificantdemandsontheengineeringcommunity.Lowpowertechniquesandmethodologies
nowexisttoaddressthisconcernandareemployedbyeveryIntegratedDeviceManufacturer(IDM)in
theindustry,inonewayoranother.
ARM,supplieroftheonethemostpervasiveprocessor
architecturesinthesemiconductorindustry,builtits
businessondesigninglowpowermicroprocessorcoresand
hasbeensuccessfulinlicensingitsIPtotheindustry.The
latestandarguablymostsuccessfulderivativeoftheARM
architectureistheCortexfamily,withthreebranches
addressingspecificsectors;theCortexAfamilytargets
applicationprocessors,theCortexRbranchfocusesonreal
timerequirements,whiletheCortexMrangenowenablesa
widerangeofpowerfulbutpowerconscious32bit
microcontrollers.
However,althoughdesignedforlowpower,thecoreitselfisphysicallyoneofthesmallestelementsofanMCU.And
whilethecoreisdesignedforlowpower,itisntsafeto
assumethatallCortexMbasedMCUsofferthesamelow
powerperformance.AsanIPprovider,ARMsphilosophyisnttohomogenizethemarketbutto
empowerit,providingeachlicenseethebasisofanMCUbutleavingtheoverallfunctionality,
optimizationanddifferentiationofindividualfamiliestotheIDM.Inthisrespect,justbecauseavendor
usesalowpowercore,itdoesntfollowthattheresultingMCUistrulylowpowernotallCortexM
basedMCUsarecreatedequal.
ThiswhitepaperdiscussestheneedforlowpowerinhighperformanceMCUs;itlooksathowthisultra
lowpoweroperationisachievedwhilemaintainingthehighperformanceandfeaturesneededinlowpowerapplicationswhile,importantly,explainingwhyengineersneedtomakethemselvesawareofthe
tradeoffsandoptimizationsdifferentIDMsmustmakeinordertoachievelowpower.
Withthisbackdrop,thispaperalsointroducestheAtmelSAM4LAtmelslatestultrapowerful,ultra
lowpowerMCUmadepossiblebyfullyunderstandinghowtobalancethepowerbudget.
Powerconsumptionisnow
ahighpriorityatevery
stageintheentire
microelectronicssupply-
chain.Nophaseisimmune
tothedemandforbetter
controloverpower
consumption.
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Concepts of Low Power - How Lo w is L ow?
Thetermlowpowerisnowsoendemicthatithaslostalotofitsimpactandsomeofitsmeaning.
FromanMCUmanufacturerspointofview,lowpowerisrelativetothecompetitionanditshouldbe
apparentto
engineers
that
not
all
Cortex
M4
based
MCUs,
for
example,
operate
within
the
same
power
envelope.
Inordertoreallydeliverlowpower,IDMsmustdeveloptheirownlowpowertechnologiesand
methodologies,whichtheycanapplytotheCortexM4IP.Atmelhasdevotedmanyyearsdeveloping
justsuchalowpowersolution,itsproprietarypicoPower.
WhilefablessIDMsmustuseplainvanillalowpowerprocessesthatareavailableontheopenmarket,
Atmelhasdevelopedprocesstechnologiesthatfurtherimproveonagenericprocess.IDMsthatare
seriousaboutlowpowerMCUdesignwillfocusnotonlyontheCPUbuttheentiresystem,developing
transistortechnologiesthatofferlowpowerandlowleakage,butwiththeflexibilitytoemployhigh
performancetransistortopologiesinareaswheretheyareneededmost.picoPowerdeliversthis
capability.
WhenanMCUisdesignedforlowpoweritmustdeliveracrossarangeofusecases.Measuringpower
isntstraightforwardunderthebestofconditions,sobeingabletorelyontheentirearchitectureto
deliverlowpoweroperationunderallconditionsisessential. BenchmarkingMCUsforpowerislargely
dependentontwostatesofoperationstaticanddynamic. Powerisoftenequatedasafunctionofa
constant(capacitance),frequencyandvoltage,where:
P=K*F*V2Thisisasomewhatsimplifiedequationbutprovidesagoodfoundationforevaluatingthearchitecture.
Underdynamic
conditions,
the
frequency
of
operation
clearly
has
an
impact,
as
power
is
nominally
onlyconsumedinaCMOScircuitwhenthereisalogictransition.Reducingthefrequency,therefore,
lowersthetransitionspersecond,butdoesntaddressthenumberoftimesatransistormustswitchin
ordertoachieveagiventask.Forthis,thecoresarchitectureiscrucial,whichiswhythemorepowerful
CortexM4candeliverresultsfaster(feweroperations,andthereforefewerlogicgatetransitions)than,
say,an8051.
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Thesecondpartoftheequationrelatestothesupplyvoltagebutisfundamentallygearedtothe
manufacturingprocess.Voltagehasanexponentialimpacton
powerconsumption.Loweringthesupplyvoltagedelivers
greaterpowersavingsthanscalingthefrequencyalone.
Operatingfromalowersupplyvoltageisntassimpleas
loweringtheclockfrequency,however.Itmustbedesignedin
attheprocesslevel.
StaticpowerisconsumedwhentheCMOSgatesaresupposed
tobeinaquiescentstate(notswitching).Whilethisshould,in
theory,bezero,inpracticeitisimpossibleandmoresoas
processnodesreducetocreateatransistorwithnoleakage
currentinmoderngeometries.Ingeneral,thesmallerthe
geometry,thegreatertheleakagecurrent,therefore,themore
transistorsintegratedinadevicethehigherthepotential
altogetherinthestaticleakagecurrent.Bydevelopinglow
leakagetransistors,aproprietaryprocesslikepicoPowercan
successfullyaddresstheseissuesandmaintaintheleakage
closetothetheoreticalzerowithoutsacrificingperformance.
Concepts of L ow Power - Respons iveness
AsthefastestandmostfrequentlyswitchingtransistorsinanMCUwillbefoundinthecoresRAMand
thecoreitself,itfollowsthatallthetimethecoreanditssubsystemisactiveitwilldissipatethe
greatestamountofsystempower.
Forthisreason,sleepmodesarenowubiquitousamongMCUs.TheCortexM4hasbeendevelopedby
ARMtosupporttwosleepmodes,eachofwhichturnsoffagreaterorlesserdegreeofsystemclocks.IDMschoosehowtoimplementtheirownsleepmodesbuttheyallessentiallyrequirethecoretohalt
andstoresystemcriticalinformationinregistersandRAM,readytobereinstatedwhenexitingsleep
mode.ThisalltakestimeandinatypicalMCUapplication,timeissynonymouswithresponsiveness.
Becauseofthis,lowpowergoesfarbeyondthetransistorsswitchingcharacteristics.Itisadirectresult
oftheoverallsystemarchitecture.Onlybyapproachingthearchitecturaldesignfromthissystemic
viewpointcananIDMtrulydevelopalowpowersolution.AtmelsfamilyofARMCortexM3and M4
MCUshasrecentlybeenextendedtoincludetheSAM4L,anultralowpowersolutiondevelopedusing
AtmelspicoPowertechnologythatintegratesnumerouslowpowertechniquesspecificallydesignedto
bringthebenefitsoftheCortexM4coretoapplicationsthatdemandtruelowpoweroperation.
ItfeaturesAtmelsprovenapproachtomanagingsystempower,throughadistributedperipheral
networkthatoperatesindependentlyofthesystemclock,allowingthecoretoremaininadeepsleep
modeformuchlongerthanincompetitiveCortexM4MCUs.
AtmelsfamilyofARMCortex-
M3and-M4MCUshasrecently
beenextended
to
include
the
SAM4L,anultra-lowpower
solutiondevelopedusing
AtmelspicoPowertechnology
tobringthebenefitsofthe
Cortex-M4coretoapplications
thatdemandtruelowpower
operation.
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Concepts of Low Power - A Hol ist ic Appr oach
Byaddressingallaspectsofpowerconsumption,IDMsarebetterabletodesignanMCUthatofferstrue
lowpoweroperation.ImplementingaCortexM4inalowleakageprocesswill,ofcourse,resultinlower
systempowerthanifitwereimplementedinahighperformanceprocess,butifthesystemdesignis
entirelycorecentric,itislikelythateventhemostmundanetaskswillrequirethecoresintervention.
Forexample,asimpleinterruptserviceroutine,evenwherenoactionistaken,wouldrequirethecore,
Flashandothersystemmodulestobefullywokenfromasleepmode.
WithahighperformancecoreliketheCortexM4,theactionofwakingthecoreanditsentiresub
systemfromdeepsleep,justtoexecuteaserviceinterruptroutineorsomeothersimpletask,would
actuallytakeconsiderablylongerthanthetimeneededtoprocesstheactualtask.Thiswouldnotonly
consumeasignificantamountofvaluablesystempower,butmostofitwouldbeusedjustinwakingthe
system.
Itfollowsthatthroughaholisticapproachthatadoptslowpowertechniquescomplementarytothe
core,anIDMcandevelopandimplementfeaturesthatmakeextensiveuseoflowleakagetransistorsinthecoreandperipheralswhilealsoreducingthetimespentprocessing. Consequently,theycan
maximizelowpoweroperation.
Thisholisticapproachisprovingtobethemostrelevantandeffectivewayformanufacturersto
optimizeforpower.ThedegreetowhichitisemployediswhatreallydifferentiatesIDMswithinthe
CortexM4sphere.
A Hi s tory of Low Po wer - Act ive Mo de
Beforestaticpowerbecameamajorfactorinsystemdesign,activepowerwaspossiblytheonlydesignparameterthatconcernedmostengineeringteams.IDMslikeAtmelhavealonghistoryofdelivering
MCUsthatoffermoreperformanceatloweractivepower.Thislegacyisntbyaccident.
Oneaspectofmaintaininglowactivepowerisfindingthemostefficientwayofmovinginandoutof
sleepmodes.Thefasterthesystemclockcanbereestablished,thefasterthecorecancompleteitstask
andthelessactivepowerused.
Furthertothis,Atmelimplementsfeaturesthatcanoperateindependentlyofthecore.Intelligent,
autonomousperipheralsareabletoprocessinputsandoutputsindependentlyoftheCPU.Runningoffa
dedicatedclock,thisapproachallowsthecoretoremaininsleepmodeforlongerandthroughcarefully
architectedintercommunicationfeatures,peripheralsarealsoabletoexchangedatausingshared
buses,enablingthemtomakeintelligentdecisionsbasedonexternalstimuliwithouthavingtowakethe
core.
Enablingperipheralstooperateautonomouslyisnowrecognizedasakeyadditiontolowpower
operation.However,itis,again,crucialthattheimplementationisintegraltotheoverallsystem
architecture.Peripheralsthatexhibitafastresponsetimetothepointofrealtimeoperationare
essentialiftheyaretomanagetasksnormallyhandledbyahighperformancecore.
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ThePeripheralEventSystemintheSAM4ListrulyindependentofboththeCPUanditsclockingsystem.
WithitsownaccesscontroltotherealtimeclockthePeripheralEventSystemisabletocontinue
operatingwhentheCPUandthesystemclockareeffectivelyoff. Theresultisamuchgreaterpower
savingthanifthesystemclockneededtocontinuerunning.
A Hi s tory of Low Po wer - p icoPo wer
Theabilitytofullyunderstandanddesignforlowpowercandifferentiatemanufacturersandtheir
MCUs,irrespectiveofthecoreused.ExperiencecountsforalotandAtmelhasalonghistoryof
developinglowpowersolutions,basedonitspicoPowertechnology.Thiswasfirstusedinthe8bit
AVRfamilyandthelatestpicoPowertechnologynowenablestheSAM4L,becomingthefirstCortexM4
devicetofeaturepicoPower.
Perhapsmostsignificantisthesupplyvoltage;forinstance,theSAM4Lisabletooperatedowntoatrue
1.62Vwithoutsacrificinganyfunctionalityofthecoreor,morecrucially,theperipherals.Thisisaclass
leader.NootherCortexM4basedMCUavailabletoday,fromanymanufacturer,isabletooperateat
suchalowsupplyvoltage.
Theimpactofthisissimple. ReferringbacktoEquation1we
canseethatthelowertheVCC thelowerthepower.Unlike
frequency,whichreturnsa lineardecline,thesupply
voltagehasanexponential impactonpower,sobeingable
tooperateatatrue1.62V makestheSAM4Lthelowest
powerCortexM4solution available.
OtherfeaturesofpicoPower technologythathelpminimize
systempowerincludeextensive useofintelligentclockgating.
Asexplainedearlier,inactive modeCMOSconsumesmost
powerwhenchangingstate,so byavoidingunnecessarylogicstatechangesactivepoweris significantlyreduced.Clock
gatingiswidelyrecognizedin thesemiconductorindustryas
aneffectivelowpowertechnique,butitsimplementationcanvarybetweenmanufacturers.Theright
levelofclockgranularityandanefficientwayofdetermininghowtogatethoseclocksarelowlevel
architecturalfeaturesthatneedtobefullyintegratedintothedesign,asitiswithpicoPower.
Inaddition,bydevelopingtechniquesforultralowpowermemoryandintegratingitintothepicoPower
methodology,AtmelsMCUsdeliverfast,accurateandrobustFlashmemorythatconsumesmuchless
powerthancompetingsolutions.ThisisachievedthroughauniqueapproachcalledFlashSampling,
whichcomparesfavorablyagainstthestandardapproach,wheretheFlashmemoryisalwaysactive.
UsingFlashSampling,thememoryblocksareonlypoweredforafewns,justlongenoughforthecontrolblocktosamplethememoryscontents.Thememoryblocksarethenimmediatelydisabled,thereby
keepingactivepowerintheFlashmemorytoanabsoluteminimum.
ThePeripheral
EventSysteminthe
SAM4Listruly
independentofboth
theCPUandits
clocking
system.
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The Evolut ion of Low Power - Bringi ng pic oPower to th eCortex-M4
Asalowpowermethodology,picoPoweristheprimarytechnologyusedinAtmelslowpowerMCUsto
addressthethreekeyareasofpowerconsumptionsleepmode,activemodeandwakeuptimes.
Atmelsfirst32bitdevicetofeaturepicoPowerwastheAVRbasedUC3L,whichsetthebenchmarkforlowpowerMCUs.ThatbenchmarkhasbeenfurtherdefinedbytheSAM4L,whichtakeslowpowertoa
newlevel.
ThepicoPowertechnologypermeatestheentirearchitecture,fromtheprocesstechnologyusedto
manufacturethedevice,tothespeedatwhichperipheralsandclocksoperate.Althoughconceptually
similartothewayitwasintegratedintotheUC3L,inpracticepicoPowerasimplementedinthe
SAM4L,whichisthefirstARMbased32bitdevicefromAtmeltoemploypicoPowerisevolutionary.
Consequently,whenimplementingthemethodologyinanewfamily,Atmelsengineershadthechance
tointroduceimprovements,suchasextendingittonewperipherals,whilemakingfurtherpower
reductions.
Thisreturnsanactivemodepowerconsumptionthatissignificantlylowerthanthecompetition;
90A/MHz,whichisachievedinpartthroughthedevelopmentofanultralowpowerbuckregulator.
Thankstoitslownoiseimmunityandhighefficiency,thefullyintegratedregulatoralsoenablesthe
SAM4Ltooperatedownto1.62V,whiletheLDOonlyconsumes180A/MHz.
TheSAM4Lconsumesaslittleas1.5AinWAITmode,withfullRAMretention.Bundledwithan
unrivalledwakeuptimeoflessthan1.5S,theSAM4Lgivesthelowesttotalpowerconsumption.In
sleepmode,theSAM4Ldrawsaslittleas0.5AwiththeRealTimeClockstillrunning,andwithawake
uptimeoflessthan2S.
Industry s Highest Ef f ic iency
Whilemanufacturersareapttoquotetheirbestfiguresindatasheets,thereexistsanindependent
industrybodythatensuresanevenplayingfieldismaintained.TheCoreMark,developedbythe
EmbeddedProcessorBenchmarkConsortium(EEBMC)providesastandardsetofbenchmarksthatIDMs
subscribeto,inordertomeasuretheperformanceoftheirMCUsunderrealworldconditions.
Ineverydocumentedtestresult,theSAM4Loutperformsitscompetitors,eventhosebasedonthe
latest,lowestpowerCortexM0+.AstheSAM4LusestheCortexM4,thelargestandmostpowerfulof
theCortexMcores,theresults(Table1)emphasizetheimpactandimportanceofdevelopingand
implementinganindustryleadinglowpowerplatform,philosophyandmanufacturingcapability.
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Table1.
AtmelSAM4L MCUsredefinethepowerbenchmark,deliveringthelowestpowerinbothactive(90uA/MHz)andsleep
modes(1.5uAwithfullrandomaccessmemory(RAM)retentionand700nAinbackupmode).Theyarethemostefficient
MCUsavailabletoday,achievingupto28CoreMark/mAusingtheIAREmbeddedWorkbench,version6.40.AtmelSAM4L
MCUsalsodelivertheindustrysshortestwakeuptimeat1.5usfromdeepsleepmode.
The Evolu t ion of L ow Power - SleepWalking
Inmostcompetitorsolutions,responsivenessisdirectlyandinverselylinkedtosystempower;itisa
simpleequationwhereafasterresponsetimerequiresgreatertransistoractivityandthereforehigher
systempower.Asoutlinedearlier,Atmelsapproachisnottoprovidelowpoweratthecostofsystem
responsiveness.Here,wetakeacloserlookathowthisachieved.
MostmanufacturersAtmelincludedmustacceptthatinordertoachievemaximumpowersavings
duringsleepmode,moreofthedeviceneedstobeswitchedoff.Wakingfromdeepsleepmodesis
notoriouslycostlyintermsofthetimeittakesforthePLLstostabilizeandthenumberofclockcyclesit
takesforthesystemtobefullyactive.Whenthetaskisshort,thisoverheadcaneasilyrepresentmore
systempowerthan,say,asimpleinterruptserviceroutine.
SleepWalkingisafeaturethatextendstheconceptofautonomousperipheralsthatoperateindependentlyoftheCPUcoreduringactivemode,toactuallykeepingtheperipheralsfunctionalwhen
thesystemclockhasbeenstopped.Thisisachievedbyclockingtheperipheralsusingtherealtimeclock
(RTC),insteadofthesystemclock.
IntheSAM4L,SleepWalkinghasbeenintegratedintomanyoftheperipherals,includingtheanalog
comparator,theADC,theI2C,UARTandthecapacitivetouchinterface.Itisthentheperipheralthat
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decideswhethertowakethesystem,insteadoftheCPUwakingperiodicallytocarryoutaninterrupt
serviceroutine.
Thisdistributedlogicapproachallowsperipheralstomakeintelligentdecisions;todecidewhetheror
nottowakeuptheCPUbyqualifyinganincomingevent.Thismaybeatemperaturereadingfroman
externalsensor,orcheckinganI2Caddressmatchonacommonexternalbus.Theabilitytomakethis
levelofqualificationattheperipherallevelcaneasilyreducethepowerconsumptionbya100foldina
typicalapplication.
WiththeSleepWalkingintegratedintoalargernumberofperipherals,theneedtowaketheCPU
reducessignificantly,whiletheabilityforperipheralstointeractandmodifytheirparameters
autonomously,thisfeaturecanconceivablyallowtheCPUtoremaininactiveforthemajorityof
operationaltime.
The Evolut i on of Low Power - Low Voltage Operation
Astheonlydeviceavailableonthemarketthatisabletooperatedownto1.62V,theSAM4Lachievesunprecedentedlevelsoflowpoweroperation.Asignificantcontributortothisperformanceisthe
integrationoftworegulators;abuckregulatorandanLDOregulator.
TheLDOregulatorisaconventionalsolutiontoregulatinganexternalpowersourceforuseinsidethe
device.Thebuckregulatorismorerevolutionary,asitreducesthepowerdrawnbytheregulatorin
activemodebyaround50%.
The Evolut i on of L ow Power - Balancing Power with
Responsiveness
Asexplained,thekeytomaintainingloweroverallpowerisensuringthattheamountoftimetheCPU
spendsinactivemodeiskepttoaminimum.ThePeripheralEventSystemand,byextension,the
SleepWalkingfeaturesoftheSAM4Lhelpdelivertheperformanceneededwhenthecoreisinadeep
sleepmode,itisinevitablethatatsomepointthecorewillneedtowakeup,performsome
computationsandgobacktosleep,andallinasshortatimeaspossible.
Acriticalelementofthisprocessisthephaselockedloop(PLL)circuitwhichpowersthesystemclock.To
achievebetterperformanceandaccuracy,AtmelhasdevelopedanewgenerationofPLL,thedigital
frequencylockedloop(DFLL).ThisreplacesthetraditionalPLLwithacircuitthatcanoperateovera
widerfrequencyrange(8 150kHz),startupinjust10Sandlockin100S.FurthermoretheDFLLcan
produceanoutputfrequencyofbetween40 150MHzwithanaccuracyof0.1%accuracyoverthefull
temperatureandvoltagerange.
ThisnewdesignalsoreducesEMI;asitusesaspreadspectrumgeneratoritdistributesradiated
emissionsacrossmultiplefrequencies,andfeaturesconfigurablestepsize,maximumspreadandstep
frequency.
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SAM4L Arch itectur e & Key Featur es
AttheheartoftheSAM4ListheARMCortexM4core;AtmelsfirstCortexM4devicetofeaturethe
revolutionarypicoPowertechnology.
AsFigure1belowshows,thecoreissupportedbyanumberofsystemfeatures,connectedthroughthe
MultilayerHighSpeedMatrix.Whatislessobviousfromthediagramistheextensiveuseofdedicated,
distributedbussesandclocks,allofwhichcanbeenabledordisabled,andclockedatdifferentspeeds.
Thisfinegranularityofbusandclocksystemsiscrucialtomaintainingcompletecontroloverthe
peripherals,allowingtheusertoturnoffanyperipheralormodulethatisntneededatanytimeand
therebydeliveringgreatercontroloveractiveandstaticpowerconsumption.
Figure1. BlockdiagramofAtmelsSAM4Lmicrocontroller.Inaddition,thereistheDMAsubsystem,whichintegrateswiththeHighSpeedMatrixandthe
PeripheralEventSystem.Thisiswhatfacilitatesthemessagepassingbetweenperipherals,withafixed
2cycleresponse.
AllofthefeaturesintheSAM4LhavebeendevelopedtodelivertheindustryslowestpowerCortexM4
MCU.WhiletheSAM4LsexceptionallylowpowerisattributabletoAtmelspicoPowertechnology,the
valueof
the
SAM4L
as
amicrocontroller
is
due
to
design
elements
that
make
it
atruly
capable
MCU.
Thesecanbecategorizedaseitherarchitecturalorfunctional.
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Key Archi tectural Features:
ThelatestinnovationsinpicoPower
o WaitmodewithfullRAMretentiondownto1.5A
o Retentionmodedownto0.9A
o BackupmodewithRTCdownto0.7A
o Fastwakeup(1.5S)
True1.6Voperation
o Fullyfunctional,includingADCandFlash,downto1.62V
o Flexiblevoltagesupply:1.8V(regulated)or1.62 3.6V(battery)
SwitchingRegulator
o Downto100A/MHz
o Lowernoiseimmunity
o Higherefficiency
LinearRegulator
o Downto190A/MHz
o Highnoiseimmunity
o Lowerefficiency
PeripheralEventSystem
o Precisetiming
o ReducedCPUoverhead
o Reducedpowerconsumption
o InterPeripheralcommunication CPUandDMAindependent
o Latencyfreeeventhandling
Safefaultprotection
100%predictablereactiontime
SleepWalking
o Intelligentperipherals
Compareinputtopresetthreshold,andalertCPUwhenthresholdexceeded
ReduceCPUoverheadbyeliminatingunnecessaryinterrupts
Reducepowerconsumptioninsleepmodes
RTC/AsynchronousTime(AST)
o Realtimeclockandcalendarfunctionality
o Anyoscillatorcanbeusedasaclocksource
o Periodicalarmsandtimealarmssupported
o Prescalertickinterrupts
60Sto36hourswith32kHzinputclock
o Digitaltuningfor1ppmaccuracy
DigitalFrequencyLockedLoop thenextgenerationinPLL
o ReplacestraditionalPLL
Widerinputfrequencyrange(8kHzto150kHz)
10Sstartup
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100Stolock
o Outputfrequency40to150MHz
o 0.1%accuracyovertemperatureandvoltagerange
o Reducedradiatednoise(EMI)
FrequencyMeter
o Automaticallydetectfailingclocks
o Allclockscanbemeasured
o Multipleuses
Key funct io nal i ty features:
Integratedatthehardwarelevel,thecapacitivetouch
moduleoperatesusingPCBtracksassensors.Aswithother
peripherals,thismoduleislinkedtothePeripheralEvent
SystemandsupportsSleepWalkingmode,whichmeansit
canbeconfiguredtowakethesystembasedondetecting
theproximityofanexternalelement,suchasausersfinger
passingacrossaninterfacepanel.
Becauseitusescapacitanceasatrigger,nophysicalcontact
isrequired.Bysimplydefiningabutton,slider,wheelor
landingpadusingstandardPCBtracking,asophisticated
userinterfacecanbeconfiguredthatismechanically
isolatedfromthesystem.Thekeyfeaturesofthecapacitive
touchpanelinclude:
Endlessconfigurationpossibilities
Eventdriven,includingtouch,outoftouchorautonomousinterrupts IntegratedwiththePeripheralEventSystem
Inadditiontocapacitivetouchsensing,theSAM4LalsointegratesanLCDcontrollerthatcandrivea
4x40segmentdisplay.Thistooiscapableofautonomousoperation,offeringautomaticscrolling,
animationandsegment/displayblinking.Whenusedinconjunctionwiththecapacitivetouchsensor
module,forexample,amessagecanbeginscrollingwhenauserisdetected,beforetheCPUcomesout
ofsleepmode.TheLCDmoduleintegratesASCIIcharactermapping,whichfurtherimprovesthedisplay
updateratewhilereducingpowerconsumption.
AdditionalkeyelementsoftheSAM4Linclude:
A12bitADC,capableof350kspswithprogrammablegainandprogrammablesampleandhold
A10bitDAC,abletosampleat500ksps
UART,supportingsynchronousandasynchronous,RS232,SPI,IrDA,RS422andRD485 FullSpeedUSBhostwithonchiptransceivers Truerandomnumbergenerator 128bitAESsecuritymodule(FIPS197compliant) AtmelsGlueLogicController(GLOC)andPARCmodules
SAM4Lmeans
engineering
teamscan
confidently
balancethepower
budget,
without
compromisingon
performance.
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Conclusion
WhencomparedwithcompetitiveCortexM4basedMCUs,preliminaryresultsshowtheSAM4L
consistentlyoutperformsitscompetitioninindustrystandardbenchmarkssuchasEEMBCsCoreMark;
ameasureofhowmuchpoweradevicetakestoexecuteastandardsetoffunctions.
Thisisnocoincidence. picoPowerhasbeencontinuouslydevelopedtoprovidetheindustrysleadinglowpowerplatformandtogetherwithfurtheroptimizationsthishasenabledAtmeltodeliverthe
worldslowestpower,highestefficiencyCortexM4basedMCU.
Byintegratingintelligenceateverystage,AtmelsSAM4Lmeansengineeringteamscanconfidently
balancethepowerbudget,withoutcompromisingonperformance.
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Editor's Notes
About Atmel Co rporat ion
Atmel Corporation (Nasdaq: ATML) is a worldwide leader in the design and manufacture of
microcontrollers, capacitive touch solutions, advanced logic, mixed-signal, nonvolatile memory and radio
frequency (RF) components. Leveraging one of the industry's broadest intellectual property (IP)
technology portfolios, Atmel is able to provide the electronics industry with complete system solutions
focused on industrial, consumer, communications, computing and automotive markets.Further information
can be obtained from the Atmel website at www.atmel.com.
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Atm el Corporation
1600 Technology Drive
San J ose, CA 95110
USA
Tel: (+1)(408) 441-0311
Fax: (+1)(408) 487-2600
www.atmel.com
Atmel Asi a Limi ted
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