reference design kit - obspm.fr

Features PCI Version 2.1 compliant

board based on the powerful PLX 9050 BusTarget Interface Chip.

PCI 9050RDK available forboth Generic and ISA BusAdapters.

PLXMon95 provides a comprehensive tool for PCIbus monitoring and debug.

Sample Windows95 device drivers.

Comprehensive program-mers reference manuals forboth PLXMon and PCI9050RDK Development Kit.

Extensive technical supportavailable from PLX to ensuresimple and painless integra-tion design.

Large prototype area and test header plus daughtercard connectors for circuitryunder development.

A piggyback ISA slot thatenables existing ISA boardsto interface with the PCI9050 for software and hard-ware purposes.

PCI 9050RDKReference Design Kit

Overview

As PCI gains momentum as the preeminent backplane standard,suppliers of add-in cards of all types are rushing to get PCI ver-sions to market. Until now, design accelerators like softwaredevelopment kits have been geared to high performance PCIbus master adapters. For designers looking for a simple andpainless way to convert their ISA adpaters, PLX offers its PCI 9050RDK. The RDK plays development host to literally thousands of 8-and 16-bitISA cards providing a complete development environment.

At the heart of the kit is the PCI 9050 Bus Target interface chip! This 160pin chip has a PCI bus on one side and a flexible local bus on the other. Itincludes a PCI board designed with the PCI 9050 chip, I/O daughter card con-nector for standard or custom functions, a breadboard area, test headers, and apiggyback ISA slot that enables existing ISA boards to be plugged into the PCI9050 for software and hardware implementation. The PCI 9050RDK also includesa set of development software tools, including PLXMon™ for PCI bus monitor-ing and debug, and example serial/modem device drivers for Windows 95.

Benef i ts

With OEM PC suppliers and system integrators demanding PCI instead of ISA,the RDK offers customers an excellent design tool kit for converting existing ISAadapter designs toPCI. Designers now have a tool to overcome compatibility,plug-and-play, and the performance downsides of legacy ISA adapters!

PCI 9050RDK Contents

Copyright © 1997 by PLX Technology, Inc. All rights reserved.

PLX and PLXMon are trademarks of PLX Technology, Inc. which may be registered in some jurisdictions.

All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies.

Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or specification.

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9050RDK Features Included

PCI board with PCI 9050 Interface Chip

PLXMon95 PCI Debug Software

Serial/Modem Development Drivers for Windows95

Off-the-shelf ISA Serial I/O card

PLXMon Reference Manual

PCI 9050RDK Development Kit Manual

Product Order ing Information

PCI 9050 PCI Bus Target Interface Chip

PCI 9050RDK PCI 9050 Software Development Kit

PLX Technology, Inc.390 Potrero Ave.Sunnyvale, CA.94086 USATel: 1-800-759-3735Fax: 1-408-774-2169Email: [email protected] and FTP Site:

www.plxtech.com

PCI 9050 Block Diagram

PCI 9050RDK Block Diagram

PCI 9050RDK

Development Kit Manual

Version 1.2January 28, 1998

Product Sales: 1-800-759-3735Fax: 1-408-774-2169Email: [email protected] and FTP Site: //www.plxtech.com

T E C H N O L O G Y ®

PCI 9050RDK Development Kit Manual i

Table of ContentsPreface ....................................................................................................................vii

Document Organization................................................................................. vii

Style Conventions .........................................................................................viii

Contacting PLX .............................................................................................viii

Chapter 1...................................................................................................................1

PCI 9050RDK User’s Guide .....................................................................................1

Who Should Use the 9050RDK?.....................................................................3

Late Breaking News ........................................................................................3

Hardware Installation.......................................................................................4

PLX 9050RDK Windows 95 Bus Driver...........................................................7

PCI Exploration Programs .............................................................................15

Configuration Issues......................................................................................19

Windows 95 Tips...........................................................................................22

Troubleshooting ............................................................................................23

Chapter 2.................................................................................................................25

PCI 9050RDK Hardware Manual ............................................................................25

PCI Interface .................................................................................................26

PCI 9050 Target Interface Chip.....................................................................26

Table of Contents

ii PCI 9050RDK Development Kit Manual

SRAM Subsystem..........................................................................................30

ISA Subsystem ..............................................................................................32

Daughter-Card Connector .............................................................................39

Test Headers and Prototype Area .................................................................40

Additional Development Resources Provided by PLX...................................42

Chapter 3 .................................................................................................................43

PCI 9050RDK Schematics ......................................................................................43

Table of Contents

PCI 9050RDK Development Kit Manual iii

PCI 9050RDK Development Kit Manual iv

PrefaceThis manual provides all the information you need to use the PCI 9050RDK Development Kit.

Document Organization

This manual is organized into the following chapters for easy reference:

• Chapter 1, “PCI 9050RDK User’s Guide,” discusses how to use the PCI 9050RDK.In particular, it provides installation information and instructions for piggybackingISA comm cards and other ISA cards.

• Chapter 2, “PCI 9050RDK Hardware Manual,” describes each subsystem found on theRDK and provides suggestions for using the tools and circuitry included as a startingpoint for a new design.

• Chapter 3, “PCI 9050RDK Schematics,” provides schematics of the PCI 9050RDKfor easy reference.

The PLXMon software used with this product is documented separately, in the PLXMonUser’s Guide.

Preface

PCI 9050RDK Development Kit Manual v

Style Conventions

The following styles are used in this manual:

• Commands, file names, keyboard keys, text you manually enter, and URL paths arein Courier type (for example, DEBUG.EXE or http://www.plxtech.com).

• Variables and parameters are in Courier italic type (for example, hbuf or x).

• Emphasized text, names of diskettes, and names of publications are in italic type(for example, PLX 9050RDK Distribution Disk).

• Screen references are in Arial Bold type (for example, “Choose OK”).

Contacting PLX

We want to hear from you! If you have comments, corrections or suggestions please letus know.

PLX Technology, Inc.390 Potrero AveSunnyvale, CA 94086

Phone (408) 774-9060

FAX (408) 774-2169

Email [email protected]

Website http://www.plxtech.com

PCI 9050RDK Development Kit Manual 1

Chapter 1

PCI 9050RDK User’s GuideWelcome to the PLX 9050RDK (Resource Development Kit). This chapter is the primarycompanion to the kit—it will help you get the most out of your kit in the shortest amountof time. Use the information in this chapter to

• Install the 9050RDK card hardware in your computer

• Piggyback an ISA comm card to the 9050RDK card (the kit includes either a modemcard or a serial card) and install the PLX 9050RDK Windows 95 bus driver.

• Piggyback any ISA card on the 9050RDK

• Use PLX PCI software to explore and configure the PCI 9050 and piggybackedISA cards

• Troubleshoot problems you may have with the PCI 9050RDK

The 9050RDK offers PCI computer engineers hardware and software to learn about thePLX PCI 9050 interface chip, to build PCI-based projects, and test functional feasibilityof migrating an existing ISA product to PCI—all quickly and easily.

The key features of the 9050RDK card include the PLX PCI 9050 interface chip and theISA 8/16 connector. You can plug most ISA cards into the 9050RDK ISA connector; and,with the 9050RDK-exploration software, configure the PCI 9050 and test the functionalityof the ISA card. Once hardware functionality is satisfactory, you can concentrate on updatingyour driver software.

Who Should Use the 9050RDK? PCI 9050RDK User’s Guide

2 PCI 9050RDK Development Kit Manual

Figure 1-1. Major Functions of PCI 9050RDK

Most piggybacked ISA cards are fully functional without hardware changes. However,if your ISA board has special interface requirements, you can add custom hardware to theprototyping area of the 9050RDK. In particular, the 9050RDK is not designed to supportthe following:

• ISA boards that require refresh cycles

• ISA bus masters or DMA adapters (the PCI 9050 does not have PCI bus mastercapabilities)

The kit includes a standard ISA comm card (either a modem card or a serial card) and a PLXRDK bus driver. These components demonstrate a successful migration from ISA to PCI.

Aside from ISA to PCI migration, you can use the 9050RDK to learn more about thePCI 9050 interface chip or build a PCI-based prototype. The 9050RDK card provides alarge daughter-card connector, along with a generous prototyping area and on-board RAM.On-board headers provide wiring access to all local-side pins of the PCI 9050 chip.

For all your uses of the 9050RDK, you will find the PCI exploration software included withthe kit to be especially useful. This software enables you to read and write all physical memoryand I/O in your system. It also provides easy access to all PCI registers on all PCI devices, aswell as local registers on the PLX family PCI devices, including the PCI 9050. The softwarecomes in DOS and Windows 95 versions.

PCI 9050RDK User’s Guide Who Should Use the 9050RDK?


Who Should Use the 9050RDK?

The 9050RDK is a PCI engineering toolkit. It is targeted for computer engineers investigatingthe PCI 9050 interface chip as part of a commercial product. You are a good candidate if youare interested in converting an existing ISA product to PCI or in designing a new highperformance PCI (slave-only) product.

To use this product, you or your team should be able to

• Use hardware tools (such as logic analyzers and oscilloscopes)

• Design and build interface logic, if necessary

• Write or modify driver code

• Use command-line style programs (such as the DOS program, DEBUG.EXE)

Late Breaking News

Be sure to read any addenda and errata to the 9050RDK. These documents discussimportant changes, corrections, and improvements to the kit. The PLX website(http://www.plxtech.com) may contain important late breaking news as well.

Hardware Installation PCI 9050RDK User’s Guide


Hardware Installation

This section will help you set up the 9050RDK.

Standard Installation

Standard installation is the best starting point for all uses of the 9050RDK. This sectiondescribes how to install the 9050RDK card along with the communications card that isfurnished in the kit.

Once you have followed the standard installation procedure, it is recommended that you go tothe PCI Exploration Programs (PLXMon or PLXMon95), on page 15. Follow this procedureto install and use the PLX PCI Exploration Software.

Your 9050RDK card should not require any special jumper settings for general access to thePCI 9050. However, if you have problems, refer to Chapter 2, “PCI 9050RDK HardwareManual,” for jumper settings.

PCI 9050RDK User’s Guide Hardware Installation


♦♦ Install the 9050RDK card with the ISA Communications card in yoursystem:

1. Carefully piggyback the ISA comm card onto the ISA connector of the9050RDK card. Note the following:

• The component side of ISA cards is opposite from PCI cards

• You will not be able to replace the cover of your computer while an ISA card ispiggybacked on the 9050RDK card

• If your computer case interferes with external cabling to the ISA card, youmay want to remove the motherboard from the case

2. Connect appropriate external cabling (by way of phone line or serial cable) to a remotecomputer.

3. Use safe and reasonable procedures to open your computer and install the9050RDK card with the ISA communications card in an available PCI slot.

4. Power on your computer and boot either DOS or Windows 95.

5. Systems running Windows 95—If this is the first time a PCI 9050 is being installedon your system, your system’s PCI bus enumerator will discover that a new PCI cardhas been installed. You will be prompted to install a driver for the new card—choosedriver from disk provided by hardware manufacturer.

6. Next, you will be asked to install from disk. Choose copy manufacturers files fromA:______. This will install all the files from the disk. (Do not specify, just a single file.The Windows O.S. will find a communication port and install the software for thecommunications port).

You should now be able to

• Use the PLX PCI programs to explore the PCI 9050 and the 9050RDK memory(refer to the section, “PCI Exploration Programs,” on page 15 and the PLXMonUser’s Guide)

• Build a PCI-based prototype circuit

• Test the ISA comm card on the 9050RDK

• Piggyback any other ISA card on the 9050RDK (refer to the section, “PiggybackingAny ISA Card,” on page 7)

Hardware Installation PCI 9050RDK User’s Guide


Once the ISA comm card is piggybacked to the 9050RDK card, you can install software totest your setup. Table 1-1 lists the installation choices.

Table 1-1. Installation Choices

Install Comments

PLXMon PCI exploration software (DOS or Windows 95 versions).

Refer to the section “PCI Exploration Programs,” on page 15 and thePLXMon User’s Guide

PLX RDKBus Driver

This Windows 95 driver allows you to use popular applications with thepiggybacked comm card as if the card were plugged into a standard ISA slot.

Refer to the section “PLX 9050RDK Windows 95 Bus Driver,” on page 7.

PCI 9050RDK User’s Guide PLX 9050RDK Windows 95 Bus Driver


Piggybacking Any ISA Card

The 9050RDK is designed to provide full functionality for most ISA cards. However, if extrainterface hardware is required, you can add it in the 9050RDK prototyping area. In particular,the 9050RDK is not designed to support

• ISA boards that require refresh cycles

• ISA bus masters or DMA adapters (the PCI 9050 does not have PCI bus mastercapabilities)

♦♦ To piggyback any ISA card:

1. Follow the steps outlined in the section, “Standard Installation,” on page 4.

2. Power off your computer.

3. Carefully piggyback your ISA card onto the ISA connector of the 9050RDK card.Note the following:

• The component side of ISA cards is opposite from PCI cards

• You will not be able to replace the cover of your computer while an ISA card ispiggybacked on the 9050RDK card

• If your computer case interferes with external cabling to the ISA card, youmay want to remove the motherboard from the case

4. Power on your computer and boot DOS or Windows 95.

Once your ISA card is piggybacked to the 9050RDK card, you can install PCI explorationsoftware for DOS or Windows 95. Refer to the section, “PCI Exploration Programs,” onpage 15 and the PLXMon User’s Guide.

PLX 9050RDK Windows 95 Bus Driver

This section discusses information related to the Windows 95 bus driver for thePLX 9050RDK.

Driver Overview

The PLX RDK bus driver is a Windows 95 VxD (virtual device driver) that logically connectsa piggybacked comm card to the rest of the system. Programmers call this type of driver a“bus enumerator”—it programs the PCI 9050, and enumerates the one-and-only device on the9050 local bus. Using the enumerator technique allows standard device drivers to be usedwith the comm card. (An alternative is to modify the device driver to directly program the PCI9050.)

PLX 9050RDK Windows 95 Bus Driver PCI 9050RDK User’s Guide


Only two files are needed for the complete driver package—PLXRDK.VXD and PLXRDK.INF.The first file is the actual PLX RDK bus driver, and the second guides the Windows 95installer program.

You do not have to set the port address of the comm card as long as it is one of the fourstandard COM addresses. The comm card can be set to use any interrupt—all interrupts areOR’d on the RDK ISA connector into one line of the PCI 9050.

Note: Windows 95 handles copying of the PLXRDK.INF file differently, depending on whichversion of Windows 95 you are running (refer to the note under Step 3 in “Install the9050RDK card with the ISA Communications card in your system” on page 5 to determinewhich version is running on your system):

• Windows 95—Renames the installer file, PLXRDK.INF, when it copies the file fromthe PLX 9050 Distribution Disk to the \WINDOWS\INF folder. The file is renamed asOEMn.INF, where n is the nth OEM driver installation.

• Windows 95 OSR 2—Copies the installer file, PLXRDK.INF, from the PLX 9050Distribution Disk to the \WINDOWS\INF\OTHER folder.

Note: PLX has seen instances where the enclosed PLX PCI 9050 Windows95 driver(PLXSDK.VXD) does not operate with Windows95 OSR2. The following is suggested.

1. Windows95 OSR2 is not supported. Customers are advised to use a third-partysoftware solution from KRFTech. You have received their software and manuals in thekit. The KRFTech solution is a device driver development tool kit. The same driverwill work on both Windows95 and WindowsNT. KRFTech can be contacted athttp://www.krftech.com.

2. The source code for the Windows 95 driver (PLXSDK.VXD) is enclosed in the PLXPCI 9050RDK package and may be modified to support Windows95 OSR2.

♦♦ PLX RDK bus driver tasks (simplified):

1. Negotiate with the Windows Configuration Manager for an eight-byte range ofstandard ISA COM addresses (maps above the ISA space if all standard addressesare taken)

2. Program the PCI 9050 for local I/O access, mapping the range of local I/O to thestandard COM address

3. Probe standard COM ranges of the PCI 9050 local I/O space for an 8250 UniversalAsynchronous Receiver Transmitter (UART)

Contact PLX if you need a copy of the PLX RDK bus driver source code for use or reference.



Install, Check, Change or Remove the Driver

This section describes how to install, check, change, or remove the Windows 95 driver for theISA comm card of the 9050RDK. Refer to Table 1-2 below to perform the desired task.

Table 1-2. What to Do when You Want to Install, Check, Change or Remove the Driver

Task Comments

Install If you boot Windows 95 with the 9050RDK card installed, and a dialog box appearsstating the system found new hardware, install the driver using the methoddescribed in the section, “Installing when Windows 95 Finds New PCI Hardware,”on page 10.

If Windows 95 boots normally with the 9050RDK card installed, and you have neverinstalled the 9050RDK bus driver, chances are you were prompted about the newPCI card hardware in a previous session, and you chose not to install the driver.In this case, use the method described in the section, “Installing after PreviouslyChoosing Not to Install a Driver,” on page11 to install the driver.

Check If you are not sure the driver was properly installed, you can verify the installationas described in the section, “Verifying the Driver Installation,” on page 11.

Change If necessary, you can change the driver or examine the driver properties (file name,provider and version) and the resource allocations (port, memory and interrupt)of the device as described in the section, “Driver Properties, Device Resources,and Changing the Driver,” on page 12.

Remove orReinstall

You can remove or reinstall the driver, as described in the section, “Removing orReinstalling the Driver,” on page 13.

Installationproblems?

If you are still having problems installing the driver, try the steps outlined in thesection, “If You Have Problems Installing the Driver,” on page 14.



Installing when Windows 95 Finds New PCI Hardware

If, during the boot process, Windows 95 displays a box saying it found a PCI card, followedby a “New Hardware Found” dialog box (“Update Device Driver Wizard” dialog box inWindows 95 OSR 2), it indicates that the Windows 95 internal configuration database doesnot know of a driver to associate with the Vendor ID and Device ID of the PCI 9050. Adialog box pops up, prompting you to install a driver for Windows 95 to associate with thecard.

♦♦ To install the PLX RDK bus driver—Windows 95:

1. Insert the PLX 9050RDK Distribution Disk into the floppy drive of your computer.

2. Choose Driver from disk provided by hardware manufacturer.

3. Choose OK.

4. Choose OK in the Install From Disk dialog box (or browse, as necessary, to findPLXRDK.INF).

♦♦ To install the PLX RDK bus driver—Windows 95 OSR 2:

1. Insert the PLX 9050RDK Distribution Disk into the floppy drive of your computer.

2. Choose Next to search for the PLXRDK.INF driver. Windows 95 displays aconfirmation window when it finds what it believes to be the correct driver.

3. Choose Finish to use this driver.

4. Choose Other Locations if this is not the correct driver, to open a browse windowto search for it manually.

Your system should show that it is adding a communications port to the system, then continueto boot normally.

You can now use any application for the piggybacked ISA comm card that you would usewhen the card is plugged into an ISA slot.

Some notes about driver installation:

• If you are prompted to restart your computer after installing the driver, the PLX RDKbus driver failed to find a comm card piggybacked to the 9050RDK.

• If you are prompted with a Select Device dialog box after installing the driver,the Vendor ID or Device ID of the 9050RDK do not match the IDs found inPLXRDK.INF.

• If you removed the 9050RDK bus driver using only the Device Manager, Windows 95can still reload the driver automatically—you will not be prompted.



• If a PLX 9050RDK driver is installed, and you no longer want to use it, follow theinstructions in the section “Removing or Reinstalling the Driver,” on page 13 to“permanently” disassociate all PLX drivers from the 9050RDK card.

• You can use the Device Manager, as described in the section, “Verifying the DriverInstallation,” on page 11 to verify the driver installation.

Installing after Previously Choosing Not to Install a Driver

If your 9050RDK card is installed, your computer boots Windows 95 normally, and you haveeither removed or never installed the 9050RDK bus driver, then chances are you chose not toinstall the driver when prompted in an earlier session.

This section describes how to remove the Windows 95 dummy driver and install the9050RDK bus driver in its place.

♦♦ To remove the Windows 95 dummy driver:

1. Open Start | Settings | Control Panel | System | Device Manager.

2. Double click Other Devices.

3. Select PCI Card.

4. Choose Remove.

5. Choose OK from the Confirm Device Removal dialog box.

6. Choose Close.

Now, use normal procedures to reboot the system and follow the instructions in the section“Installing when Windows 95 Finds New PCI Hardware,” on page 10.

Verifying the Driver Installation

After installing the driver, you can verify whether it was installed properly.

♦♦ To verify the driver installation:

1. Open Start | Settings | Control Panel | System | Device Manager.

2. Double click System devices.

If you see PLX 9050RDK Bus in the list, then the correct driver is installed.

For more details on the driver, refer to the section, “Driver Properties, Device Resources, andChanging the Driver,” on page 12.



Driver Properties, Device Resources, and Changing the Driver

This section describes how to examine the properties of the serial port driver (suchas provider and version) and resources (such as ports, memory, and interrupts). Thissection also provides information for changing the driver.

The following procedures are standard. You use the Device Manager to examine theproperties and resources of the serial port driver, and optionally change the device driver.

♦♦ To examine the driver properties and resources:

1. Follow instructions in the section, “Verifying the Driver Installation,” on page 11to open the Device Manager, and show the list of system devices.

2. Select PLX 9050RDK Bus.

3. Choose Properties to open the properties box for the selected device.

a. You can examine the driver properties by selecting the Driver tab.

b. You can examine the resources (such as ports, memory, and interrupts) allocatedto the 9050RDK by selecting the Resources tab.

♦♦ To change the driver—Windows 95:

1. Select the Driver tab in the properties box of the selected device.

2. Select the PLXRDK.VXD entry.

3. Choose Change Driver.

4. You can either choose Have Disk -or- from the list of models, choosePLX 9050RDK Bus.

5. Close all the dialog boxes.

♦♦ To change the driver—Windows 95 OSR 2:

1. Select the Driver tab in the properties box of the selected device.

2. Choose Update Driver.

3. Allow Windows 95 to search for the driver or select it from the list provided.

4. Choose Finish to complete the installation.

5. Close all the dialog boxes.



Removing or Reinstalling the Driver

In Windows 95, the terms removing or reinstalling a driver really mean removing orreinstalling references to devices that use the driver.

♦♦ To remove the PLX 9050RDK bus driver:

1. Follow instructions in the section, “Verifying the Driver Installation,” on page 11to open the Device Manager, and show the list of System devices.

2. Select PLX 9050RDK Bus. (If you do not see PLX 9050RDK Bus listed, then thedriver is not installed.)

3. If PLX 9050RDK Bus is selected, choose Remove.

To reinstall the driver, use normal procedures to reboot the system and follow the instructionsin the section “Installing when Windows 95 Finds New PCI Hardware,” on page 10.

PCI devices are “Plug and Play” (PnP)—and Windows 95 makes it difficult to get rid ofdrivers for PnP devices. Follow these steps to permanently disassociate the PLX 9050RDKbus driver from the PLX 9050RDK card.

♦♦ To “permanently” remove the PLX 9050RDK bus driver—Windows 95:

1. Follow the instructions above to remove the PLX 9050RDK bus driver.

2. In the \WINDOWS\INF folder, find the PLXRDK.INF files named OEMn.INF (wheren as the nth OEM driver installed on your system). Open each of these files, using anytext editor (such as Notepad or WordPad).

3. Within each file, look for text identifying the file as a PLX 9050RDK bus driverinstallation file.

4. Delete all INF files that are PLX 9050RDK bus driver files. (There should onlybe one, but it’s a good idea to check for more. There will be multiple files if youinstalled the file more than once.)

5. Use normal procedures to reboot your computer.

6. When Windows 95 prompts you for a driver, choose Do not install a driveras described in the section “Standard Installation,” on page 4.



♦♦ To “permanently” remove the PLX 9050RDK bus driver—Windows 95OSR 2:

1. Follow the instructions above to remove the PLX 9050RDK bus driver.

2. Delete the PLXRDK.INF file from the \WINDOWS\INF\OTHER folder.

3. Use normal procedures to reboot your computer.

4. When Windows 95 prompts you for a driver, cancel out of the Update Device DriverWizard, as described in the section “Standard Installation,” on page 4.

If You Have Problems Installing the Driver

If you have problems installing the driver, it may be because of an installation error thatoccurred in a previous Windows 95 session. You might want to use the Windows 95 registryto resolve the problem.

♦♦ To use the Windows 95 registry to resolve installation problems:

1. Follow driver removal instructions in the section, “Removing or Reinstalling theDriver,” on page 13 to remove references to the driver.

2. Open the registry (REGEDIT.EXE).

3. Expand the registry tree to HKEY_LOCAL_MACHINE\Enum.

4. Look for, and delete the PlxEnum key.

5. Expand the registry tree to HKEY_LOCAL_MACHINE\Enum\PCI.

6. Look for, and delete the VEN_10B5&DEV_9050 key.

7. Close the registry.

8. Reboot the system to ensure the changes take effect.

If you did not find these registry keys, your problem may be somewhere else.

Note: Ensure the PCI 9050 configuration registers have the correct Vendor ID andDevice ID. The Device Manager associates the 9050RDK bus driver to the PCI device witha Vendor ID of 0x10B5 and a Device ID of 0x9050. You can use PLXMon95 to check theseregisters (refer to the section, “PCI Exploration Programs,” on page 15 for additionalinformation).

PCI 9050RDK User’s Guide PCI Exploration Programs


PCI Exploration Programs

PLX provides two applications to aid PCI engineering development and verification—PLXMon and PLXMon95. As the names imply, these programs are basically the same—oneruns under DOS, the other under Windows 95. Common aspects of these programs aredescribed using the name, “PLXMon”. Differences between the programs are clearly labeled.

PLXMon is a command-line style program that provides open access to all physical memoryand I/O on your computer. The PLXMon PCI commands enable you to

• Select any PCI device on the PCI bus

• Read and write the PCI configuration registers of the selected device

• Read and write PLX local registers (if the selected device is in the PLX familyof PCI devices)

• Read and write the EEPROM of a PLX device

and more.

PLXMon features include user-defined variables, macros and several unique commands thatare useful during product development.

PLXMon is described further in the PLXMon User’s Guide. If you are not familiar withPLXMon, it is recommended that you install it and become familiar with it.

Installing and Starting the Programs

Refer to the PLXMon User’s Guide for proper installation and startup of the PCI explorationprograms.

Selecting the PCI 9050 in the 9050RDK

When PLXMon starts, it registers all the PCI devices it can find, then selects the firstPLX device it registers. Use the dev command to see the PCI devices that PLXMon found,then verify the 9050 of the 9050RDK is selected. The PLX Vendor ID is “0x10B5”, and theDevice ID of the 9050 is “0x9050”. If your computer has other PLX devices in it, or if theVendor ID of the 9050 is being changed by the 9050RDK EEPROM, you may need to use theparameterized variation of the dev command to select the PCI 9050 (refer to the PLXMonUser’s Guide for information about this command).

Displaying the PCI 9050 PCI Configuration Registers

If necessary, select the 9050 of the 9050RDK (refer to the section, “Selecting the PCI 9050in the 9050RDK,” on page 15). Use the pcr command to display (and modify) thePCI configuration registers (refer to the PLXMon User’s Guide for information about thiscommand).

PCI Exploration Programs PCI 9050RDK User’s Guide


Displaying the PCI 9050 Local Configuration Registers

If necessary, select the 9050 of the 9050RDK (refer to the section, “Selecting the PCI 9050in the 9050RDK,” on page 15 for additional information). Use the lcr command to display(and modify) the local configuration registers (refer to the PLXMon User’s Guide forinformation about this command).

Accessing ISA Memory, I/O and 9050RDK Memory

First, display the PCI 9050 PCI Configuration Registers as described in the section,“Displaying the PCI 9050 PCI Configuration Registers,” on page 15.

Table 1-3 lists the four PCI Base Address for Local Address Space registers (PCR 0x18through 0x24) and the Interrupt Line register (PCR 0x3C).

Table 1-3. Notable PCI Configuration Registers

PCR PCI 9050 Name 9050RDK Chip Select

0x18 PCI Base Address for Local Address Space 0 ISA MEMCS

0x1C PCI Base Address for Local Address Space 1 ISA IOCS

0x20 PCI Base Address for Local Address Space 2 CSRAM

0x24 PCI Base Address for Local Address Space 3 CSROM

0x3C Interrupt Line (8 bit) —

When your computer starts, the PCI BIOS dynamically sets up these registers, based onvalues in various PCI 9050 configuration registers and the system resource allocations of yourcomputer. The local configuration register values are usually loaded from the 9050RDKEEPROM; otherwise, they are loaded with PCI 9050 reset values.

If everything is set up properly, you should be able to use the values in the PCI Base Addressfor Local Address Space registers (after stripping off any control bits) to activate the variouschip selects.

Use memory access commands, such as d, e, and m (display, enter and move) formemory-mapped addresses; and I/O commands such as i and o (input and output) forI/O-mapped addresses (refer to the PLXMon User’s Guide for information about thesecommands).

PCI 9050RDK User’s Guide PCI Exploration Programs


For example:

Perhaps you are interested in accessing I/O registers from an ISA card piggybacked on the9050RDK. You look at Table 1-3 and see that to activate the ISA IOCS line, you must readthe PCI Base Address for Local Address Space 1 Register (PCIBAR3; PCR 0x1C). You usethe pcr command, and find that the PCI BIOS has set PCIBAR3 to 0x0000E001. Bit zero isset, indicating the register refers to a PCI I/O address, and bits 1 and 0 should be treatedas zeros. Therefore, the base address for ISA IOCS is a PCI I/O port at 0xE000. The rangefor this address space can be determined from Local Address Space 1 Range Register(LAS1RR; LCR 0x04). Use the input and output commands to read and write theISA registers, using 0xE000 as the base address.

If you have problems with local-side addresses or chip selects, your local configurationregisters may be set wrong. Refer to the section, “Accessing EEPROM,” on page 18 forinformation about setting up local configuration registers, and to the sections, “SRAMSubsystem Register Settings” and “ISA Subsystem Register Settings,” on pages 30 and 34,respectively. Use the lcr command (refer to the PLXMon User’s Guide for informationabout this command) to examine and change these registers.

Any changes to the PCI configuration registers or the local configuration registers will be lostat reset or power-down unless you change the appropriate EEPROM registers. To modify theEEPROM, refer to the section, “Accessing EEPROM,” on page 18.

Note: The PCI Base Address for Local Address Space registers can be programmed to bereferenced by either I/O or memory PCI cycles. This means that you can program theISA IOCS (or any other chip select) to be memory or I/O mapped. Read the PCI 9050 datasheet regarding Local Address Space Range Registers for additional information.

PCI Exploration Programs PCI 9050RDK User’s Guide


Accessing EEPROM

Use the eep command to read and write EEPROM. The eep command works the sameas pcr and lcr. You can also read and write EEPROM with the re and we commands;however, they are less intuitive.

Writing to EEPROM is successful under most conditions; however, National NM93CS46(and compatible) EEPROMs may have special write-protection features enabled. It isrecommended that you verify the EEPROM values after writing them.

If you want to reload all EEPROM locations used by the PCI 9050, you can run a PLXMoncommand file that writes all EEPROM locations with 9050RDK factory defaults. The file,named RDK_EEP.MON, is on the PLX 9050RDK Distribution Disk. Use the read commandto read and execute the file, as in

read RDK_eep.mon

This command file contains several lines of eep commands. You may find it useful to make acopy of the file and modify it for your own needs, using any text editor (such as Notepad orWordPad).

It is possible to program the EEPROM with values that prevent your computer from booting.If this happens, and your EEPROM is in a socket, you can remove the EEPROM and restartyour computer. If you are careful, you can reinstall the EEPROM “hot,” then reprogram theEEPROM with less-offensive values.

Note: PLXMon and the EEPROM programming commands are discussed in the PLXMonUser’s Guide.

PCI 9050RDK User’s Guide Configuration Issues


Configuration Issues

This section describes issues associated with configuring the PCI 9050.

Configuring PCI 9050 Registers to Access an ISA Card

This section describes how to configure the PCI 9050 registers to access an ISA card, by wayof an example. The example applies to the comm card included in the kit, so it can easily betested. You can use PLXMon to quickly test the example and set up your own ISA card.

Of the four chip select lines (ISA MEMCS, ISA IOCS, RAMCS and ROMCS) onlyISA IOCS is used in the example. For reference, however, the PCI 9050 registers associatedwith all chip selects are listed in Table 1-4 through Table 1-7.

Table 1-4. PCI 9050 Registers Used for ISA MEMCS

PCI 9050 Registers Used for ISA MEMCS

PCI 9050 Register Name Mnemonic Register Offset

PCI Base Address for Local Address Space 0 PCIBAR2 PCR 0x18

Local Address Space 0 Range LAS0RR LCR 0x00

Local Address Space 0 Local Base Address (Remap) LAS0BA LCR 0x14

Local Address Space 0 Bus Region Descriptors LAS0BRD LCR 0x28

Chip Select 0 Base Address CS0BASE LCR 0x3C

Table 1-5. PCI 9050 Registers Used for ISA IOCS (Referenced in the Example)

PCI 9050 Registers Used for ISA IOCS (Referenced in the Example)


PCI Base Address for Local Address Space 1 PCIBAR3 PCR 0x1C



Local Address Space 1 Bus Region Descriptors LAS1BRD LCR 0x2C

Chip Select 1 Base Address CS1BASE LCR 0x40

Configuration Issues PCI 9050RDK User’s Guide


Table 1-6. PCI 9050 Registers Used for CSRAM

PCI 9050 Registers Used for CSRAM




Local Address Space 2 Local Base Address (Remap) LAS2BA LCR 0x1C



Table 1-7. PCI 9050 Registers Used for CSROM

PCI 9050 Registers Used for CSROM



Local Address Space 3 Range LAS3RR LCR 0x0C




The 9050RDK EEPROM, as configured at the factory, sets up the PCI 9050 to access thefull range of ISA I/O ports (0 to 0x3FF). PLX configured it this way so you can plug inany ISA board and start accessing its I/O ports, quickly and easily. Any individual board,however, requires only a fraction of the 0x400 port addresses. The following exampleconfigures the PCI 9050 for the small range of I/O ports required by a single channel ofan ISA comm card.

♦♦ Assume the following:

• The ISA comm card is setup as COM1 only (eight consecutive I/O ports—0x3F8 through 0x3FF)

• The ISA card will be accessed using PCI I/O cycles

• The chip select base address for ISA IOCS is arbitrarily chosen to be 0x03000000

• The PCI 9050 data sheet and this manual are available for easy reference (you willneed to reference Chapter 2, “PCI 9050RDK Hardware Manual”) and the PLXMonUser’s Guide)

PCI 9050RDK User’s Guide Configuration Issues


♦♦ Apply the following settings:

1. Set LAS1RR to 0xFFFFFFF9, because only three bits are required to select a uniqueregister on the comm card and the card will be referenced using PCI I/O cycles.

2. Set LAS1BA to 0x030003F9, because the COM1 base address is 0x3F8 and thechip select base address is 0x03000000.

3. Set CS1BASE to 0x030003FD, following the outline for local chip selects in thebus operation section of the PCI 9050 data sheet.

4. Set LAS1BRD. This setting must also be set properly; however, its values are notdiscussed here. Your best sources for configuring this register can be found in Chapter2, “PCI 9050RDK Hardware Manual,” and the PCI 9050 data sheet.

Note: Any changes to the local configuration registers will be lost when you power off yourcomputer unless you change the EEPROM. To modify the EEPROM, refer to the section,“Accessing EEPROM,” on page 18.

You can use this example as a basis for configuring the PCI 9050 registers that control theISA MEMCS line.

Configuring the PCI 9050 Local Interrupt Register

Refer to the PCI 9050 data sheet for a complete description of the PCI 9050 local interruptcontrol/status register (INTCSR). The 9050RDK ORs all ISA interrupts together, and thelogic level is inverted before entering the PCI 9050 interrupt 1 input (LINTI1). Therefore, thelocal interrupt 1 polarity (INTCSR bit 1) should be “0”. To enable interrupts, both the localinterrupt 1 enable (INTCSR bit 0) and PCI interrupt enable should be “1”.

Ensure the system BIOS of your computer is configuring interrupts correctly. The BIOSof some systems enable you to configure specific interrupts for PnP, ISA or PCI.

PCI Base-Class, Sub-Class, and Programming Interface

PCI Configuration Registers 0x0B, 0x0A, and 0x09 specify the PCI base-class, sub-class andprogramming interface, respectively. Refer to the latest PCI specifications for values that areappropriate to your project. You must change the proper EEPROM entries for any newvalues to be loaded into PCI 9050 registers at reset or power-up. To modify the EEPROM,refer to the section, “Accessing EEPROM,” on page 18.

Windows 95 Tips PCI 9050RDK User’s Guide


Windows 95 Tips

This section includes other useful tips that do not fit anywhere else.

Often, you will not want to waste time booting Windows 95—you can use DOS programs,such as the DOS version of PLXMon.

♦♦ To make your Windows 95 machine boot DOS first:

1. Find the MSDOS.SYS file on your system (usually located under the root, C:\).

2. Create a backup copy of the MSDOS.SYS file (for example, MSDOS.BAK) beforeyou edit it.

3. Remove the hidden, read-only, and system attributes from the file.

4. Open the file using a standard text editor (such as Notepad or WordPad).

5. Modify the line “BootGUI=1” to “BootGUI=0”.

6. Save and close the file.

7. Optional: Replace the attributes of the file.

8. Reboot your computer.

Your computer will now boot DOS first. You can type win at the DOS prompt to bootWindows 95 at any time.

♦♦ To make your Windows 95 machine boot Windows 95 first:

1. Rename the MSDOS.SYS file you created in the previous process (for example, renamethe file to MSDOS.DOS).

2. Rename the MSDOS.BAK file you created in the previous process to MSDOS.SYS.

3. Reboot your computer.

PCI 9050RDK User’s Guide Troubleshooting


Troubleshooting

The most common problems encountered in an otherwise working configuration are

• 9050RDK card jumpers set incorrectly

• PCI 9050 local configuration registers set incorrectly

There are only a few jumper settings on the 9050RDK card, so it is probably easiest to checkthe jumper settings of the 9050RDK documented in Chapter 2, “PCI 9050RDK HardwareManual.”

The EEPROM values loaded into the PCI 9050 at reset time are “factory set” for runninga piggybacked ISA card. These values may have changed or are not appropriate for yourproject. The first step is to install the PLX PCI exploration programs (refer to the section,“PCI Exploration Programs,” on page 15). These programs are useful in tracking down andcorrecting PCI 9050 local configuration registers and EEPROM values. Chapter 2,“PCI 9050RDK Hardware Manual,” provides guidelines for correct local configurationregister settings. The section, “Accessing EEPROM,” on page 18 also includes registerconfiguration tips.

Other troubleshooting information can be found in the section, “If You Have ProblemsInstalling the Driver,” on page 14.

Troubleshooting PCI 9050RDK User’s Guide


Notes:


Chapter 2

PCI 9050RDK Hardware ManualThis chapter describes each subsystem found on the RDK and provides suggestions for usingthe tools and circuitry included as a starting point for a new design.

The RDK is designed as both a demonstration board and a launch pad for new designs.The hardware consists of the following:

• PCI slot interface

• PCI 9050 bus target interface chip

• SRAM system to demonstrate PCI memory accesses

• ISA slot and controller to facilitate migration of existing designs to a PCI platform

• Daughter-card connector, to which developers can attach new circuit board designs

• Prototyping space and headers, for testing and benchtop experimentation

PCI Interface PCI 9050RDK Hardware Manual


PCI Interface

The PCI 9050 is fully compliant with version 2.1 of the PCI specification. The RDK isdesigned to plug directly into a PCI expansion slot. As the 9050 is intended as a target only,all expansion slot signals relating to bus mastering are appropriately terminated.

The two halves of the PCI slot connector are labeled J1 and J2. Please refer to the schematicsprovided in Chapter 3, “PCI 9050RDK Schematics,” for specifics regarding connectionsto the PCI slot.

PCI 9050 Target Interface Chip

The PCI 9050 IC represents the core of the RDK. The 9050 is responsible for translatingthe PCI bus cycles to the appropriate local bus cycles to properly interface to theRDK subsystems. Some of the relevant features of this part are

• PCI Specification 2.1 compliance

• Low cost

• Five remappable local address spaces and four internally decoded chip selects

• Bidirectional FIFO for zero wait state bursts

• Performs to the PCI maximum 132 MB/sec transfer rate

• Supports a 32-, 16-, or 8-bit wide, multiplexed or nonmultiplexed local bus

• Allows the local bus to operate asynchronously to the PCI clock

• Performs Big Endian/Little Endian conversion (if required by the local bus)

• Supports local bus clocks up to 40 MHz

• Serial EEPROM interface for storage of configuration information

Discussion here is limited to board-level configuration concerns and certain aspectsof the 9050 that are directly applicable to the RDK. For a full discussion of chipoperation, refer to the PCI 9050 data sheet, available from PLX and the PLXwebsite (http://www.plxtech.com).

PCI 9050RDK Hardware Manual PCI 9050 Target Interface Chip


Chip Operating Modes

Test mode—The JP3 jumper places the 9050 chip into Factory Test mode (referto Table 2-1). This jumper should be removed for normal operation.

Table 2-1. Test Mode Jumper Settings

JP3 in Place Effect on Operation

Yes Test mode enabled

*No Test mode disabled

* Default loading

Local Bus Multiplex mode—The JP1 and JP2 jumpers determine whether the local busis operating in Multiplexed or Nonmultiplexed mode (refer to Table 2-2). When operatingin Multiplexed mode, the address and data paths share the same IC pins, whereas whenoperating in Nonmultiplexed mode, the address and data paths operate independently. Anysubsystems accessed must share the same multiplex setting. The SRAM and ISA subsystemsare defined as nonmultiplexed; however, developers are free to use Multiplex mode whenaccessing custom circuitry through the daughter-card connector or prototype areas.

Table 2-2. Mux Mode Jumper Settings

JP1 in Place JP2 in Place Effect on Operation

No No Invalid

No Yes Multiplexed operation

*Yes *No Nonmultiplexed operation

Yes Yes Invalid

* Default loading

Local Bus Clock

The local bus clock may be set to any frequency up to 40 MHz. Several clock signals aremade easily available—8 MHz for ISA operation, 33 MHz for fast access to the staticRAM, and a buffered version of the PCI clock. An additional user-selectable clock may beconnected to post 1 of header J10. Note that there are two methods available for routing thesesignals to the local clock input of the 9050—two pin header jumpers (on header J10), forquick selection, and pads for 0 Ω resistors for a more dependable connection (referto Table 2-3).

See text for defaults.

Caution: Ensure that only one method is used, as damage may result if clock signals areshorted together.

PCI 9050 Target Interface Chip PCI 9050RDK Hardware Manual


Table 2-3. Clock Selection

Local Clock Signal J10 Jumper Position Resistor Location

BCLK or PCI Clock Jump Pins 1 - 2 R28

33 MHz Jump Pins 3 - 4 R27



Note: R28, R27, R25, & R26 are not installed on the 9050RDK board

Local Bus Interrupts

The PCI 9050 provides two inputs for two local bus interrupts. When using the ISA circuitryon the RDK, both interrupts are used for handling ISA events. LINTi1 is used for theISA IRQ interrupts, and LINTi2 is used to service ISA error conditions. Jumpers are providedon the J10 header (refer to Table 2-4) to allow routing of interrupts from custom circuitrylocated on the daughter-card connector, or tied directly to the posts of J10.

Table 2-4. Interrupt Routing

J10 Jumper Position PCI 9050 Input System Source

*Jump Pins 9 - 10 LINTi1 ISA IRQ Interrupt

Jump Pins 11 - 12 LINTi1 Custom Interrupt 1

*Jump Pins 13 - 14 LINTi2 ISA Bus Error Signal

Jump Pins 15 - 16 LINTi2 Custom Interrupt 2

* Default loading

PCI 9050RDK Hardware Manual PCI 9050 Target Interface Chip


Local Bus Chip Selects

The PCI 9050 will internally decode up to four chip selects, set at user-defined ranges.Jumpers on the J14 header are provided to route these chip selects to the circuitry on theRDK as described in Table 2-5. The chip selects are also routed to the daughter-cardconnector for use in user designs, or may be tapped from the header posts of J14 to routeto the prototyping area.

Note: When used for purposes other than the standard circuitry, remove the appropriatejumper from the J14 header to prevent conflict. Chip selects CS2 and CS3 may also beconfigured as user definable I/O pins; in this case also, remove the appropriate jumper.

All loaded by default.

Note: Pins 3 –4, 7 –8, 11 –12, 15 – 16 are not used.

Table 2-5. Local Bus Chip Selects

J14 Jumper Position PCI 9050 Signal RDK System Usage

Jump Pins 1 - 2 CS0# (ISA) MEMCS#

Jump Pins 5 - 6 CS1# (ISA) IOCS#

Jump Pins 9 - 10 CS2#/USER2 CSRAM#

Jump Pins 13 -14 CS3#/USER3 CSROM#

SRAM Subsystem PCI 9050RDK Hardware Manual


SRAM Subsystem

The following sections discuss the SRAM subsystem architecture and register settings.

Subsystem Architecture

There is a small amount of static RAM supplied on the RDK to demonstrate memory accessesfrom the PCI bus. The memory is organized to use the full 32 bit local bus, and is 32k longwords deep. The memory is accessed using CSRAM, and the proper jumper must be in place,as indicated in Table 2-5. The RAM system operates at 33 MHz and is capable of supportingzero wait state read and write accesses.

There are five gates added to use the Burst mode capabilities of the 9050. Burst modeprovides a single address cycle, followed by many data cycles to what are understood to besuccessive addresses, thereby deleting the additional address cycles and increasing throughput.In new designs where only single accesses are to be supported, the gates can be eliminatedand the 9050 interface to the static RAM would be entirely glueless.

SRAM Subsystem Register Settings

To access the static RAM, choose one of the four mappable address spaces. Table 2-6through Table 2-9 provide examples as to how to set up the PCI 9050 local registers.

Note: All four registers should reference a consistent address space, and the base addressof the local memory space, and the base address of the chip select, although configurable,should match.

Table 2-6. Local Address Space Range Register (LAS2RR)

Bit Field Field DescriptionSetto Value Setting Indicates

0 Memory SpaceIndicator

0h SRAM is memory mapped

2:1 Mapping location 0h Locate anywhere in PCI space.

3 Prefetch support 0h Prefetching from SRAM is acceptable

27:4 Decode range FFE0000h Address lines 27:17 are used to decode

31:28 Unused 0h Must be set to zero

PCI 9050RDK Hardware Manual SRAM Subsystem


Table 2-7. Local Address Space Base Address Register (LAS2BA)


0 Space Enable 1h Enable decoding of this address space

1 Unused 0h Must be set to zero


27:4 Remap address 1000000h Arbitrary, but must match chip select base


Table 2-8. Local Address Space Region Descriptor Register (LAS2BRD)


0 Bursting Enable 1h Enable SRAM bursting

1 Ready Input Enable 0h Use internal wait state generator

2 BTERM Enable 1h Disable BTERM input

4:3 Prefetch Count 0h Prefetch 16 long words

5 Prefetch Count Enable 0h Enable prefetching

10:6 NRAD Wait States 0h No address to data wait states

12:11 NRDD Wait States 0h Zero wait state on burst accesses

14:13 NXDA Wait States 0h Zero wait state from data to address

19:15 NWAD Wait States 0h No address to data wait states

21:20 NWDD Wait States 0h Zero wait state for burst accesses

23:22 Bus Width 2h 32 bit local bus to SRAM

24 Endian Order 0h Little Endian (adjust for system)

25 Big Endian Byte Lane 0h 32 bit bus

27:26 Read Strobe Delay 0h Assert RD immediately

29:28 Write Strobe Delay 0h Assert WR immediately

31:30 Write Cycle Hold 0h No need for additional wait states

Table 2-9. Chip Select Base Register (CS2BASE)


0 Chip Select Enable 1h Enable this chip select


27:2 Local Base of ChipSelect

1010000h Must match the address space


ISA Subsystem PCI 9050RDK Hardware Manual


ISA Subsystem

One of the principle uses of the PCI 9050 will be to upgrade existing ISA bus designs to PCI.A designer can get a head start in this process by simply plugging their ISA card into the slotprovided on the RDK. This allows the engineer to get a feel for the operation of the 9050and the PCI bus, and provides a development tool to begin software driver development.The PCI 9050, as well as additional ISA conversion logic on the RDK, convert the ISA buscycles to PCI and vice versa.

The ISA bus interface is a compilation of several different card styles and backward-compatibility issues. The RDK is designed to support a wide variety of ISA cards operatingas slaves to the bus. The heart of the ISA interface is the PLD, which houses a state machineto provide the requisite signals to the card and responds to signals returned for bus sizing andwait state control.

As only one slot is needed for development, the designer’s driver software can indicate to thestate machine whether the card is an 8-bit or 16-bit device. This is done by using one of the9050 user controlled I/O pins. The PLD can then be expected to behave as if the card isplugged into an ISA motherboard.

The PCI 9050 provides four independent chip selects to assist in address decoding. Twoof these chip selects are used by the state machine to distinguish between memory andI/O accesses to the ISA card so that the proper timings can be observed.

Bus Cycle Conversion

The ISA Controller is embedded into an AMD MACH210 PLD. The goal of thestate machine is to converse between the PCI 9050 IC and an ISA expansion card bymimicking the behavior of an ISA motherboard as closely as possible. The controller isdesigned to handle ISA slave accesses only, and does not provide for ISA masters, DMA,or refresh cycles.

The controller is driven at twice the ISA bus frequency, and consists of eight, two-phasestates. Each state represents one full cycle of the ISA clock, with Phase 0 correspondingto a logic high voltage of the clock, and Phase 1 corresponding to a logic low. Alternatively,the controller could be viewed as a 16-state machine, but the naming convention is chosento match the state of the system as viewed from the ISA perspective.

Three distinct bus cycles are supported:

• 16 bit memory accesses

• 16 bit I/O accesses

• 8-bit accesses (of either type)

PCI 9050RDK Hardware Manual ISA Subsystem


These cycles may be shortened or lengthened by the expansion card within the limitsmaintained by the standard ISA motherboard. Additional control is provided by the PCI 9050in the form of two chip selects and one user I/O pin. One chip select is intended to be usedto indicate an I/O access (referred to as “IOCS~”) and the other indicates memory accesses(referred to as “MEMCS~”). The user I/O pin indicates whether the card is an 8-bit or 16-bitdevice (referred to as “8BIT”).

Two additional states have been added to the standard ISA cycle to support the timingrequirements of that bus. There is a leading wait state that supports the split addressing,or address pipelining of the ISA bus signals LA[23:17], and there is a trailing state thatmaintains the proper data hold times of the bus. For back-to-back accesses, these two statesare merged, resulting in only one additional state to minimize overhead.

Following the leading bus cycle, the standard ISA addressing cycle is performed, and BALEand ~SBHE are asserted as expected. The chip selects, address, and ~M16/~IO16 aredecoded to generate the proper ~IORD, ~IOWR, ~MEMRD, ~MEMWR, ~SMRD, and~SMWR commands to the slot.

Use of ~NOWS and CHRDY are supported to shorten or extend the bus cycles to theISA card, and wait states are added or removed, as required. A data latch is presentto provide the data hold times expected by an ISA device after the final data cycle.

Upon completion of the ISA access, ~LRDYI is asserted to the 9050, and the local bus cycleis concluded.

Several signals are driven locally, regardless of the selection state:

• RESET—The ISA reset signal is opposite in sense to the 9050 local bus reset.

• ISAA0 and ISAA1—These signals are derived from the 9050 local bus byte enables,depending on whether the addressed device is 8 or 16 bits.

• SBHE—This signal indicates to the ISA device whether the upper 8 bits of a 16 bit databus are being accessed.

• DATARW—This signal determines the direction of the ISA bus data transceiver.

• G1MB—This signal is used internally to indicate whether the current access is above the1 MB boundary. This signal is not driven externally.



ISA Subsystem Register Settings

Table 2-10 through Table 2-17 list the ISA subsystem register settings:

Table 2-10. Local Address Space Range Register (Memory) (LAS0RR)



0h I/O and Memory are Memory Mapped

2:1 Mapping Location 0h Locate anywhere in PCI space

3 Prefetch Support 0h Do not prefetch from ISA

27:4 Decode Range F000000h Address lines 27:24 are used to decode


Table 2-11. Local Address Space Range Register (I/O) (LAS1RR)



0h I/O and Memory are Memory Mapped

2:1 Mapping Location 0h Locate anywhere in PCI space

3 Prefetch Support 0h Do not prefetch from ISA

27:4 Decode Range F000000h Address lines 27:24 are used to decode


Table 2-12. Local Address Space Base Register (Memory) (LAS0BA)





27:4 Remap Address 2000000h Arbitrary, but must match chip select base




Table 2-13. Local Address Space Base Register (I/O) (LAS1BA)





27:4 Remap Address 3000000h Arbitrary, but must match chip select base


Table 2-14. Local Address Space Region Descriptor (Memory) (LAS0BRD)


0 Bursting Enable 0h No ISA bursting

1 Ready Input Enable 1h Use external LRDY indicator


4:3 Prefetch Count 0h No prefetching

5 Prefetch Count Enable 0h No prefetching

10:6 NRAD Wait States 1h One address to data wait state

12:11 NRDD Wait States 0h No bursting

14:13 NXDA Wait States 0h Data to address controlled by LRDY

19:15 NWAD Wait States 1h One address to data wait state

21:20 NWDD Wait States 0h No bursting

23:22 Bus Width 1h 16 bit (according to ISA card)

24 Endian Order 0h Little Endian

25 Big Endian Byte Lane 0h Use lower data path



31:30 Write Cycle Hold 1h One wait state on writes



Table 2-15. Local Address Space Region Descriptor (I/O) (LAS1BRD)


0 Bursting Enable 0h No ISA bursting

1 Ready Input Enable 1h Use external LRDY indicator


4:3 Prefetch Count 0h No prefetching

5 Prefetch Count Enable 0h No prefetching

10:6 NRAD Wait States 1h One address to data wait state

12:11 NRDD Wait States 0h No bursting

14:13 NXDA Wait States 0h Data to address controlled by LRDY

19:15 NWAD Wait States 1h One address to data wait state

21:20 NWDD Wait States 0h No bursting

23:22 Bus Width 0h 8bit (according to ISA card)

24 Endian Order 0h Little Endian

25 Big Endian Byte Lane 0h Use lower data path



31:30 Write Cycle Hold 1h One wait state on writes

Table 2-16. Memory Chip Select Base Register (CS0BASE)




27:2 Local Base ofChip Select



Table 2-17. I/O Chip Select Base Register (CS1BASE)




27:2 Local Base ofChip Select





Handling of ISA Interrupts

ISA interrupts are supported by a cascade of OR gates that allow the ISA interruptsto generate a local bus interrupt to the 9050. If the ISA slave uses multiple interrupts, caremust be taken in the design of the PCI driver software to account for this, especially in caseswhere the interrupts may occur simultaneously. The ISA ~CHCHK error signal is routedto the second 9050 local bus interrupt to allow handling of these conditions.

ISA Features Not Supported on the RDK

The RDK supports a wide variety of ISA expansion cards; however, it does not supportISA bus masters or boards requiring DMA support. For ISA designs that make use of thesefeatures, PLX offers a range of PCI bridge chips that allow migration to the PCI bus.

The RDK does not provide refresh cycles to the ISA slot. If this is necessary for supportof a specific card, the designer may make use of the prototyping area of the RDK to createthe needed timing logic and to integrate into the existing ISA support circuitry.

Sixteen-bit accesses to an 8-bit peripheral are not supported and must be managed by thedriver firmware.

Moving to a New Design

The ISA implementation of the 9050RDK is designed to be as general as possible to supporta wide range of legacy cards. Depending on the design, most or all of this ISA conversionlogic can be eliminated when doing the actual PCI development. This section calls out severalpoints of analysis for reducing the required hardware.

Determine what interrupt sources are required and route them directly to the 9050 localinterrupt lines. The OR/NAND gates used for interrupt routing (U15, U17 and U18) can thenbe removed. If there is no need to support a CHCHK-type error signal, this interrupt sourcecan be removed. If the design can benefit from multiple interrupt sources, both 9050 inputlines may be used.

Note: The polarity of the interrupt lines is programmable.

Note: The address buffers (U11 and U12) are not required for the ISA design, but are presentto reduce the loading on these buses, and to allow the SRAM to function as fast a possible.Check the fanout of the new design, as the drive capability of the 9050 is probably sufficientin most cases.

Check the address setup and data hold requirements of the resident hardware. If the designuses an ASIC, or standard ICs with an integrated ISA interface, review the specifications.Many parts can tolerate, but do not require the setup and hold times provided. The leadingand trailing bus wait state cycles are more likely a limitation of the ISA bus than a limitationof the hardware on the card, and can probably be eliminated as the design is migrated to thePCI bus.



The data latch (U16) can be removed if the data hold times are satisfied by the standard localbus cycle. If the design requires longer data hold times, check the PCI 9050 documentationto determine whether the programmable wait state generator can save the extra component.

Check the clocking requirements of the design. If there is no need for the 14.31818 MHzclock, you can eliminate its crystal (Y2). If the various strobes and timing signals of the 9050are sufficient to synchronize the bus cycles, the 8 MHz and 16 MHz clocks (Y1 and U14) mayalso be removed. Check the 9050 documentation, as many of the bus control signals haveprogrammable timings that may ease this interface considerably. If the full PLD state machineis to be used, a 16 MHz standard is still required. The 9050 provides a buffered version of thePCI bus clock, which may be used by the local bus. Keep in mind that the PCI specificationallows this clock to vary in frequency dynamically, from 0 to 33 MHz. If the performanceof the local bus hardware is capable of being scaled, or if it can be safely assumed that thePCI clock is fixed, this buffered clock can save the complications of multiple clock sources.

For many designs, the intermediate conversion to ISA can be eliminated entirely, and the PLD(U15) removed with it. This is the ideal solution, and is very likely, given the flexibility in the9050 local bus cycles. For designs where this is not possible (such as ASICs or standard ICsthat expect an ISA interface), the state machine equations are available to make thisintegration straightforward. In cases where the ISA interface is required, analysis may revealthat only a subset of the functionality present in the state machine is required, which wouldallow a reduction of the equation set, and the use of a more compact PLD. Obviousopportunities for economy include the knowledge of the bus width at design time, knowingwhether the design is to operate in Memory or I/O mode, and in many cases, knowing howmany wait states are required for each access. Selecting these parameters allows much of theflexibility to be removed from the PLD, and much of the logic can then be removed along withit.

PCI 9050RDK Hardware Manual Daughter-Card Connector


Daughter-Card Connector

The RDK provides several facilities for building up new designs. One of these is a daughter-card connector (J3), located midway down the board. This connection point breaks out mostof the 9050 local bus connections for use on a plug in PC board module. Table 2-18 describesthe pinout of J3.

Note: Use of a daughter card affects the jumper settings. Other functions of the RDK mayrequire disabling to accommodate the added PC card.

Table 2-18. Daughter-Card Connector (J3)

Pin # Function Pin # Function Pin # Function Pin # Function

1 ADS# 26 BD29 51 n.c. 76 LA8

2 GND 27 BD28 52 n.c. 77 LA7

3 LCLK 28 BD27 53 n.c. 78 LA6

4 GND 29 BD26 54 n.c. 79 LA5

5 BLAST# 30 BD25 55 LA27 80 LA4

6 USER1 31 BD24 56 LA26 81 LA3

7 LW/R 32 GND 57 LA25 82 LA2

8 GND 33 BD23 58 LA24 83 5V

9 LRDY# 34 BD22 59 5V 84 BD7

10 LRESET# 35 BD21 60 LA23 85 BD6

11 LBE0# 36 BD20 61 LA22 86 BD5

12 LBE1# 37 BD19 62 LA21 87 BD4

13 LBE2# 38 BD18 63 LA20 88 BD3

14 LBE3# 39 BD17 64 LA19 89 BD2

15 USER2 40 BD16 65 LA18 90 BD1

16 GND 41 GND 66 LA17 91 BD0

17 XINT1 42 BD15 67 LA16 92 GND

18 XINT2 43 BD14 68 5V 93 5V

19 n.c. 44 BD13 69 LA15 94 LHOLDA

20 n.c. 45 BD12 70 LA14 95 LHOLD

21 USER0 46 BD11 71 LA13 96 GND

22 GND 47 BD10 72 LA12 97 n.c.

23 5v 48 BD9 73 LA11 98 n.c.

24 BD31 49 BD8 74 LA10 99 12V

25 BD30 50 GND 75 LA9 100 -12V

Test Headers and Prototype Area PCI 9050RDK Hardware Manual


Test Headers and Prototype Area

In addition to the daughter-card connector, the RDK provides a series of open header posts(J8 through J11) and a large prototyping area. The combination of these two features are idealfor signal monitoring, fast benchtop prototyping, and small simple circuits where formal PCcard development is not practical. Local bus signals may be accessed by wiring directly to theposts of these and other headers on the board, and routing directly to the prototype area.Again, it may be necessary to disable some of the native circuitry of the RDK to preventresource contention.

Table 2-19 through Table 2-24 describe the pinout of the test headers.

Note: The odd numbered pins on each of these connectors is connected to the internal groundplane.

Table 2-19. Pinoutfor J5

Pin # Function

4 LBE0#

6 LBE1#

8 BA2

10 BA3

12 BA4

14 BA5

16 BA6

18 BA7

20 BA8

22 BA9

24 BA10

26 BA11

28 BA12

30 BA13

32 BA14

34 BA15

36 GND

38 LBE0#


Pin # Function

4 BA16

6 BA17

8 BA18

10 BA19

12 BA20

14 BA21

16 BA22

18 BA23

20 BA24

22 BA25

24 BA26

26 BA27

28 LBE0#

30 LBE1#

32 LBE2#

34 LBE3#

36 GND

38 BA16


Pin # Function

4 BD0

6 BD1

8 BD2

10 BD3

12 BD4

14 BD5

16 BD6

18 BD7

20 BD8

22 BD9

24 BD10

26 BD11

28 BD12

30 BD13

32 BD14

34 BD15

36 GND

38 BD0

PCI 9050RDK Hardware Manual Test Headers and Prototype Area



Pin # Function

4 BD16

6 BD17

8 BD18

10 BD19

12 BD20

14 BD21

16 BD22

18 BD23

20 BD24

22 BD25

24 BD26

26 BD27

28 BD28

30 BD29

32 BD30

34 BD31

36 GND

38 BD16


Pin # Function

4 LCLK

6 LRESET#

8 ADS#

10 ALE

12 LW/R

14 BLAST

16 LRDYI#

18 BTERM#

20 CS0#

22 CS1#

24 RD#

26 WR#

28 n.c.

30 n.c.

32 n.c.

34 n.c.

36 GND

38 LCLK


Pin # Function

4 LINTi1

6 LINTi2

8 LHOLD

10 LHOLDA

12 USER0

14 USER1

16 USER2

18 USER3

20 n.c.

22 n.c.

24 n.c.

26 n.c.

28 n.c.

30 n.c.

32 n.c.

34 n.c.

36 GND

38 LINTi1

Additional Development Resources Provided by PLX PCI 9050RDK Hardware Manual


Additional Development Resources Providedby PLX

In addition to a broad family of PCI bridge chip products, PLX Technology provides a varietyof resources, including evaluation boards and software, to simplify the development of PCIboards and systems. For an index of resources, contact PLX directly or through our website athttp://www.plxtech.com.


Chapter 3

PCI 9050RDK SchematicsThis chapter provides schematics of the PCI 9050RDK for easy reference.

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97

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144

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289

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D28

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27A

D26

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25A

D24

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23A

D22

AD

21A

D20

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19A

D18

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17A

D16

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15A

D14

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9

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31A

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CLK

1

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3,9

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

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Num

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Rev

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of

BD

0B

D1

BD

2B

D3

BD

4B

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BD

6B

D7

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LA3

LA4

LA5

LA6

BD

31LA

7B

D30

LA8

BD

29LA

9B

D28

LA10

BD

27LA

11B

D26

LA12

BD

25LA

13B

D24

LA14

LA15

BD

23B

D22

LA16

BD

21LA

17B

D20

LA18

BD

19LA

19B

D18

LA20

BD

17LA

21B

D16

LA22

LA23

BD

15B

D14

LA24

BD

13LA

25B

D12

LA26

BD

11LA

27B

D10

BD

9B

D8

5V5V

+12V

-12V

5V+1

2V-1

2V

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ON

N

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SET

10BE

011

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12BE

213

BE3

14S

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15G

ND

16IR

Q1

17IR

Q0

18B

R19

BG20

EX

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D21

GN

D22

5V23

D31

24D

3025

D29

26D

2827

D27

28D

2629

D25

30D

2431

GN

D32

D23

33D

2234

D21

35D

2036

D19

37D

1838

D17

39D

1640

GN

D41

D15

42D

1443

D13

44D

1245

D11

46D

1047

D9

48D

849

GN

D50

A31

51A

3052

A29

53A

2854

A27

55A

2656

A25

57A

2458

5V59

A23

60A

2261

A21

62A

2063

A19

64A

1865

A17

66A

1667

5V68

A15

69A

1470

A13

71A

1272

A11

73A

1074

A9

75A

876

A7

77A

678

A5

79A

480

A3

81A

282

5V83

D7

84D

685

D5

86D

487

D3

88D

289

D1

90D

091

GN

D92

5V93

NC

94N

C95

GN

D96

SD

A97

SC

L98

12V

99-1

2V10

0A

DS

#1,

6,7,

8

LCLK

1,4,

6,7 B

LAS

T#

1,6,

8

LW/R

#1,

6,7,

8

SQ

_LR

DY

#1

LRE

SE

T#

1,6,

7LB

E0#

1,4,

6,7

LBE

1#1,

4,6,

7LB

E2#

1,4,

6LB

E3#

1,4,

6,7

XIN

T17

XIN

T27

LHO

LD1,

6LH

OLD

A1,

6U

SE

R1/

LLO

CK

#1,

6,7

US

ER

0/W

AIT

O#

6,7

US

ER

2/C

S2#

1,6,

7,8,

9

LA[2

7..2

]1,

4,5

BD

[31.

.0]

1,4,

6,8

5V1,

2,4,

5,7,

8,9 12

V4,

9-1

2V2,

9

E E

D D

C C

B B

A A

EE

DD

CC

BB

AA

PC

I 90

50R

DK

4

SR

AM

& E

EP

RO

M

49

Thur

sda y

, Ja

nuar

y 08

, 199

8

Titl

e

Siz

eD

ocu

me

nt

Nu

mb

er

Rev

Dat

e:S

he

et

of

LA2

LA3

LA4

LA5

LA6

LA7

LA8

LA9

LA10

LA11

LA12

LA13

LA14

LA15

LA16

LA17

BD

15

BD

1LA3

LA4

BD

23

BD

4

BD

2

LA9

LA2

LA15

LA7

BD

5LA

8

LA3

BD

4

LA13

LA12

LA14

BD

6

BD

31

BD

13

LA3

BD

27

LA12

LA2

LA2

BD

6

LA16

LA14

LA10

LA12

BD

14B

D21

BD

1

LA15

BD

12

BD

5

LA16

LA7

LA3

BD

19B

D18

LA6

BD

9B

D8

LA8

BD

29

BD

3

LA11

LA6

LA13

LA8

LA11

BD

2

BD

28

BD

22

LA15

BD

0

BD

11B

D26

LA16

BD

7

LA12

LA7

LA14

LA5

LA10

LA13

BD

24B

D16

LA11

BD

20

LA9

LA5

BD

17

LA15

BD

10

LA9

LA6

LA6

LA14

BD

25

LA10

LA11

LA7

LA4

LA5

LA2

LA5

BD

0

BD

7

LA10

LA4

BD

3LA16

LA9

BD

30

LA4

LA13

LA8

5V12V

5V

5V

U10

28F0

2090

NS

EC

A01

2A1

11

A21

0

A39

A48

A57

A66

A75

A82

7

A92

6A

102

3A

112

5

A12

4

A13

28

A14

29

A15

3

A16

2A

173

0

CE

22

OE

24

WE

31

VPP1

I/O0

13

I/O1

14

I/O2

15

I/O3

17

I/O4

18

I/O5

19

I/O6

20

I/O7

21

VCC32

GND 16

U9A

74A

C32

1 23

14 7

U8B

74A

C32

4 56

U8C

74A

C32

9

10

8

U8D

74A

C32

12

13

11

U8A

74A

C32

1 23

14 7

U7 S

RA

M 3

2KX

8

A01

0

A19

A28

A37

A46

A55

A64

A73

A82

5

A92

4A

102

1

A11

23

A12

2A

132

6A

141

CS

20

OE

22

WE

27

I/O0

11

I/O1

12

I/O2

13

I/O3

15

I/O4

16

I/O5

17

I/O6

18

I/O7

19

U6 S

RA

M 3

2KX

8

A01

0

A19

A28

A37

A46

A55

A64

A73

A82

5

A92

4A

102

1

A11

23

A12

2A

132

6A

141

CS

20

OE

22

WE

27

I/O0

11

I/O1

12

I/O2

13

I/O3

15

I/O4

16

I/O5

17

I/O6

18

I/O7

19

U5 S

RA

M 3

2KX

8

A01

0

A19

A28

A37

A46

A55

A64

A73

A82

5

A92

4A

102

1

A11

23

A12

2A

132

6A

141

CS

20

OE

22

WE

27

I/O0

11

I/O1

12

I/O2

13

I/O3

15

I/O4

16

I/O5

17

I/O6

18

I/O7

19

U4 S

RA

M 3

2KX

8

A01

0

A19

A28

A37

A46

A55

A64

A73

A82

5

A92

4A

102

1

A11

23

A12

2A

132

6A

141

CS

20

OE

22

WE

27

I/O0

11

I/O1

12

I/O2

13

I/O3

15

I/O4

16

I/O5

17

I/O6

18

I/O7

19

RD

#1,

6,8

WR

#1,

6,8LA

[27.

.2]

1,3,

5

LBE

0#1,

3,6,

7LB

E1#

1,3,

6,7 C

SR

OM

#7,

9

BD

[7..0

]1,

3,6,

8

BD

[31.

.0]

1,3,

6,8

LA[2

7..2

]1,

3,5

RD

#1,

6,8

CS

RA

M#

7,9

LBE

0#1,

3,6,

7

LBE

1#1,

3,6,

7

LBE

2#1,

3,6

WR

#1,

6,8

LCLK

1,3,

6,7

LBE

3#1,

3,6,

7

11

22

33

44

55

66

77

88

AA

BB

CC

DD

PC

I 9050RD

K4

AD

DR

Latch, b ypass CA

Ps

59

Thursda y, January 08, 1998

Title

Size

Docum

ent Num

berR

ev

Date:

Sheet

of

LA16

LA14

BA

20B

A3

BA

9

LA17

LA11

BA

22

BA

24

LA22

LA12

LA6

BA

5

LA18

LA10

LA26

BA

16B

A15

BA

12B

A11

BA

26LA

9

BA

19

LA7

LA13

LA25

BA

18

LA20

BA

8

LA19

LA2

LA3

LA15

BA

27B

A10

LA27

BA

4LA

4

LA24

BA

13

BA

6

LA8

BA

17

BA

7B

A23

BA

14

BA

25

LA5

BA

2

LA23

BA

21LA

21

5V5V

5V5V

5V5V

5V

VC

CV

DD

+5V+5

+12V12V

5V

VS

S

12V5V

-12V

U11

16244

A0

47A

146

A2

44A

343

A4

41A

540

A6

38A

737

A8

36A

935

A10

33A

1132

A12

30A

1329

A14

27A

1526

Q0

2Q

13

Q2

5Q

36

Q4

8Q

59

Q6

11Q

712

Q8

13Q

914

Q10

16Q

1117

Q12

19Q

1320

Q14

22Q

1523

OE

11

OE

248

OE

325

OE

424

+ 7+ 18+ 31+ 42

-4

-10

-15

-21

-28

-34

-39

-45

C1

.1uF

C2

.1uFC

3.1uF

C4

.1uFC

5.1uF

C6

.1uFC

7.1uF

C8

.1uFC

10.1uF

C11

.1uF

C23

.1uF

C24

.1uFC

25.1uF

C26

.1uFC

27.1uF

C28

.1uFC

29.1uF

C30

.1uFC

31.1uF

C32

.1uF

C33

.1uF

C12

.1uF

C13

.1uFC

14.1uF

C15

.1uFC

16.1uF

C17

.1uFC

18.1uF

C19

.1uFC

20.1uF

C21

.1uF

C22

.1uF

C34

.1uF

C35

.1uFC

36.1uF

C37

.1uFC

38.1uF

C39

.1uFC

40.1uF

C41

.1uFC

42.1uF

C43

.1uF

C44

.1uF

C9

.1uF

C45

22uFC

4622uF

RN

2

10K0

CO

M1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

U12

16244

A0

47A

146

A2

44A

343

A4

41A

540

A6

38A

737

A8

36A

935

A10

33A

1132

A12

30A

1329

A14

27A

1526

Q0

2Q

13

Q2

5Q

36

Q4

8Q

59

Q6

11Q

712

Q8

13Q

914

Q10

16Q

1117

Q12

19Q

1320

Q14

22Q

1523

OE

11

OE

248

OE

325

OE

424

+ 7+ 18+ 31+ 42

-4

-10

-15

-21

-28

-34

-39

-45

LA[27..2]

1,3,4

BA

[27..2]6,7,8

IRQ

14IR

Q15

5V1,2,3,4,7,8,912V

3,4,9-12V

2,3,9

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

PC

I 90

50R

DK

4

TES

T H

eade

rs

69

Tues

day,

Feb

ruar

y 03

, 19

98

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

BA

2

BA

8

BA

12

BA

15

BA

25B

A26

BA

10B

A9

BA

11

BA

6B

A5

BA

4

BA

7

BA

3

BA

24

BA

27

BA

22

BA

17

BA

21B

A20

BA

23

BA

18B

A19

BA

16

BA

13B

A14

BD

8

BD

10B

D9

BD

11

BD

6

BD

1

BD

5B

D4

BD

7

BD

2B

D3

BD

0

BD

12B

D13

BD

14B

D15

BD

16B

D17

BD

18B

D19

BD

20B

D21

BD

22B

D23

BD

25B

D26

BD

27B

D28

BD

29B

D30

BD

31

BD

24

R7

K10

0

116

215

314

413

512

611

710

89

R4

K10

01

162

153

144

135

126

117

108

9

R13

K10

0

116

215

314

413

512

611

710

89

R10

K10

01

162

153

144

135

126

117

108

9

R8

K10

0

116

215

314

413

512

611

710

89

R5

K10

01

162

153

144

135

126

117

108

9

R14

K10

0

116

215

314

413

512

611

710

89

R11

K10

01

162

153

144

135

126

117

108

9

R9

K10

0

116

215

314

413

512

611

710

89

R6

K10

01

162

153

144

135

126

117

108

9

R15

K10

0

116

215

314

413

512

611

710

89

R12

K10

01

162

153

144

135

126

117

108

9

J4

HE

AD

ER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

37 3938 40 J7

HE

AD

ER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

37 3938 40

J6

HE

AD

ER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

37 3938 40 J9

HE

AD

ER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

37 3938 40

J8

HE

AD

ER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

37 3938 40J5

HE

AD

ER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

37 3938 40

LBE

0#1,

3,4,

7LB

E1#

1,3,

4,7

LBE

2#1,

3,4

LBE

3#1,

3,4,

7

LIN

TI1

1,7

LIN

TI2

1,7 LH

OLD

1,3 LH

OLD

A1,

3

BA

[27.

.2]

5,7,

8

US

ER

0/W

AIT

O#

3,7

US

ER

1/LL

OC

K#

1,3,

7U

SE

R2/

CS

2#1,

3,7,

8,9

US

ER

3/C

S3#

1,8,

9

AD

S#

1,3,

7,8 LW

/R#

1,3,

7,8

BLA

ST#

1,3,

8

BTE

RM

#1

ALE

1

LRE

SE

T#1,

3,7

CS

0#1,

7,8,

9

LCLK

1,3,

4,7

WR

#1,

4,8

RD

#1,

4,8

CS

1#1,

7,8,

9

BD

[31.

.0]

1,3,

4,8

LRD

YI#

1

11

22

33

44

55

66

77

88

AA

BB

CC

DD

33MH

z

*only load one*.

clock connection.

La yout for all 4,

Resistor jum

pers for direct

PC

I 9050RD

K4

ISA

MA

CH

210 & C

LOC

K

79

Thursda y, January 08, 1998

Title

Size

Docum

ent Num

berR

ev

Date:

Sheet

of

BA

20

BA

LE

IOW

C#

LBE

0#

IOR

C#

SB

HE

#C

HR

DY

LW/R

#

BA

23S

MW

TC

#

CS

2#

ISA

A0

BA

21

DA

TA

OU

TN

OW

S#

LRE

SE

T#

SM

RD

C#

LBE

3#

8MH

Z

CS

1#

ISA

A1

CS

0#

AD

S#

MW

TC

#

DA

TA

RW

ISA

_RE

SE

T

IO16#

LBE

1#

16MH

Z

MR

DC

#

BA

22

DA

TA

LCH

M16#

8BIT

ISA

_LRD

Y#

5V

5V

5V

5V

5V

5V

5V

U14

74AC

163

A3

B4

C5

D6

ENP

7E

NT

10C

LK2

LOA

D9

CLR

1

QA

14Q

B13

QC

12Q

D11

RC

O15

VCC 16

GND8

R16

221

2J10

CO

N 2X

8

13579111315

246810121416

Y1

33 MH

z

NC

1

GN

D7

OU

T8

VC

C14

R18

22

12

R17

22

12

R19

221

2U

15A74A

C02

231

147

RN

3

10K0

CO

M1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

U13

MA

CH

210

I/O0

2I/O

13

I/O2

4I/O

35

I/O4

6I/O

57

I/O6

8I/O

79

I010

I111

CLK

0/I213

I/O8

14I/O

915

I/O10

16I/O

1117

I/O12

18I/O

1319

VC

C44

I/O31

43I/O

3042

I/O29

41I/O

2840

I/O27

39I/O

2638

I/O25

37I/O

2436

CLK

1/I535

GN

D34

I433

I332

I/O23

31I/O

2230

I/O21

29I/O

2028

I/O19

27I/O

1826

GN

D12

I/O14

20I/O

1521

VC

C22

GN

D23

I/O16

24I/O

1725

GN

D1

R27

0K0

12

R25

0K0

12

R26

0K0

12

R28

0K0

12

RN

4

10K0

CO

M1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

U9B

74AC

32

456

U9D

74AC

32

121311

U9C

74AC

32

9108

US

ER

2/CS

2#1,3,6,8,9

IOR

C#

9

SM

WT

C#

9

8MH

z9

MR

DC

#8

BA

225,6,8

CH

RD

Y1,8

CS

1#1,6,8,9

SB

HE

#8

MW

TC

#8

ISA

_INT

9

LBE

0#1,3,4,6

DA

TA

RW

8

CS

0#1,6,8,9

BA

LE9

ISA

A0

8

LBE

1#1,3,4,6

US

ER

1/LLOC

K#

1,3,6

LCLK

1,3,4,6

IO16#

9IO

WC

#9

8MH

Z9

XIN

T23

BA

235,6,8

BC

LK1

16MH

z

AD

S#

1,3,6,8

LW/R

#1,3,6,8

XIN

T13C

HC

HK

#8

LINTi2

1,6

ISA

A1

8

16MH

ZIS

A_R

ES

ET

9

BA

215,6,8

LRE

SE

T#1,3,6

SM

RD

C#

9

LBE

3#1,3,4,6

BA

205,6,8

DA

TA

OU

T8

NO

WS

#9

DA

TA

LCH

8

M16#

9

LINTi1

1,6

CH

CH

K#

8

M16#

9N

OW

S#

9

XIN

T23

LINTi2

1,6

XIN

T13

ISA

_INT

9

IO16#

9

CS

RO

M#

4,9IO

CS

#9

ME

MC

S#

9C

SR

AM

#4,9

LINTi1

1,6U

SE

R0/W

AITO

#3,6

ISA

_LRD

Y#

1

11

22

33

44

55

66

77

88

AA

BB

CC

DD

PC

I 9050RD

K4

ISA

(A) &

Data Latch

A

89

Thursday, January 08, 1998

Title

Size

Docum

ent Num

berR

ev

Date:

Sheet

of

SB

HE

#C

HR

DY

SD

7S

D6

SD

5S

D4

SD

3S

D2

SD

1S

D0

BD

0S

D0

BD

1S

D1

BD

2S

D2

BD

3S

D3

BD

4S

D4

BD

5S

D5

BD

6S

D6

BD

7S

D7

BD

8S

D8

BD

9S

D9

BD

10S

D10

BD

11S

D11

BD

12S

D12

BD

13S

D13

BD

14S

D14

BD

15S

D15

SD

8S

D9

SD

10S

D11

SD

12S

D13

SD

14S

D15

SD

[15..0]

BA

3

BA

7

BA

12B

A13

BA

10

BA

17B

A16

BA

14

BA

21

BA

17

BA

23

BA

20

BA

22

BA

19

BA

0

BA

4

BA

19

BA

1

BA

11

BA

9

BA

6

BA

2

BA

18

BA

8

BA

5

BA

15

BA

18

5V

5V

U16

16646

A0

5A

16

A2

8A

39

A4

10A

512

A6

13A

714

A8

15A

916

A10

17A

1119

A12

20A

1321

A14

23A

1524

B0

52B

151

B2

49B

348

B4

47B

545

B6

44B

743

B8

42B

941

B10

40B

1138

B12

37B

1336

B14

34B

1533

OE

156

OE

229

DIR

11

DIR

228

+ 7+ 22+ 35+ 50

-4-11-18

-25-32-39-46-53

SA

B1

3S

AB

226

SB

A1

54S

BA

231

CP

AB

12

CP

AB

227

CP

BA

155

CP

BA

230

J11

ISA

16A

CH

CH

K#

1S

D7

2S

D6

3S

D5

4S

D4

5S

D3

6S

D2

7S

D1

8S

D0

9C

HR

DY

10A

EN

11S

A19

12S

A18

13S

A17

14S

A16

15S

A15

16S

A14

17S

A13

18S

A12

19S

A11

20S

A10

21S

A9

22S

A8

23S

A7

24S

A6

25S

A5

26S

A4

27S

A3

28S

A2

29S

A1

30S

A0

31

SB

HE#

32LA

2333

LA22

34LA

2135

LA20

36LA

1937

LA18

38LA

1739

MR

DC

#40

MW

TC

#41

SD

842

SD

943

SD

1044

SD

1145

SD

1246

SD

1347

SD

1448

SD

1549

RN

5

10K0

CO

M1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

MW

TC

#7

MR

DC

#7

SB

HE

#7

CH

RD

Y1,7

CH

CH

K#

7

DA

TA

RW

7

DA

TA

OU

T7

DA

TA

LCH

7

BD

[15..0]1,3,4,6

BA

[27..2]5,6,7

AD

S#

1,3,6,7LW/R

#1,3,6,7

BLA

ST

#1,3,6

RD

#1,4,6

WR

#1,4,6

CS

0#1,6,7,9

US

ER

3/CS

3#1,6,9

US

ER

2/CS

2#1,3,6,7,9

CS

1#1,6,7,9

ISA

A1

7IS

AA

07

11

22

33

44

55

66

77

88

AA

BB

CC

DD

14.31818 MH

z

IRQ

14

IRQ

12

IRQ

11

IRQ

10

IRQ

9

IRQ

7IR

Q6

IRQ

5

IRQ

4

IRQ

3

IRQ

15

PC

I 9050RD

K4

ISA

(B) &

OR

Int

A

99

Thursday, January 08, 1998

Title

Size

Docum

ent Num

berR

ev

Date:

Sheet

of

NO

WS

#

ISA

_RE

SE

TS

MW

TC

#S

MR

DC

#IO

WC

#IO

RC

#B

ALE

M16#

IO16#

5V-12V

12V

5V

5V

5V

5V12V

5V-12V

Y2

14.31818 MH

z

NC

1

GN

D7

OU

T8

VC

C14

U18A

74AC

02

231

147

U17B

74AC

209 10 12 13

8

U15B

74AC

02

564

U15C

74AC

02

8910

U15D

74AC

02

111213

U18B

74AC

02

564

U18C

74AC

02

8910

U18D

74AC

02

111213

J13

CO

N 2X

8

13579111315

246810121416

J12

ISA

16B

GN

D1

RE

SET2

5V3

IRQ

2/94

-5V5

DR

Q2

6-12V

7N

OW

S#

812V

9G

ND

10S

MW

TC

#11

SM

RD

C#

12IO

WC

#13

IOR

C#

14D

AK

3#15

DR

Q3

16D

AK

1#17

DR

Q1

18R

FSH

#19

BC

LK20

DA

K2#

26T

C27

BA

LE28

5V29

OS

C30

GN

D31

M16#

32IO

16#33

DA

K0#

39D

RQ

040

DA

K5#

41D

RQ

542

DA

K6#

43D

RQ

644

DA

K7#

45D

RQ

746

5V47

MS

TR16#

48G

ND

49

IRQ

721

IRQ

622

IRQ

523

IRQ

424

IRQ

325

IRQ

1034

IRQ

1135

IRQ

1236

IRQ

1537

IRQ

1438

R20

10k

12

R21

10k

12

RN

610K

0

COM 1IN 2IN 3IN 4IN 5IN 6IN 7IN 8IN 9IN 10

U17A

74AC

20

1245

6

147

J14

CO

N 2X

8

13579111315

246810121416

NO

WS

#7

ISA

_RE

SE

T7

SM

WT

C#

7S

MR

DC

#7

IOW

C#

7IO

RC

#7

BA

LE7

M16#

7IO

16#7

8MH

z7

ISA

_INT

7

IOC

S#

7

US

ER

3/CS

3#1,6,8

CS

1#1,6,7,8

CS

RA

M#

4,7

ME

MC

S#

7

US

ER

2/CS

2#1,3,6,7,8

CS

RO

M#

4,7

CS

0#1,6,7,8 5V

1,2,3,4,5,7,812V3,4

-12V2,3

PLX Technology, Inc.390 Potrero Ave.Sunnyvale, CA. 94086 USATel: 1-800-759-3735Fax: 1-408-774-2169Email: [email protected] and FTP Site:

www.plxtech.comPLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minorvariations to this publication, know as errata. PLX assumes no liability whatsoever, including infringement of any patent orcopyright, for sale and use of PLX products.

PLX and PLXMon are trademarks of PLX Technology which may be registered in some jurisdictions. All other product namesthat appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarksof their respective companies.

The license agreement provided with this product documents any other limitations

Copyright © 1997 PLX Technology, Inc. All rights reserved.

Order Number: 9050RDK-M002

T E C H N O L O G Y ®

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