refinement hardware and software interfaces
TRANSCRIPT
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Refining Hardware/Software interfaces
APresentation On
By :
Arun Kishor Johar
&
Suresh Kumar
M-Tech VLSI Design
Guided By :
Dr. Lava Bhargava
(Associate Professor )
MNIT Jaipur
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Refining Hardware/Software
interfaces
Any behavioral description can be implemented as eitheras Software or Hardware.
If Software then behavioral description will be compiledinto instruction set of chosen processor.
If Hardware then it will be synthesized into structure ofcomponents from a given library.
Processor with memory is considered as SoftwareComponent.
While others are termed as hardware components likeASIC.
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A Hardware software system
architecture
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1. The hardware and Software components are connected
by a bus.
2. A bus master is any component that can control the bus
and initiate data transfer such as processors ,Disk
controllers and DMA controllers.
3. A bus slave is any component that can respond to bus
master.
4. When two or more bus masters are connected to asingle bus we need a bus arbiter.
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A partitioned specification
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Target Architecture
v1 to v6 represents variables .
B1 to B4 represents behaviors .
p1 to p3 are ports .
Software variable v1Software ports p1
Hardware variables v3 v5 v6
Hardware ports p3
Shared variables v2 v4
Shared port p2
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Variable Distribution
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Fig(a) Both Hardware and shared variable reside in the
memory
Fig(b)Hardware variable reside in ASIC while shared variable
resides in memoryFig(c)both hardware and shared variable reside in ASIC
If we assign Software variables to ASIC then it will increase the
cost of ASIC due to extra Silicon.
Assigning Hardware variables to ASIC will increase BUS Traffic
and Slow down ASIC
So here we will find a Tradeoff between performance and cost
for any shared variable
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Figure aspects..
Behavior A is executed on processor
Behavior B1 and B2 are synthesized into ASICIf we assume average channel rates of X , Y1 and Y2 are
avgrate(X), avgrate (Y1) and avgrate (Y2) then bus transfer
rate for fig(a) will be
avgrate(X)+avgrate (Y1) +avgrate (Y2)
For fig( (b)
avgrate(X)+avgrate (Y1)
For fig (c)
avgrate(X)
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Algorithm : Variable distribution
Determine Sb /* set of buses*/
Determine Sv /* set of variables */
mincost =
mincost_bus = unknownmincost_var_dist = unknown
for each B Sbloop
for each D of Svloop
datarate(D,B) Cmapped to Bavgrate(C)
if (datarate(D,B) rate(B)) then
mincost = currcostmincost_bus=B
mincost_var_dist = D
end if
end if
end loop
end loop
if (mincost = )
then return( failure)
else return(mincost_bus, mincost_var_dist)
end if
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Interface Generation
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Figure(a) Two components
(b) Component and a bus
Sometimes designer encounters a situation where
communication protocol of selected bus and selected
component are incompatible and no off-the-shelf component
available to be used for interface.
Here we generate a technique for interfacing between two
incompatible components which consists of following steps:-
1. Represent the protocols of components to be interfaced as
ordered relations.
2. Partition relations into relation groups.
3. Generate an interface description by inverting eachoperation in relation group i.e. replacing each operation in the
relation group with its dual operation.
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Algorithm : Generate Interface Process
/* generate relations for each protocol*/
Ra = CreateRelations(Pa)Rb= CreateRelations(Pb)
/*partition relations into a set G of relation groups
G = GroupRelations(Ra,Rb)
/* add dual statement for each operation in G to
interface procsess
for each relation group Gi G loop
for each relation Rj Giloop
for each atomic operation Ok Rj loop
AddDualStatement(IP,Ok)
end loopend loop
end loop
CreateAndOptimizePorts(IP,Pa,Pb)
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Data Access Refinement
When we assign a behavior and variable it
accesses to different partitions, we need to
refine the variable access in the description
since the definition of the variable has beenmoved away from the behavior.
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After The Variable Distribution:
Assume that
The Shared variable V2 and hardware variable
V5 have been assign to memory. Shared variable V4 has been assign to the
ASICs dual port buffer.
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A Specification Mapping to target
architecture
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Data accesses within the samepartition are not a problem, since theywill be taken care of either by
software compilation, as is the caseV1 in the figure or by a hardwaresynthesis tool, as is the case with V3
and V6.
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A Specification Mapping to target
architecture
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Therefore, the task of data access
refinement is to refine data accessacross partitions as in case V2, V4 &
V5.
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Component A:
ADDRP
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Protocol Protocol
in (a) in (b)
-----------------------------------------------A1 (32) B1 (32) G1=(A1 B1)
-----------------------------------------------
A2 (32) B2 (32) G2=(B2 A2)
------------------------------------------------
Relations Groups
Generated Interface
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Software Behaviors Access Memory
Locations
This type of data access is carried out through the
processors Load/Store instructions.
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Hardware Behaviors Access Memory
Locations
Since this type of data access is carried out by
ASIC through a direct-memory access (DMA)
mechanism we called them DMA operations.
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Software Behaviors Access Ports or
the ASICs Buffer
This type of data access is carried out through
the processors in/out or moveinstructions
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Hardware Behaviors Access the
ASICs Buffer
This type of data access is carried out by ASICsaccess to its buffer locations, we call them bufferoperations. These operations use separate bus inthe ASIC.
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Tasks of Data Access Refinement Assign address to variables or ports that have been
mapped to the global address space. Replace the software access to those variables assigned
to the memory by the load and store operations.
Similarly, replace hardware access to those variables with
DMA operations. Use in and out operations to replace software access to
those variables that are mapped to ASICs. Use buffer
operations to replace their access from hardware
behaviors. Use in and out operations to replace any software access
to the ports that are mapped to global address space
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Control Access Refinement
Unlike data access channel which exists betweenbehavior and variable, control channel existsbetween two behaviors to indicate the starting orcompletion of behavior
Assigned tohardware
implementation
Error
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One solution to this problem would be to introduceHand-Shaking Protocol.
Using two shared variables: Startand Done.
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Could be mapped to the target architecture
Control refinement will be completed after the data
access refinement for shared variable Start and Done is
performed
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This control refinement scheme is a simple
one since the rest of software parts will not beaffected by B2sbeing moved to hardware.
We should be aware however, that this
scheme would require the processor to pullthe location that store the value of the
variable Done, and this may waste processors
clock cycles.
Since commercial processors usually provide an interrupt mechanism
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More efficient method of control access
refinement is possible.
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Tasks of Control access refinement
Chose a control scheme, such as polling orinterrupt. Then insert the correspondingcommunication protocols in the software and
the hardware behaviors. Insert any necessary software behaviors, such
as interrupt service routines.
Refine the accesses to shared variables thathave been introduced by insertion of theprotocols.
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THANK YOU