Register Transfer Language

� A digital system is an interconnection of digital modules.

� Digital modules can be defined by the registers they contain and operations that are performed on the data stored in them� Operations are called micro-operations (MO).� MO is an elementary operation performed on the information

(data) stored in one or more registers, e.g.: shift, count, clear, add, and load.

� E.g. a counter can have two MOs: load and increment.

� Hardware organization of a digital computer can be defined by:� Set of registers it contains and their function

� The sequence of MOs performed on the binary information

� The control for initiating the sequence of MOs

� The symbolic notation describing MO transfers among registers is called a register transfer language. � Implies availability of logic circuits for performing MOs and

and transfer results of the operations to another (or same) register.

Register Transfer

� Registers are designated by capital letters followed by optional number: MAR, PC, IR, R1, R2, etc.

� Individual flip-flops, i.e. bits, are numbered from 0 to nstarting from the right:

R1 7 6 5 4 3 2 1 0

R2

015

PC(H) | PC(L)

015 8 7

PC(8-16) | PC(0-7)

015 8 7

=

� Register transfer: R2 ← R1� ← denotes replacement operator� transfers the content of register R1 into register R2. The

content of R1remains intact� Implies that the necessary hardware for performing the

transfer is available, and� that the destination register has a parallel load capability

� Conditional transfer with control functionP, which is a Boolean variable equal to 0 or 1.

P: R2 ← R1

“ if (P == 1) then (R2 ← R1)”

R2 clock

R1

n

Control circuitP load

Transfer from R1 to R2 when P = 1; transfer occurs of the clockedge transition (rising edge in this example).

clock

load

t t+1

transfer

� Basic symbols of the register transfer notation

R2 ← R1, R1 ← R2Separates two MOsComma ,

R2 ← R1Denotes transfer of informationArrow ←

R2(0-7), R2(L)Denotes a part of a registerParentheses ( )

MAR, R2Denotes registerLetters and numerals

ExamplesDescriptionSymbol

Bus and Memory Transfer

� A common bus provides paths to transfer data from one register to another => no separate lines between each register.

� Control signals determine the register(s) connected to the bus.

� Multiplexers can be used to construct a common bus.

� Example: 4-line common bus

Bus system for four registers (Mano, 1993)

selection lines (address)

address = 11 address = 10 address = 01 address = 00

� The number of multiplexers equals the bus width n.

� The size of each multiplexer must be k x 1, where k is the number of n-bit registers, e.g. 16-bit bus and 8 registers: � 16 8 x 1 multiplexers

� 3 address (selection) lines: encodes 8 addresses, one for each register.

� Transfer of information from the bus to a destination register can be accomplished by connecting the bus to the register inputs and by activating the load control of the selected register.

� The bus can be stated explicitly in the register transfer statement:

BUS ← C, R1 ← BUS

or the existence of the bus is implied by the statement:

R1 ← Cfrom this statement designer knows which control signals must be activated to produce the transfer through the bus: place C on bus, activate load control input of register R1.

� Bus system can be also constructed with 3-state buffers� when control input e is 1 A = B

� when control input e is 0 B (output) is in high impedance state: not loading effect to a bus line.

bus switch channel

selection lines (address)

register outputs for bit 0

Implementing a bus using 3-state buffers (Mano 1993)

1 0 0 0

• bus width n• registers k• buffers k x n• log2(k) x k decoder

high impedancestate

� Memory readRead: DR ←M[AR]

“Read memory word M from address ARto data register DR”

� Memory writeWrite: M[AR] ← R1

“Write data from R1to a memory word M at address AR”

Arithmetic Micro-operations

� Micro-operation is an elementary operation performed with the data stored in registers

� Four (typical) micro-operation (MO) categories1. Register transfer

2. Arithmetic, e.g.: addition, subtraction, increment, decrement, shift

3. Logic

4. Shift

� Add micro-operation:R3← R1 + R2

� to implement this statement with hardware we need three registers and addition circuits.

� Subtract micro-operation:R3← R1 + R2 +1

� R2 represents the 1’s complement of R2

� Adding 1 to 1’s complement produces 2’s complement

� Arithmetic micro-operations (Mano 1993)

� Binary adderis a digital circuit that generates the arithmetic sum of two binary numbers of any length.

� Full-adderform the arithmetic sum of two bits and a previous carry.

� Binary adder is constructed with full-adder circuits connected in cascade, with the output carry from one full-adder connected to the input carry of the next full-adder.

� n-bit binary adder requires n full-adders.

� The n data bits for the inputs A and B come from two registers (such as R1and R2, for example).

� Sum can be transferred to a third register or to one of the source registers.

� The addition and subtraction operations can be combined into one common circuit by including exclusive-or (XOR) gate with each full-adder.

� 1’s complement can be implement with inverters, and a one can be added to sum through the input carry C0.

� When M = 0 the circuit is an adder, when M = 1 the circuit becomes a subtractor

� XOR(M,B) = B, M = 0 => B inputs are not inverted, C0 = 0

� XOR(M,B) = B, M = 1 => B inputs are inverted, C0 = 1

� The increment operation adds one to a number in a register, e.g.:

0110 => 0111� Increment MO can be implement with a combinatorial

circuit by means of half-adders connected in cascade.� n-bit binary incrementer requires n half-adders. � Least significant bit must have one input connected to

logic-1.� The other inputs receive the number to be incremented

or the carry from the previous stage.� The output carry C4 is 1 only after incrementing binary

1111. This causes outputs S0 through S3 to go to 0.

truth table for a half adder

most significant bit least significant bit+

sum

end carry

� Arithmetic micro-operations listed in Table 4-3 can be implemented in one composite arithmetic circuit.

� Basic component is parallel adder.� Control inputs are used to obtain different types of

arithmetic operations.� E.g. 4-bit arithmetic circuit:

� 4 full-adders constitute the 4-bit adder� 4 multiplexers for choosing operations� two 4-bit inputs A and B, and 4-bit output D� two selection inputs S0 and S1 and input carry Cin

� Output: D = A + Y+ Cin

� With S0, S1 ,and Cin is possible to control the value of Y, and the operation of the 4-bit adder, and to implement the arithmetic operations listed in Table 4-4.

4-bit arithmetic circuit (Mano 1993)

� Table 4-4 Arithmetic Circuit Function Table

Transfer A (same as the 5th MO)D = A1111

Decrement A (D = A – 2’s complement of 1)D = A - 11011

Increment A D = A + 10101

Transfer AD = A0001

SubtractD = A + B’ + 1B’110

Subtract with borrowD = A + B’B’010

Add with carryD = A + B + 1B100

AddD = A + BB000

Micro-operationD = A + Y + CinYCinS0S1

Note: B’ is used for indicating the logic complement of B

Logic Micro-operations

� Logic micro-operations specify binary operations for strings of bits stored in registers.

� These operations consider each bit of the register separately and treat them as binary values, e.g. XOR:

P: R1 ← R1 R2� e.g.: 1010 (=R1) 1100 (=R2) = 0110 (new value of R1)� Bit-by-bit logic operation

� Logic MOs are useful for bit manipulation of binary data and for making logical decisions.

� Symbols of logic micro-operations:Λ denotes ANDV denotes OR

denotes XOR� Logic complement (1’s complement) is denoted with

bar on the top of register name (in these slides quotation mark ’ is also used for word processing reasons).

� Different symbols for logic MOs are used in order to distinguish from Boolean functions.

� + denotes arithmetic addition. However, in control function it denotes Boolean OR-function

P + Q: R1 ← R2 + R3, R4← R5 V R6

E.g. F5(0,0) = 0, F5(0,1) = 1

(Mano 1993)(Mano 1993)

� The hardware implementation of logic MOs requires a logic gate for each bit or bit pair.

� From 16 possible logic MOs only four is typically used (AND, OR, XOR, and complement) from which all others can be derived.

� Fig. 4-10 shows one stage (for one bit pair) of a circuit that generates the four basic logic micro-operations.

� The selection inputs in Fig. 4-10 choose one of the data inputs of the multiplexer and direct its value to the output.

� The stage must be repeated n times for a logic circuit with n bits.

(Mano 1993)

(OR)

(XOR)

(complement, NOT)

selection inputs

(AND)

� Logic MOs are very useful for manipulating individual bits or a portion of a word stored in a register� changing bit values

� deleting group of bits

� insert new bit values into a register

� e.g.:

A 1010 1010 1010B (operand) 1100 1100 1100A after 1110 0110 1000

selective-set (OR)

selective-complement (XOR)

mask-operation (AND)

� Insert operation, e.g. replace four most significant bits with 1001:

first masking with AND…

0110 1010 A before0000 1111 B (mask)0000 1010 A after masking

..and then insert new value with OR

0000 1010 A before1001 0000 B (insert)1001 1010 A after insertion

� Clear operation compares the words in A and B and produces an all 0’s result if the two numbers are equal.

� The all-0’s result can be checked for determining if the two numbers are equal

1010 A1010 B0000 A← A B

Shift Micro-operation

� Shift MOs are used to serial transfer of data.� They are also used in arithmetic, logic, and other data

processing operations.� The contents of a register can be shifted to the left or

right.� The first flip-flop receives binary information from the

serial input� left shift: serial input to the rightmost bit position.� right shift: serial input to the leftmost bit position� serial input information defines the type of shift: logical,

circular, and arithmetic.

� Logical shift: shl, shr� serial input is constant 0: loss of information

� Circular shift (rotate): cil, cir� serial input is connected to serial output: no information loss

� Arithmetic shift: ashl, ashr� ashl multiplies the number by 2

� all bits are shifted left� sign-bit is replaced with a bit in position n – 2� zeros are added to the bit position 0� overflow occursif sign-bit changes from initial value (Vs = 1)

� ashr divides the number by 2� sign-bit is preserved, all bits are shifted right, including the sign bit

(see Fig. 4-11).� Bits shifted out from bit position 0 are lost

,overflow will occur at next left shiftif Vs = 1.

(Mano 1993)

(Mano 1993)

� Hardware implementation with combinational circuit� A content of a register is first place onto a common bus whose

output is connected to the combinational shifter

� The shifted number is loaded back into the register

� A combinational circuit shifter can be implemented with multiplexers (see Fig. 4-12)� 4-bit shifter

� 4 data inputs: A0 – A3

� 4 data outputs: H0 – H3

� 2 serial inputs: one for right shift (IR) and one for left shift (IL)

� serial inputs can be controlled by another multiplexer to provide the three possible types of shifts.

� When S = 0 we have a right shift (down)

� When S = 1 we have a left shift (up)

(Mano 1993)

Arithmetic Logic Shift Unit

� Instead of having individual registers performing the MOs directly, computer system employ a number of storage registers connected to a common operational unit called an arithmetic logic unit or ALU.

� To perform a MO, selected register(s) are placed in the inputs of ALU.

� ALU performs an MO and result is the transferred to a destination register.

� ALU is a combinational circuit so that the entire register transfer operation from the source registers through the ALU and into the destination register can be performed during one clock pulse period.

� The arithmetic, logic, and shift circuits can be combined into one ALU with common selection variables.

� One stage of an ALU is shown in Fig. 4-13� i designates a typical stage (n stages for n bit inputs and

output)

� Ai and Bi denote inputs from registers

� MO is selected with selection inputs

selection inputs

Fig. 4-9

Fig. 4-10

one stage(Mano 1993)