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PORTFOLIOMETRIX BCI BOND FUND OF FUNDS (B1) MANAGED BY: PORTFOLIOMETRIX - AUTHORISED FSP 42383 MINIMUM DISCLOSURE DOCUMENT 31 DECEMBER 2019 INVESTMENT OBJECTIVE The Poroliometrix BCI Bond Fund of Funds offers the potenal for capital growth, together with a regular and high level of income. INVESTMENT UNIVERSE Investments to be included in the porolio may, apart from assets in liquid form, consists of parcipatory interests and other forms of parcipaon of local and global collecve investment schemes, or other similar schemes operated in territories with a regulatory environment which is to the sasfacon of the manager and trustee of a sufficient standard to provide investor protecon at least equivalent to that in South Africa and which is consistent with the porolio’s primary objecve, invesng in liquid form, debentures, bonds, fixed deposits, money market instruments and other interest-bearing securies. The underlying porolios may invest in short, intermediate and long-dated securies and the porolio’s underlying exposure will be predominately bond investments. PERFORMANCE (Net of Fees) -5% 0% 5% 10% 15% 20% 25% 30% % Cumulative Return 01-2018 08-2018 03-2019 12-2019 Date PorolioMetrix BCI Bond Fund of Funds (B1) Fund Benchmark Cumulave (%) 1 Year 3 Years 5 Years 10 Years Since Incepon Fund 9.62 - - - 25.00 Fund Benchmark 10.32 - - - 24.36 Annualised (%) Fund 9.62 - - - 9.29 Fund Benchmark 10.32 - - - 9.07 Incepon date: 27 Jun 2017 Annualised return is the weighted average compound growth rate over the period measured. Risk Stascs Fund 1 Year 3 Years Standard deviaon 3.00% - Maximum drawdown -0.38% - Highest and Lowest Calendar year performance since incepon High 9.62% Low 8.37% MONTHLY RETURNS JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC YTD 2019 2.6 -0.1 0.8 0.8 0.6 1.6 -0.4 1.0 0.6 -0.2 0.3 1.6 9.62 2018 1.7 3.3 1.8 -0.2 -1.5 -0.7 2.0 -1.8 0.7 -1.3 3.8 0.6 8.37 2017 - - - - - - 1.2 1.1 1.2 -1.1 -0.5 4.2 6.04 FUND INFORMATION Porolio Manager: Brandon Zietsman Launch date: 27 Jun 2017 Porolio Value: R 1 927 009 423 NAV Price (Fund Incepon): 103.27 cents NAV Price as at month end: 107.80 cents JSE Code: PMFB1 ISIN Number: ZAE000246039 ASISA Category: SA Interest Bearing Variable Term Fund Benchmark: JSE/ASSA All Bond index (ALBI) Minimum Investment Amount: None #Monthly Fixed Admin Fee: R15 excl. VAT on all direct investor accounts with balances of less than R100 000 Valuaon: Daily Valuaon me: 08:00 (T+1) Transacon me: 14:00 Regulaon 28: No Date of Income Declaraon: 28 February/31 August Date of Income Payment: 2nd working day of Mar/Sep Income Distribuon (cpu) 28 Feb 2018 4.29 31 Aug 2018 4.61 28 Feb 2019 4.51 31 Aug 2019 4.51 FEE STRUCTURE Annual Service Fee: (A) 0.55% - (B1) 0.09% (Incl. VAT) Inial Advisory Fee (Max): 0.00% (Incl. VAT) Annual Advice Fee: 0 - 1.15% (if applicable) Inial Fee: 0.00% (Incl. VAT) Performance Fee: None * Total Expense Rao (TER): Sep 19 : 0.54% (PY: 0.54%) Performance fees incl in TER: Sep 19 : 0.00% (PY: 0.00%) Porolio Transacon Cost: Sep 19 : 0.00% (PY: 0.00%) Total Investment Charge: Sep 19 : 0.54% (PY: 0.54%) All Values (Incl. VAT) RISK PROFILE Low Risk This porolio has less than 10% equity exposure, if any, resulng in low risk, stable investment returns. The porolio is not directly exposed to currency risk, but it is exposed to default and interest rate risks. The porolio is suitable for shorter term investment horizons. PORTFOLIOMETRIX BCI BOND FUND OF FUNDS (B1) | 1 of 2 DATE OF ISSUE: 17 JANUARY 2020

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Page 1: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

Relay Scheme Design Using Microprocessor

Relays

A report to theSystem Protection Subcommittee of the

Power System Relay Committee ofthe IEEE Power & Energy Society

Prepared by working group C16June 2014

Presented at PSRC Main Committee Meeting- January 2015

Page 2: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

2Title

1/16/2015

Members of the working group

Raaluca Lascu – chair Tony Seegers – vice-chair

Brian Boysen Alla Deronja

Kevin Donahoe Robert Frye

Gene Henneberg Rich Hunt

Don Lukach Bruce Mackie

Cristian Paduraru Don Sevcik

Jim O’Brien Adi Mulawarman

Michael Stojak Michael Thompson

Rich Young Don Sevcik

Past members:

Ken Birt Ken Behrendt

Angela Higdon Vajira Pathirana

Page 3: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

3Title

1/16/2015

This paper is intended to supplement to the existing 1999 relay trip circuit design paper to address the use microprocessor relays

� Modern relays are changing the way substations are engineered

� They enable many functions to be carried out through one piece of hardware

� This flexibility and compactness is sometimes the cause of increasing levels of complexity

Page 4: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

4Title

1/16/2015

Typical Trip circuit using Electromechanical relays

Page 5: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

Considerations When Using Microprocessor Relays

Page 6: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

6Title

1/16/2015

Trip circuits� Typical breaker trip circuit using microprocessor relay

IN1 IN2

52a

01/T

TRIP/OUT1

86/BF

52a

TC-1

BFI*/OUT4

ExternalBF Relay

79 I*/OUT5

External79 Relay

StationBatteryVoltage

(+)

(-)

TRIP*/OUT2

CLOSE/OUT3

ExternalBFI

External79 I

IN4IN3

Integral to microprocessorbased relay

TC-2 CC

IN1 = Breaker status inputIN2 = Trip circuit monitor input (optional)

TC-1 = Breaker trip coil 1TC-2 = Breaker trip coil 2

CC = Breaker close coil

OUT1 = Protective relay trip contactOUT2 = Protective relay trip contact (* if second trip coil present)

OUT3 = Protective relay close contact (manual or autoreclosing)OUT4 = Protective relay breaker fail initiate contact (*if external BF relay present)

OUT5 = Protective relay reclose initiate output (*if external 79 relay present)01/T = Manual control switch trip contact

52a = Breaker auxiliary form “a” contact

86/BF = Breaker failure lockout contactBFI = Breaker Failure initiate

79 I = Auto reclose initiate

Page 7: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

General Scheme Design

Page 8: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

8Title

1/16/2015

Trip Circuit

� Microprocessor relays can simplify trip circuit design

� Multiple isolated outputs on a single relay can be used to trip multiple breakers

Page 9: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

9Title

1/16/2015

Integration, Separation, and Redundancy

� Combining functions into one relay can reduce size of equipment, reduce wiring, and lower cost

� However, it can lead to problems such as measurement or programming errors effecting multiple protection functions

� Thought must be given to creating redundant systems which can function despite total failure of a relay◦ Ex: Duplicate functions using relay from different manufacturer

Page 10: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

10Title

1/16/2015

Direct Tripping

Microprocessor Relay

TC-1

52a

PR-101

T

( - )

( + )

Multiple protection

functions, auxiliary

timers, etc. included in

microprocessor relay

logic.

52a

52b

TC-1

01/T

PR

Breaker auxiliary form “a” contact

Breaker auxiliary form “b” contact

Trip Coil 1

Breaker control handle Trip

Protective relay trip contact

Page 11: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

11Title

1/16/2015

Dual Relay Tripping

Page 12: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

12Title

1/16/2015

Dual Trip Coils with One Relay

Page 13: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

13Title

1/16/2015

Dual Trip Coils with Two Relays

Page 14: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

14Title

1/16/2015

Dual Trip Coils with Breaker Re-trip

TC-1

52a

PR-1a

01

T

( - )

( + )

( + )

( - )

TC-2

52a

BFR

BFR retrips TC-1 on

breaker failure initiate.

PR-1b trips TC-2 on

backup trip

Microprocessor

Relay

52a

TC-1

TC-2

01/T

PR

PR-1b

BFR

Breaker auxiliary form “a” contact

Trip Coil 1

Trip Coil 2

Breaker control handle Trip

Protective relay trip contact

Protective relay backup trip contact

Breaker failure retrip contact

PR-1b

Page 15: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

15Title

1/16/2015

Dual Trip Coils, Relay Cross-Tripping

Probably most common today

Page 16: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

16Title

1/16/2015

Dual Breaker Scheme

TC

52a

01

T

( + )

TC

52a

PR-1a01

T

( - )

( + )

Microprocessor

Relay

PR-1b

Protection logic trips

both circuit breaker

coils simultaneously.

( - )

52a

TC

01/T

PR

Breaker auxiliary form “a” contact

Trip Coil

Breaker control handle Trip

Protective relay trip contact

Page 17: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

17Title

1/16/2015

There are a few problems

Page 18: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

18Title

1/16/2015

Circuit Contacts

� One leading cause of failure is burned and failed output contacts due to inductive DC current

� Must ensure circuit contact being used is properly rated for all possible signals

� Often can assess by calculating L/R rating:Load Inductance

Load Resistance + Cable Resistance to Load

� Relay manufacturers are developing ways to mitigate burnout

L/R rating =

Page 19: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

19Title

1/16/2015

Circuit Contacts (cont.)

� Speed of relay contacts must be considered

� Typical closing time is 3 to 8 milliseconds

� Choosing incorrect contacts can lead to leakage or sneak currents

� Extend Seal-in time and/or add arc suppression

Page 20: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

20Title

1/16/2015

PRO

� Low CT burden

Page 21: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

21Title

1/16/2015

CONBattery Creep

� Upgrading stations typically leads to increased continuous DC system loads

� Once adequate DC supply systems may need to be revisited

Page 22: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

22Title

1/16/2015

Sneak Currents

� Sneak currents are unintended design flaws that can result in serious consequences

� With increased complexity, sneak currents are more likely

� With Microprocessors, the sneak circuits have often moved inside

� Systematic testing and inspection is most common way to prevent

� Many sneak conditions are located through trial and error over time in the field

Page 23: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

23Title

1/16/2015

Battery System Grounding

� Can use spare input contacts on relay to monitor grounding conditions of DC system

IN 3

13

0 V

dc

IN 4

Page 24: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

24Title

1/16/2015

It’s Not All Badthere are a few new perks

Page 25: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

25Title

1/16/2015

Trip Circuit Monitoring

� Typical breaker trip circuit using microprocessor relay

IN1 IN2

52a

01/T

TRIP/OUT1

86/BF

52a

TC-1

BFI*/OUT4

ExternalBF Relay

79 I*/OUT5

External79 Relay

StationBatteryVoltage

(+)

(-)

TRIP*/OUT2

CLOSE/OUT3

ExternalBFI

External79 I

IN4IN3

Integral to microprocessorbased relay

TC-2 CC

IN1 = Breaker status inputIN2 = Trip circuit monitor input (optional)

TC-1 = Breaker trip coil 1TC-2 = Breaker trip coil 2

CC = Breaker close coil

OUT1 = Protective relay trip contactOUT2 = Protective relay trip contact (* if second trip coil present)

OUT3 = Protective relay close contact (manual or autoreclosing)OUT4 = Protective relay breaker fail initiate contact (*if external BF relay present)

OUT5 = Protective relay reclose initiate output (*if external 79 relay present)01/T = Manual control switch trip contact

52a = Breaker auxiliary form “a” contact

86/BF = Breaker failure lockout contactBFI = Breaker Failure initiate

79 I = Auto reclose initiate

Page 26: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

26Title

1/16/2015

Lockout Function

Page 27: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

27Title

1/16/2015

Breaker Control Switch

CC

52b

( + )

TC

52a

PR-1a01

T

( - )

( + )

Microprocessor

Relay

PR-1b

PR-1b closes circuit

breaker. Relay logic

includes control

handle supervision.

( - )

Microprocessor Relay

01

C

Digital

Input

( + )

( - )

52a

TC

CC

01/T

01/C

PR

Breaker auxiliary form “a” contact

Trip Coil

Close Coil

Breaker control handle Trip

Breaker control handle Close

Protective relay trip contact

Page 28: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

SCADA Functions

Page 29: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

29Title

1/16/2015

SCADA Control

� An RTU or other gateway is used to issue open/close commands to circuit breakers, motor-operated switches, and other devices remotely

� Microprocessor relays can act as I/O hardware to implement commands

Page 30: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

30Title

1/16/2015

SCADA Circuit Breaker Control

� CB control implemented using “select-before-operate” concept

� This is intended to prevent any other device from issuing untimely commands to the breaker with unintended results

Page 31: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

31Title

1/16/2015

SCADA Metering and Monitoring

� Microprocessors can greatly simplify monitoring and metering of stations through digital communication through the gateway

� SCADA data collection can be distributed to the microprocessor relays

� These functions used to require an independent electromechanical unit for each

Page 32: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

Maintainability and Testing

Page 33: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

33Title

1/16/2015

Multifunction Relay Testing Considerations

� Testing occurs at many stages: acceptance, commission, and as scheduled

� Desire method to conduct tests without changing any relay settings since this could introduce unintended errors

� Some designs may allow for spare contacts which can be used for testing

� Built-in recording functions can be used to determine if appropriate response to test occurred

Page 34: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

A couple of additional issues

Page 35: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

35Title

1/16/2015

Test Switches

� Approach on test switches can vary widely

� Test switches may become more rare with microprocessor units since removing all the functions of a single relay at once may be unacceptable

� Test switches enable a relay to be isolated for hot change out

Page 36: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

36Title

1/16/2015

Test Switches part 2

� Testing relays has become more complicated since each relay may be programmed completely differently

� Test switches enable more isolation for testing to prevent inadvertant trips (iebreaker fail outputs)

� Consistent design methods are needed to decrease complexity

Page 37: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

37Title

1/16/2015

Logic Performance Considerations

� Loss of power or network connection can dramatically effect output from relay logic

� Consideration must be given for the default state given either condition

� Volatile memory will reset whereas non-volatile memory will maintain the previous value

Page 38: Relay Scheme Design Using Microprocessor Relays Scheme...Relay Scheme Design Using Microprocessor Relays A report to the System Protection Subcommittee of the Power System Relay Committee

Questions?