reliability handbooksewoon.com/icmaster/semi/hitachi/pdf/reliability.pdf · 2003. 12. 11. ·...

Reliability Handbook

ADE-410-002

Rev. 1.01/15/2002Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’spatent, copyright, trademark, or other intellectual property rights for information contained inthis document. Hitachi bears no responsibility for problems that may arise with third party’srights, including intellectual property rights, in connection with use of the informationcontained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that youhave received the latest product standards or specifications before final design, purchase oruse.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.However, contact Hitachi’s sales office before using the product in an application thatdemands especially high quality and reliability or where its failure or malfunction may directlythreaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclearpower, combustion control, transportation, traffic, safety equipment or medical equipment forlife support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachiparticularly for maximum rating, operating supply voltage range, heat radiation characteristics,installation conditions and other characteristics. Hitachi bears no responsibility for failure ordamage when used beyond the guaranteed ranges. Even within the guaranteed ranges,consider normally foreseeable failure rates or failure modes in semiconductor devices andemploy systemic measures such as fail-safes, so that the equipment incorporating Hitachiproduct does not cause bodily injury, fire or other consequential damage due to operation ofthe Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this documentwithout written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachisemiconductor products.

Rev. 1.0, 01/02, page iii of vi

Contents

Section 1 Quality Assurance.......................................................................................... 11.1 Quality Assurance ............................................................................................................. 11.2 Quality Policy (Principle)..................................................................................................21.3 Quality Objectives............................................................................................................. 2

1.3.1 Independence of Design, Manufacture, & Quality Assurance Departments ........ 31.4 Contract Review................................................................................................................ 51.5 Reliability Design.............................................................................................................. 6

1.5.1 Reliability Objectives ........................................................................................... 61.5.2 Design Review ..................................................................................................... 91.5.3 Design Certification ............................................................................................. 10

1.6 Management of Documents and Data ............................................................................... 121.7 Quality Assurance System for Affiliated and Associate Companies................................. 131.8 Product Identification and Traceability ............................................................................. 151.9 Production Process Control ............................................................................................... 151.10 Inspection .......................................................................................................................... 18

1.10.1 Acceptance Inspection for Purchased Parts and Materials ................................... 191.10.2 Process Inspection ................................................................................................ 211.10.3 Shipping Inspections ............................................................................................ 211.10.4 Control of Inspected Products .............................................................................. 22

1.11 Control of Calibration of Measuring Equipment............................................................... 231.12 Control of Defective Products ........................................................................................... 24

1.12.1 Verification of Type of Defects and Management Measures............................... 251.13 Corrective and Preventive Measures ................................................................................. 25

1.13.1 Corrective Measures............................................................................................. 251.13.2 Preventive Measures ............................................................................................ 26

1.14 Handling, Storage, Packaging and Preservation................................................................ 271.14.1 General ................................................................................................................. 271.14.2 Handling............................................................................................................... 271.14.3 Storage..................................................................................................................271.14.4 Packaging ............................................................................................................. 271.14.5 Preservation.......................................................................................................... 28

1.15 Quality Records................................................................................................................. 281.16 Internal Quality Audit and Periodic Process Survey ......................................................... 281.17 Education and Training .....................................................................................................28

1.17.1 Education at Departmental Level ......................................................................... 291.17.2 Education at the Company Level ......................................................................... 29

1.18 Quality Control through Statistical Methods..................................................................... 311.18.1 Calculation of the Process Capability Index......................................................... 31

Rev. 1.0, 01/02, page iv of vi

Section 2 Reliability.......................................................................................................... 332.1 Properties of Semiconductor Reliability............................................................................ 332.2 Reliability Criteria ............................................................................................................. 35

2.2.1 Initial Failure Period Criteria ............................................................................... 352.2.2 Random Failure Period Criteria ........................................................................... 352.2.3 Criteria to Express Lifetime ................................................................................. 392.2.4 Functional Failure—Criteria to Express Malfunction .......................................... 39

2.3 Reliability Theory.............................................................................................................. 402.3.1 Fundamental Failure Model ................................................................................. 412.3.2 Probability Distribution Used in Reliability Analysis .......................................... 452.3.3 Methods of Data Analysis .................................................................................... 48

Section 3 Failure Mechanisms and Failure Analysis Technologyfor Semiconductor Devices.......................................................................... 53

3.1 Failure Classification......................................................................................................... 533.2 Failure Modes and Mechanisms........................................................................................ 61

3.2.1 Oxide Film Degradation Over Time .................................................................... 613.2.2 Hot Carrier ........................................................................................................... 653.2.3 Soft Errors Due to Memory Alpha ( Particles .................................................. 723.2.4 Retention Characteristics of Non-Volatile Memory............................................. 773.2.5 Aluminum Migration............................................................................................ 823.2.6 Moisture Resistance ............................................................................................. 883.2.7 Package Cracking during Reflow Solder Processing ........................................... 943.2.8 Electrostatic Discharge......................................................................................... 1123.2.9 Latchup................................................................................................................. 1213.2.10 Power MOS FET Damage.................................................................................... 1243.2.11 Luminance Deterioration of Optical Devices....................................................... 128

3.3 Failure Analysis Technology............................................................................................. 136

Section 4 Reliability Tests on Semiconductor Devices.......................................... 1474.1 Reliability Tests................................................................................................................. 1474.2 Sampling Methods for Reliability Tests............................................................................ 148

4.2.1 Sampling Tests ..................................................................................................... 1484.2.2 Sampling Based on a Failure Distribution............................................................ 1494.2.3 Confidence Limits on the Failure Rate................................................................. 153

4.3 Screening........................................................................................................................... 1564.3.1 The Purpose of Screening..................................................................................... 1564.3.2 Screening Methods............................................................................................... 156

4.4 Methods of Testing Reliability .......................................................................................... 160

Section 5 Reliability Prediction..................................................................................... 1775.1 Basic Failure Model .......................................................................................................... 1785.2 Accelerated Lifetime Test Methods .................................................................................. 180

Rev. 1.0, 01/02, page v of vi

5.3 Examples of Failure Rate Prediction ................................................................................. 1835.3.1 Reliability Data .................................................................................................... 1835.3.2 Failure Prediction by Aggregation of Failure Data .............................................. 194

Section 6 Important Information Regarding Use..................................................... 1976.1 Warnings Regarding Device Selection.............................................................................. 197

6.1.1 Maximum Ratings ................................................................................................ 1976.1.2 Derating................................................................................................................ 1986.1.3 Using a Device with Equivalent Function............................................................ 2056.1.4 When a Device is Used in a Severe Environment ................................................ 2086.1.5 When Using a Device in an Application that Requires High Reliability ............. 208

6.2 Protection of Devices from Electrostatic Discharge (ESD) Damage ................................ 2106.2.1 ESD Damage........................................................................................................ 2106.2.2 Excess Voltage Destruction.................................................................................. 2176.2.3 Latchup................................................................................................................. 2256.2.4 Destruction Induced by Excess Current ............................................................... 2276.2.5 Thermal Runaway ................................................................................................ 2286.2.6 ASO Destruction .................................................................................................. 2286.2.7 Destructive Avalanche ......................................................................................... 228

6.3 Protecting Devices from Mechanical Destruction............................................................. 2296.3.1 Lead Forming ....................................................................................................... 2296.3.2 Mounting on a Printed Circuit Board ................................................................... 2336.3.3 Flux Cleaning Methods ........................................................................................ 2376.3.4 Attachment of the Heat Radiation Plate ............................................................... 239

6.4 To Protect the Device from Thermal Destruction ............................................................. 2486.4.1 Soldering Temperature Profile ............................................................................. 2496.4.2 Precautions in Handling a Surface-Mount Device ............................................... 2516.4.3 Using Reflow to Attach Surface-Mount Devices ................................................. 2536.4.4 Recommended Conditions for Various Methods of Mounting Surface-Mount

Devices................................................................................................................. 2536.5 Protecting Devices from Malfunction ............................................................................... 258

6.5.1 Precautions with Respect to Hardware................................................................. 2586.5.2 Precautions Relating to Software ......................................................................... 273

6.6 Being Prepared for Possible Malfunction.......................................................................... 2746.7 Failure-Detection Ratio during Test .................................................................................. 2776.8 Other Examples ................................................................................................................. 282

6.8.1 Precautions in Packaging ..................................................................................... 2826.8.2 Storage of Semiconductor Devices ...................................................................... 2846.8.3 Precautions in Transport....................................................................................... 2876.8.4 Product Safety ...................................................................................................... 2886.8.5 Examples of Other Categories of Problems ......................................................... 289

Rev. 1.0, 01/02, page vi of vi

Rev. 1.0, 01/02, page 1 of 292

Section 1 Quality Assurance

1.1 Quality Assurance

Semiconductor miniaturization seems to be almost limitless and year by year integration densityincreases (fig. 1.1). This does not result only in the incorporation of larger circuits, but also in therapid development of systemization, and of more complex functions in the semiconductor deviceitself.

G

103

106

109

M

K

1

10

1

0.1

1960 1970 1980 1990 2000

Decade (Generation)

Density (Element Count)

Process Dimensions (µm)

Transition of Products(ProductDevelopment)

IC

GeTRS

SiTRS

LSI VLSI ULSI

15 12 85 3 2 1.3 0.8

0.5 0.3 0.20.1

Figure 1.1 Advancements in Miniaturization of Semiconductors

As the contribution of semiconductor devices to finished products in terms of their function,characteristics and reliability increases daily, further improvement in quality is becoming evermore important. In order to maintain these changes and the device quality, it is extremelyimportant to have a consistent quality assurance system, starting with the planning of developmentdown through the after sales service.

This section describes Hitachi’s quality maintenance and improvement program with focus on ISO9001 quality system, design control, inspections, corrective and preventive actions.

Rev. 1.0, 01/02, page 2 of 292

1.2 Quality Policy (Principle)

Hitachi is one of the leading companies in the electronics industry, striving to contribute to socialdevelopment and prosperity through pursuit of infinite possibilities in accordance with ourprinciples of “No pain, no gain,” “Fight against time,” and “Backup words with action.”

1.3 Quality Objectives

(1) Develop leading-edge technology with innovation and effort, and make products which earnthe customers’ confidence and trust.

(2) Take action with consideration for every partner’s situation.

(3) Honor the basic principles of quality, cost, and delivery.

(4) Create a bright and active work environment through improved communication.

(5) Nurture one’s own ability and character, while striving for the highest goals.

Each and every employee of Hitachi observes and practices the principle of “the customer comesfirst” to contribute to society through products and technology. We will quickly supplyinexpensive quality products, and will consider our objectives have been met if a user can say,“We are extremely satisfied with Hitachi products.” We strive to make all decisions whileconsidering the customers’ expectations.

Rev. 1.0, 01/02, page 3 of 292

1.3.1 Independence of Design, Manufacture, & Quality Assurance Departments

In order to help insure the production of quality products, the Design, Manufacturing and QualityAssurance Departments coordinate their work so that each department has independent authorityover the quality of its own work.

As shown in fig. 1.2, the departments, while independent, coordinate their activities yet, at thesame time retain authority over the final decisions within their respective areas. The QualityAssurance Department retains the responsibility for overall quality, including customersatisfaction after shipping.

The roles of each department are to cover various fields of technology to ensure completecustomer satisfaction. Each Design Department is responsible for each product family, while theSemiconductor Technology Development Center is responsible for handling elementaltechnologies common to each section.

The Quality Assurance Department is organized and managed as shown in fig. 1.3. The QualityAssurance Group liaise directly with customers and coordinate the quality assurance activities ofeach product line. The other groups are the Analysis Group, Parts Quality Assurance Group, andthe Process Quality Control Group. Quality certification is divided into quality certification foreach product line and element technology certification (Standard Technical Measurement), whichmaintain a close working relationship to contribute to continued improvement in quality andreliability.

Rev. 1.0, 01/02, page 4 of 292

Business Planning HQ

Management Improvement HQ

General Sales HQ

System LSI Operations(section)

System Memory Operations (section)

Applied Micro-computer HQ Operation (section)

Design Department

System LSI HQ

Design Department

Advanced Micro-computer HQ

General Production HQ Production Technology Development Center

Production Technology Department

LSI Manufacturing Plant

Manufacturing Department


Kofu Manufacturing Plant

Takasaki Manufacturing Plant

Design Department

Design and Development Department

DRAM Memory Operations (section)


Applied Semiconductor Operations (section)

Sales Department


Semiconductor Technology Development Center

Process Technology Department

Packaging Technology Department

Mask Technology Department


Production Technology Department

Semiconductor and IC Division

Quality Assurance Department

Materials Department

Sales HQ

Sales Department

The 1st and 2nd Sales HQ, Sales HQ for Europe & U.S.A. System LSI Technology HQ

Note: The names of headquarters and departments are selected and arranged to represent their respective functions.

Figure 1.2 Organization Chart of Semiconductor Operations

Rev. 1.0, 01/02, page 5 of 292

Planning Group


Quality Assurance Group

Process Quality Control Group

Quality Certification Group

Analysis Group

Parts Quality Assurance Group

ISO 9000 Promotion Group

Planning and Quality Index Control

Shipping Inspections and Customer Service Desk

Management of Process Quality and Measuring Instrumental Calibration

Quality Certification and Reliability Evaluation Techniques

Characteristic Analysis and Failure Analysis

Certification of Parts and Materials and Acceptance Inspection

Internal Quality Audit

Figure 1.3 Quality Assurance Department Internal Organization Chart

1.4 Contract Review

For customized and semi-customized products, the review of a contract content (contact review)starts when a request for an examination of a customer’s requirements is submitted by Sales to theProduct Headquarters responsible for design and development. This procedure also applies whena customer presents his own purchasing or Delivery Specifications.

The Product Headquarters prepares Delivery Specifications or Development Specificationsaccording to the client’s specifications. Finally, customer agreement to the Specification Notes isconfirmed in the Specification Contract.

The Specification Contract for standard products is made according to product catalogues such asvarious data books, data sheets and manuals.

If there are any amendments to the contractual content, both amendment and confirmation areexecuted according to the amendment and confirmation procedure of the technological contracts.

Rev. 1.0, 01/02, page 6 of 292

1.5 Reliability Design

1.5.1 Reliability Objectives

Hitachi’s concept for the verification of reliability objectives realizes that in order to improve thequality of semiconductor devices, it is essential to incorporate quality and reliability at the designand the development stages of new products. For this reason, the accurate input of customer’srequirements, the execution of design review to prevent recurrences of identified defects, anddesign verification before mass production starts has become extremely important.

As shown in the reliability program (fig. 1.4), we must understand the exact operatingenvironment for new products at the development and design stage, and establish the appropriatereliability objectives. The design, manufacturing, and process management procedures are thendefined.

Rev. 1.0, 01/02, page 7 of 292

Decide Quality Targets CharacteristicsSpecifications

Requested SpecificationStudy

Start Development Program

Market Research

New Devices

New Circuits

Existing Devices

Quality Design Process Design, Standardization,

Electrical PerformanceDesign Review

Development Pilot-runQualification of Partsand Materials

Certificationof Design Quality

Inspection of Partsand Materials

In-process QC Mass Production

100% Testing

Shipping Inspections Feedback

Market

Periodic Reliability Tests

QualityInformation

FailureAnalysis

In-process ModificationControl

Mass Production Pilot-runIn-process QC

Mass Production SampleCertification

Characteristics Approval

Working Samples (WS)

Engineering Samples (ES)

Reliability Data

Commercial Samples (CS)

Planning

Developmentand

Design

MassProductionPilot-run

MassProduction

Figure 1.4 Reliability Monitor Program

Rev. 1.0, 01/02, page 8 of 292

Generally the reliability objectives for semiconductors such as IC’s and transistors are expressedas in terms of a failure rate. As shown in fig. 1.5, the failure rate is represented as a “bathtub”curve plotted against time. The curve is divided into three regions, representing the three stages offailure: initial failure, random failure, and wear-out failure.

Fai

lure

Rat

e λ

(t)

Initial Failure Period: Failure Rate Decreasing (m < 1)

Wear-out Failure Period: Failure Rate Increasing (m > 1)

Prescribed Failure Rate

Random Failure Period: Constant Failure Rate (m = 1)

Functional Lifetime

Time (t)

Improvement in Failure Rate through Maintenance

m: Weibull Distribution Shape Parameter

Figure 1.5 Typical Failure Rate Curve

Each region requires its own reliability objectives to be verified. Since in the initial failure period,failure rate is more important than the time factor, criterion for this region is expressed in ppm(parts per million). The random failure region is expressed in FITs. In the wear-out failure periodconcern is for how long the product can be used. This means that the functional lifetime becomesthe objective standard. It is important to remember that the term “failure” does not mean that thedevice is destroyed or totally malfunctioning. There may be intermittent problems, such as areduction in functions or a decrease in the operating margin. For this reason it is necessary toestablish clear criteria for failure judgment. Further, as described above, since the exact cause of afailure can result from various factors, it is necessary to observe the differences in failure detectionand operating margins used during the product use. As shown in fig. 1.4, Hitachi evaluates qualitythrough:

(a) Quality Design Certification at the Development Pilot-run Stage;

(b) Mass Production Quality Certification at the Mass Production Pilot-run Stage and;

(c) Throughout Mass Production Stage with Periodic Reliability Tests and

(d) Shipping Inspections Outgoing Quality.

The initial failure rate is defined using data from product tests and burn-in data. The randomfailure rate is confirmed (monitored) continuously from data accumulated both from acceleratedlifetime tests and Periodic Reliability Tests, as well as from as much failure rate data as can be

Rev. 1.0, 01/02, page 9 of 292

obtained from the field. The functional lifetime is also confirmed using data from acceleratedlifetime tests, in the same way as in the random failure period.

Since semiconductor devices usually have a long lifetime in the market, it is not feasible to waitfor devices to fail in order to collect accurate reliability data. It is important to evaluate reliabilityin a shorter time frame at the manufacturing plant. This is done using accelerated lifetime tests,which speed up the effect of defects. However, the impact of accelerating conditions such astemperature, humidity, and voltage differs, depending on the failure mode and mechanism. Suchtests are performed at the Development Stage, the Mass Production Pilot-run Stage, and the MassProduction Stage.

1.5.2 Design Review

There are various practical methods that must be used at the Design and Manufacturing Stages todesign-in reliability. Design Review enables us to systematically confirm if the design satisfiesthe performance goals, including customers’ requirements. If the design work is based onstandardized forms, the requirements for technological improvement obtained from theaccumulated test data and field data from each specialist area can be put into effect. It alsoenables us to make products more competitive and to secure suitable product quality andreliability necessary for market value.

We have emphasized incorporating “Quality from the Outset.” The greatest part of design qualityis decided during Design Review. It is critical that Design Review be performed during each stageof the development program in order to incorporate design quality from the beginning ofdevelopment onward. Therefore, both for new products and design-altered (modified) products,Design Review is conducted at the following three stages: during product conception, intermediatedesign, and final design.

For example, if a flaw is found in test production or at the beginning of manufacturing, it takesseveral weeks to amend the product. However, if it is found when the product design iscompleted, all we need is to do is to change a drawing. Thus modifications of basic design haveserious consequences and become more complicated if they are made at later stages of thedevelopment program. Therefore, it is most important to find and improve a potential flaw asearly as possible. We believe that prompt action helps incorporate quality from the outset.

The following steps are employed in the general Design Review process:

(a) Explain product contents based on design documents.

(b) Discuss the design document from the standpoint of each participant’s specialty. If any unclearitems are discovered, organize and execute separate projects, including calculations,experiments and investigations, as needed. Use a Design Review log for follow-up.

(c) Determine the Test Element Group (TEG) reliability test contents and methods based on thecontents of design documents and drawings.

Rev. 1.0, 01/02, page 10 of 292

(d) Verify that the manufacturing plant processing capabilities can meet the design goals.

(e) Procure the equipment and establish the production schedule.

(f) Organize and execute sub-programs for tests, experiments, and calculations to evaluate thedesign modification proposals from each specialist.

(g) Execute plans for the confirmation of test programs, referring to prior examples of malfunctionwith similar product types and confirmation of preventative measures.

Design Review discussions are performed using a standardized Design Review checklist as well asa checklist customized for the specific product.

1.5.3 Design Certification

To help ensure the desired quality and reliability, quality certification, which is based on reliabilitydesign, is conducted at each stage of device design trials and mass production.

The concept is as follows:

(1) Use an objective viewpoint of customers’ situation.

(2) Incorporate examples of past failures and field information.

(3) Certify design modifications and operation alterations.

(4) Certify parts, materials, and processes using stringent criteria.

(5) Investigate the process capability and causes of deviation and varify the control points duringmass production. The process of certification is divided into four steps:

(a) Certification of Parts and Materials

(b) Characteristics Approval

(c) Certification of Design Quality

(d) Mass Production Quality Certification

Design verification for parts and materials is performed during the Certification of Parts andMaterials. Product design verification is covered in Characteristics Approval. Design validationis through Certification of Design Quality. Finally the product quality level on the massproduction line is checked through Mass Production Quality Certification. If modifications of themanufacturing process or operating conditions are necessary after Productive Certification,Hitachi conducts quality re-certification as required.

Certifications are performed for each stage. Quality certification, based on the approach describedabove, is performed as shown in fig. 1.6.

Rev. 1.0, 01/02, page 11 of 292

Confirmation of Characteristics and Reliability Concerning Parts and Materials

Target Specifications Focusing on Electrical Properties

Confirmation of Quality and Reliability Concerning Design

Confirmation of Quality and Reliability during Mass Production

(1) Certification of Partsand Materials

(2) Characteristics Approval

(3) Certification of Design Quality

(4) Certification of Mass Production Quality

Stage Contents

TargetSpecifications

Design Sample

MassProduction

Design Review

Parts and Materials Characteristics:• External Appearance• Dimensions• Thermal Resistivity• Mechanical Properties• Electrical Properties• Other

Electrical Properties:• Function• Voltage• Current• Temperature• Other• External Appearance

and Dimensions

Reliability Test:• Lifetime Test• Thermal Stress Test• Thermal Resistivity Test• Mechanical Stress Test• Other

Reliability Test:• Quality Certification:

Same as (3) above• Process Stability

Check

Purpose

Figure 1.6 Qualification Flow

Rev. 1.0, 01/02, page 12 of 292

1.6 Management of Documents and Data

Documents include Operation Standards, Product Specifications and Manufacturing Instructionsin either printed or in electronic form. Table 1.1 shows the classification of documents accordingto their objectives. The documentation system is shown in fig. 1.7, and fig. 1.8 shows thefundamental system of documentation for Operation Standards and Product Specifications.

Approval, issuance, distribution, and management of all documents are controlled by adocumented process.

Table 1.1 Document Classification

Operation Standards

Regulations of Semiconductor and IC Division,Business Standard,

Technical Standards of Semiconductor and IC Division,Operation Instructions,

Business Operating Standards for each Department

Product Specifications, ManufacturingSpecifications

Drawings, Manufacturing Specifications

Manufacturing Instructions and Arrangement Specifications, Notice

Contract Documents Purchasing Specifications, Delivery Specifications

External Documents Standards and Drawings from Customers,External Quality Standards

Business Operating Instructions, Standards for each Department

Quality (Control)Manual

Regulations ofSemiconductors and IC Division

Technical Standardsof Semiconductors

and IC Division

Business Standards

Drawings, Specifications,Manufacturing Specifications,

Operation Instructions

Figure 1.7 Documents of the Quality System

Rev. 1.0, 01/02, page 13 of 292

Regulations of Semiconductorand IC Department

(Product Specifications)

Technical Standards of Semiconductor

& IC Section

Business Standards

Specifications

ManufacturingSpecifications

Drawings

Notice

Direct Manufacturing Operations Management Operations

OperationInstructions

(Instruction) (Operation Standards)

(TechnicalDepartment)

(ManagementDepartment)

Business OperatingStandards for

each Department

Figure 1.8 The Basic System of Instruction Documents for Product Specifications andOperation Standards

1.7 Quality Assurance System for Affiliated and Associate Companies

Hitachi’s products are produced domestically and overseas by affiliated companies and associatedcompanies. The Quality Control Division of each company is responsible for process control.Information from each Quality Control Division is tied into a network to provide online data andcreating a real-time quality assurance system through the close cooperation among the operationbases of the Semiconductor Operations Department. Fig. 1.9 shows the total quality control(TQC) system for these affiliated and associated companies, including the Quality AssuranceDepartment of the Semiconductor Operations Department. As can be seen below, the preventiveand corrective measures within the Semiconductor Operations Department are carefully executedin partnership with the affiliated and associated companies.

Rev. 1.0, 01/02, page 14 of 292

Affiliated and AssociateCompanies

Semiconductor andIC Division

Issuance of Drawingsand Specifications

Periodic Process AuditAction on StipulatedParticulars

Quality InformationProcess Control DataPeriodic Reliability Test Data

Follow-up

Customer Claims

Shipping InspectionQuality Abnormalities

Necessary Countermeasuresincluding Design Modification

Registration

Issue Inspection Sheet

Shipping Inspection Data

Customer’s Quality Status

AbnormalProcess Quality

ProcessCountermeasures

Issue CountermeasureCompletion Report

Registration

Issue Inspection Sheet (QC report), and

Abnormal Yield Data

PreventionMeasures

CorrectionMeasures

YesImportant?

No

ProcessCountermeasures

Analysisand Investigation

YesModificationof StandardsNecessary?

No

QA meeting

YesImportant?

No

Figure 1.9 Quality Assurance System for Affiliated and Associated Companies

Rev. 1.0, 01/02, page 15 of 292

1.8 Product Identification and Traceability

Products are controlled and identified in single lots for each product type throughout themanufacturing process down to the finished product. Finished products are marked according tothe applicable Product Specification, the product name and the lot identification. Throughout theproduction process to the Shipping Inspections, Operation Notes (Run card) are used in theprocess control for products and lots. With this process, the lot history is traceable.

1.9 Production Process Control

In-process Quality Control is a very important function in the quality assurance of semiconductordevices. Fig. 1.10 shows an example of production process control for semiconductor devices.

Using crystal (wafer) as starting material, processes such as surface oxidation, photo resist, etch,ion implant and diffusion are repeated until the elements of transistors, diodes, resistors, andcapacitors are formed in the wafer. Then metalization interconnects are added by sputtering,photo resist and etch processing. These metallizations connect the devices to each other and to thebonding pads. The semiconductor devices undergo wafer and chip properties inspection in orderto ensure that only acceptable chips or dice are shipped to assembly. The wafers are sawn toseparate the chips. Acceptable quality chips are bonded to the lead-frame (die bonding process),followed by wire bonding. The products are sealed with the packaging material such as plasticmolding compound. Finally, the package undergoes lead forming, marking, electrical test, andexternal visual inspections before reach completion.

Manufacturing Specifications for the process are defined by the Design Department’s drawings foreach product type and the Production Specifications produced by the Manufacturing Department.If a customer requires a change to the specifications of a standard product in terms of electricalproperties, external shape, or appearance, the Design Department issues new drawings with theadditional requirements that distinguish the new product from the standard products. Workers arethen trained the production process requirements to instill the necessary knowledge and skills.

When new equipment is introduced into the process, the Manufacturing Department checks theequipment for its functionality and quality. They conduct inspections on each piece of equipmentto maintain the process capability. The measuring equipment undergoes the periodic inspectionsor calibration using documented methods to maintain the required measuring performance.

Rev. 1.0, 01/02, page 16 of 292

Remove flaws and items with defective crystalsMaintain resistance values

Confirm pinholes and flaws

Confirm dimensional tolerance Photolithography checkControl of foreign matter in Photolithography equipmentConfirm conditions of diffusion

Manage basic characteristics (such as Vth)

Surface purity level and Vth preliminary checkBreakdown voltage level check

Confirm ion implantation condition

Maintain standard film thickness

Particle size, reflection rate, CV characteristics

Confirmation of wafer thickness and quality of surface condition Electrical propertiesEvaluation of chip qualityPrevention of breakages Confirm dicing conditions

Check die bonding qualityPaste wetting characteristics

Bonding quality check

Prevent broken and short circuits

Check conductivity, external inspection

Check conductivity, external inspection

Sealing quality check

External appearance and assurance of dimensionsExternal appearance and assurance of dimensionsExternal appearance and assurance of dimensions

Feedback and analyzed data

Wafer

Photo Resist

Lead Frame

Bonding Wire

Plastic MoldingCompound

Process Flow

Purchase of materials

Surface oxidation

Surface oxidation inspection

Photolithography

Photolithography inspection

PQC level check

Diffusion

Diffusion inspection

PQC level check

Ion implantation

Dose inspection

Sputtering deposition

Deposition inspection

PQC level check

Wafer inspection

Chip characteristics test

Wafer dicing

Chip external inspection

Die bonding

PQC level check

Wire bonding

PQC level check

External inspection after wire bonding

PQC lot evaluation

Molding

PQC level check

Lead forming

PQC level check

Marking

Final inspection of electrical properties Defect analysis

External Inspection

Shipping inspection

Periodic reliability test

Stock/Storage

Shipping

Control Points

WaferOxidation

Photolithography

Diffusion

Oxidation

Ion implantation

Deposition

Wafer

Die bonding

Wire bonding

Molding

Lead forming

Marking

Characteristics and external appearance

External appearance and oxidation film thickness

Dimensions and external appearance

Foreign matter

Diffusion depth and comparative resistanceBase width (Channel length)

Oxidation film characteristicsBreakdown voltage

Specific resistance

Deposition film thickness flaws and contamination

Film qualities

Wafer thickness and external appearance, Vth, resistanceProduct operating characteristics

Chip external appearance

External appearance after die bonding Paste thickness and external appearance

External appearance after bonding

Tensile strength, compressed width, shearing strength, external appearanceExternal inspection

External appearance

Appearance after molding

Internal void and wire layout



Marking strength

Analysis of defective pieces, failure modes, and mechanisms

Control Objectives

: Operation: Assessment: Inspection

Figure 1.10 Example for Quality Control within the Process

Rev. 1.0, 01/02, page 17 of 292

When the Manufacturing Department requires a change in Manufacturing Specifications or ofequipment, the necessary clerical procedures are completed in advance. Fig. 1.11 shows the flowof procedures to make changes.

Since the environment of semiconductor production can be critical, temperature, humidity andpurity within each process are carefully controlled, and as are the materials used in manufacturing,such as gases, chemicals and deionized water. Dust and other airborne particles are minimized bythe care taken in the construction of rooms and facilities. Air filtration systems are employed toreduce airborne contamination, clothing and outside materials are checked for and cleaned of dust,and periodic checks are made for floating dust and floor dirt in the manufacturing site.

Proposed Process Modificationand Improvement Plan

Contents Confirmation

Preparation of Documentation

Contents Confirmation

Determination of the Application of

Modifications*

Pilot-run and PreliminaryInvestigations

Reliability TestsConfirmation of CharacteristicsConfirmation of Pilot-run Data

Evaluation of Results*

Instruction for Application

Application to Mass Production

Report on Results (Quality Assurance Department at each Production Site)

OK

OK

(Planning Section)

(Quality Assurance Department) (Design and Development Department)

NG

NG

* (Quality Assurance Department)

(Production Engineering Department)(Planning Section)

(Planning Section)

* (Quality Assurance Department)

(Planning Section)

(Production Engineering Department)

(Planning Section)

Figure 1.11 Flow Chart of Managing Changes in Mass Production and Operations

Rev. 1.0, 01/02, page 18 of 292

1.10 Inspection

In order to assure the quality of mass produced products, quality-control functions aresystematically divided among the relevant departments, in particular the Manufacturing andQuality Assurance Departments. The flow chart in fig. 1.12 illustrates this process.

Parts and Materials

Partsand Materials

Inspection

ShippingInspection

Process

Inspection of Parts and Materials for Properties Necessary for Use in Manufacturing Semiconductor Devices

Stocking

Lot Inspection for External Appearance and Electrical Properties

Periodic Reliability Test

Shipping

Customer

Manufacturing Manufacturing Equipment, Environment, Sub-materials, and Operator Management

Screening

100% Final Inspection

Quality Control within the Process

Lot Inspection for External Appearance and Electrical Properties

Sampling Judgement

Confirmation of Reliability Level

Confirmation of the Quality Level

Lot Judgement to Cconfirm the Quality Level

100% Inspection

Lot Evaluation and Quality Level Inspection

Parts and Materials

Product

Quality Control

Quality Information

ClaimsField PerformanceOther General Quality Information

Method

Information Feedback

Figure 1.12 Manufacturing Process Quality Control Flowchart

Rev. 1.0, 01/02, page 19 of 292

1.10.1 Acceptance Inspection for Purchased Parts and Materials

The increasing complexity and demands for reliability of semiconductor devices demands acorresponding increase in the reliability of both the materials used in the device structure (such aswafer, crystals, lead frames, bonding wire and packaging) and the manufacturing processes(including masks patterns, photo masks or reticles, photo resist and chemicals).

The pillars for parts and materials quality control are the acceptance inspection together with thesystem of Certification of Parts and Materials described above. To prevent quality problems afteracceptance, the Acceptance Inspection of purchased parts and materials is conducted throughcooperation between the Materials Department and the Quality Assurance Department and isdivided into “control rest products” and “acceptance inspected products.” These inspections areconfirmed to judge, pass or fail on each lot in accordance with the drawings as stipulated by theDesign Department and inspection procedure stipulated by the Quality Assurance Department.

Table 1.2 shows the main checkpoints for parts and materials.

Rev. 1.0, 01/02, page 20 of 292

Table 1.2 Checkpoints for Quality Control of Parts and Materials(Representative Example)

Parts and Materials Main Control Points Points Observed

Wafer External appearance

Dimensions

Specific resistance

Fault density

Crystal orientation

Surface damage, Contamination

Planarity

Resistance value

Fault count

Photo Resist Viscosity

Moisture level

Impurities

Foreign matter

Characteristics

Viscosity

Reaction stability

Fe, Na concentration

Concentration of particles in solution

Sensitivity, Film thickness

Bonding Wire External appearance

Dimensions

Purity

Coefficient of extension

Contamination, Flaws, Deflection, Twisting

Dimensional tolerance

Purity level

Mechanical strength

Lead Frame External appearance

Dimensions

Processing accuracy

Plating

Mounting characteristics

Contamination, Flaws

Dimensional tolerance

Bonding ability

Solderability

Thermal resistively

Ceramic Package External appearance

Dimensions

Air seal leaks

Plating


Electrical properties

Mechanical strength

Contamination, Flaws

Dimension level

Airtightness

Bonding ability

Solderability

Acid resistance

Mechanical strength

Plastic Sealing Resin ormolding compound

Composition

Electrical properties

Heat characteristics

Formability


Various material characteristics

Formability


Rev. 1.0, 01/02, page 21 of 292

1.10.2 Process Inspection

It is essential to eliminate potential causes of failure from the production process of semiconductordevices. Therefore, checkpoints are established and an element or item considered to be a likelycause of failure is prevented from passing to the next process step. To obtain highly reliablesemiconductor devices, it is not enough to merely conduct thorough quality control on carefullyselected production lines and test samples from each lot after each process. To eliminate thosecauses of failure that are due to variations in the production process, it is important to execute “a100% inspection at appropriate process” and, as necessary, such screening as high-temperatureaging and temperature cycling. These tests are executed by the In-process Quality ControlDepartment in accordance with the standards defined by the Staff of the Design, QualityAssurance and Production Departments. The content of In-process Quality Control is listedbelow.

1. Management of conditions by device and operator; standards check for unfinished products

2. Proposals and execution of operation improvements

3. Operator training

4. Maintenance and improvement of yield

5. Detection of quality problems and execution of corrective action

6. Dissemination of quality information

1.10.3 Shipping Inspections

The Quality Assurance Department does the Shipping Inspections, as a final assurance of thequality of customers’ products. It checks that customer quality requirements have been met andthus endeavors to prevent quality problems arising after delivery to the customer. The QualityAssurance Department is responsible for the certifying the quality of shipped products. It alsoconducts Periodic Reliability Tests in order to monitor product reliability.

If a lot fails during Shipping Inspections, the Quality Assurance Department issues an “InspectionSheet” and returns the entire lot to the Manufacturing Department. The ManufacturingDepartment investigates the cause and takes action. The cause and corrective actions are enteredonto the Inspection Sheet, with which the lot, in question, is sent for re-inspection. The QualityAssurance Department rechecks the re-submitted lot and verifies the results of the correctiveactions. Finally, the lot is sent to storage. The inspectors must be qualified to undertakeresponsibility for inspections.

All passes and failures from all inspections, the Acceptance Inspection of purchased parts andmaterials, Process Inspections, and Shipping Inspections are kept on record and filed.

Rev. 1.0, 01/02, page 22 of 292

1.10.4 Control of Inspected Products

For product inspection, each respective department is responsible for designating and marking thelocations for holding un-inspected products (pre-inspection), certified products (passed), andrejected products (failed). The Quality Assurance Department confirms the test results of thecertified (passed) products under the procedure for shipping tests. A designated inspector certifiesthe operations note with the inspectors name and the official stamps of the department responsiblefor the product quality assurance, ensuring that certified products done be shipped.

Rev. 1.0, 01/02, page 23 of 292

1.11 Control of Calibration of Measuring Equipment

Measuring equipment that is used in product inspections and reliability tests, must be calibrated asdescribed below. The calibration procedure is shown in fig. 1.13.

(1) All measuring equipment used in setting up production equipment that has a direct effect onquality, and measuring equipment used in product testing and assessment must be calibrated.Calibrated equipment is registered with the Calibration Unification Department, thedepartment that is responsible for the equipment used in calibrations. After registration andregularly thereafter, the section responsible for calibrated equipment requests the CalibrationUnification Department to maintain and calibrate the equipment. Calibration shall be valid fora defined period. In the cases where it is impossible to directly calibrate equipment built intofacilities or other equipment, a standardized sample is used in the calibration.

(2) The Calibration Unification Department maintains a list of all calibrated equipment andowning department and is responsible for the calibration of equipment when requested to doso. It also notifies the respective departments of the period of validity for all calibratedequipment, stipulating that each department is responsible for requesting re-calibrations withinthe period of validity. The Calibration Unification Department records the period of validityon a prescribed label and attaches the label to the calibrated equipment. The CalibrationUnification Department attaches a failure label to any equipment that fails certification,prohibiting its use. The owning departments repair or dispose of failed equipment. When theequipment is repaired, calibration is repeated. Also, any process or equipment measured withfailed equipment must be traced and appropriate action taken. All calibration documents arefiled for a specified period of time.

(3) The standard instruments used in calibration are calibrated regularly by the National StandardInspection Authority. Records of those calibrations are filed. If it is impossible for theNational Standard Inspection Authority, to trace a standard instrument, another suitablecalibration method is to be provided.

Rev. 1.0, 01/02, page 24 of 292

Calibrated ProductsControl Section

Registration and Applications• New Registrations• Action • Idle• Transfer

Calibration Request

Control of CalibratedEquipment

Response tothe Inspection Sheet

AcceptanceJudgment

Calibration ScheduleReport

Data Input

Calibration Report(Monthly)

CalibrationUnification Department

Control of Registered Calibration Products• New Registration• Acceptance• Schedule Control

Failure

Certified (Passed)

Issue an Inspection Sheet

Attachment of Failure Label

Attachment of a Periodof Validity Label

Confirmation of the Response to the Inspection

Sheet Confirmation of Countermeasures

Figure 1.13 Calibration of Measuring Equipment

1.12 Control of Defective Products

(1) The Manufacturing Department, through an independent inspection process, separatesdefective products by product type according to regulations for evaluation of defectiveproducts. If it is impossible to separate or eliminate defective products during a given process,those products are labeled to distinguish them. The defective products are separated at eachprocess step into an exclusive box for rejects.

(2) Irregular products (including defective products) that occur during the production process aresubject to “irregularity control” which is conducted according to specific and documentedprocedures. The suspect lot is placed in a controlled area to prevent it becoming mixed withstandard lots.

Rev. 1.0, 01/02, page 25 of 292

(3) In cases where a defective lot is found during inspection by the In-process Quality ControlDepartment, an exclusive place for the suspect lot is set up to manage and prevent it becomingmixed with standard lots.

(4) In the case a defective lot is found during Shipping Inspections by the Quality AssuranceDepartment, an exclusive place for the suspect lot is set up to manage and prevent it becomingmixed with standard lots.

(5) Shipping can be suspended as a result of customer claims or at the discretion of the QualityAssurance Department, based on the quality information given in (2)–(4) above.

1.12.1 Verification of Type of Defects and Management Measures

1. Defective product detected during the independent inspection process by the ManufacturingDepartment is scrapped.

2. The cause for irregular product or suspect lots which are subject to “irregularity control” isinvestigated by the inspecting section with the cooperation of the personnel involved. Theinspecting section determines what action should be taken.

3. The Quality Assurance Department issues an Inspection Sheet for failed and suspect productlots stopped at shipping and instructs the department responsible for the defective product toinvestigate the cause and determine what action to take. The action taken is recorded on theInspection Sheet by the responsible department or section. The Inspection Sheet is returned tothe Quality Assurance Department. After verification and approval of the reported cause, thesuspect product is re-inspected by the Quality Assurance Department.

1.13 Corrective and Preventive Measures

1.13.1 Corrective Measures

(1) If a customer finds a defect and makes a claim, the details are relayed promptly to theresponsible and related sections with a prompt report of the claim or Inspection Sheets. At thesame time, the section responsible is required to research the cause and implement correctiveactions. When defective product is found during Process or Shipping Inspections, theinspecting section issues an Inspection Sheet and provides information to the sectionresponsible, which is then required to investigate the cause and implement corrective actions.

(2) The section responsible for the defective product thoroughly investigates and determines thecause by investigation and analysis of the defective product; by investigating the process dataof suspect defective lots, and a review of production history, finally implementing thenecessary corrective actions. The responsible section, clarifies the measures and the extent ofsuspect products, confirms the effectiveness of the corrective actions, completes a Response tothe Inspection Sheet and submits it to the issuing section. If the corrective action changes tospecifications, the section responsible for implementing the corrective actions suggests

Rev. 1.0, 01/02, page 26 of 292

changes to the drawings, which are then made as appropriate. Fig. 1.14 shows a flow chart ofmeasures for customer claims.

Customer



Customer

Sales Department andSystem Technology Department

Sales Department andSystem Technology Department

Design DepartmentManufacturing Department

Failure Analysis

Complaint (Failed Product, Report)

Report

Report

Reply

Recommendations and Confirmation and Execution of Countermeasures

Countermeasures to Prevent Recurrence, and Execution of Countermeasures

Figure 1.14 Flow chart of measures for customer claim

1.13.2 Preventive Measures

(1) To detect, analyze, and eliminate latent failure factors, we preserve records such as customers’claims, process irregularity, process documents, process investigation results, part and productcertification, and investigation and analysis of results of periodic reliability tests. Thenecessary preventive measures are determined and taken at each of these steps.

(2) Each department within the production process, is chartered to improve and maintain qualityand uses “irregularity control” to quickly detect quality irregularities at each moment of theproduction process. Further, the In-process Quality Control Department, working to improvequality management, produces a control chart on various acquired data and defines controlitems for each production process and to detect the quality level within the process.

(3) The Quality Assurance Department identifies quality problems of specific products throughperiodic quality meetings with the respective staff of the Manufacturing and DesignDepartments, and then implements preventive actions and follow-up to prevent recurrence.

Rev. 1.0, 01/02, page 27 of 292

(4) If changes are required, the Technology Department completes the procedures forimplementing changes to the manufacturing process, drawings and standards.

1.14 Handling, Storage, Packaging and Preservation

1.14.1 General

It is necessary to manage purchased in-process parts and materials, unfinished and finishedproducts in a way that avoids harmful effects on product quality. For this reason, the necessarylimitations and tolerances for handling, storage, packaging and preservation must be defined andcontrolled by the respective departments. Further, if a customer has special requirements forproduct specifications, the details of the special specifications are documented in a drawing.

1.14.2 Handling

The procedure for handling parts, materials, unfinished and finished products are standardized,documented and followed to prevent quality deterioration in the respective section. The followingpoints are considered as limitations.

(1) Handling and period of validity after opening packages of parts and materials

(2) Method of transfer of unfinished products and finished wafers to a subsequent process

(3) Controls to protect products from damage due to Electrostatic Discharge (ESD)

1.14.3 Storage

(1) Storage is necessary for purchased parts and materials, finished wafers and products, and ismanaged by each respective department according to defined standards.

(2) Storage is controlled by defining product name and lot number. The number of productentering an area or involved in shipping is controlled.

1.14.4 Packaging

(1) Parts and materials of packaging is labeled with Purchasing Specifications, reflecting theircharacteristics.

(2) When waters are transferred outside of water fabrication area, the packaging method isconducted according to defined specifications.

(3) Product package specification are documented in drawings.

Rev. 1.0, 01/02, page 28 of 292

1.14.5 Preservation

Documented drawings show requirements for preservation measures such as dust-proof andmoisture-proof packaging, buffer, and the other fixed articles, and protection of products.

1.15 Quality Records

1. Each department is responsible for keeping and maintenance of its records related to quality.They are to be titled and filed for the records regarding quality in design, manufacturing andshipping described in the quality manual.

2. If a customer has specific requirements regarding the storage of quality records, and if there isagreement under contractual terms, then additional standards are defined and followed.

1.16 Internal Quality Audit and Periodic Process Survey

The Quality System is audited regularly. Before conducting an audit, the auditor prepares anagenda for all the related departments. In the event that there is some nonconformity or findingwithin the department under audit, the auditor, prepares a report describing the substance of theaudit with approval of Quality Assurance Department manager and submits it to the auditeddepartment. The audited department takes corrective action within a specified period of time, atthe same time compiling a letter of response addressed to the auditor. The corrective action isconfirmed and followed up in one of the following ways.

(1) Confirmation by checking report of results of corrective action

(2) Audit for result of corrective action

In addition to the internal quality audits described above, periodic process surveys are conductedto identify problems in the production process. The process audits conform to the internal qualityaudits in the method of execution and follow-ups, but are conducted with consideration fortechnological content, the real conditions of operation, and comparison of production lines.

1.17 Education and Training

The principles of education for the workplace are self-improvement and OJT (on-the-job training).Off-JT (off-the-job training) is also included in the various educational activities shown in Fig.1.15, the Education System. The chart is divided by level and profession, and by departmentallevel and company level. All elements correspond to their respective business strategies and havea complementary relationship.

Rev. 1.0, 01/02, page 29 of 292

1.17.1 Education at Departmental Level

Before starting a new operation, the respective department provides the required lead-in educationto technicians, inspectors, and designers under its authority. Afterwards, the level of knowledgeacquired is checked and determined. Daily education is executed mainly as OJT and is theresponsibility of each section. As a systematic supplement, education is given as shown accordingto the level of the employee. In order to execute such systematic education according to schedule,the Educational Promotion Section runs educational programs, which supplement OJT and fulfillindividual workplace needs.

1.17.2 Education at the Company Level

The company’s educational institution furnishes the needed education when it supports thebusiness strategies of the company or there is a common need. Administrative training,technological training, technical training, and education for internationalization are all given atthis corporate level.

Each department executes the necessary education, compiles individual education records, andfiles them.

Rev. 1.0, 01/02, page 30 of 292

Office and Technological Works

OJT

Pro

mot

ion,

Sm

all G

roup

Act

ivity

Technical Works

Lang

uage

Edu

catio

n, E

nglis

h S

emin

ars,

In-h

ouse

Eng

lish

Exa

min

atio

n

Dis

patc

h to

Com

pany

Tra

inin

g

Man

ager

E

duca

tion

Sen

ior

Eng

inee

r an

dS

ectio

n C

hief

Edu

catio

n

Ope

ratio

n C

hief

Edu

catio

n

Senior Engineer and Section Chief Training

Administrator Safety Education

Administrator Finance Education

Legal Affairs Training

New Section Chief Education

Department Manager Training


Administrator Finance Education

Legal Affairs Training

Operation Chief Administration Lecture


New Administrators Training

Dis

patc

h to

Com

pany

Tra

inin

g

OJT

Pro

mot

ion,

Sm

all G

roup

Act

ivity

Engineers and Chiefs Administration Lecture


New Administrator Education

Technological Lecture

External Professional Lecture

Cost Education

Trainer Thesis Presentation

Patent Education

Technologic Lectures on Semiconductors

Computer Training

General Clerical Thesis Presentation

Education for the Entrance Examination for Hitachi Technical College

Experience Reporting Meeting

Education in Basic Subjects

General Clerical Lectures

Foreman Safety Education

New Foreman Education

Leader Safety Education

Preservation Work Education

Course for the Certification for the Handling of Chemical Substances

Technical Safety Education

Professional Technical Training

Maintenance Work Education

Technical Ability Developing Training

Technical Training Education (Certification)

Eng

inee

r an

d C

hief

E

duca

tion

Pla

nner

Edu

catio

nG

ener

al C

leric

al E

duca

tion

For

eman

Edu

catio

nLe

ader

Edu

catio

nTe

chni

cal E

duca

tion

Tech

nica

l Com

petit

ions

, Tec

hnic

al E

xam

inat

ions

Edu

catio

nfo

r R

ecru

its

Trai

nees

Edu

catio

nfo

r R

ecru

its

Figure 1.15 Education System

Rev. 1.0, 01/02, page 31 of 292

1.18 Quality Control through Statistical Methods

Hitachi Semiconductor began using statistical quality control methods after they were introducedto Japan from the United States in 1945. At present they are widely used by everyone fromprocess controllers to operators. In particular, the control chart is effectively used to continuouslymonitor process quality for each process and to take definite action in case of abnormalities.Further, SPC (Statistical Process Control) is used as a control not only for suppressing variationwithin the control standards but also for keeping products outside the standard limits below aspecified value by minimizing dispersion and approaching the standard centered values.

In particular, a method was introduced to support quality assurance on the ppm level bycalculating the Process Capability Index (CP, Cpk) and controlling it to realize a higher standardvalue. Hitachi Semiconductor has achieved stabilized and high quality and high reliability for theuser by using CP/Cpk control in the incoming inspections for parts and material, in wafermanufacturing, in assembly, and in the Shipping Inspection process. A high standard CP/Cpk valuehas been realized at each process.

1.18.1 Calculation of the Process Capability Index

Process capability is measured by comparing the actual distribution of a process parameter withthe specification range within which product quality is attainable.

The process capability index (CP) is calculated by dividing the total specification range by sixtimes the standard deviation (6) of the observed process distribution.

The formula is:

Cp = (USL – LSL)/6

The worse-case process capability index (CP k) supplies information on how far the mean of theactual process distribution (designated by X) is displaced from the center of the specificationrange. Expressions in graphs (fig. 1.16) and equations follow.

At the Upper Specification Limit:Cp-usl = (USL – ) / 3At the Lower Specification Limit:Cp-lsl = ( – LSL) / 3

The CP - m i n or CP k is then defined as the lower of those two values.

It is evident that large Cpk values predict a low failure rate. Some examples follow:

Cpk = 1.00 Failure Rate = 2700 ppmCpk = 1.33 Failure Rate = 63 ppmCpk = 1.67 Failure Rate = 0.6 ppm

Rev. 1.0, 01/02, page 32 of 292

It is, of course, necessary to continuously improve centering of the process as well as to reduce itsvariation to decrease failure rates.

Hitachi Semiconductor executes CP, Cpk control on the important parameters in each process.

6 times the standard deviation (σ) of the Process

Parameter Distribution

LSL (Lower Specification Limit)

Distribution of the Process Parameter

USL (Upper Specification Limit)

Mean Value of the Process Parameter

Figure 1.16 Distribution of the Process Parameter

Rev. 1.0, 01/02, page 33 of 292

Section 2 Reliability

This section describes the properties of semiconductor devices from the reliability perspective ofreliability, and the criteria to express reliability quantitatively. Following are accounts of modelsof electronic parts failures and an account of “acceleration coefficients” computation methods.Continued section 2.3.2/2.3.3 present the statistical methods used for reliability analysis.

2.1 Properties of Semiconductor Reliability

Reliability of semiconductor devices can be summarized as follows:

1. Semiconductor devices (fig. 2.1) have a configuration, which is fundamentally very sensitiveto impurities and foreign particles, and the stability status of the surface state is extremelyimportant. Consequently, to manufacture these devices it is necessary to manage manyprocesses while completely controlling the level of impurities and foreign particles.Furthermore, the quality of the finished product is dependent upon the complex relationship ofeach interacting substance in the semiconductor, including the die material, metallization andthe package.

2. The problems of thin films and micro-processes must be fully understood as they apply tometallization and bonding. It is also necessary to analyze surface phenomena form the aspectof thin films.

3. Due to the rapid advances in technology, many new products are developed using newprocesses, and there is a high demand for product development in a short time period.Consequently, it is not possible to apply the reliability achievements of existing devices.

4. The mass-production of semiconductor products has many process steps. In addition, repair offinished semiconductor products is impractical. Therefore incorporation of reliability at thedesign stage and reduction of variation in the production stage have become extremelyimportant requisites for reliability improvement.

5. Reliability of semiconductor devices is dependent may factors, example stress, application,and environment. Stress factors effecting device reliability include: voltage, current density,temperature, humidity, gas, dust, contamination, mechanical stress, vibration, shock, radiation,and strengths of electrical and magnetic fields.

Rev. 1.0, 01/02, page 34 of 292

Al(1) Al(1)

Al(2)

PSGP Emission → Al Corrosion

Through Hole Resistance

Coating DefectCrack → Al CorrosionPinhole

Na Contamination,Moisture Permeation

Passivation Film

Diffusion Layer SiO2

Si Substrate

Crack → Interlayer Short Circuit

Interlayer Insulation Film

Figure 2.1 Semiconductor Device Cross-Section

In recent years high-level functions, systemization, and large (scale) integration have advancedrapidly, therefore ensuring reliability has become extremely important. When discussingreliability it is customary to talk about “Failure Rate.”

Generally, the failure rate of electronic parts and devices, including semiconductor devices, followthe ‘bathtub’ curve as shown in fig. 1.5. The manner in which failures occur can be divided intothree areas or periods—an initial failure period, a random failure period and a wearout failureperiod.

Failures during the “initial failure period” most commonly result from deficiencies in production.During this period the failure rate falls with time and finally becomes stable. The “random failureperiod” is the useful lifetime of semiconductor devices and the failure rate in this period isgenerally constant. The “wearout failure period” (aging period) is a period of concentratedincidence of failures of specific defects coinciding with the end of the component life. Generally,the useful lifetime of semiconductors is long enough provided the application environmentalstresses are not excessive, therefore reliability and integrity of devices are mainly dependent uponthe “initial failure (infant mortality) period” and the “random failure period.”

By using the testing with such techniques as burn-in can usually be screened some ofsemiconductor devices with latent defects. For details on screening see section 4.

Rev. 1.0, 01/02, page 35 of 292

2.2 Reliability Criteria

Reliability is defined by JIS Z 8115 “Reliability Terms” as;

“The features that enable the accomplishment of specified functions of an item under givenconditions for a specific period of time.” In this definition, reliability includes the concept of time.However, initial product quality should be considered independently, irrespective of time. Inpractice reliability is often expressed as the defect rate irrespective of time during this “initialfailure period.”

2.2.1 Initial Failure Period Criteria

In the initial failure period, measurement of defect rate or failure rate against the total number oftested components, irrespective of the time parameter, is generally expressed by (%) or ppm.Where ppm is the abbreviation for “parts per million,” 1 ppm means one defective component outof 1,000,000 semiconductor devices. Therefore, if the defect rate is 100 ppm then there are 100defective components out of 1,000,0000 or 1 component out of 10,000.

2.2.2 Random Failure Period Criteria

In the random failure period it is necessary to consider the time parameter. The following criteriaare used:

Reliability Function

Unreliability Function

Probability Density Function

Conditional Failure Rate Function (Failure Rate Function)

These criteria are related. In particular the unit of FIT (Failure in Time) is widely used, this isexplained in the paragraph on failure rate function below.

(1) Reliability Function and Unreliability Function

The Reliability Function is the proportion of components (devices, parts and elements) whichcontinue to perform their designed functions and remain stable after time (t). This can beexpressed by the equation:

R(t) = [n – c(t)] / n (2-2-1)

where R(t) = Reliability Functionn = The Total Number of Tested Componentsc(t) = The Total Number of Failures up to Time (t)

Rev. 1.0, 01/02, page 36 of 292

On the other hand, the complement of the Reliability Function is the Unreliability Function.

The Unreliability Function, alternatively known as the Cumulative Failure Distribution Function,is defined as the total cumulative number of failures (expressed as the proportion of componentswhich cease to perform their designed functions) up to and including time (t).

This can be expressed by the equation:

F(t) = c(t) / n (2-2-2)

where F(t) = Unreliability Functionn = The total number of tested componentsc(t) = The number of failures to develop up to time (t)

In addition, the following relation is true:

R(t) + F(t) = 1 (2-2-3)

Further, as shown in fig. 2.2, the reliability function R(t) is a monotonically decreasing functionand the unreliability function F(t) is a monotonically increasing function.

1.0

0.5

R(t) F(t)

t10 t2 t3 tn

Figure 2.2 Example of R(t) and F(t)

(2) Probability Density Function

The Probability Density Function (of failures) is defined as the probability of failure of anyparticular device or component after being used for a period of time (t). From this definitionprobability density function can be expressed by the equation:

f(t) dF(t) /dt = dR(t) /dt (2-2-4)

Rev. 1.0, 01/02, page 37 of 292

As can be seen from the above equation, the Reliability Function R(t) and the UnreliabilityFunction F(t) can be calculated by taking the integral of the Probability Density Function, asbelow:

F(t) = ∫ f(t) dtt

0(2-2-5)

R(t) = 1 − F(t) = 1 − ∫ f (t) dt = ∫ f (t) dt∞

0

t

0(2-2-6)

Fig. 2.3 shows a schematic of f(t), R(t), F(t).

f (t )

f (t )

t

F (t) R(t)

Figure 2.3 Schematic of f (t), R(t), F(t)

(3) Failure Rate Function

The Failure Rate Function is also known as the “hazard function.” The Failure Rate Function isdefined as the probability that an item will fail after time t given that it has survived (functionednormally) from initial use up to time (t). The Failure Rate Function, (t), is given by

(t) = f(t) /R(t) (2-2-7)

Using previously described information and by developing equations (2-2-4), (2-2-5), (2-2-6) and(2-2-7), we can calculate R(t) and f(t) and (t).

The Failure Rate Function is also known as the Momentary Failure Rate. This is often used toexpress reliability of semiconductor devices and other components. Momentary Failure Rate istheoretically very accurate, but in practice it is impractical to calculate failure rate at a point oftime in a short period. Therefore, one time period of 1000 hours, one month or one year, isselected and the Average Failure Rate is used.

Average failure rate Total failure in the period / Total operating time in the period

Rev. 1.0, 01/02, page 38 of 292

The values of average failure rates are expressed in unit of % per 1000 hours or ppm/1000 hours.A more commonly term of FIT (Failures in Time: 109 the number of failures in total operationtime) is widely used as the unit to express the degree of failure rate.

1 FIT = 1 10–9 = 1ppm/1000hNumber of failures / (actual number of devices tested actual operation time)

However, if the failure rate is 100 FIT the probability of a failure developing is 1 in 107 ofoperating hours, but this does not mean that the life of an individual component is 107 operatinghours.

It is important to understand that the total operating hours (= actual number of devices tested actual operation time) are not obtained by focusing on one single component.

(4) Cumulative Hazard Function

The Reliability Function R(t) and Failure Rate Function (t) can be determined by expanding (2-2-7) from equation (2-2-4) to produce the following relation shown in equation (2-2-8).

R(t) = exp − ∫ λ(t) dtt

0

(2-2-8)

Further if the cumulative hazard function H(t) is defined by the expression (2-2-10), then

H(t) = ∫ λ(t) dtt

0(2-2-9)

where (t) expresses a Weibull distribution, the following relation applies.

R(t) = exp [– (t /)m]

Therefore, H(t) = (t /)m (2-2-10)

Further R(t) = exp [– H(t)] (2-2-11)

This relation will be applied later to hazard analysis.

Rev. 1.0, 01/02, page 39 of 292

2.2.3 Criteria to Express Lifetime

Like the failure rate, “Time to Failure” is widely used. Time to Failure is defined as the time untilfailure develops in components (devices, parts, and elements) from when they commence to beused.

Generally semiconductor devices cannot be repaired, maintained and reused once a componentfails. Therefore, they can be referred to as non-repairable (non-maintainable) products. Theaverage time for non-repairable components (devices, parts, elements) to fail is defined as theMean Time to Failure (MTTF) and can be expressed by the equation:

MTTF = ∫ tf (t) dt∞

0(2-2-12)

or as the exponential distribution,

where f(t) = exp (– t)

R(t) = exp (– t)

(t) = (constant)

then from equation (2-2-12) MTTF can be expressed as

MTTF = ∫ tλ exp (−λt) dt = 1/λ∞

0

becoming the reciprocal of the failure rate.

2.2.4 Functional Failure—Criteria to Express Malfunction

Functional failure and malfunction do not result from deterioration phenomena. They can bedivided into two types; inherent defects which are detected after assembly, due to undetecteddefects (loophole defects), and defects due to timing, functional combination or malfunctionswhich occur in the application due to particle radiation. The initial failures are expressed in ppm,the latter are expressed in FIT.

As the scale of semiconductor devices increases, measurement of internal circuits becomes moredifficult, the test program of LSI testers become unable to test the internal components 100% andexternal circuits at tester terminals require modification. For this reason, experience shows, whenthe detection rate of a tester is low the functional failure rate tends to increase.

Depending upon the product the customer may be required to provide the test pattern, in whichcase we also select the circuits critical path. This is more effective in reducing functional failurerates by detecting defects in the test pattern.

Rev. 1.0, 01/02, page 40 of 292

Fig. 2.4 shows the relation between the approximate functional failure rate and test detection rates.

1

0.1

0.01

80 10090

Test Detection Rate (%)

Fai

lure

Rat

e (%

)

Figure 2.4 Test Detection Rate and Failure Function

2.3 Reliability Theory

The reliability of semiconductors varies greatly with environmental factors such as junctiontemperature, ambient temperature, humidity, voltage and current. For this reason it is common touse accelerated lifetime tests, based on reliability theory, to estimate the failure rate in theapplication environment (during commercial use).

The accelerated lifetime test is a method to estimate the failure rate of a component during actual(commercial) use. The test focuses on the specific stresses of the environment in which thecomponent is used and observations are made of the failures using the conditions of these stressesas parameters. This method is widely used in the adoption of new processes and the developmentof new products.

Following is an explanation of failure models, which form the basis for accelerated lifetimemodels, and statistical analysis methods.

Rev. 1.0, 01/02, page 41 of 292

2.3.1 Fundamental Failure Model

(1) Reaction Theory Model

The reaction theory model is the most commonly used failure model for accelerated lifetime testsof semiconductor devices. Generally, deterioration and destruction of substances are due tochanges at the atomic and molecular level. The mechanism of such change includes diffusion,oxidation, adsorption, dislocation (displacement), electrolysis, and development of corrosioncracks. The progression of these changes promotes deterioration of material and parts, thensurpasses a certain threshold and finally fails. This is called the reaction theory model. At onepoint in the process, from normal conditions to deteriorated conditions, there is an energythreshold. The energy needed to surpass this threshold must be drawn from the environment.This threshold energy is called the activation energy. Fig. 2.5 shows a schematic of the energycondition before and after the reaction.

Normal State

Activated State

Destructive State

Ea (Activation Energy)

Figure 2.5 Activation Energy

The dependence of reactions on temperature was discovered by Arrhenius and the ArrheniusEquation is widely used.

If the reaction speed is K, then this equation can be expressed as

K = exp (– Ea/ kT)

where : ConstantEa: Activation Energy (eV)k: Boltzmann Constant [8.6159 10–5 (eV/K)]T: Absolute Temperature (K)

If the time to failure is L, then

L = A exp (Ea/kT)

Rev. 1.0, 01/02, page 42 of 292

and by taking the logarithm gives the equation

ln L = A + Ea/ kT

where A: ConstantEa: Activation Energy (eV)k: Boltzmann Constant [8.6159 10–5 (eV/K)]T: Absolute Temperature (K)

This equation shows the logarithm of lifetime (L) plotted against the reciprocal of temperature islinear, and the gradient of the straight line produced represents the activation energy. Then, basedon this, the acceleration coefficient between two given temperatures can be derived.

For example, if L1 and L2 represent the lifetimes at T1 and T2 respectively, then

ln (L1/L2) = 11606 (1/T1 – 1/T2) Ea

This equation provides an acceleration standard to determine the activation energy of a reaction.Fig. 2.6 shows a schematic of this model.

Life

time

(ln L

)

Temperature 1/T (°K−1)

Extrapolation

Activation Energy (Ea)

L1

L2

T2 T1

Figure 2.6 Schematic of the Arrhenius Model

Rev. 1.0, 01/02, page 43 of 292

(2) Eyring Model

While the Arrhenius model emphasizes the dependency of reactions on temperature, the Eyringmodel is commonly used for demonstrating the dependency of reactions on stress factors otherthan temperature, such as mechanical stress, humidity and voltage.

The standard equation for the Eyring model is as follows

K = a(kT/ h) • exp (– Ea/ kT) • Sa

where a, : Constantsh: Planck ConstantS: Stress Factors other than TemperatureT: Absolute Temperature

If the temperature range T is small, then this equation can be expressed as

K = exp (– Ea/ kT) • Sa

Further, if we focus on stress factors other than temperature then lifetime (L) is proportional to 1/Kand then taking the logarithm gives the equation

ln L = A – ln S

where A: Constant

The Eyring equation is often applied to when conducting accelerated tests for stress.

For example consider heat fatigue of plastics. If the stress is represented by alternating reactionstress S and lifetime by a repeated lifetime N then the repeated lifetimes N1 and N2 for thealternating reaction strengths S1 and S2 can be expressed by the equation:

ln (N1/N2) = – ln (S1/S2)

Further in the example of temperature cycle tests by substituting the change in temperature T forstress and let N be the number of temperature cycles to failure, then the above equation can beexpressed as

ln (N1/N2) = – ln (T1/T2)

Fig. 2.7 shows a schematic of the Eyring Model.

Rev. 1.0, 01/02, page 44 of 292

S1 S2

N1

N2

Life

time

(ln L

)

Extrapolation

Stress (ln S)

Figure 2.7 Schematic of the Eyring Model

(3) Stress Strength Model

As shown in fig. 2.8, this model, after previously ensuring a safe margin between material strengthand stress, demonstrates failure when material strength due to deterioration over time falls tobelow stress.

As shown by stress strength distribution failure includes an element of probability.

Rev. 1.0, 01/02, page 45 of 292

Time (t )t = 0

Failure (Overlapping Area)

Strength Deterioration

Stress Distribution

Safety Margin

Strength Distribution

Str

ess

Str

engt

h

Figure 2.8 Stress Strength Model

2.3.2 Probability Distribution Used in Reliability Analysis

(1) Exponential Distribution

The exponential distribution presents a random failure distribution pattern. Many results obtainedfrom semiconductor device reliability tests present a diminishing failure rate, but do not correlatewith the exponential distribution. However, the exponential distribution may be used because, it isthe most fundamental distribution of reliability lifetime tests, and failure incidence is of a randomnature, except for initial failures.

The probability density function f(t) of the exponential distribution, reliability function R(t) can beexpressed by

f(t) = exp (– t) (t 0)

R(t) = exp (– t)

If plotted, this would be as shown in fig. 2.9. (failure rate) is the only characteristic parameter ofthe exponential distribution. MTTF is the reciprocal of .

MTTF = 1/

Rev. 1.0, 01/02, page 46 of 292

f(t)

λ

20 4t

R(t

)1.0

20 4t

t

f (t ) = λe–λt

R(t) = e–λt

λ(t ) = λ const

1M

TT

F λ

( t)

1.0

Figure 2.9 Exponential Distribution

(2) Normal Distribution

Normal Distribution is widely used in data analysis, quality control, managed characteristic valuesand variable (error) distribution. Further, it is also used for failure lifetime (time to failure)distribution. In particular, it is often applied where there is a concentrated incidence of failuressuch as in the wearout period. The probability density function f(t) of normal distribution andreliability function R(t) can be expressed as

f (t) = 1 / (√2π • σ) • exp [− (t − µ)2/ (2σ2)]

R(t) = 1 − 1 / (√2π • σ) • ∫ exp [− (t − µ)2/ (2σ2)] dt (− • < t < + •) t

−∞

The normal distribution, as shown in fig. 2.10, is a symmetrical bell shape with a mean of and astandard deviation of . In general, the normal distribution can be expressed by N(,2), where is the mean and is the standard deviation. At , 2, 3, include (define) adistribution of 68.3%, 95.54%, 99.73% between each, likewise, at 1.645, 1.96, include(define) a distribution of 90%, 95%.

Rev. 1.0, 01/02, page 47 of 292

f (t )

µ–3σ µ–2σ µ–σ µ µ+σ µ+2σ µ+3σ t

Figure 2.10 Normal Distribution

(3) Lognormal Distribution

When ln t, not lifetime t itself, forms a normal distribution, this is called the lognormaldistribution. Probability density function f(t) and reliability function R(t) can be expressed as

f (t) = 1 / (√2π • σt) • exp [− (ln t − µ)2/ (2σ2)] (t ≥ 0)

R(t) = 1 − 1 / (√2π • σ) • ∫ (1/t) • exp [− (t − µ)2/ (2σ2)] dtt

0

(4) Weibull Distribution

The Weibull distribution, used by the Swedish professor Waloddi Weibull in research on metalfatigue lifetime, can be considered an extension of the exponential distribution. The probabilitydensity function and the reliability function can be expressed by

f(t) = (mtm–1/m) • exp [– (t /)m] (t 0, > 0, m > 0)

R(t) = exp [– (t /)m]

where m is the shape parameter and is the scale parameter.

In the Weibull distribution, to determine the proportion of deterioration, or failure rate as afunction of time, the following becomes true:

(t) = mtm–1/m

and

d(t) /dt = m(m – 1) tm–2 /m

Rev. 1.0, 01/02, page 48 of 292

Consequently, for m < 1, m = 1, m > 1 failure rates are decreasing, constant and increasingaccordingly.

As discussed, in semiconductor device lifetime tests, a distribution shape of m < 1 is common. Ifm in the Weibull distribution is determined, the change of failure rate as a function of timebecomes clear. This is helpful to investigate the lifetime phenomena.

Generally, it can be considered that given deterioration phenomena and that failure mechanismshave characteristic failure distribution, therefore, the failure mode (mode of failure) and failuremechanism vary. Moreover, the parameters m and in the Weibull distribution vary relative tovariations in stress (stress variation).

Therefore,

1. When, m does not vary and only varies, then the physical cause of failure does not change, itmay be considered that only the speed of incidence of such phenomena would change.

2. When m varies it may be considered that the physical cause of failure before and after thatmoment also varies.

The Weibull distribution is widely used in failure analysis. In addition, Weibull distributionparameters m, are easily determined using the Weibull probability paper.

2.3.3 Methods of Data Analysis

(1) Reliability Data Analysis Using Weibull Probability Paper

The Weibull probability paper uses the double logarithm of both sides of the distribution functionF(t) to produce a linear graph.

The reliability function of the Weibull distribution is

R(t) = exp [– (t /) m]

F(t) = 1 – R(t) = 1 – exp [– (t /) m]

1/ [1 – F(t)] = 1/R(t) = exp [– (t /) m]

Then taking the double logarithm (a logarithm of a logarithm) on both sides gives

1n 1n 1 / [1 – F(t)] = m 1n t – m 1n

Let X = 1n t, Y = 1n 1n 1 / [1 – F(t)], b = – m 1n

Then Y = mX + b

Rev. 1.0, 01/02, page 49 of 292

This equation produces a straight line from which the shape parameter (m) can be easilydetermined. Also, the scale parameter () corresponds to the time when Y = 0,

Y = 1n 1n 1 / [1 – F(t)] = 1n 1n [1 /R(t)] = 0

1n [1 /R(t)] = 1 R(t) = 1 /e = 0.368

Consequently the time corresponding to when F() = 0.632 becomes the scale parameter.

In other words, the vertical axis represents “the negative log of logarithm of the Weibull function”and the horizontal axis represents the “logarithm of time.” This is known as the WeibullProbability Paper.

In the Weibull Probability Paper the mean lifetime (), and the standard deviation () can beeasily determined.

When (X1,Y1), (X2,Y2) , (Xn,Yn) n sets of data have been obtained, the following is anexplanation of the method of calculation.

From Y = mX + b

The optimum values of m and b can be obtained using the least square method as shown below,

Observation Equation: mXi + b = Yi (i = 1, 2, , n)

Normal Equation: (Xi) m + nb = (Yi)

((Xi)2) m + (Xi) b = (Xi • Yi)

This equation can be solved by

m = [n(Xi • Yi) – (Xi) (Yi)] / [n(Xi)2 – (Xi)2]

b = [(Xi)2 (Yi) – (Xi) (Xi • Yi)] / [n(Xi)2 – (Xi)2]

The value of m obtained here becomes the shape parameter.

Also, when Y = 0 the value of X becomes the scale parameter.

(2) Hazard Analysis

Here we consider an example of a lifetime test of (th) hours on a sample size (n), where the seriesof data consists of a variety of hazards. During this lifetime test, the time (ti) for each failedsample can be determined, however after an interval of time (tj), (m) number of samples areremoved, dismantled and inspected. These (m) samples cannot continue to be tested and theiractual lifetime value cannot be obtained.

Rev. 1.0, 01/02, page 50 of 292

Alternatively, when investigating tensile strength of IC leads, the lead breaks or the lead contactbreaks at the joint, it is necessary to obtain the properties both of the breaking strength of the leadsand of the joints. For analysis of these examples the hazard analysis is a viable method.Following is an explanation of the hazard function and the procedure.

Hazard Function

Taking the Probability Variable for time (t) (t 0), where f(t) is the Probability Density Functionof failures at time (t) and F(t) is the Unreliability function,

then F(t) = f(t) dt and dF(t) / dt = f(t)

and if the hazard function h(t) is defined,

h(t) = f(t) / [1 – F(t)]

from this we obtain,

dF(t) / [1 – F(t)] = h(t) dt

Then taking the integral of both sides of the equation

– ln [1 – F(t)] = h(t) dt

If we substitute with the Cumulative Hazard Function H(t)

H(t) = h(t) dt

this becomes

F(t) = 1– exp [– H(t)]

Then considering Weibull Function as an example

F(t) = 1 – exp [– (t /)m]

Therefore, from the above equations the Cumulative Hazard Function is

H(t) = (t /)m

Then by taking the logarithm on both sides of the equation:

ln H(t) = m (ln t – ln )

Consequently, plotting H(t) and t on Weibull Probability Paper, which has log-log scales, bothproduce a linear relationship and thereby obtaining m and .

Rev. 1.0, 01/02, page 51 of 292

In addition to the Weibull distribution, the Hazard Analysis Paper, consists of the common normaldistribution and lognormal distribution. These are very useful in the analysis of samples with anyhazard that contain;

Data of mixed multi-mode distribution

Interrupted data

Data which, like market data, does not define the correlation between the failed product lot andthe total number of samples

Hazard Analysis Procedure

If we consider observed data at time t, we can analyze this data using table 2.1, following the 6steps of the procedure below.

1. Arrange the observed data, based on statistical procedure, in ascending order, from smallest tolargest values, and enter into the “Ranking (i)” column, also enter the corresponding samplenumber.

2. In the “Reverse (descending) Order” column, label the observed data (n, n – 1, , 2, 1), indescending order from the largest value. This reverse order is expressed by Ki.(Ki = n – i + 1)

3. Using the equation below calculate and record the hazard value h(ti) for each observed value(ti) arranged in ascending order.

Hazard value h(ti) = (ti) ti – 1

if ti – 1 = ti – ti – 1, t0 = 0

then h(ti) = (ti) ti – 1 = (1 /Ki) 100(%)

4. Enter the failure mode into (Mj) column for each observed value. If there is no failure, leavethe cell blank, but enter “C” as the observed value if the sample was removed for inspection.However, j represents the failure mode number.

5. The hazard values which correspond to the failure mode to be analyzed (Mj) are addedsuccessively to calculate the cumulative hazard value Hj(ti).

Hj(ti) = ∑ h(tl )i

1=1(For failure mode Mj alone)

Rev. 1.0, 01/02, page 52 of 292

6. For cumulative hazard values corresponding to failure mode, the shape parameter m, and thescale parameter can be obtained using the same method as shown in section 2.3.3 (1)Reliability Data Analysis Using Weibull Probability Paper.

However, for the Cumulative Hazard Function

When t = ,

then H() = 1.0

Table 2.1 Cumulative Hazard Function

Cumulative Hazard Hj (t i )Sample

No.Ranking

i

ReverseOrder

Ki = n – i – 1

ObservedValue

t i

FailureMode

Mj

HazardValue

h (t i )M1 M2 M3

References:

Hiroshi Shiomi; Introduction to Failure Physics, JUSE Press, 1982

Hiroshi Shiomi; Introduction to Reliability Engineering, Maruzen, 1972

Hisashi Mine, Hajime Kawaii; Fundamental Mathematics of Reliability and Integrity, JUSE Press,1984

Shozo Shimada; Reliability and Lifetime Tests, JUSE Press, 1984

JUSE Press Committee on Reliability Probability Papers: Know-how of Using Probability Papers,JUSE Press, 1982

Rev. 1.0, 01/02, page 53 of 292

Section 3 Failure Mechanisms and Failure AnalysisTechnology for Semiconductor Devices

The objective of the study of failure physics is to understand the underlying causes forsemiconductor device failures in order to attain higher device reliability.

Failure analysis investigates failure phenomena (failure modes) in order to identify failuremechanisms which clearly indicate the causes of failure modes on the atomic or molecular level.

This chapter details the main failure mechanisms found in semiconductor devices.

3.1 Failure Classification

Statistical methods and methods for treating failure from a physical standpoint are used to analyzesemiconductor device reliability. This approach is called failure physics. Its objective is to makefailure mechanisms clear by understanding the physical characteristics of failure down to theatomic and molecular levels.

Semiconductor device failure modes are generally divided into open circuits, short circuits,degradation, and others.

The relationship between these failure modes and their failure mechanisms is detailed in table 3.1.

Rev. 1.0, 01/02, page 54 of 292

Table 3.1 Failure Mechanisms and Modes of Various Device Elements

Failure Elements Failure Mechanisms Failure Modes Example

Diffusion

Junction

Substrate

Diffused junction

Isolation

Crystal defect

Impurity precipitation

Photo resist mask misalignment

Surface contamination

Breakdown voltage decrease

Leak current increase

Short-circuit

Fig. 3.1

Oxide Gate Oxide

Field Oxide

Mobile Ion

Pinhole

Surface states

TDDB

Hot Carrier Degradation


Short circuit

Leakage current increase

HFE and/or Vth drift

Fig. 3.2

Metallization Interconnection

Contact hole

Via hole

Scratch or Void Damage

Non-ohmic contact

Stage sharpness

Adhesion strength defect

Low thickness or step coverage

Corrosion

Electromigration

Stress migration

Open circuit

Short circuit

Increased resistance

Fig. 3.3

Passivation Surface protection

Layer insulation

Pinhole or Crack

Thickness variation

Contamination

Surface inversion


Short circuit

Leakage current increase

HFE and/or Vth drift

Noise deterioration

Die attach Die attach Delamination from frame

Cracked die

Open circuit

Short circuit

Increased thermal resistance

Unstable/intermittent operation

Fig. 3.4

Lead bond Wire bonding Loose wire bond (non-stick-onpad)

Off-center wire bond

Bond pad cratering or damage

Formation of undesirableintermetallic compounds (purpleor tan plague)

Increased resistance

Intermittent operation

Open circuit

Short circuit

Fig. 3.5

Wire lead Inner wiring Cut wire

Loose wire

Open circuit

Short circuit

Fig. 3.6

Rev. 1.0, 01/02, page 55 of 292

Failure Elements Failure Mechanisms Failure Modes Example

Enclosurepackage

Packaging

Hermetic seal

Enclosure gas

Lead frame

Hermeticity

Impure gas

Water intrusion

Exfoliation

Surface contamination

Oxidation of leads

Lead planarity/bent leads

High temperature

Open circuit

Short circuit

Increased leakage current

Solderability failure

Wire/lead corrosion

Fig. 3.7

Foreignmaterial

Foreign material inpackages

Electro-conductive material

Organic/carbon-based material

Short circuit


Fig. 3.8

Input/Outputpin

Surge of staticelectricity

Over voltage

Excess current

Junction breakdown

Oxide damage

Metallization defect/destruction

Open circuit

Short circuit


Fig. 3.9

Others Alpha particles

High electric field

Noise

Electron-hole pair generation

Surface inversion

Soft error


Rev. 1.0, 01/02, page 56 of 292

Figure 3.1 Crystal Defect (Binary Digit Failure of a 16MB DRAM)

Rev. 1.0, 01/02, page 57 of 292

Figure 3.2 SEM Image of an Oxide Pinhole (4MB DRAM Gate Oxide)

Figure 3.3 Break in Al Interconnect (Metallization Failure)

Rev. 1.0, 01/02, page 58 of 292

500 µm

Figure 3.4 Die Crack

Figure 3.5 Bonding Damage

Rev. 1.0, 01/02, page 59 of 292

5 µm

Figure 3.6 Bond Wire Failure Due to Ultrasonic Fatigue

Figure 3.7 Open Circuit Due to Corrosion on Bond Pad

Rev. 1.0, 01/02, page 60 of 292

Figure 3.8 Short Circuit in Package Due to Conductive Foreign Material

Figure 3.9 Break Down Output Pins (Open)

Rev. 1.0, 01/02, page 61 of 292

3.2 Failure Modes and Mechanisms

3.2.1 Oxide Film Degradation Over Time (1) (2)

As the degree of integration increases, MOS IC gate oxide films become thinner.

Supply voltages have also dropped from 5 volts to 3.3 volts and 2.5 volts, but it cannot be entirelyavoided that higher electric fields are applied to the gate oxide films.

Decreased capacitance is a natural consequence of smaller geometries, but can be compensated forby thinner oxide films, especially in DRAMs (Dynamic Random Access Memory). This also hasthe end effect of higher electric fields across the thin oxide films.

Field intensity increases to about 4–5 MV/cm for sub-micron processes. Therefore, oxide filmreliability becomes ever more important. Fig. 3.10 shows the relationship of electric field to oxidethickness, emphasizing the need for reliable oxide films.

Good quality thermal oxide films can withstand electric fields of around 10 MV/cm, but evenlower intensity fields are a major cause of oxidation film (insulation film) failure over time.

100

10

1

Thickness of gate oxide film (nm)

Field intensity inside gate oxide film (MV/cm)

10

1

0.1

( )

( )

Wafer process dimension (µm)

0.1 1 10

Figure 3.10 Scaling of Gate Oxide and Electric Field Fault Phenomenon

Rev. 1.0, 01/02, page 62 of 292

(1) Failure Phenomena

Destruction occurring over time is called TDDB (time dependent dielectric breakdown).

Stressing an actual product under conditions designed to accelerate failures to evaluate its TDDBperformance is difficult. Therefore a specially designed TEG (test element group) is used for thispurpose.

Fig. 3.11 and 3.12 show the results of a TDDB stress of such a TEG. The time-to-failure decreaseswith increased electric field or temperature.

Two general TDDB failure model equations have been proposed, one of them with a directcorrelation to the electric field E, the other with an inverse correlation:

MTTF = A 10–ßE eEa/kT (3-2-1)

and

MTTF = A 10–ß' /E eEa/kT (3-2-1')

where

MTTF: Mean Time to Failure in HoursA: Constantß: Field Intensity Coefficient (cm/MV)ß': Field Intensity Coefficient (MV/cm)E: Field Intensity (MV/cm)Ea: Activation Energy (eV)k: Boltzmann ConstantT: Absolute Temperature (°K)

The values for A, ß, ß', and Ea are usually established empirically for each technology.

The field intensity coefficient ß has been found to have values of 2 or more for oxide thicknessesabove 10nm, based on a direct correlation with the electric field. This resulted in reasonableacceleration values. Values for ß drop to less than 2 for oxides thinner than 10nm.

Work done at Hitachi has established thermal activation energy values in the range of 0.3–0.5 eV,which agrees with values published in technical literature.

The most commonly known value for the thermal activation energy for oxide failure is 0.3 eV. (2)

Rev. 1.0, 01/02, page 63 of 292

Tim

e to

bre

akdo

wn

(s)

Stress electric field (MV/cm)

Tim

e to

bre

akdo

wn

(y)

1018

1017

1016

1015

1014

1013

1012

1011

1010

109

108

107

106

105

104

103

102

101

100

10−1

10−2

1010

109

108

107

106

105

104

103

102

101

100

10−1

10−2

10−3

10−4

10−5

10−6

10−7

10−8

10−9

0 5 10 15 20

FG (−)PWELL (+)

Figure 3.11 TDDB Test Result of a 16MB DRAM Gate Oxide as a Functionof Electric Field

Rev. 1.0, 01/02, page 64 of 292

106

105

104

103

102

101

100

10−1

10−2

Tim

e to

bre

akdo

wn

(s)

1000/ambient temperature (1000/K)

Ea = 0.32eV

200°C 175°C 150°C 125°C 100°C 75°C 50°C 30°C

2.0 2.5 3.0 3.5

Figure 3.12 TDDB Performance of a 16MB DRAM Gate Oxide as a Function ofTemperature

TDDB is affected by both temperature and electric field. The field intensity coefficient ß and thethermal activation energy Ea are often approximated as constants, but for critical forecasting theirdependence on temperature and electric field must be considered. The electric field is thedominant factor on TDDB.

Rev. 1.0, 01/02, page 65 of 292

(2) Failure Mechanisms

Various models are used for TDDB failure mechanisms. The following models are given asqualitative mechanisms:

(a) Positive Charge Model (due to impurity ions, etc.): Impurity ions such as Na+ ions move intime to the negative electrode under the influence of an applied electric field and are capturedby Si/SiO2 surface defects (large trap state density).

As a result, the barrier height becomes non-uniform and a localized increase in current occursin low sections of the barrier, resulting in the eventual failure of the oxide.

(b) Electron or Hole Trap Model: Electrons flow into the SiO2 conduction band from the negativeelectrode due to the Fowler-Nordheim tunnel effect (3) and are accelerated by the electric fieldacross the SiO2. The electrons release phonons and lose energy, but some gain energy in excessof the SiO2 band gap and thus continue collisions and impact ionization.

Electrons quickly pass through the SiO2 because of their high mobility and are trapped near thepositive electrode of the SiO2 film, locally increasing the electric field and eventually causingtotal breakdown of the oxide.

On the other hand, because holes have low mobility, some are lost due to drift and re-combination, while the rest collect near the negative electrode, resulting in a space charge thatpromotes electron injection. These injected electrons leave holes behind as they move.

The level of traps in an oxide strongly influences TDDB, so it is necessary to characterize theoxide quality with accelerated tests and feed the results into design rules. The same results must beused to improve oxide processing in order to reduce oxide fault density.

3.2.2 Hot Carrier

Wafer processing has advanced to higher integration and miniaturization of semiconductordevices, producing new products with physical dimensions in the sub-micron region.

This is the result of intensive and comprehensive efforts in device, circuit, and systemtechnologies, including semiconductor manufacturing facility development, supported bymicroscopic processing technology.

While it is desirable to scale or lower the applied voltage as device dimensions are reduced,system demands often require that the supply voltage remain fixed at 5 volts. One way to avoidexcessive electrical fields on sensitive devices is to include on-board voltage conversion circuitry.Recently, systems have been designed for supply voltages of 3.3 volts and less.

An analysis of scaling effects for devices has been performed to avoid exceeding limit values forfield intensity.

Table 3.2 shows scaling considerations (4) with k as the scaling factor.

Rev. 1.0, 01/02, page 66 of 292

Table 3.2 Scaling to Stay within Field Intensity Limits

Scaling ConsiderationsDimension or Parameter

Constant Electric Field Constant Voltage Quasi-constant Voltage

Oxide Thickness tox 1/k 1/k 1/k

Channel Length L 1/k 1/k 1/k

Channel Width W 1/k 1/k 1/k

Junction Depth xj 1/k 1/k 1/k

T (Si), t (Al) 1/k 1/k 1

Impurity Concentrations Na, Nd k k k

Voltage V 1/k 1 1

Electric Field E 1 k k

Current I 1/k k k

Capacitance C = A/tox 1/k 1/k 1/k

Diffused Resistor L/A k k k

Interconnects L/A k k 1

Contact Resistance k2 k2 k2

Interconnect Current Density k k3 k2

Contact Current Density k k3 k3

For example, when device dimensions (channel length L, channel width W) are scaled by a ratioof 1:2, device area (A) is scaled to a ratio of 1:4.

This also shows that if the impurity concentration (N) is doubled, the voltage (V) and current (I)must be scaled to a ratio of 1/2 in the Constant Electric Field scaling.

Increasing miniaturization without scaling source voltage implies increasing the field intensity ofthe internal elements of a device. This is especially the case for MOSFETs, where the fieldintensity near the drain area increases and a hot carrier degradation effect (device characteristicinstability phenomenon) occurs.

Carriers (electrons or holes) that pour into the high intensity field area are accelerated by thestrong field and gain substantial energy.

Some of the carriers become hot carriers, which means they have enough energy to overcome theelectric potential barrier existing between the Si substrate and gate oxide film.

These hot carriers are injected into the gate oxide film (some are trapped), form a space charge,and over a period of time cause a change or degradation of MOSFET characteristics such asthreshold voltage (Vth) and transconductance (gm ).

Rev. 1.0, 01/02, page 67 of 292

These degradations cause the deterioration of all semiconductor device characteristics andultimately lead to failure.

Injected carriers which are not trapped become gate current, while carriers flowing into thesubstrate are detected as substrate current.

Fig. 3.13 illustrates hot carrier injection mechanisms.

Examples of hot carrier injection are

(a) Channel hot electron (CHE) injection (5)

(b) Drain avalanche hot carrier (DAHC) injection (6, 7)

(c) Secondary generated hot electron (SGHE) injection (7, 8, 9)

(d) Substrate hot electron (SHE) injection (10)

Source ICH

VB

Gate IG

VG VD

VG ≈ VD

Drain Source ICH

VB

Gate IG

VG VD

VG < VD

IBB

IBB

VB VB

VDVG < VD|VB| > 0 VGate IG

VG

DrainSource DrainSource

Gate |VB| >> 0 VIG

ICH

a. Channel HE injection b. Drain avalanche HC injection

c. Secondary generated HE injection d. Substrate HE injection

Drain

Figure 3.13 Hot Carrier Injection Mechanism

Rev. 1.0, 01/02, page 68 of 292

Hot carrier phenomenon will be explained using DAHC as an example, because it causes theworst degradation in the normal operating temperature range.

A high voltage is applied to a MOSFET drain. When the gate voltage Vg is less than the drainvoltage Vd, the device is in the non-saturation range and the channel does not extend to the drainedge. See fig. 3.13 (b). A high electric field area forms near the drain. Electrons flowing out of thesource gain enough energy from the high electric field near the drain to become “hot” electronsand to generate electron-hole pairs by collision with the silicon lattice in a process called impactionization. The electrons and holes thus formed then flow in response to the applied electric fields.

Most of the holes flow toward the substrate, becoming substrate current.

Some holes overcome the potential barrier due to the substantial energy gained from the hotelectrons, and by means of the field from the drain to the gate are injected into the oxidation filmand become trapped there. This generates positively charged trapping sites that are very attractiveto injected electrons.

Most of the electrons generated by the impact ionization are swept up as part of the drain current,while some of them are injected into the gate oxide, ultimately raising the threshold voltage Vth onN-Channel devices. If such an injected electron is trapped in one of the positive traps generatedearlier by an injected hole, the trap returns to a neutral charged state. At the same time an interfacestate is produced (by a mechanism not yet understood) that becomes negatively charged during thetransconductance measurement.

Fig. 3.14 shows the relationship between gate current, gate voltage, and substrate current, withdrain voltage as a variable. (11)

Fig. 3.15 shows the relationship between the degree of threshold voltage (Vth ) degradation, andgate voltage.(11)

It can be seen that Vth degradation increases as the substrate current increases; so it is clear that Vth

degradation and substrate current are closely related.

Rev. 1.0, 01/02, page 69 of 292

TOX = 20 nmLeff = 1.1 µm

VD = 7 V

6 V

5 V

4 V

3 V

lG 7 V

6 V

5.5 V5 V

10−3

10−5

10−7

10−9

10−11

10−13

10−15

0 2 4 6 8 10 12

lBB

Substrate current IBB gate current IG (A/µm)

Gate voltage VG (V)

Figure 3.14 Gate and Substrate Current Dependence on Vg

Rev. 1.0, 01/02, page 70 of 292

Gate voltage VG(V)


As drain

VD(V)

103

102

10

1

8.48.2

8.07.8

7.6

7.4

7.2

7.0

6.8

6.66.4

6.2

6.0

5.8

0 1 2 3 4 5 6 7 8

VG = VD

Threshold voltageshift ∆Vth (mV)

Figure 3.15 Dependence of Vth Shift on Vg Stress

Fig. 3.16 shows the relationship between substrate current and Vth drift lifetime (defined as thetime until Vth changes 10 mV from its initial value).(11)

The relationship between Vth hot carrier degradation and substrate current is as follows: (11, 12, 13)

t = A e–BIsub/W (3-2-2)

where: A, B: ConstantsW: Channel WidthIsub : Substrate Current

In addition to the factors that influence hot carrier degradation, such as drain current, supplyvoltage, channel length, and substrate current, the environmental temperature and the presence ofhydrogen in the protective films must also be considered.

The atomic radius of hydrogen is small, so that even if it is taken into the protective film, it caneasily diffuse throughout the MOSFET. Hydrogen diffuses to the boundary between the gate oxideand the Si substrate and reacts with hot carriers injected from the substrate. This reaction releaseshigh energy in the boundary between the oxide and the Si substrate and breaks down chemicalbonds in OH, Si and O and creates a space charge.

Rev. 1.0, 01/02, page 71 of 292

Most semiconductor failure factors accelerate as temperature increases. However, hot carrierdegradation tends to increase as temperature decreases. This is because silicon lattice vibrationsdecrease with temperature and the probability that electrons flowing in the Si substrate will collidewith the lattice is also reduced. That increases the mean traveling distance of electrons, allowingthem to absorb more energy from the electric field. Consequently, the number of high energy hotcarriers increases and the probability of impact ionization and injected carriers also becomesgreater.

In addition, high temperature facilitates annealing of the oxide damage caused by hot carrierinjection. It is therefore important to evaluate hot carrier degradation under low temperatureconditions.

Fig. 3.17 shows the correlation of substrate and gate currents to temperature. (9) It can be seen thatas the temperature decreases, current values increase.

Device life (∆Vth = 10 mV)

VD(V)2.7 Tox = 7 nm

Leff = 0.25 µm

Tox = 10 nmLeff = 0.5 µm



lDS = 1 mA

Substrate current IBB(A)

107

106

105

104

103

102

10−6 10−5 10−4 10−3

3.8

3.5

2.8

2.9

3.0

Figure 3.16 Dependence of Device Life on Peak Substrate Current

A structure that alleviates or reduces the electric field concentration occurring near the MOSFETdrain edge is an effective technique to reduce hot carrier degradation.

Design measures such as lengthening the channels of MOSFETs with large electric field intensityor optimizing the internal timing in integrated circuits effectively reduce hot carrier phenomena.

Rev. 1.0, 01/02, page 72 of 292

In future, it will be necessary to lower externally applied voltages in order to reduce hot carrierdegradation. At this time, voltage conversion circuits inside the integrated circuit are used to scalevoltages, while the external voltage is left as is.

10−4

10−5

10−6

10−7

10−8

10−11

10−12

10−13

10−14

0 2 4 6 8 10 0 2 4 6 8 10Gate voltage VG (V)Gate voltage VG (V)


VD = 5 V

Temp. (K)

77

300

355420

a.

b.


VD = 5 V

Temp. (K)

77

300355

420

Substratecurrent IBB (A)

Gate current IG (A)

Figure 3.17 Temperature Dependence of Substrate Current and Gate Current

3.2.3 Soft Errors Due to Memory Alpha ( Particles

(1) Soft Error Model

One of the problems which hinder development of larger memory sizes or the miniaturization ofmemory cells is the occurrence of soft errors due to alpha particles. This phenomenon was firstdescribed by T. C. May.

U (uranium) and Th (thorium) are contained in very low concentrations in package materials andemit alpha particles that enter the memory chip and generate a large concentration of electron/holepairs in the silicon substrate.

This causes a change in the electric potential distribution of the memory device amounting toelectrical noise, which, in turn can cause changes in the stored information.

Inversion of memory information is shown in fig. 3.18.

The generated holes are pulled towards the substrate with its applied negative potential.Conversely, electrons are pulled to the data storage node with its applied positive potential.

Rev. 1.0, 01/02, page 73 of 292

A dynamic memory filled with charge has a data value of 0. An empty or discharged cell has avalue of 1.

Therefore, a data change of 1 0 occurs when electrons collect in the data storage node. Such amalfunction is called “memory cell model” of a soft error.

a. Memory information 1 (no electrons) status

b. α ray penetrates, generating electron/hole pairs.Electrons drawn to information storage section holes drawn by substrate supply.

c. Reversal of memory information 1(electron empty) to 0 (electron full)

Polysilicon gates

Information storagesection (no e−)Silicon substrate

α rays

Note: α particles penetrating into the silicon chip cause a high density of electrons and holes, which results in information reversal of the memory cell.

Figure 3.18 Memory Cell Model of Soft Error

The “bit line model” occurs due to change of the bit line electric potential.

The bit line’s electric potential varies with the data of the memory cell during readout, and iscompared with the reference potential, resulting in a data value of 1 or 0.

Rev. 1.0, 01/02, page 74 of 292

A sense amplifier is used to amplify the minute amount of change.

If -particles penetrate the area near the bit path during the minimal time between memory read-out and sense amplification, the bit path potential changes.

An information 1 0 operation error results when the bit path potential falls below the referencepotential.

Conversely, if the reference potential side drops, an information 0 1 operation error results.

The memory cell model applies only to information 1 0 reversal, while the bit path modelcovers both information 1 0 and 0 1 reversals.

The generation rate of the memory cell model is independent of memory cycle time becausememory cell data turns over.

Since the bit path model describes problems that occur only when the bit line is floating after dataread-out, increased frequency of data read-out increases the potential for soft errors, i.e. the bitpath model occurrence rate is inversely proportional to the cycle time.

In product, the “mixed model” combined model describes the combination of the memory cell andbit path models.

(2) Soft Error Evaluation Methods

Evaluating and understanding soft errors due to -particles is an important element of memoryreliability.

Installation tests using actual memory devices are the best source for evaluating memory soft errorfailure rates, but they require large sample sizes and long monitoring times. Specifically, aminimum of 2,000 hours (about 3 months) and a sample size of 500 are required to evaluate to a60% confidence level the soft error rate of a product with a reliability performance of severalhundred FITs.

For that reason, soft error rates are evaluated with accelerated test methods with a particle sourcefor quick evaluation and on products representing standard processing.

Fig. 3.19 shows a simplified evaluation system.

The system, which allows evaluation of the effect of -particle energy and angle of incidence onthe soft error rate is housed in a vacuum and is composed of

-particle source-particle detector to measure the energy spectrum and intensityMemory circuit to be tested

Rev. 1.0, 01/02, page 75 of 292

(RAM = Random Access Memory)

α raydetector

α ray source

Organic film

RAM

Vacuum pumpPattern generator

Multi-channelanalyzer

Figure 3.19 Soft Error Evaluation System

The -particles generated by the -particle source are controlled by an organic film deceleratorand can be directed onto the sample or onto the -particle detector, which measures the energyspectrum and intensity.

By changing the organic film it is possible to match the -particle source energy spectrum to the-particle energy spectrum emitted from the package material.

Varying the -particle intensity is accomplished by changing the distance between the -particlesource and the sample.

Memory operation errors due to -particle irradiation are monitored in the memory operationsection, and the error occurrence rate per unit time is measured.

From this data it is possible to estimate failure rates for the memory under use conditions.

In recent years, evaluations have been done by positioning the source directly in contact with thetop surface of the packaged memory. This accelerated test method is simple and easy.

(3) Countermeasures for Soft Errors

Methods for reducing or controlling memory soft errors due to -particles include

(a) Reduction of -particles emitted from the package material

(b) Coating the chip surface with a material to block -particle radiation from the packagematerial

(c) Reduction of the memory device’s sensitivity to -particles

Rev. 1.0, 01/02, page 76 of 292

Table 3.3 shows -particle emissions from various package materials. Selection of high puritypackaging materials offers the possibility of reducing those emissions.

Table 3.3 Typical -particle Emissions from Package Materials

Package Type Material -particles/cm 2 • hours

Package itself 0.4Ceramic

Metal lid 0.1 or less

Ceramic base cap 0.4Glass seal Package

Seal glass Up to 3

Plastic Package Entire package 0.1 or less

The objective is to reduce -particle emission, so chip coat technology is becoming indispensablein large memory sizes. In order to prevent radiation from the package material from reaching thechip, the chip surface is coated with a material that does not contain radioactive elements such asU or Th.

Hitachi uses a polyimide (PI) coating as a countermeasure to -particles.

Fig. 3.20 shows the effectiveness of PI film for prevention of soft errors.

The failure rate decreases as PI film thickness increases.

PIQ film thickness (µm)

105

104

103

102

10

10 15 30 45

Am α source

Ra α source

Soft error rate(relative values)

Figure 3.20 Soft Error Protection Effect of PIQ

Rev. 1.0, 01/02, page 77 of 292

The main point of strengthening memory devices against -particles is to maintain sufficientcharge per bit. However, the area occupied by one memory cell decreases as memory capacityincreases, so it becomes ever more difficult to maintain sufficient charge per bit.

New memory cell configurations with trench and/or stack structures and improved dielectriclayers are being used to maintain the charge and reduce sensitivity to -particles.

More recently, other cosmic rays (gamma rays and neutrons) and their effects on memory deviceshave become a matter of concern and subject for intense studies.

3.2.4 Retention Characteristics of Non-Volatile Memory

Non-volatile memories retain their data mainly by accumulating electrons in a floating gate withinthe memory cell, such as EPROM/flash memory (stack type gate, fig. 3.21), or by accumulatingelectrons/holes in an MNOS/MONOS gate, such as EEPROM (MNOS/MONOS type gate,fig. 3.22). In addition, FRAM products have come on the market, using the polarizationcharacteristics of ferro-electric materials.

The principle of writing into flash memory (stack type gate) is described in the next paragraph.

Generally electron injection into the floating gate of a flash memory is accomplished by supplyinghigh voltages to the drain (VD ) and control gate (VG ), while the source is at ground potential(fig. 3.21).

Source

VG Control gate

Floating gate

VD

Drain

N+ N+

P-type substrate

Figure 3.21 Stack Type Memory Cell Cross-section

Electrons flowing from the source gain sufficient energy in the high field area near the drain togenerate electron-hole pairs by impact ionization. The generated electrons are injected into thefloating gate due to the high voltage on the control gate. Since the floating gate is insulated fromits surroundings, the electrons become isolated.

The condition under which electrons were injected (write) is defined as data 0. A data 1 conditionexists when electrons are not injected (erase).

Rev. 1.0, 01/02, page 78 of 292

Drain

Control gate

MNOS gate

Source

Si3N4

n substrate

n+ n+n−n−

p well

Figure 3.22 MNOS Memory Cell Cross-section

The write and erase conditions are shown with relation to memory threshold value (Vth ) infig. 3.23.

IDS

1b. erase side

Readvoltage

(+) Gate voltage

0a. write side

Figure 3.23 Stack Type Memory Cell Vth Change

The threshold voltage Vth of a memory cell is high for written state, and low for the erased state.

Rev. 1.0, 01/02, page 79 of 292

(1) Data Retention Characteristics

Writing to EPROM/flash memory is accomplished with hot electrons.

Although the ability to retain the written condition (electrons isolated in the floating gate) for longperiods of time is desirable, there is a finite probability that electrons stimulated by heat will belost because the written condition is essentially non-equilibrium. Electrons isolated in the floatinggate gain sufficient thermal energy to overcome the energy barrier of the surrounding oxide layer.Consequently, the higher the energy barrier between the floating gate and the surrounding oxidefilm, the better the ability of the cell to retain data.

The thermion excitation model expresses the loss of electrons from the floating gate due tothermal excitation:

VCC(t) / VCC(0) = N(t) / N(0) = exp [– v • t • exp (–Ea / kT)]

where VCC: Floating Gate VoltageN: Amount of Charge on the Floating Gatev: Relaxation Frequency (1012 cycles per second).Ea: Activation Energy (eV)k: Boltzmann ConstantT: Absolute Temperature (°K)

The time in this data retention model has a strong correlation to temperature. Fig. 3.24 shows therelation between temperature and time until the non-volatile memory cumulative failure ratereaches 1%, based on the Arrhenius Equation (see section 2.3.1).

It can be seen from the figure that the Ea (activation energy) related to data retentioncharacteristics is 1eV or greater.

Rev. 1.0, 01/02, page 80 of 292

1/T (× (10/T)/K)

1M flashmemory

4 MEPROM

106

105

104

103

102

101

300°C250°C

200°C 150°C 85°C 40°C70°C175°C

2.0 2.5 3.0

256 kEEPROMTime until

accumulatedfailure rate reaches 1% (h)

Figure 3.24 Non-Volatile Memory Data Retention Characteristics

(2) Failure Mechanisms

Data retention for ten years or more is guaranteed if the device is operated within its specifiedoperating temperature range.

However, if there are defects near the floating gate, the memory may not be able to retain data asmentioned above and a failure may occur due to charge loss or gain within a relatively short timeperiod.

Causes of deterioration in data retention characteristic can be divided into two broad categories:

Charge loss/gain due to an initial defect in the oxide film

Data retention degradation due to ionic contamination

If a leakage path or a particle exist in the gate oxide film (fig. 3.25), charge gain or loss occursthrough those defects when a bias voltage is applied to the control gate.

Rev. 1.0, 01/02, page 81 of 292

If the defect is in the interlayer dielectric, (fig. 3.26), no failure occurs in the erased state, butfailure is possible in the written state due to the loss of electrons from the floating gate through thedefect.

Failure for both modes can occur in a short time at elevated temperatures. It is possible toeliminate initial data retention failures by the use of high temperature bias testing (screening) atthe end of the manufacturing process.

Loss of electrons from the floating gate can also be caused by ionic contamination in the oxidefilm. The high temperature bias test (data 1 and 0 mixed or checkerboard pattern) is an effectivescreen for this failure mode also.

Another type data retention degradation occurs in flash memory/EEPROM.

During each write/read cycle, high energy electrons or holes pass through the oxide film.

If this write/read cycle is repeated often enough (typically 1000 times or more), it is probable thatelectrons or holes will become trapped in the oxide film forming interface states and reducing thedifference between the threshold values of the 1 and 0 states.

This causes an intrinsic degradation of data retention characteristics.

Source

Control gate VG

Floating gate

VD

DrainDefect

N+ N+

P-typesubstrate

Figure 3.25 Gate Oxide Defect Mode (Charge Gain)

SourceDrain

Defect

Control gate VG

Floating gate

VD

N+ N+

P-typesubstrate

Figure 3.26 Interlayer Dielectric Defect Mode (Charge Loss)

Rev. 1.0, 01/02, page 82 of 292

3.2.5 Aluminum Migration

(1) Electromigration

Most semiconductor integrated circuits use Aluminum (Al) metallization wires for at least part oftheir interconnects. Electromigration is a design concern for semiconductor integrated circuitsbecause Al metallization films have a polycrystalline configuration with many grain boundaries.Advances in function, speed, and processing on the sub-micron level have caused the currentdensity in the Al metallization to increase to as much as 104 to 105 A/cm2.

Electromigration is the movement of metal ion due to the current flow in a metallization wire. InAl metallization wire, Al ions move in the direction of electron flow. A void occurs near thenegative electrode, and an open failure results. Near the positive electrode hillocks and whiskersdevelop, which lead to failures by shorting to adjacent conductors either laterally or vertically.Fig. 3.27 shows a photographic example.

Figure 3.27 Electromigration Open Failure Example

Rev. 1.0, 01/02, page 83 of 292

Two kinds of forces act on the ions in metal. One (FE) is due to the electric field’s influence onpositively charged ions and is in the direction of the current. The other force (FP) works by thetransfer of momentum from the electrons to the ions. FP is larger than FE.

Al metallization wire have polycrystalline structure and diffusion of metal atoms is of threedifferent types: lattice, grain boundary, and surface diffusion. See Fig. 3.29. In polycrystallinefilms there are many grain boundaries with possible defects and the activation energy of metalatoms on grain boundaries is small. Therefore, grain boundary diffusion is a primary factor ofcurrent transport in Al metallization wire. The thinner the films are, the greater the ratio of surfaceto volume of the conductor becomes, thus increasing the importance of surface diffusion. (16)

Ee

FPFE

Figure 3.28 Ion Movement into an adjacent Lattice Vacancy

DS: Surface diffusionDGB: Grain boundary diffusionDL: Lattice diffusion

DS

DGB

DL

Figure 3.29 Lattice, Grain Boundary, and Surface Diffusion in Polycrystalline Aluminum

Rev. 1.0, 01/02, page 84 of 292

The electromigration failure model equation is expressed (3-2-4) as

MTTF = A J– n eEa / kT (3-2-4)

MTTF: Mean Time to Failure (h)A: Constant Determined by Metallization Type and Structure

J : Current density (MA/cm2) n: Constant (n = 2: refer to J. R. Black (15, 16)) Ea: Activation Energy (eV) k: Boltzmann Constant T: Absolute Temperature of Metallization (°K)

Pulsed currents can flow in many metallization wires within devices. The life of wires underpulsed operation is longer than under the direct current. Lifetime under pulsed current is inverselyproportional to the nth power of the duty cycleratio, where n 2. (17)

(2) Stress Migration

The phenomenon of Al conductor wires failing during 125°C storage or temperature cycling inunbiased condition has been reported. (18, 19) Al wires 2µm to 3 µm width break with no currentbeing forced through them.

This phenomenon, called stress migration, results from the difference in the thermal coefficient ofexpansion of the Al metallization film and the dielectric films above and below. As the Al wirebecome narrower, the probability of one grain boundary crossing the entire width of the Al wireincreases, resulting in a bamboo structure.

Compressive stress in the dielectric films translates a tensile stress to the Al wire. Movement of Alaway from the grain boundary relieves the stress. The result is a slit void that may finally break asshown in Fig. 3.31.

Rev. 1.0, 01/02, page 85 of 292

Figure 3.30 Stress Migration Failure Example

(a)

F

F

F

Bamboo grain boundary

Tensile stress

Movement of AI atom

Start point of void

(b)

F

F

Slit void

(c)

F

Figure 3.31 Slit Void Growth Mechanism

Rev. 1.0, 01/02, page 86 of 292

(3) Silicon Migration

The Al metallization in general use contains 1 to 2% Si. To improve the ohmic characteristics ofthe contact between Al and the diffusion layer (source or drain) to the substrate, anneal, hightemperature heat treatment, is performed. Some of the substrate silicon diffuses into the Almetallization during this anneal cycle, while aluminum migrates into the silicon substrate.

If there is a shallow junction below the contact area, aluminum can migrate to part or all of thejunction, resulting in increased leakage currents or total shorts to the substrate. It is possible toprevent this Al breakthrough by adding silicon in excess of its solid solubility in aluminum. This,however, will result in silicon nodules in the Al metallization. They form and grow because duringheat processing small crystals dissolve and then re-precipitate around the remaining larger onesduring cooling. Some nodules may grow in contacts and over steps. This causes an increase incontact resistance (Fig. 3.32) and possibly in an outright break or short in the metallization at thestep.

Countermeasures include the use of a barrier metal below the Al metallization and siliciding thediffusion layer surface. Sub-micron processes invariably include a barrier metal.

Figure 3.32 Example of Si Precipitation

Rev. 1.0, 01/02, page 87 of 292

(4) Improvement for EM, SM and SiM by applying barrier metal

Tungsten (W) and Titanium (Ti) have high melting points and are used below and/or above thealuminum layer to increase the resistance to Electromigration (EM), Stress Migration (SM) andSilicon Migration (SiM). An example is shown in Fig. 3.33. Tungsten plugs are frequently used incontacts and vias.

Jmax (Ta = 85°C, F(0.01%) = 10 ) [MA/cm2]

Silicon process technology [µm]

MoSi/AlCuSi/MoSiTiW/AlCuSi/TiW

TiN/AlCuSi/Ti/TiN/Ti

Allowable current density (target)Allowable current density (actual situation)0.155

(MoSi)

0.46 (TiV)

0.78 (TiN)

10

1

0.11.3 0.8 0.6 0.5 0.4 0.3 0.25

Trend of metal interconnect structure

Figure 3.33 EM Tolerance and allowable Current Density for Sandwiched MetalInterconnects

Rev. 1.0, 01/02, page 88 of 292

3.2.6 Moisture Resistance (20, 21, 22)

Aluminum corrosion or moisture induced leakage were a problem in the past, but advances inpackaging material technology have improved this situation significantly.

(1) Failure Mode

Moisture penetrating the sealing resin or migrating along the leads will reach the chip surface andcorrode aluminum that is exposed in the bonding pads or at passivation defects such as pinholesand cracks. Failure mode classifications are shown in Fig. 3.34.

Moisture resistance test

High temperature,high humidity

unbiased

Random High potentialside

Low potentialside

Pin corrosion Pin corrosionGrain boundary

corrosion

High temperature,high humidity

bias

Figure 3.34 Classification of Al Corrosion Modes

In high temperature and high humidity, corrosion occurs at random pins due to passivation defectson the device chip surface. Longer exposure times to unbiased conditions typically do not result ina substantial increase in failures. Failures are caused by initial defects of the package or chip dueto manufacturing variation. On another occasion, delamination of the chip surface from sealingresin and contamination to the chip surface are considered to be alternate causes of the samefailure mode.

High temperature and high humidity bias test induces pitting corrosion occurring in the Almetallization on the high potential side and grain boundary corrosion occurring on the lowpotential side. For these modes, wear out failure results for almost every piece in a comparativelyshort time after failure begins. The time to failure due to moisture soaking is directly related to thevolume resistivity.

Rev. 1.0, 01/02, page 89 of 292

Chip surface leakage current due to moisture soaking by the sealing resin is caused by

Insulation resistance degradation of resin

Formation of a water film in the gap between chip surface and the resin

Leakage currents of less than 5pA indicate moisture soaking into the molding compound, while avalue of 5pA or greater indicates the formation of a water film between the chip and resin.

If there is a potential difference across the chip surface, charge will leak to the oxide film betweenthe electrodes and generate a potential of its own. For surface sensitive MOS devices, the potentialon the oxide surface may cause the silicon under the oxide to invert and form a parasitic MOSFETresult in increased leakage currents (Fig. 3.35).

p

n

V0

V0

V

Time increase

0 X+++++++++++++++– – – – – – –

Figure 3.35 Surface Charge Spreading Phenomenon

(2) Failure Mechanism (20, 21, 22)

Fig. 3.36 summarizes the Al corrosion mechanism. The water penetration path is due to resinsoaking, permeability (water diffusion phenomenon), and delamination at the lead frame or diesurface and the sealing resin interface. Moisture entering along these paths collects contaminationfrom the resin or the package surface (flux, cleaning solvents), and becomes a corrosive solutionthat attacks exposed Al metallization.

Rev. 1.0, 01/02, page 90 of 292

Water intrusion Corrosive impurity dissociation

Water intrusion

Corrosive characterof penetrating water,impurity dissociation

Die/resincontact areaseparation

Corrosivewater film

AI electrode exposure

Mechanism

AI electrode Passivation film

Die/resin contactarea separation

AI electrodeexposure

Biastype AI

corrosion

Unbiasedtype AI

corrosion

Resin bulkwater penetration

Bonding surfaceseparation Soiled chip lead

Impurities in resin

Solder installationheat stress

Bonding pad

Passivationdefect

Separation force

Die/resin contactarea stress

Figure 3.36 Cross Section showing Aluminum Corrosion Mechanism

Aluminum (Al) is chemically a very active metal that in air forms a stable, inactive oxide film(Al 2O3 ) of several nm in thickness. If sufficient moisture exists, Al(OH)3 is easily formed, whichis easily dissolved in both acid and alkaline solutions, resulting in pitting. If there is a potentialdifference between the Al wires and if the necessary moisture exists, corrosion will result quicklythrough electrochemical reaction. On the high potential side, Al becomes Al3

+ and reacts with anyOH– nearby to form Al(OH)3. If even small quantities of halogen ions such as Cl– are present, theywill move to the high potential side and react with the Al, causing corrosion fairly quickly. On thelow potential side, Al(OH)3 results from OH– generated from H2 gas generation or O2 reduction.The area near the Al wire becomes highly alkaline, causing alkali corrosion along the Al grainboundaries.

If there is a high concentration of phosphorus in the phosphosilicate glass (PSG) film used as apassivation film, the P2O5 in the PSG film draws moisture and by applied voltage becomes anelectrolyte and selectively corrodes the low potential side Al wire. Recent countermeasuresinclude keeping the phosphorus concentration low in manufacturing and the use of silicon nitrideas a passivation film.

Rev. 1.0, 01/02, page 91 of 292

Estimation of product lifetimes must take into account that moisture-related failures may becaused by a combination of different factors. Formulas and activation energies used to estimatelifetimes must take into account which failure modes are present or dominant. The equation belowtakes into consideration temperature and relative humidity.

MTTF = A • exp (Ea/ kT) • exp ( / RH) (3-2-5)

Where MTTF: Mean time to failure (h)A, : ConstantEa: Activation Energy (eV)k: Boltzmann ConstantT: Absolute Temperature (K)RH: Relative Humidity

This equation is changed as below when Voltage V is applied.

MTTF = A • exp (Ea/ kT) • exp ( / RH) • V –n (3-2-6)

Where n is voltage coefficient.

Below is the equation traditionally used in Japan.

MTTF = A • Vp – (3-2-7)

Where Vp: Absolute Water Vapor PressureA, : Constant

(3) Improvement of Moisture Resistance(20, 21, 22)

Molded plastic packaging is used primarily for economic reasons. Quality and reliability areadvancing rapidly through improvements in chip processes, passivation film specifications, andassembly materials and molding compounds.

Factors enhancing moisture resistance:

Prevention of water film formation on the chip Al metallization

Assembly and sealing materials with low impurity concentrations to prevent metallizationmaterial corrosion even if moisture reaches the Al wire

Improvement of chip surface protective film to prevent moisture from reaching the electrodematerial

Ensuring the bonding strength between the molding compound and the chip surface to preventwater film formation

Use of corrosion resistant metallization

Rev. 1.0, 01/02, page 92 of 292

These procedures are continually being improved to cope with the problem of moisture resistance.The historical improvement of resin sealing materials at Hitachi is shown Fig. 3.37. Stress andimpurities in resin materials are being reduced as chip sizes increase, package types get smaller,and surface mounting becomes more prevalent. Moisture resistance of the present phenol-hardened resins is improved tens of times as compared with the original acid anhydride hardenedresins. Inorganic metal oxides are added to the resin materials to lower impurity levels by servingas ion trap material.

Impurities in the die bonding material also influence moisture resistance, so use of purer diebonding material and cleaner processes are important to improving moisture resistance.

1970 1975 1980 1985 1990 1995

16K 64K 256K 1M 4M 16M 64M

Year

Degree of integration (DRAM)

Demand

Corresponding technology

Physicalcharacter-istics

Productioncharacter-istics

Reliability

Heat stress (MPa)

Heat expansioncoefficient (×10−5/°C)

C1− content (ppm)

U content (ppb)

Flammability

Cure time (sec)

Minimum meltingviscosity (poise)

Moisture resistivity

Temperature cyclingruggedness

Non-flammability

High reliability

Low stress

Low α ray

Solder reflow correspondence

Non-hydrate hardened type

Phenol hardened typeSilicon degradationtechnologySpherical fillet technology

12 8 4–5 3–4 < 2

2.5 2.2 1.9 1.7 1.4 1.0 0.7

1000 100 < 100

100 10 < 1

UL-94 HB UL-94 V-0

120–150 90120 60–90

100–300 300 350 400 500 1000

1 5 10 20–30

1 10 100 500 700 1000

Figure 3.37 Material Characteristic Change

Rev. 1.0, 01/02, page 93 of 292

Chip moisture resistance varies greatly with passivation and Al metallization materials.Phosphosilicate glass (PSG) and nitride film (P-SiN, Si3N4) are used for semiconductor devicepassivation. Phosphosilicate glass is an SiO2 film containing phosphorus to reduce cracking and toprevent migration of Na+ ions that might be present. This film is water permeable and cannot beconsidered a good passivation film for moisture resistance. By comparison, nitride film does notallow water passage and is an excellent passivation film for moisture resistance. It is moreexpensive than phosphosilicate glass, but is more common at present. It provides excellentprotection from surface current leakage and has been used in many of the recent devices.

Printed circuit board assembly has changed from the original insertion type (through-hole)packages in which only the leads were soldered to surface mounting in which the entire package isheated. The package is subjected to temperatures above the resin glass transition temperature(approximately 150°C). The heat stress can cause delamination of the molding compound from thechip surface and decrease moisture resistance. Molding compound stress has been reduced andadhesion improvements have been made to prevent delamination. Prevention of delamination isalso possible through improved passivation specifications. A polyimide type resin coating overthe phosphosilicate glass or silicon nitride passivation alleviates stress to the chip surface duringsoldering and prevents degradation of moisture resistance levels (Fig. 3.38).

PSG + PIQ

PSG

Passivation (PSG + PIQ) SOP14/16 pinStandard logic IC solder heat tolerance temperature (10 sec)

01

101

102

103

230 260 290

Soldering heat tolerance temperature (°C)

PCT: 121°C, 100% RH

Time to 1% cumulative failures (h)

320 350

Figure 3.38 Relation between PCT and Tolerance to Soldering Heat

Moisture resistance is determined by packaging technology (configuration, material design,manufacturing method),chip and passivation specifications.

Moisture resistance levels have been increased through various countermeasures.

Rev. 1.0, 01/02, page 94 of 292

However, further improvement in packaging technology is needed as packages continue tobecome smaller and thinner, chip sizes become larger, board mounting processes change, andoperating environmental conditions become more varied and demanding.

3.2.7 Package Cracking during Reflow Solder Processing

(1) Crack Mechanism

Soldering techniques such as vapor phase, infrared, or convection reflow soldering are commonlyused for surface mount packages. These methods heat the entire package. While all surface mountcomponents on the printed circuit board can be soldered at one time, package cracks due to heatmay occur in plastic semiconductor devices containing large chips. (23, 24, 25, 26, 27) These cracks arisefrom the combination of the moisture that the package has absorbed and heat added duringsoldering. As shown in Fig. 3.39, ambient water vapor diffuses into the resin during storage andwater vapor reaches to the interfaces such as between resin and die pad.

ResinDie

Die pad

Moisture

Contact areaseparation progresses

Water vapor crackingprogresses

Crack

Storage

Reflow mounting(heating)

Atmospheric moistureis diffused in packageduring storage

Frame-resin contactarea separates withwater vapor pressure

Cracking due to watervapor expansionprogresses

External appearanceinspection

Package crack isdiscovered

Figure 3.39 Cracking Mechanism in Reflow Soldering

When packages with absorbed moisture pass through the reflow oven and are heated, the resin-diebonding strength drops, differences in thermal expansion coefficients of the different material giverise to a shear stress, and microscopic area separation or delamination results. Since the speed ofwater vapor diffusion increases at high temperatures, water vapor is forced out of the resin into thedelamination, and with a rise in pressure there, the delamination region expands and the moldingcompound becomes increasingly swollen. The swelling stress is concentrated in the die pad areaeventually a crack in the resin results.

Rev. 1.0, 01/02, page 95 of 292

The stress varies greatly with the amount of moisture content in the resin near the die pad, the diepad size, and the temperature and exposure time.

Inspecting the package with a microscope is a simple method of package crack inspection, but thismethod detects only those cracks that extend to the surface. Recently, ultrasonic techniques,scanning acoustic tomograph (SAT), have become common for non-destructive detection ofinternal delamination and cracks (fig. 3.40). (27, 28, 29)

Location of internal crack

Figure 3.40 Non-Destructive Ultrasonic Inspection for Package Cracks

(2) Problems Caused by Package Cracks

Various types of package cracks are expected and are listed in Table 3.5. Quality problems differ,depending on the type of package crack. Package cracks confined to the back surface occur mostfrequently. As the swollen unit pushes against the printed circuit board, it is displaced from theoptimum assembly location and cannot be soldered correctly. The possibility of degradation ofelectrical characteristics with back surface cracks is small, so this type causes the least damage.The die bonding resin used in Hitachi’s packaging operation adheres more strongly to the die thanto the die pad, so delamination occurs primarily between the die pad and the resin. This is why theproportion of back-surface cracks originating at the die pad is high.

Rev. 1.0, 01/02, page 96 of 292

Table 3.4 Package Cracking Types and Problems

No. Form Illustration ProblemsPackage Crack Form

1

2

3

4

Package back-surface crack

Package side crack

Crack intersecting a bounding wire

Package top-surfacecrack

• Moisture resistivity degradation (minimal degradation)

• Moisture resistivity degradation(minimal degradation)

• Wire damage, open• Moisture resistivity degradation

• Wire damage, open• Wire bond separation• Moisture resistivity degradation

(3) Package Moisture Soaking Characteristics

Package cracks are caused by the diffusion of water around the first interface, the die pad’s rearsurface and the chip’s surface. To calculate the quantity of water in resin, we use the diffusionmodel assuming that water diffuses from package surfaces toward the first interface (fig. 3.41). (24,

30, 31)

Rev. 1.0, 01/02, page 97 of 292

Resin

Package back surface

Die pad

Lead

Die pad

Die

Expanded view

Atmos-phere

Resin

SOP resin thickness: 1 mm

Package backsurface

Contact areawith die pad

Moisturediffusion

Figure 3.41 Water Diffusion Model in Humidification (24)

The concentration of water in resin can be determined using Fick’s diffusion equation.

In case of a one-dimensional diffusion model with resin thickness as x, the diffusion equation is asfollows (equation 3-2-8).

∂C(x,t)∂t

= D ∂ C(x,t)∂x

(3-2-8)

Where C(x, t): Water Concentration at Coordinate x, at Time tD: Diffusion Coefficient

This equation is solved with boundary conditions of before and after moisture soaking. Waterconcentration of resin is calculated using the solution. For example, for the water concentration atdie pad (x = 0), the solution is as follows (equation 3-2-9).

4π

∞

n=0∑1 −C(0,t) = Qs exp − (− 1)n

2n + 1(2n + 1)2π Dt

4d2([ ]) (3-2-9)

Where Qs: Saturated water concentration in resin, which is determined by temperature andhumidity of atmosphere

d: Resin thickness to the first interface

Exponential term of the equation (3-2-9) means speed of moisture soaking and it is inverselyproportional to 2nd power of resin thickness d, so thinner packages become saturated quickly.

Rev. 1.0, 01/02, page 98 of 292

Qs and D are shown below.

Qs = Pn S0 exp (Es/ kT) (3-2-10)

D = D0 exp (Ed/ kT) (3-2-11)

Where P: Pressure of Water Vaporn, S0, Es, D0, Ed: Constants which are determined experimentally for each resin.

Fig. 3.42 shows the calculation result of the moisture soaking in case of 1mm resin thickness(from package surface to die pad). Water concentration near the first interface increases withelapsed time, saturating after about 2000 hours.

1000 h 2000 h

500 h

168 h

48 h

10

8

6

4

2

0 0.2 0.4 0.6 0.8 1

Packagesurface

Contact areawith die pad

Distance into the package (mm)

Resin moisture concentration(mg/cm3)

Figure 3.42 Calculation Result of the Moisture Soaking

(4) Moisture Soaking Weight Gain and Associated Problems

Moisture soaking weight gain (wt%) may be used as indicator of moisture soaking of a package.

Moisture absorption rate = × 100(wt%)W1 − W0

W0(3-2-12)

Where W0: Baseline dried package weightW1: Package weight after soaking

The moisture soaking weight gain is calculated from the total weight change of a package anddoes not give enough information about the local water concentration near the first interface (topsurface of die or rear surface of die pad), which actually causes the crack. The average ofmoisture soaking, weight gain, is therefore a poor indicator of the probability of cracking.

Rev. 1.0, 01/02, page 99 of 292

Water tends to collect near the resin surface, but not much near die pad (fig. 3.43 (a)). Therefore,the average moisture soaking, weight gain, initially tends to overestimate the water concentrationnear the first interface. After sufficient time the moisture soaking is saturated, and enough waterreaches the first interface (fig. 3.43 (b)). Conversely, during the drying process, the resin surfacemay have been dried but water still remains near the first interface (Fig. 3.43 (c)).

Although the moisture soaking weight gain are the same (same area as shown in Fig. 3.43), thequantity of water actually near the first interface is different, so risk of cracks is different.

Bottom side of package

Moisture

Moisture

Moisture

ResinDistribution of moisture content

Die pad

(c) Halfway of drying or baking

Moisture which causes the crack

(a) Halfway moisture soaking

(b) Saturated moisture soaking

The first interface

Figure 3.43 Package Internal Water Distribution in Each State (Same Quantity of Water)

Rev. 1.0, 01/02, page 100 of 292

0.5

0.4

0.3

0.2

0.1

0 20 40 60 80 100

Time (h)

Absorption (wt%)

No crack occurrence

Crack occurrence

Calculated values

Absorption85°C 85% RH

Moisture release85°C bake

Figure 3.44 Package Crack and Moisture Soaking Rate

(5) Moisture Soaking Process in dry packing

Currently many types of surface mount products are shipped in dry packing. IC tray or magazinewith product, desiccant and a humidity indicator are put into a moisture proof bag made fromaluminum-laminated film. The absorbed moisture in the product, the IC tray and the desiccant justbefore packing determines the humidity of the air in the dry packing. Since the moisturepermeability of aluminum-laminated film is very low, the bag can keep humidity constant for along time if there are no defects.

At Hitachi, relative humidity in the bag is controlled to less than 30% throughout production anddistribution. The customer is asked to confirm that the humidity indicator shows less than 30%RHwhen the dry pack is opened. The customer is also asked to store product under specifiedcondition once it has been removed from the bag, and to assemble it under recommendedconditions in order to prevent package cracks.

Moisture soaking process of dry packed surface mount product is shown in Fig. 3.45.

Rev. 1.0, 01/02, page 101 of 292

Moisture

Moisture

Moisture

Moisture

(a) Just after resin mold

(b) Storage in device assembly line

(c) Dry packing

(d) Long storage in the dry pack

(e) Few hours after opening dry pack

(f) Repacking of dry pack

(g) One week after repacking

(h) Opening the dry pack to soldering

— Saturated moisture distribution determined by relative humidity (less than 30% RH) in the dry pack

— Dried perfectly

— Halfway of moisture soaking— Upper limit of storage time is

specified

— Drying package by decreasing moisture of air in the dry pack

— Surface of package is absorbed

— Drying

— Recovery to the beginning

— By limitation of storage time the crack is prevented

Moisture causes the crack

Reflow soldering

Bottom side of package

ResinDiepad

Distribution of moisture content

Moisture while opening dry pack



Figure 3.45 Moisture Soaking Process of Dry Packed Product

Rev. 1.0, 01/02, page 102 of 292

(6) Evaluation of the Soldering Heat Resistance of Dry Packed Products

To evaluate the soldering heat resistance of surface mount packages, it is necessary to reproducethe moisture soaking occurring in storage and to apply a heat stress similar to the actual soldering.

(a) Moisture soaking treatment

Moisture soaking treatment must be equivalent to the actual storage condition of a package. Apackage is classified by whether its packing is dry pack or not. Devices qualified to be storedwithout dry pack may be stored in a warehouse for long times. On the other hand, dry packeddevices stored are stored in the dry pack for a long time, but after the dry pack is opened, theymay be stored at room conditions only temporarily before soldering on a PCB. The devices notused after opening a dry pack may be put back into the dry pack or stored in a controlled dryatmosphere (Ex. dry cabinet) for an long time. These conditions should be considered when thetest devices are humidified.

Moisture soaking saturates after several months of warehouse storage. Therefore it is necessaryto bring the test devices to a saturated condition. Moisture soaking time is shortened byelevated temperature. At 85C, moisture soaking is saturated within 168 to 336 hours, so testdevices are generally soaked at 85C to reproduce the moisture soaking of several months atroom condition. Fig. 3.46 shows saturated moisture concentration characteristics of a resin andmay be used to determine soak conditions for test devices.

The upper limits for storage temperature and humidity are 30C/85%RH for devices that donot require the dry pack. Devices which must be stored in the dry pack are limited to30C/30%RH. The soak conditions for test devices are 85C/85%RH and 85C/30%RHrespectively. Soak times are 168 to 336 hours.

For dry packed devices, an additional moisture soak, the second stage moisture soaking, isneeded to simulate the moisture soaking after the dry pack is opened.

Rev. 1.0, 01/02, page 103 of 292

Saturated moisture concentration of resin (mg/cm3)

Temperature (°C)

12

10

8

6

4

2

0200 40 60 80 100

None dry pack

Dry pack

(correspond to the first stage soaking)

Moisture soaking condition at 85°C

Real storage environment (30°C)

30%RH

50%RH

100%RH

Figure 3.46 Saturated Moisture Concentration Characteristics of a Resin (24)

(b) Storage conditions after opening the dry pack and soak conditions

At Hitachi, six different storage levels (A to F) are defined as shown in Table 3.6. For eachlevel, soak conditions have been determined to make evaluation devices for soldering heatresistance evaluation.

The level is different for each product. Most of the products satisfy Level D, but some Level Eproducts remain. The information on the dry pack is level E even if the product satisfies levelD. If level E specifications do not meet your expectations, please contact Hitachi for the actuallevel of the products you are interested in.

Rev. 1.0, 01/02, page 104 of 292

Table 3.6 Storage Conditions and Equivalent Soak Conditions

Level Dry Pack Real Storage Condition Moisture Soaking Condition Remarks

A NA 30C, 85%RH, 1 year 85C, 85%RH, 168h or 336h This level covers floorlife level of JEDEC*

B A 30C, 70%RH, 1 monthafter opening the dry pack

85C, 30%RH, 168h or 336h +30C, 70%RH, 744h

C A 30C, 70%RH, 336hafter opening the dry pack

85C, 30%RH, 168h or 336h +30C, 70%RH, 336h

D A 30C, 70%RH, 168hafter opening the dry pack

85C, 30%RH, 168h or 336h +30C, 70%RH, 168h

E A 30C, 60%RH, 168hafter opening the dry pack

85C, 30%RH, 168h or 336h +30C, 60%RH, 168h

These levels cover floorlife level 3 of JEDEC*

F A Others

* Floor life provided in JEDEC-IPC/J-STD-020, JEDEC JESD22-A112A, IPC-SM-786A (cf. table 3.11)

A dual stage moisture soaking have been applied for level B to level E in Table 3.6. The firststage soaking is corresponds to soaking under worst-case conditions (30C/30%RH) in the drypack for long period of time. The second stage soaking corresponds to soaking after the drypack has been opened. (32)

The dual stage moisture soaking is an ideal method, which is not dependent on moisturesoaking characteristics of resin or package structure, but it takes a long time to makeevaluation of devices.

Hitachi uses the dual stage moisture soaking. Alternative accelerated conditions such as85C/70%RH may be used to shorten evaluation time. Temperature dependence of moisturesoaking is different for each resin, so soak conditions should be adjusted to the moisturesoaking characteristics of resin and package structure. It is difficult to specify the single stagesoak conditions equivalent to the dual stage soaking conditions, so some margin is needed forthe dual-stage soak by using a more severe condition. If the dual-stage soak produces abnormalfailures, the test is repeated using the dual stage soak method.

For example, Level D devices which have a package resin thickness less than 1.5 mm aresoaked at 85C/70%RH for 24 hours, while package resin thickness of more than 1.5 mm ishumidified at 85C/70%RH for 48 hours. The moisture soak can be completed quickly, butcracks may occur because of the severe condition. The sample passes if there are no cracks. Ifcracks do occur, the test is repeated with the dual stage soak.

Fig. 3.48 shows calculation results of moisture concentration near the first interface and howthe moisture concentration reached inside the package differ for different types of package andresin thicknesses. In this figure, resin thickness is defined from package surface to die pad orchip as shown in fig. 3.47.

Rev. 1.0, 01/02, page 105 of 292

Resin

Bottom surface of die pad

Top surface of die

a

b

Resin thickness: a or b

Figure 3.47 Resin Thickness

Package thickness: below 1.5 mm

Package thickness: over 1.5 mm

30°C, 30%RH, 1 year

(Long period of storage in the dry pack)

85°C, 70%RH, 24h

85°C, 70%RH, 48h

Dual stage moisturesoaking (for level D)

Real storage conditions (level D)

10

8

6

4

2

00 0.5 1

Resin thickness (mm)

Moisture content at the first interface (mg/cm3)

Figure 3.48 Comparison of Soak Conditions for Level D

The dual stage moisture soaking method gives results that are very similar to those under withreal storage conditions. The 85C/70%RH/24 hours soak condition is not enough for thickerresin, so 48 hours is needed for thicker packages.

Rev. 1.0, 01/02, page 106 of 292

(c) Allowed storage condition other than 30C/70%RH

The soak condition described above assumes a worst storage condition of 30C/70%RH.Storage under different conditions results in different maximum storage periods.

Tables 3.7–3.9 show maximum storage periods (including safety margin) after opening the drypack for several resins in temperatures of 20–30C and relative humidity of 30–90%. Allassume that the product has been stored in the dry-pack for long period of time, with30C/30%RH inside the pack. Table 3.10 shows maximum storage period (including safetymargin) for a storage condition of 30C/60%RH/168 hours.

Table 3.7 Level B Product Maximum Open Storage Period*(Standard Value: 30C/70%RH/31 days)

PackageThickness

3.2 mm to 3.5 mm

2.5 mm to 2.8 mm

2.0 mm to 2.2 mm

1.4 mm to 1.6 mm

1.0 mm

Temperature

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

∞∞∞∞∞∞∞∞∞∞∞∞∞∞∞

141

∞∞∞∞∞∞∞∞∞∞∞∞∞∞

52

68

90

80

112

165

∞∞∞∞∞∞∞∞∞

37

48

62

41

54

72

56

79

120

∞∞∞∞∞∞

31

39

50

31

39

51

31

40

54

31

45

75

∞∞∞

23

31

42

19

26

37

12

18

26

5

8

12

1

1

2

19

25

33

14

19

26

9

12

17

4

5

7

0.5

1

1

RemarksRelative Humidity

40%30% 50% 60% 70% 80% 90%

QFJ,Large sizeQFP

QFP, SOJSOP

LQFP

TQFP,TSOP

* Allowable storage period of days after take out devices from the dry pack or the dry cabinet (30C max,30%RH max).

Rev. 1.0, 01/02, page 107 of 292

Table 3.8 Level C Product Maximum Open Storage Period*(Standard Value: 30C/70%RH/14 days)

3.2mm to 3.5mm

2.5mm to2.8mm

2.0mm to 2.2mm

1.4mm to 1.6mm

1.0mm

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

∞∞∞∞∞∞∞∞∞∞∞∞∞∞∞

23

30

40

36

48

67

∞∞∞∞∞∞∞∞∞

17

22

28

20

26

34

27

36

49

∞∞∞∞∞∞

15

19

24

16

20

26

17

22

30

24

33

48

∞∞∞

14

17

22

14

17

22

14

17

23

14

18

24

14

∞∞

11

15

20

10

14

19

9

12

17

5

7

11

1

1

2

10

13

18

9

12

15

7

9

13

4

5

7

0.5

1

1

40%30% 50% 60% 70% 80% 90%

QFJ,Large sizeQFP

QFP, SOJSOP

LQFP

TQFP,TSOP

PackageThickness Temperature Remarks

Relative Humidity


Table 3.9 Level D Product Maximum Open Storage Period*(Standard Value: 30C/70%RH/7 days)

3.2 mm to 3.5 mm

2.5 mm to 2.8 mm

2.0 mm to 2.2 mm

1.4 mm to 1.6 mm

1.0 mm

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

∞∞∞∞∞∞∞∞∞∞∞∞∞∞∞

8

11

14

10

13

17

15

20

27

∞∞∞∞∞∞

7

9

12

8

10

13

9

12

16

14

19

26

∞∞∞

7

9

11

7

9

12

7

10

12

8

11

15

∞∞∞

7

8

11

7

8

11

7

8

11

7

8

11

7

9

13

6

8

10

6

7

10

5

7

9

4

5

8

1

1

2

5

7

9

5

6

9

4

6

8

3

4

6

0.5

1

1

40%30% 50% 60% 70% 80% 90%

QFJ,Large sizeQFP

QFP, SOJSOP

LQFP

TQFP,TSOP


Relative Humidity


Rev. 1.0, 01/02, page 108 of 292

Table 3.10 Level E Product Maximum Open Storage Period*(Standard Value: 30C/60%RH/7 days)

3.2 mm to 3.5 mm

2.5 mm to 2.8 mm

2.0 mm to 2.2 mm

1.4 mm to 1.6 mm

1.0 mm

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

30°C

25°C

20°C

∞∞∞∞∞∞∞∞∞∞∞∞∞∞∞

8

10

13

9

12

16

12

16

21

46

∞∞∞∞∞

7

9

12

7

9

12

8

10

13

10

13

17

∞∞∞

7

8

11

7

8

11

7

8

11

7

9

11

7

9

13

6

8

10

5

7

9

5

6

9

3

5

7

0.5

1

2

5

7

9

5

6

8

4

5

7

2

3

5

0.5

0.5

1

5

6

8

4

5

7

3

4

6

2

3

4

0.5

0.5

0.5

40%30% 50% 60% 70% 80% 90%

QFJ,Large sizeQFP

QFP, SOJSOP

LQFP

TQFP,TSOP


Relative Humidity


(d) Soldering heat condition

The moisture soaked device is heated using infrared, convection, or vapor-phase solderingmethods, or wave soldering method as applicable (see section 4.4, Methods of TestingReliability). The applied heat must be sufficient to simulate actual soldering conditions. Ingeneral, the maximum condition accepted in the semiconductor industry is used.

Hitachi’s methodology is based on EIAJ ED-4701, Amendment 2, testing method A-133A.

(e) Soldering heat method for wave soldering

In the past, it is said that large surface mount LSI can not endure heating by wave soldering. Inthose days, the soldering heat tests were done by the immersion of entire package into thesolder bath (see Fig. 3.49). Cracked packages were the usual result.

It was determined that this test method is significantly more severe than actual conditionsbecause the entire package surface comes in contact with the solder bath, and the packagetemperature rises almost instantaneously.

In actual practice, the package is temporarily held in place on the PCB by an adhesive. As thePCB passes over the solder bath (Fig. 3.50), only the front surface of the device is dipped intothe solder, while the rear surface is not. The resulting package temperature is therefore muchlower than in the original test method mentioned above.

Rev. 1.0, 01/02, page 109 of 292

The soldering heat test has been modified to more closely simulate actual conditions by theadhered package to a PCB as shown in Fig. 3.50. Packages that cracked under the immersionmethod were re-evaluated with the new method. Package cracks did not occur, even at thesevere condition of 260C for 10 seconds.

We re-evaluated many surface mount LSIs and verified that they can be wave soldered with nocracks. (33) (34)

Solder bath

Tweezers

260°C molten solder

Figure 3.49 Manual Dipping (Old Method)

FR-4 or polyamide board

260°C flowing solder

Moving

Figure 3.50 Wave Soldering (New Method)

Rev. 1.0, 01/02, page 110 of 292

(5) Soldering Heat-Test Method in the United States

Storage and assembly conditions for surface mount devices are evaluated in the USA differentlythan in Japan.

JEDEC (Joint Electron Device Engineering Council) and IPC (The Institute for Interconnectingand Packaging Electronic Circuits) Technical Standard such as JEDEC JESD22-A112A and IPC-SM-786A, which are essentially the same, define the methods in general use in the US. JEDECand IPC have jointly published Technical Standard J-STD-020. It has been adopted as the ANSITechnical Standard.

Storage and soak conditions as defined in J-STD-020 are shown in table 3.11. LEVEL-3 toLEVEL-6 define the environmental storage conditions (Floor life) after the dry pack has beenopened and corresponding soak time. Soak time for LEVEL-3 to LEVEL-5 is 24 hours longer thanthe floor life.

The Manufacturer’s Exposure Time (MET) is defined as the sum total of the time to seal thedevices into a dry-pack after baking them plus the elapsed time between opening the bag and re-packing the bag in the distributors. Maximum MET is set at 24 hours.

EIA/JEP113-A specifies the maximum relative humidity in the moisture proof bag as 20%RH. Incontrast, J-STD-020 defines soak time under the assumption that the device is completely dry(0%RH) and relative humidity of 20%RH is not considered.

Peak temperature for infrared or air reflow and vapor phase reflow is 220C.

Table 3.11 Storage Levels per J-STD-020

Storage Environment and Time Soak Requirements

LevelTemperature

RelativeHumidity

MaximumTime

TemperatureRelativeHumidity

Time

1 90% Unlimited 85%

2 1 year

85C 168 hours

3 168 h 24 h + 168 h

4 72 h 24 h + 72 h

24 h 24 h + 24 h5

48 h 24 h + 48 h

6

30C

60%

6 h

30C

60%

0 + 6 h

The JEDEC/IPC Standards specify single-stage moisture soaking. This is based on the assumptionthat devices in the dry packs are completely dry (0%RH). To achieve this condition, the devices,IC tray, etc. should be packed as soon as bake-out is completed and relative humidity of 0% insidethe dry pack must be checked by humidity indicator card. That assumption must be met in order tobe able to evaluate devices per the US Standards.

Rev. 1.0, 01/02, page 111 of 292

In Japan, devices may be stored in a humidity-controlled cabinet or room for an long period oftime, to be used as needed. That methodology accepts the fact that the devices cannot becompletely dry due to the storage environment and time. An evaluation using Japanese testmethodology is therefore needed if devices are to be stored out of the bag in humidity controlledcabinet or room, even if they have passed under the JEDEC/IPC Standards.

It must be recognized that un-used devices will not recover back to the dry condition even if theyare re-packed in the bag. There is not enough desiccant in the dry pack to keep humidity at thespecified level unless the bag remains hermetically sealed intact, so damage due to pinholes mustbe avoided.

By contrast, devices evaluated with the dual stage moisture soaking can be stored for an long timeperiod in a cabinet or room in which humidity is controlled to less than 30%RH. Should amoisture-proof bag develop a pinhole, the devices can still be used as long as the humidity in thebag is less than 30%RH, which can be checked with the indicator in the bag. Un-used devices re-packed in the dry pack with desiccant will be recover to 30%RH in several days.

It is therefore necessary to understand what test methods were used to evaluate the devices,especially if only JEDEC/IPC methodology was used. Therefore JEDEC is revising J-STD-020that will be applied relative humidity of 10% inside the dry pack, under relationship betweenJEDEC and EIAJ.

Rev. 1.0, 01/02, page 112 of 292

3.2.8 Electrostatic Discharge

Semiconductor devices are known for their miniature geometry. High-speed large-scale devicesare based on this miniature geometry and are therefore easily damaged by electrostatic discharge.

This damage is a problem for both device manufacturers and electronic instrument makers.Semiconductor manufacturers have designed protection circuits, but geometry constraints place anupper on their capability, so it is necessary to handle semiconductor devices carefully duringprocessing, assembly and use to avoid damage due to electrostatic discharge.

Please refer to section 6.4 for handling precautions.

(1) Device Damage

Devices can be damaged or destroyed by electrostatic discharge (ESD) as a consequence of thelocal heating caused by the discharge current flowing in the device and or by device breakdowncaused by the electric field.

The Si and SiO2 used as the primary materials in semiconductor devices can by nature withstandheat and voltage stress very well, but due to miniaturization of the devices, discharge currentdensity is so high that melting and destruction of insulation layers occur.

Insulation films can be destroyed by voltages due to currents flowing through resistances and bypotential differences caused by sudden changes in currents flowing in inductances andcapacitances.

Rev. 1.0, 01/02, page 113 of 292

Table 3.12 MOS Type Device Failure Due to Electrical Stress

Failure Mechanism Stress Factors Failure Characteristics

Bonding wire breakdown due tomelting

EOS Generated by large current. The broken ends of wireare rounded

Melting metal breakdown Mainly EOS Generated by large current. Hillocks as inelectromigration are not seen

Melting polysilicon breakdown EOS or ESD For polysilicon, as resistance values are large, powerconcentrates and melting occurs easily

Contact section damage EOS or ESD Due to reverse bias current in junction, heat istransferred to contact section and aluminummetallization melts

Heat degradation of oxidation film EOS or ESD Junction reverse bias current heat is transferred tooxidation film, resulting in degradation

Side area polysilicon resistancedamage

EOS or ESD Related to heat caused oxidation film degradation,heat transferred through oxidation film meltspolysilicon

Junction degradation EOS or ESD Generated by junction reverse bias current heat andthe like

Hot eletron trapping EOS or ESD Carriers accelerated by high electric fields aretrapped in MOS transistor oxidation films

Oxidation film degradation due toelectric field

Mainly ESD Generated by application of voltage to gate oxidationfilm

As shown in table 3.12, damage due to ESD and electrical over-stress (EOS) such as surges resultin similar failure modes, and it can be very difficult to determine which was the cause.

For example, high energy EOS is typically the cause of wires that have melted open, but lowenergy EOS and ESD result in similar damage and failure analysis becomes complicated, andthere are many cases where the true cause cannot be determined. (35, 36)

Device damage by EOS can be classified into junction breakdown, oxide breakdown, breakdownof metallization interconnects, and parametric drift due to charges being injected into the oxides.

The mechanisms of junction, metallization film, and oxide breakdown are somewhat differentfrom each other, but heat is one of the causes common to all.

For example, the well-known Wunsch & Bell model explains that junction breakdown is causedby the melting of silicon at a junction when the local temperature is exceeds the melting point ofSi, which is 1415°C or 1688K. The temperature rise is due to the adiabatic heating caused by thereverse bias ESD current.

Rev. 1.0, 01/02, page 114 of 292

The allowable applied power per unit area of the junction (P/A) is expressed in the followingequation. (37, 38, 39, 40)

= √πKρCp (Tm − Ti) t−1/2PA

(3-2-13)

where P: Applied Power (W)A: Junction Area (cm2)K: Thermal Conductivity near the Junction (Si: 0.306 W/cm • K): Junction Density (Si: 2.33 g/cm)Cp: Specific Heat of the Junction (Si: 0.7566 J/g • K)Tm: Junction Melting Temperature (Si: 1688°K)Ti: Junction Initial Temperature (Room temperature = 298°K)t: Pulse Width (ESD duration)

All values with the exception of the pulse width (t) are constant, so power tolerance per unit areais proportional to t -½.

Fig. 3.51 shows a plot of experimental values, which fall between those calculated from theequation above and 1/10 of those values.

= 181t −1/2PA

PA

: Examples based on different semiconductor devices

104

103

102

10

10.01 0.1 1.0 10 102 103 104

Pulse width, time (µs)

Power per unit area (kW/cm2)

, , , = 1809.7t −1/2

Figure 3.51 Wunsch & Bell Plot

Rev. 1.0, 01/02, page 115 of 292

In an oxide film, leakage currents increase due to a high electric field until finally damage ordestruction occurs due to Joule heating.

A change of device parameters is due to charge injection into the oxide caused by local potentialdifferences. Such changes may recover or anneal out at elevated temperatures.

Failure analysis is difficult since there are no visual indications for this failure mode.

(2) ESD Phenomena that Cause Damage (41) (42)

Electrostatic damage of devices occurs when ESD current flows within the device. ESDphenomena are divided into three classifications:

Human Body Model (HBM)

Charged Device Model (CDM), which includes the Charged Package Model (CPM)

Field Induced Model

Field induced ESD occurs when MOS devices are placed in a high electric field and the deviceconductors (lead frame, interconnects) are induced. The resulting voltages cause oxide breakdown.This type is rare and will be omitted here.

(a) Human body model

Fig. 3.52 shows the Human Body Model (HBM): A human body charged with static electricitytouching a device and discharging to a device pin.

If any of the other pins are grounded or connected to a potential, a discharge current passesthrough the device and the device can be destroyed.

Chargedhuman body

DischargeCurrent

Device

GND

Figure 3.52 Example of Human Body Model Discharge

The ESD test circuit for the HBM is illustrated in fig. 3.53. The charge on capacitor Crepresents the amount of charge on a typical human body. The resistor R simulates the skinresistance. EIAJ and MIL standard specify 100pF and 1500. See table 3.12. Conditions usedwidely in Japan (R = 0, C = 200pF) do not consider skin resistance and are called theMachine Model (MM) outside of Japan. EIAJ merely makes reference to it because the modeldoes not correlate with field failures.

Rev. 1.0, 01/02, page 116 of 292

High voltagepower supply DUTC

R

Figure 3.53 ESD Test Circuit for Human Body Model

Table 3.13 HBM Method ESD Test Standards

Technical Standard Resistance Capacitance # of Pulses

EIAJ ED-4701-1, C-111A 1500 100 pF 3 each positive and negative

Reference 0 200 pF 1 each positive and negative

MIL-STD-883D, M3015.6 1500 100 pF 3 each positive and negative

(b) Charged device model

As automation of assembly increases, there are fewer operations in which humans touchdevices, and ESD countermeasures for HBM have proved effective. Therefore, ESD damagedue to HBM is declining.

However, CDM discharge is increasing with expanding process automation and this problemshould be investigated. (41, 42, 43, 44)

In addition, almost all electrostatic discharges start with discharge that is equivalent to theCharged Device Model, so this model is the most important ESD model. (45) (46)

CDM discharge occurs when a charged device pin comes in contact with metallic objects on apiece of equipment. (Figure 3.54)

Devices become charged through friction or by electrostatic induction from another chargedobject or from its own charged package surface. The latter charging model is referred to as theCharged Package Model (CPM). (47) All conductors of the device (chip, lead frame, bond wires)are charged equally. In both cases the phenomenon is the same at discharge.

Discharge

Metal plate, etc.

Dropped, etc.

Charged device

Figure 3.54 Charged Device Model Discharge

Rev. 1.0, 01/02, page 117 of 292

ESD damage due to CDM is caused by the current concentration discharging all of the storedcharge through the pad of the discharge pin.

The discharge current waveform shows oscillations of several GHz as shown in fig. 3.55, andis accompanied by severe transients within the device. Oxide damage results in most cases dueto excessive voltage spikes, but thermal damage sometimes occurs due to energyconcentration.

1A/div

0

500ps/div

Figure 3.55 Discharge Current Waveform for 16-Pin DIP Charged to 500 V

An example of CDM method ESD test circuit is shown in fig. 3.56.

High voltagesupply

Relay activatedsupply & trigger

108 Ω

1 Ω 50 Ω

SW1

SW2

Oscilloscope

ZIN = 50 Ω

Note: After charging the device through switch 1, release switch 1, close switch 2, and discharge from the device.

Figure 3.56 CDM Method ESD Test Circuit Example

Rev. 1.0, 01/02, page 118 of 292

Due to the high frequency of the discharge, it is influenced by the distributed parameters of thedischarge path. Therefore, IC sockets cannot be used in actual test circuits. There is also a limitto wiring length, which must be restricted to roughly the same dimensions as the device leadlength.

Fig. 3.57 is an example of a CDM test circuit developed at Hitachi. A device pin is chargedthrough the socket pin and a 100 M resistor. When the pin socket contacts GND, the deviceis discharged.

Lower

Pin socketDischarge

100 MΩ DUTHigh voltage

supply

Metal plate

Figure 3.57 CDM Method ESD Test Circuit, Developed at Hitachi (40)

The device capacitance is only a few pF, so the charge time is short, even if high resistancevalues and reverse-biased junctions are in the charge path. 0.1 second is usually sufficient.

The socket pin becomes the discharge path which is several mm long.

Since the current from the high voltage supply is limited by the 100M resistor, it can beignored at discharge.

Because this test circuit closely resembles actual discharge conditions (fig. 3.54) it is regardedas the most realistic one. Application to complex package configurations is difficult at best.

The latest CDM test circuit is shown in fig. 3.58.

Rev. 1.0, 01/02, page 119 of 292

Grounding wire

XYZ movementstage

Relay(containsinert gas)

Electromagnet

Insulationsheet

Charge/dischargeprobe

Electrode

1 MΩ

100 MΩ

High voltagesupply

Groundprobe

Ground plate

Figure 3.58 Latest CDM Test Circuit

The circuit has a charge/discharge probe with a voltage-sensitive relay. The device is chargedwhen the relay is off, and discharged to ground when the relay is on. The test procedure is asfollows.

The board circuitry could be simplified because it is not necessary to initialize the devicepotential in this test circuit.

This allows application to a wide variety of package types and results in consistent andrepeatable results. (40, 41, 42)

Test methodology for the CDM is described in EIAJ temporary Standard EDX-4702 and inJEDEC JESD22-C101.

(c) Complex discharge, including CDM

It is natural to suppose that the discharge resulting from a charged person touching a pin of thedevice in his hand to a metal fixture (see fig. 3.59) is purely a HBM type of discharge. Closeinvestigation reveals that it contains, in fact, components equivalent to both HBM and CDMdischarges.

Rev. 1.0, 01/02, page 120 of 292

Chargedhuman body

Finger

Current

Discharge

Metal plate, etc.

GND

Figure 3.59 Complex Discharge, Including CDM and HBM Components

The discharge occurs as follows: At first, the device itself starts to discharge through the pin.This portion is equivalent to CDM discharge. Then, after the device charge has droppedsufficiently, the charge on the person flows through the device and out the pin. This isequivalent to HBM discharge. Fig. 3.60 shows the resulting waveforms.

0.5A/div

Figure 3.60 Complex Discharge Current Waveform

The peak current during the CDM portion is large, while it is more limited during the HBM-dominated portion. It has been found that most discharges contain some CDM equivalentcurrents, so it should not come as a surprise that the CDM contributes a large portion of ESDdamage seen in the field. (45) (46)

Rev. 1.0, 01/02, page 121 of 292

3.2.9 Latchup

(1) Outline

Due to their low power consumption and wide noise margin, CMOS devices are widely used inlow power and high performance applications. Large capacity memory chips and highperformance microprocessors are made using miniaturized CMOS technology.

CMOS designs include parasitic NPN and PNP bipolar transistors in the input and outputcircuitries. Those transistors combine to form parasitic thyristor. When an operating CMOS deviceis exposed to an external noise spike, there is the possibility that the spike will turn on parasiticthyristor, allowing excessive current to flow, even after the noise spike has stopped. This Latchupcan cause destroy a device. Small geometry devices are particularly susceptible to thisphenomenon, so they require careful consideration during design.

(2) Mechanism

Because basic CMOS devices use inverters made from MOS transistors with two differentcharacteristics as basic elements, parasitic bipolar transistors occur everywhere on a chip.

Equivalent circuits differ slightly depending on the parasitic element combinations, but oneexample of a cross section is shown in fig. 3.62.

VCC Input pin Output pin VSS

VSS

VCCN+ N+ N+ N+ N+ N+ N+

TR3

RN

Rp

P-Well

N-Sub

TR1 TR4 TR2Input pin

Output pin

Figure 3.61 Cross Section of CMOS Inverter

Rev. 1.0, 01/02, page 122 of 292

VCCOutput pin Output pin VCC

RN RN RN

TR2 TR2

TR1Ig

TR1TR3

VSS VSS

For + application

RP RP

TR4

For − application

Figure 3.62 Cross Section of Parasitic Thyristor Equivalent Circuit

First we’ll consider the case where a sufficiently large positive DC or pulse current is applied tothe output pin:

1. Transistor TR3 base-emitter junction is forward biased. TR3 turns on.

2. Current Ig flows through TR2 base resistance RP to VSS.

3. TR2 base potential increases due to RP voltage drop. TR2 turns on.

4. Current flows from VCC through resistance RN and TR2 to VSS.

5. Due voltage drop across RN, TR1 turns on.

6. Current flows from VCC through turned on TR1 and base resistance RP to VSS.

7. This current sustains TR2 in the turned-on state.

Positive feedback in the TR1, TR2 closed loop circuit maintains the current flow between VCC andVSS even if the trigger stops. TR4 transfers negative triggers. Positive feedback in the TR1/TR2closed loop circuit maintain current flow just as in the case of the positive trigger.

(3) Evaluation Method

There are various methods to evaluate a circuit’s susceptibility to Latchup. Two methods definedin EIAJ ED-4701-1, EIA/JESD17, and EIA/JESD78 are explained below.

1. Current Pulse Injection (I-test) Method

A trigger pulse is applied to the input and output pins of a device with a set supply voltageapplied, as in fig. 3.63. The amplitude of the trigger pulse is increased until Latchup occurs.

If input/output resistances are high and could result in high power dissipation during Latchup,the trigger pulse is clamped at a maximum value to prevent destruction of the device. Caremust be taken not to cause destruction due to excessive current injection. After the Latchup testit is important to confirm that the device being tested has not been destroyed.

Rev. 1.0, 01/02, page 123 of 292

A

A

(a) Positive current pulse exposure (JESD17)

Trigger source

Pin under test

Pin under test

VCC

Input pins(VCC or ground level)


DUT

GND

VCC

DUT

GND

Output pins(open)

Output pins(open)

Vsupply

Vsupply

Isupply measurement

Isupply measurement

Trigger source

+

−

−

+

(b) Positive and negative pulse (JESD78) and negative pulse exposure (JESD17)

Figure 3.63 Current Pulse Injection Test (I-test)

2. V-supply Over-voltage test Method

High supply voltage method is shown in fig. 3.64. The device is evaluated with its supplyvoltage set to absolute maximum rating and checking for Latchup.

Rev. 1.0, 01/02, page 124 of 292

A

VCC

DUT

GND


Output pins(open)

Isupply measurement

Vsupply

Figure 3.64 V-supply Over-voltage Method

3.2.10 Power MOS FET Damage

Power MOS FETs are superior power devices with excellent high speed switching characteristicsand a negative temperature characteristic. Power MOS FETs are therefore widely used inswitching power supplies and motor controls where high efficiency and accuracy are importantconsiderations. Their uses in electrical installations, office automation (OA), and lighting areexpanding.

However, damage occurs in high frequency and high power applications due to the miniaturizedcell design peculiar to power MOS FETs (fig. 3.65 and 3.66).

G

N+ N+

S

P

N−

D

N++

Figure 3.65 Cross Section of a Power MOS FET

Rev. 1.0, 01/02, page 125 of 292

Drain

Source

Gate

BaseresistanceRB

Parasiticbipolartransistor

CCBCGD

CGS

Figure 3.66 Equivalent Circuit of a Power MOS FET

(1) Inductive Load Damage (Avalanche Damage)

Avalanche breakdown of a MOS FET is caused by the back electromotive force generated in ahigh speed switching application by an inductive load such as a transformer or a motor. Duringthis avalanche breakdown, current flows through the base resistance RB under the source. Whenthe voltage drop across resistor Rp becomes large enough to turn on the parasitic bipolartransistor, a destructive high current concentration results.

Rev. 1.0, 01/02, page 126 of 292

(2) Evaluation Method

An evaluation circuit diagram and operating waveform are shown in fig. 3.67 and 3.68. When theMOS FET is turned off, the drain current ID flowing through the inductance L decreases, and thedrain voltage VDS rises rapidly. Once the voltage reaches VDSX(SUS), an avalanche breakdown occursin the power MOS FET, and the drain voltage becomes constant. Energy stored in inductance L isreleased as heat and dissipates within the power MOS FET. Avalanche tolerance is the ability todissipate the energy stored in inductance L without destroying the power MOS FET.

VGS

VDD

DUT

L

C+

−

Figure 3.67 Evaluation Circuit Diagram

+15 V

0 V

−15 V

VGS

VDD

ID

IDP

VDS

VDSX (SUS)

Figure 3.68 Evaluation Waveforms

(3) Electrostatic Gate Oxide Damage

Power MOSFETs are power elements, but they are susceptible to damage due to electrostaticsurges or excessive gate voltages because they incorporate MOS structures.

Gate protection structures are necessary for device reliability. However, a DMOS (double diffusedMOS) FET design is optimized for high voltage and large current applications, so incorporation ofprotective elements using PN junctions is difficult due to their parasitic effect.

Rev. 1.0, 01/02, page 127 of 292

Resistance to ESD can be improved through the use of polycrystalline silicon elements above thedielectric film (fig. 3.69).

With protectivediodeNo protective

diode

For chip size 2.2 × 2.2 mm2

100

50

0 100 200 300 400 500 600

Electrostatic destruction voltage (V)

Survival rate %

Figure 3.69 Electrostatic Strength of a Gate Oxide

(4) Damage by Voltage Drop

The gate voltage for most applications is about 10 V. Low voltage applications use a gate voltagearound 4 V. Should the gate voltage be allowed to drop, the device may then operate in the activeoperation range and out of the Area of Safe Operation (ASO), potentially damaging the device(see fig. 3.70). Therefore, it is necessary to check the excessive load, and that the gate voltage hasnot been lowered transitionally due to change the power supply voltage at power-on.

1.2

0.8

0.4

0 2 4 6 8 10 12VGS(th) (V)

VDS(ON) (V)

ID = 20A(B)

(A)

Product name: 2SK1297

(A) Saturation area (small loss)(B) Active area (large loss)

Figure 3.70 VDS(ON) - VGS(th) Characteristics

Rev. 1.0, 01/02, page 128 of 292

3.2.11 Luminance Deterioration of Optical Devices

(1) Failure Phenomena of Laser Diode

Semiconductor laser diode (LD) degradation modes are classified by the change over time of theirdevice characteristics. The two LD modes of operation are automatic current control (ACC) andautomatic power control (APC). The extent of degradation is generally measured by the drop oflight output for the ACC mode or the increase in operating current in the APC mode.

Fig. 3.71 shows a deterioration over time in the APC operation.

Gradual degradation region

Initial degradation region Accelerated degradation region

Time t (h)

Operating current Id (mA)

Figure 3.71 Deterioration of Semiconductor Laser Over Time

The initial degradation for long wavelength LDs used in communication applications is due to PNjunction leakage. (48) These failures can be eliminated through screening during production.

Failure of LDs used for laser disk applications and emitting visible near-infrared light is not yetcompletely understood, but junction defects are thought to be one possibility.

Lifetime of a LD is determined by the almost constant deterioration rate in the gradual degradationregion. Once deterioration of a visible infrared LD has reached a critical value, deteriorationcontinues rapidly until ultimate failure.

Evaluation results for a short wavelength visible LD (HL6712G) are shown in fig. 3.72. This testwas carried out with light output Po = 5mW in APC mode at a heat sink temperature Ths = 50°C.The initial deterioration region is indistinct in this example, but the gradual deterioration region upto 5,000 hours and the accelerated deterioration region beyond 5,000 hours are noticeable.

Rev. 1.0, 01/02, page 129 of 292

0

Test time (h)

1000 2000 3000 4000–20

0

20

40

60

Operating currentincrease rate (%)

PO = 10 [mW]

Figure 3.72 Evaluation Example (HL6712G)

(2) Deterioration Causes of Laser Diodes

A representative structure of a Laser Diode with 670nm wavelength is shown in fig. 3.73.Fig. 3.74 shows a Laser Diode structure and its energy band.

0.8 µm

20 mW fixed

2. End surface light emitting section

1. Active layer Metal contact

n-GaAsn-GaAIAsn or p-GaAIAs

n-GaAIAsn-GaAs

Metal contact

Figure 3.73 Structure of a Short Wavelength visible Laser Diode

Rev. 1.0, 01/02, page 130 of 292

−+Hole

Electron

Laser light

Reflective mirror (cleaved surface)

Energy

1. Semiconductorlaser construction

2. Energy band type diagram

Reflective mirror (cleaved surface)

pGaAIAs

pGaAIAs

nGaAIAs

Heterobarrier

Laser light

Figure 3.74 Structure and Energy Band of a Short Wavelength Laser Diode

Laser diodes use multi-layers composed of an n-GaAs substrate, n-AlGaInP clad layer, n- or p-GaInP active layer, p-AlGaInP clad layer, n-GaAs current blocking layer, and finally a p-GaAsepitaxial layer. The laser emits light with a current flow in the clad and active layers.

Energy levels of several heterostructures are shown in fig. 3.74. When current flows in theforward direction, carriers accumulate in the active layer (carrier close-in effect) at the heterobarrier. As these carriers recombine, the recombination energy is given off as light.

The emitted light is trapped in the active layer due to the refractive index, and through repeatedreflection from both edges becomes laser light.

Deterioration of laser diodes is caused by defects in the active layers. These defects increase intime under the influence of external factors such as current, temperature, and light, with the resultthat light output drops.

Primary causes and their specific effects of deterioration are junction leakage which increasescurrent loss, crystal dislocations lowering the efficiency of light transformation, and damage to ormelting of the laser edges, lowering the emission efficiency.

Rev. 1.0, 01/02, page 131 of 292

(a) Deterioration caused by leakage

Deterioration of long wavelength LDs begins with an increase of leakage current at the p-InPclad layer/n-InP buried layer junction interface. (48)

n n

n

n

p

p

p

IF p-InP clad layer

n-InP buried layer

Active layer

Leakage current

Figure 3.75 Edge Structure of a Long Wavelength LD

EBIC (electron beam induced current) images of the edge of a long wavelength LD after lifetest are shown in fig. 3.76. (50) Leakage occurs at the junction interface. Leaky areas are dark.This failure mode is typically removed by screening, allowing only reliable product to beshipped.

The initial deterioration region for visible infrared LDs is quite short, extending to only severalhundred hours. Poor processing conditions are suspected to be the cause, but this has not yetbeen confirmed.

Rev. 1.0, 01/02, page 132 of 292

p ppn n

n p ppn n

n p ppn n

n

100

80

60

400 2000

EBIC images

40°C, 5 mW/facet

4000 6000

Test time (h)

Operating current (mA)

Defects

Figure 3.76 EBIC Image of the Edge of a Long Wavelength LD

(b) Deterioration caused by Crystal Dislocations

The gradual deterioration region is thought to be dominated by the increase of dislocationswithin the active layer due to current and thermal stress.

Fig. 3.77 shows an electro-luminescence (EL) image of the active layer after the surface hasbeen etched away.

Dislocations generate heat (phonons) rather than light and become non-luminescent, so theyshow up as dark lines or spots.

Rev. 1.0, 01/02, page 133 of 292

Stripe form active region

Figure 3.77 Deterioration of the Active Layer

(c) Deterioration of the cleaved surface

The cleaved surface degrades due to dislocation growth or due to ESD or voltage spikes. ELimages of a high power LD after a long life test show dislocations growing from the cleavedsurface towards the interior of the device. A large number of dislocations exist near the laser’scleaved surface. They absorb light, which is released as heat, thus promoting the growth ofadditional dislocations. (See fig. 3.78).

Dark region

Figure 3.78 Deteriorated Cleaved Surface

The area of safe operation (ASO) for LDs differs from Si devices, in that it is dependent notonly on power consumption, but also on catastrophic optical damage (COD).

Rev. 1.0, 01/02, page 134 of 292

COD occurs during high output at light intensity around 1 MW/cm2, light is absorbed at theedge of the diode, the temperature of the active layer increases to 200°C to 500°C, resulting ininstantaneous crystal meltdown and destruction. (51)

Some examples of surge damages are shown in fig. 3.79.

Failure Mode

EBIC MethodEL Method

Observed in saturated region

Stain Etch Method

Optical damage in active layer central section

Figure 3.79 Surge Damage of High Power LD

Representative characteristics of high power LD damaged by COD are shown in fig. 3.80.

20

0

20

0100 0.4 Saturated region

change to multipleChange to multiple

mode

Light output (P O) Monitor current Is WavelengthFFP

Representative Characteristics

PO (mW)

PO (mW)

IF (mA) IS (mA)

Figure 3.80 Representative Characteristics of Surge Damaged High Power LD

Light output Po must be considered during the design stage. Protection circuits for noise andvoltage spike suppression must be designed in as well.

Rev. 1.0, 01/02, page 135 of 292

(3) Lifetime Estimation Methods

Lifetime is typically estimated using data collected during monitored aging tests with continuouswave or pulsed operation under APC or ACC conditions.

The collected data is statistically processed to calculate a mean change rate and lifetimeestimate.(52) An example of life estimation is given in fig. 3.81.

99.9 3σ

2σ

1σ

−1σ

−2σ

−3σ

0

99

9590

70

50

30

105

1

0.1

Duration time (h)101 102 103 104 105

Estimation by the mean change rate of 1000h test data

Sigma

Tc = 50°C, Po = 10 mW, APC

Specification of lifeTc = 50°C, Po = 10 mW, APCt = 500 h, F(t) ≤ 1%

(N = 20) (N = 10)

Tc = 40°C, Po = 10 mW, APC

Tc = 25°C, Po = 10 mW, estimation results

Failure criteria; ∆Io = 20%

Cumulative failure rate F(t) (%)

Current temperature acceleration (×4.2)

Figure 3.81 Estimated Lifetime Distribution for a 630nm, 10mW Laser Diode)

(a) The Eyring model adds thermal and current stress effects to the Arrhenius model and is shownbelow.

∆Iop = A • Iop • • exp

mt duty

100−Eak • T( ) ( ) .......................................................................... (1)

Where Iop: Rate of Change of Operating Current (%)A: Deterioration Constant (experience)Iop: Initial Operating Currentm: Time Parameter (experience)k: Boltzmann Constant (8.617 • 10–5 eV/K)Ea: Activation Energy (eV) (experience)T: Junction Temperature in Operation in Kduty: 100% for Continuous Operation

Rev. 1.0, 01/02, page 136 of 292

(b) Equation (1) shows the relation between lifetime, current, and temperature as follows.

Life µ = • exp 1m1

Iop

Eam • k • T( ) ( ) ................................................................................ (2)

To estimate the lifetime at (Tc = 25C, PO = 10mW, APC) from the data shown in fig. 3.81,taken at (Tc = 50C, PO = 10mW, APC) with equation (2):

Eak

Life acceleration rate α = = • exp − 1T(25)

1T(50)

Life(25)Life(50)

Iop(50)

Iop(25) ([ ]) .......... (3)

Where Ea = 0.35 eV from experience

m = 1 from experience

Iop(50) /Iop(25) = 1.5 from measurement on the device

Life(25): Life time at Tc = 25C, Po = 10mW, APC

Life(50): Life time at Tc = 50C, Po = 10mW, APC

(c) An acceleration rate = 4.2 is obtained from equation (3) and distribution of lifetime estimatesis shown in fig. 3.81.

Note: In case the activation energy is unknown or difficult to measure due to small change inoperating current, the conservative value of Ea= 0 eV is used, which is worst-case forestimating life time.

3.3 Failure Analysis Technology

Mil Standard 883E, Method 5003 defines failure analysis as “A post mortem examination of faileddevices employing, as required, electrical measurements and many of advanced analyticaltechniques of physics, metallurgy, and chemistry in order to verify the reported failure andidentify the mode or mechanism of failure as applicable.”

As semiconductor devices become more highly integrated and more multi-functional, as themanufacturing processes become more complicated, and as applications become more widespread,the reliability requirements for semiconductor devices are continuing to increase.

In order to achieve those high reliability levels, it is essential that reliability is built into theproduct from device development down through the manufacturing process. Devices that havefailed during reliability tests, at a customer or in the field must be analyzed to clearly identify thefailure mode and cause. That information is fed back into the design and manufacturingorganizations in order to improve the processes there. Therefore, failure analysis technology is anessential pert of the process of manufacturing high quality devices.

An example of failure analysis is shown in fig. 3.82.

Rev. 1.0, 01/02, page 137 of 292

This is a basic flowchart. The nature of the may determine which analysis is unnecessary and canbe omitted to shorten analysis time. It may also drive a change of the analysis method or to theorder of steps. Failed samples contain information essential for process improvement, but sincethey are usually limited in number, they are very valuable. No information can be gained from afailed analysis, so utmost attention must be paid to thorough failure analysis.

Here are some suggestions for failure analysis. (53)

1. Do not change failure state.

Mechanical, electrical, thermal stress applied to the failure device may change the failure stateand will prevent getting valid results.

2. Collect as much information as possible.

Collect information such as product name, manufacturing lot number, failure number, failurerate, failure description, mounting condition, circuitry, failed location, operating environment,test environment, etc.

Knowledge about device design and manufacturing process technology is necessary duringanalysis.

3. Select correct analytical equipment.

Use analytical equipment that matches the object of the analysis.

Non-destructive analysis should be done first.

4. Accumulate the data systematically.

Systematically record the failure analysis result in order to make effective use of theinformation.

Major equipment used for failure analysis is listed in table 3.14. Some equipment outlines areshown in table 3.15, fig. 3.83 shows the outputs of some equipment.

As devices become more complex, it becomes more difficult to identify failures. EB tester andemission microscopes have been developed to aid in the analysis of complex failures.

Analysis equipment using laser or infrared is under development to allow inspection and analysisof the deep layers of multi-layer devices.

Rev. 1.0, 01/02, page 138 of 292

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Rev. 1.0, 01/02, page 139 of 292

Table 3.14 List of typical Failure Analysis Equipment

Classification Equipment Name

Observation AnalysisEquipment

Stereo microscope

Metallurgical microscope

Infrared microscope

Scanning laser microscope

Scanning acoustic transmission (SAT) equipment

Scanning electron microscope (SEM)

Scanning ion microscope (SIM)

Transmission electron microscope (TEM)

Scanning transmission electron microscope (STEM)

Atomic force microscope (AFM)

X-ray viewing equipment

Scanning surface thermometer

Emission microscope (EMS)

Other

Parameter MeasuringEquipment

Curve tracer

Various testers

Oscilloscope

Multimeter

LCR meter

Electrical noise analyzer

Electron beam (EB) tester

Optical beam induced current meter (OBIC)

Manipulator

Other

Sample PreparationEquipment

Shearing and cutting equipment

Grinder

Polishing equipment

Resin mold jig

Vacuum metal deposition equipment

Plastic package decapsulation equipment

Ion milling equipment

Focused ion beam equipment (FIB)

Plasma etcher

Other

Rev. 1.0, 01/02, page 140 of 292

Classification Equipment Name

Analysis Equipment X-ray microprobe analyzer (XMA)

X-ray Fluorescence spectroscope (XRFS)

Scanning auger electron spectroscope (SAM)

Analyzing electron microscope (AEM)

Secondary ion mass spectroscope (SIMS)

Ion microprobe analyzer (IMA)

Infrared absorption spectroscope (IR)

Fourier transform infrared absorption spectroscope (FTIR)

Light spectrum analyzer

High frequency plasma light emission spectroscope (ICAP)

Micro Raman spectrum analyzer

Atomic absorption photometer

Zeeman atomic absorption photometer

Low speed electron beam diffractometer (LEED)

X-ray diffractometer

Electron spectrum analyzer (ESCA)

Ion chromatography

Gas chromatography

Liquid chromatography

Mass spectrometer

Thermal differential analyzer

Other

Rev. 1.0, 01/02, page 141 of 292

Table 3.15 Outline of F/A Equipment Use and Sample Preparation

Equipment Use Sample Preparation

Infrared Microscope Silicon is transparent to infrared, so it is usedto confirm integrity of ball bond ball to Al padconnection, as well as pattern of lowest layerin multi-layer chip from rear surface of chip.

Chip rear surface should be mirrorfinished.

Scanning ElectronMicroscope (SEM)

Electron beam is incident on the sample.Secondary emitted electrons are captured toform the image. Elemental analysis can bedone using characteristic radiation emitted atthe same time. (XMA)

Samples may be cleaved orpolished. Etching the sampleenhances the difference betweenlayers in a cross section. Sampleneeds a conductive film to be ableto properly image insulators. C, Au,Pt may be used.

Emission Microscope(EMS)

Capture small amount of emitted light fromsmall area by CCD and light amplifier, anddigitize the data to determine the failure.

Need to open package with chipoperable.

Fourier Transform InfraredAbsorption Spectrometer(FTIR)

Subject the sample with infrared, varying itsfrequency, and observe absorption spectrum.It is used mainly for analysis of organic matter.

Identify the sample by comparingits absorption spectrum with that ofa known samples.

Rev. 1.0, 01/02, page 142 of 292

Cross section by FIB Picture of luminescence observed by EMS

Picture by IR-microscope (bottom view of die)

XMA analysis chart

Figure 3.83 Analysis Result

Rev. 1.0, 01/02, page 143 of 292

References

(1) Reliability Center of Japan; “Report on Failure Model and Acceleration Factor of ReliabilityTest for LSI,” R-2-R5-02 (1990).

(2) Reliability Center of Japan; “Report on In-process Reliability Technique for ICs,” R-6-R5-02(1995).

(3) M. Lenzlinger and E.H. Snow; “Fowler-Nordheim Tunneling into Thermally Grown SiO2,”J.Appl.Phys., pp. 278–283, vol. 40, 1969.

(4) M.H. Woods; “Inplication of Scaling on VLSI Reliability,” Tutorial Notes, 1984 IEEE IRPS.

(5) T.H. Ning; “Hot-carrier emmission currents in n-channel IGFET’s,” Int. Election deviceMeet. Tech, Dig., pp. 144–147, 1977.

(6) E. Takeda, H. Kume, Y. Nakagome and S. Asai; “An As-P (nn) double diffused drainMOSFET for VLSIs,” 1982 Symp. on VLSI Tech. Dig., pp. 40–41, Sep. 1982.

(7) Y. Nakagome, E. Takeda, H. Kume and S. Asai; “New Observation of hot-carrier injectionphenomena,” Jpn. J. Appl. Phys. vol. 22, Supplement 22–1, pp. 99–102, 1983.

(8) A. Toriumi, M. Yoshimi and K. Taniguchi; “A Study of gate current and reliability in ultra-thin gate oxide MOSFET’s,” 1985 Symp. on VLSI Technology, Tech, Dig., pp. 110–111,May, Kobe.

(9) S. Tam, F.C. Hsu, P.K. Ko, C.Hu and R.S. Muller; “Hot-Electron induced excess carriers inMOSFET’s,” IEEE Electron Device Letters, vol. EDL–3, No.12, Dec. 1982.

(10) T.H. Ning, C.M. Osburn and H.N. Yu; “Emission Probability of hot-electron from siliconinto silicon dioxide,” J. Appl. Phys., pp. 286–293, vol. 48, 1977.

(11) E. Takeda; “Hot Carrier Effect,” pp. 31–50, Nikkei McGraw Hill Co, 1987.

(12) C. Hu et al; “Hot-Electron induced MOSFET degradation-Model, monitor andimprovement,” IEEE J. of Solid State Circuit, Vol. SC–20, pp. 295–305, 1985.

(13) E. Takeda; “Hot-carrier and wear out phenomena in submicron VLSI’s” Dig, Tech. PaperSymp. on VLSI Technol., pp. 2–5, Kobe, 1985.

(14) T.C. May, et al; “A new physical mechanism for soft errors in Dynamic RAMs,” Proc. 1978IEEE IRPS pp. 33–40.

(15) J.R. Black; “Physics of Electrmigration” Proc. 1974 IEEE IRPS pp. 142–159.

(16) J.R.Black; “Electromigration-A brief survey and some recent results” IEEE, ED-4, (1969)pp. 338–347.

(17) K. Hinode, et al; “Relaxation Phenomenon During Electromigration Under Pulsed Current”.Proc 1992. IEEE IRPS pp. 205–210.

(18) N. Owada, K. Hinode, M. Horiuchi, T. Nishida, K. Nakata and K. Mukai; “Stress inducedslit-like void formation in a fine-pattern Al-Si interconnect during again test” IEEE 2ndinternational VLSI Multilevel Interconnection conference, pp. 173–179, 1985.

(19) T. Turner and K. Wendel; “The influence of Strees on Aluminum Conductor Life” Proc. 1985IEEE IRPS pp. 142–147.

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(20) K. Tsubosaki et al.; “Rate-determing Factor of aluminum corrosion and rapid method ofassessing the moisture resistance of plastic encapsulated LSI”, Proc. 1983, IEEE IRPSpp. 83.

(21) H. Serizawa, S. Sasaki, I. Ishi, I. Shimizu, and A. Hoshi; “Plasitc IC Package HeatResistivity Shock Characteristic Improvement,” Japan Science Technology Association 14thSymposium on Reliability, Integrity Proc. pp. 85–88, 1984.

(22) T. Ozaki et al; “Plastic Encased LSI Corrosive Conduct,” Japan Metal Institute Report,Volume 26 Number 4, p. 290, 1987.

(23) A. Suzuki, M. Murakami, and M. Sakimoto; “Flat Package IC High Reliability Viewed fromSolder Installation,” Japan Science Technology Association 14th Symposium on Reliabilityand Integrity Proc. pp. 303–306, 1984.

(24) M. Tanaka, M. Sakimoto, H. Konishi, K. Nishi, K. Ohtsuka, and J. Yoshida; “Investigation ofSurface Mount Package Reflow Heat Tolerance Evaluation Methods,” Japan ScienceTechnology Association 18th Symposium on Reliability, Integrity Proc. 1988, pp. 165–172.

(25) K. Kitano, A. Nishimura, S. Kawai, K. Nishi; “Analysis of Package Cracking During ReflowSoldering Process”, Proc. 1988 IEEE IRPS, pp. 90–95.

(26) K. Nishi, I. Anjo, M. Ogata, M. Kitano, and T. Yoshida: “Surface Mount package ReflowCrack Mechanism Analysis and Countermeasures,” Japan Science Technology association18th Symposium on Reliability, Integrity Proc., pp. 173–178, 1988.

(27) M. Tanaka, M. Sakimoto, K. Nishi, K. Ohtsuka; “A Novel Test Method of Resistance toSoldering Heat of Plastic Encapsulated Surface Mount LSIs,” Nikkei Electronics, Dec. 24,1990.

(28) M. Tanaka, M. Sakimono, and K. Nishi; “Surface Mount Package Reflow Soldering HeatEvaluation through Non-Destructive Inspection,” Semiconductor World, Monthly, August1987, pp. 90–96.

(29) Nonaka, Okigawa; “Development of Ultrasonic Inspection Images,” Technical Report(Reliability) by the Society of Electronic Data Communications, R86–68, March, 1987.

(30) Y. Orii, O. Suzuki, A. Nakanishi, K. Takahashi, R. Kimoto, T. Nishita, M. Tanaka, M.Sakimoto; “An Advanced Evaluation Method of Soldering Heat Resistance for Ultra ThinPlastic Encapsulated LSIs”, 1991 ISTFA, pp. 213–220.

(31) M. Tanaka, M. Sakimoto, H. Ishida, Y. Orii, T. Nishita, “An Advanced Evaluation Techniqueof Resistance To Soldering Heat for Ultra Thin Surface Mount LSIs,” JUSE 22th Reliabilityand Maintainability Symposium, pp. 155–160, 1992.

(32) K. Okada, M. Tanaka; “Novel Moisture Soaking Techniques of Soldering Heat Test ofSurface Mount LSIs,” JUSE 25th Reliability and Maintainability Symposium, pp. 39–44,1996.

(33) M. Tanaka, T. Syouji, R. Kimoto, H. Kawakubo, K. Ishigaki; “Resistance to Wave-SolderingHeat Test Method for SMDs,” RCJ 3rd Reliability Symposium, pp. 21–26, 1993.

(34) Mount LSIs; “JUSE 26th Reliability and Maintainability Symposium,” pp. 39–44, 1996.

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(36) A. Okada and S. Shumi; “Realization of Semiconductor Failure Analysis Methods throughGrasping Stress and Failure Mode,” Japan Science Technology Association 15th Reliabilityand Maintainability Symposium, pp. 201–206, 1985.

(37) D.C. Wunsch; “The Application of Electrical Overstress Models to Gate ProtectiveNetworks”, IEEE 16th Annual Proceedings Reliability physics, April 1978, pp. 47–55.

(38) N. Murasaki; “Electronic System Electrostatic Damage Countermeasures ResourceCollection, Revised Edition,” Dai Ichi International Corp., 1982.

(39) “Report on Investigation Results for Semiconductor Device Electrostatic DestructionPhenomenon and Its Evaluation Methods,” Japan Electronic Part Reliability Center, 1985.

(40) D.C. Wunsch and R.R. Bell; “Determination of threshold failure Levels of Semiconductordiodes and Transistors Due to Pulse Voltages,” IEEE Trans. Nuclear Science Vol. NS-15No.6, Dec 1968, pp. 244–259.

(41) P.R. Bossard, R.G. Chemelli, B.A. Unger; “ESD Damage From Triboelectrically Charged ICPins,” 1980 EOS/ESD Symposium Proc., pp. 17–22.

(42) B.A. Unger, “Electrostatic Discharge of Semiconductor Devices,” IEEE 19th AnnualProceedings Reliability Physics, pp. 193–199, 1981.

(43) M. Tanaka, H. Konishi and K. Ando; “A New Electrostatic Discharge Test Method forCharged Device Model,” 1989 ISTFA Proc., pp. 177–182.

(44) M. Tanaka, M. Sakimoto, I. Nishimae, K. Ando; “An Advanced ESD Test Method ForCharged Device Model,” EOS/ESD Symposium 1992, pp. 76–87.

(45) M. Tanaka, K. Okada, M. Sakimoto; “Clarification of Ultra-high-speed ElectrostaticDischarge & Unification of Discharge Model”, EOS/ESD Symposium 1994, pp. 170–181.

(46) M. Tanaka, K. Okada, M. Sakimoto; “Phenomenon of ESD Failure with DisplacementCurrent,” RCJ 3rd EOS/ESD Symposium, pp. 21–28, 1993.

(47) Y. Fukuda and N. Otsuki; “Static Electricity Charged on IC Packages Destroys IC,” NikkeiElectronics, 4.23, 1984.

(48) S. Todoroki et al; “Semiconductor Laser Reliability Evaluation,” Japan Science TechnologyAssociation 14th Symposium on Reliability and Integrity L-1, pp. 69–74, 1984.

(49) H. Nakajima; “Introduction to Semiconductor Lasers,” Chapter 4, Akiha Publishers, 1986.

(50) K. Mizuki; “Reliability of InGaAsP/InP buried heterostructure 1.3 mlasers,” IEEE J.Quantum Electron, vol. QE-19, pp. 1294–1301, 1983.

(51) S. Todoroki et al; “Semiconductor Laser Microscopic Section Temperature Investigation,”Manuscript prepared for 1984 Akio Physical Society, 14a-R-10, p. 183.

(52) R. Kunimitsu et al; “Improvement of Laser Diode Life Estimation Techniques,” JapanScience Technology Association 17th Symposium on Reliability and Integrity S-14, pp. 231–236, 1987.

(53) RCJ: “Semiconductor Device Failure Analysis Technology (R-63-RS-02),” Japan ElectronicParts Reliability Center, 1989.

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Section 4 Reliability Tests on Semiconductor Devices

Various test methods are available to confirm the reliability of a semiconductor device. Thischapter describes a sampling test for the reliability of semiconductor devices. It also discusses thescreening techniques used to enhance the reliability, and provides an overview of reliability testmethods and applicable standards.

4.1 Reliability Tests

Before conducting a reliability test, appropriate test methods must be selected depending uponwhat is to be tested, the intended application of the product, and the purpose of the test. Inaddition, suitable test parameters and evaluation criteria must be established. For example, in theresearch and development phase you might be interested in reliability limits or the acceleration ofthe rate at which reliability failures occur, for quality assurance and periodic tests in the massproduction environment, you may require a different set of test contents, parameters, and testplans.

For semiconductors, a serial model is generally considered appropriate as the reliability model.

When conducting a reliability test, what is to be tested as a failure mode is of critical importance.This is especially important in design reviews (DRs) for the product development stage.

A major requirement for the product development stage is the confirmation of the three elementsof reliability goals discussed in section 1. One of the elements is the life of the product.

Although the time of life can vary according to the specific application of the product, we assumea life span of 10 years. If the product is to be tested in 1000 hours for the failure mode mentionedabove, it is need to have an acceleration rate of approximately 100 times, 100X. If the life span istargeted for 20 years, you need either an acceleration rate of 200 X or test duration of 2000 hours.For wear out failures, this is where the occurrence of one failure often triggers or is followed by asuccession of similar failures, the number of test samples can be substantially reduced by setting alittle higher acceleration rate and test duration than for other failure modes. For an initial failuremode, where the rate of failure declines with the passage of time, you should increase the numberof samples as opposed to increasing the test duration.

Examples of acceleration stress parameters are temperature, voltage, humidity, and mechanicalstress. These parameters must be established by considering the acceleration rate and the failuremode being studied.

Critical requirements in a reliability test are:

1. The ability to provide appropriate projections.

2. The ability to contribute to the improvement of product reliability. This requires theaccumulation of reliability data from the tests performed, feedback of the results for fault

Rev. 1.0, 01/02, page 148 of 292

analyses to the process design, the device design, and the manufacturing process to ensure thatreliability improvements are built into the design and manufacture of the product.

4.2 Sampling Methods for Reliability Tests

4.2.1 Sampling Tests

The characteristics of a particular sampling method are often identified by its OC curve (OperatingCharacteristics curve).

This curve, an example of which is illustrated in fig. 4.1, is similar to the curves that are used inquality control operations, with the exception that the horizontal axis now represents the defectrate at the end of the life span test. In this example, a lot with a defect rate P0 at the conclusion ofthe life span test has a pass rate of 1 – . On the other hand, a lot with a defect rate of P1 has apass rate of .

In this case, the mean failure rate λ , which is a measure of reliability, is determined from thedefect rate, the acceleration rate, and the test duration.

The quantity λ 1 obtained in this manner is called the lot tolerance failure rate (LTFR). Insampling tests, the term “lot tolerance percent defective” (LTPD) is often used, which refers to thedefect rate (P1) that occurs in a given test duration.

Because reliability tests on semiconductor devices are generally destructive (with the exception ofthe screening test), these tests are necessarily conducted on a sampling basis.

Sampling tests for the determination of reliability have the following characteristics:

1. Because the failure rate, rather than the defect rate, is required, the quantity λ is substituted,and a time element is added, after statistical processing.

2. Therefore, what specific failure distribution is to be selected is the important question.

3. Whereas we consider the risk rate in an ordinary sampling inspection, it suffices to considerthe risk to the manufacturer and the risk to the consumer. In reliability sampling tests it isnecessary to consider the reasonableness of any assumptions made regarding the life spandistribution of the product.

4. Because tests normally require a long time to complete, an error in initial measurements can becostly.

5. Because reliability tests are destructive, with the exception of screening tests, it is notreasonable to employ 100% testing all items in a failed lot.

6. An acceleration coefficient appropriate for a given failure mode must be used.

Rev. 1.0, 01/02, page 149 of 292

Lot P

ass

Rat

e (P

) (%

)

Defect Rate after a Life Span Test

100

0P0 P1 (LTPD)

α

β

Figure 4.1 OC Curve of a Failure Rate

4.2.2 Sampling Based on a Failure Distribution

(1) Using an Exponential Distribution

Following is a brief discussion of a single sampling method based on an exponential distribution.

The theory of the sampling test based on an exponential distribution has been studied for manyyears and is well established. Table 4.1 is a sampling table for one-count sampling.

Rev. 1.0, 01/02, page 150 of 292

Table 4.1 Table of Single Sampling Used in Reliability Tests

One-count sampling method (MIL-S-19500E), confidence level: 90% ( = 0.1)LT

PD

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 25

5030

2015

107

53

21.

51

0.7

0.5

0.3

0.2

0.15

0.1

Min

imum

Sam

ple

Siz

e n

Fig

ures

in th

e pa

rent

hese

s in

dica

te th

e m

inim

um p

rodu

ct q

ualit

y ne

cess

ary

to e

nsur

e th

at 1

9 lo

ts c

an b

e ac

cept

ed fr

om 2

0 lo

ts (

appr

oxim

ate

AQ

L).

5 (1

.03)

8 (4

.4)

11

(7.4

)13

(1

0.5)

16

(12.

3)19

(1

3.8)

21

(15.

6)24

(1

6.6)

26

(18.

1)28

(1

9.4)

31

(19.

9)33

(2

1.0)

36

(21.

4)38

(2

2.3)

40

(23.

1)43

(2

3.3)

45

(24.

1)47

(2

4.7)

50

(24.

9)52

(2

5.5)

54

(26.

1)65

(2

7.0)

8 (0

.64)

13

(2.7

)18

(4

.5)

22

(6.2

)27

(7

.3)

31

(8.4

)35

(9

.4)

39

(10.

2)43

(1

0.9)

47

(11.

5)51

(1

2.1)

54

(12.

8)59

(1

3.0)

63

(13.

4)67

(1

3.8)

71

(14.

1)74

(1

4.6)

79

(14.

7)83

(1

5.0)

86

(15.

4)90

(1

5.6)

109

(16.

1)

11

(0.4

6)18

(2

.0)

25

(3.4

)32

(4

.4)

38

(5.3

)45

(6

.0)

51

(6.6

)57

(7

.2)

63

(7.7

)69

(8

.1)

75

(8.4

)83

(8

.3)

89

(8.6

)95

(8

.9)

101

(9.2

)10

7 (9

.4)

112

(9.7

)11

8 (9

.86)

124

(10.

0)13

0 (1

0.2)

135

(10.

4)16

3 (1

0.8)

15

(0.3

4)25

(1

.4)

34

(2.2

4)43

(3

.2)

52

(3.9

)60

(4

.4)

68

(4.9

)77

(5

.3)

85

(5.6

)93

(6

.0)

100

(6.3

)11

1 (6

.2)

119

(6.5

)12

6 (6

.7)

134

(6.9

)14

2 (7

.1)

150

(7.2

)15

8 (7

.36)

165

(7.5

4)17

3 (7

.76)

180

(7.8

2)21

7 (8

.08)

22

(0.2

3)38

(0

.94)

52

(1.6

)65

(2

.1)

78

(2.6

)91

(2

.9)

104

(3.2

)11

6 (3

.5)

128

(3.7

)14

0 (3

.9)

152

(4.1

)16

6 (4

.2)

178

(4.3

)19

0 (4

.5)

201

(4.6

)21

3 (4

.7)

225

(4.8

)23

6 (4

.93)

248

(5.0

2)25

9 (5

.12)

271

(5.1

9)32

6 (5

.38)

32

(0.1

6)55

(0

.65)

75

(1.1

)94

(1

.5)

113

(1.8

)13

1 (2

.0)

149

(2.2

)16

6 (2

.4)

184

(2.6

)20

1 (2

.7)

218

(2.9

)23

8 (2

.9)

254

(3.0

)27

1 (3

.1)

288

(3.2

)30

5 (3

.3)

321

(3.3

7)33

8 (3

.44)

354

(3.5

1)37

0 (3

.58)

386

(3.6

5)46

6 (3

.76)

45

(0.1

1)77

(0

.46)

105

(0.7

8)13

2 (1

.0)

158

(1.3

)18

4 (1

.4)

209

(1.6

)23

4 (1

.7)

258

(1.8

)28

2 (1

.9)

306

(2.0

)33

2 (2

.1)

356

(2.2

)37

9 (2

.26)

403

(2.3

)42

6 (2

.36)

450

(2.4

1)47

3 (2

.46)

496

(2.5

1)51

8 (2

.56)

541

(2.6

0)65

2 (2

.69)

76

(0.0

7)12

9 (0

.28)

176

(0.4

7)22

1 (0

.62)

265

(0.7

5)30

8 (0

.85)

349

(0.9

4)39

0 (1

.0)

431

(1.1

)47

1 (1

.2)

511

(1.2

)55

5 (1

.2)

594

(1.3

)63

2 (1

.3)

672

(1.4

)71

1 (1

.41)

750

(1.4

4)78

8 (1

.48)

826

(1.5

1)86

4 (1

.53)

902

(1.5

6)10

86

(1.6

1)

116

(0.0

4)19

5 (0

.18)

266

(0.3

1)33

3 (0

.41)

398

(0.5

0)46

2 (0

.57)

528

(0.6

2)58

9 (0

.67)

648

(0.7

2)70

9 (0

.77)

770

(0.8

0)83

2 (0

.83)

890

(0.8

6)94

8 (0

.89)

1007

(0

.92)

1066

(0

.94)

1124

(0

.96)

1182

(0

.98)

1239

(1

.0)

1296

(1

.02)

1353

(1

.04)

1629

(1

.08)

153

(0.0

3)25

8 (0

.14)

354

(0.2

3)44

4 (0

.31)

531

(0.3

7)61

7 (0

.42)

700

(0.4

7)78

3 (0

.51)

864

(0.5

4)94

5 (0

.58)

1025

(0

.60)

1109

(0

.62)

1187

(0

.65)

1264

(0

.67)

1343

(0

.69)

1422

(0

.71)

1499

(0

.72)

1576

(0

.74)

1652

(0

.75)

1728

(0

.77)

1803

(0

.78)

2173

(0

.807

)

231

(0.0

2)39

0 (0

.09)

533

(0.1

5)66

8 (0

.20)

798

(0.2

5)92

7 (0

.28)

1054

(0

.31)

1178

(0

.34)

1300

(0

.36)

1421

(0

.38)

1541

(0

.40)

1664

(0

.42)

1781

(0

.43)

1896

(0

.44)

2015

(0

.46)

2133

(0

.47)

2249

(0

.48)

2364

(0

.49)

2478

(0

.50)

2591

(0

.52)

2705

(0

.52)

3259

(0

.538

)

328

(0.0

2)55

5 (0

.06)

759

(0.1

1)95

3 (0

.14)

1140

(0

.17)

1323

(0

.20)

1503

(0

.22)

1680

(0

.24)

1854

(0

.25)

2027

(0

.27)

2199

(0

.28)

2378

(0

.29)

2544

(0

.3)

2709

(0

.31)

2878

(0

.32)

3046

(0

.33)

3212

(0

.337

)33

77

(0.3

44)

3540

(0

.351

)37

02

(0.3

58)

3864

(0

.364

)46

56

(0.3

76)

461

(0.0

1)77

8 (0

.045

)10

65

(0.0

80)

1337

(0

.10)

1599

(0

.12)

1855

(0

.14)

2107

(0

.155

)23

55

(0.1

7)25

99

(0.1

8)28

42

(0.1

9)30

82

(0.2

0)33

23

(0.2

1)35

62

(0.2

2)37

93

(0.2

2)40

29

(0.2

3)42

65

(0.2

35)

4497

(0

.241

)47

28

(0.2

46)

4956

(0

.251

)51

83

(0.2

56)

5410

(0

.260

)65

18

(0.2

69)

767

(0.0

07)

1296

(0

.027

)17

73

(0.0

45)

2226

(0

.062

)26

63

(0.0

74)

3090

(0

.085

)35

09

(0.0

93)

3922

(0

.101

)43

29

(0.1

08)

4733

(0

.114

)51

33

(0.1

20)

5546

(0

.12)

5936

(0

.13)

6321

(0

.134

)67

16

(0.1

38)

7108

(0

.141

)74

96

(0.1

44)

7880

(0

.148

)82

60

(0.1

51)

8638

(0

.153

)90

17

(0.1

56)

1086

3 (0

.161

)

1152

(0

.005

)19

46

(0.0

18)

2662

(0

.031

)33

41

(0.0

41)

3997

(0

.049

)46

38

(0.0

56)

5267

(0

.062

)58

86

(0.0

67)

6498

(0

.072

)71

03

(0.0

77)

7704

(0

.080

)83

19

(0.0

83)

8904

(0

.086

)94

82

(0.0

89)

1007

3 (0

.092

)10

662

(0.0

94)

1124

4 (0

.096

)11

819

(0.0

98)

1239

0 (0

.100

)12

957

(0.1

02)

1352

6 (0

.104

)16

295

(0.1

08)

1534

(0

.003

)25

92

(0.0

13)

3547

(0

.022

)44

52

(0.0

31)

5327

(0

.037

)61

81

(0.0

42)

7019

(0

.047

)78

45

(0.0

51)

8660

(0

.054

)94

68

(0.0

57)

1026

8 (0

.060

)11

092

(0.0

62)

1187

2 (0

.065

)12

653

(0.0

67)

1343

1 (0

.069

)14

216

(0.0

70)

1499

2 (0

.072

)15

759

(0.0

74)

1652

0 (0

.075

)17

276

(0.0

77)

1803

4 (0

.078

)21

726

(0.0

81)

2303

(0

.002

)38

91

(0.0

09)

5323

(0

.015

)66

81

(0.0

18)

7994

(0

.025

)92

75

(0.0

28)

1053

3 (0

.031

)11

771

(0.0

34)

1299

5 (0

.036

)14

206

(0.0

38)

1540

7 (0

.040

)16

638

(0.0

42)

1780

8 (0

.043

)18

964

(0.0

45)

2014

6 (0

.046

)21

324

(0.0

47)

2248

7 (0

.048

)23

639

(0.0

49)

2478

0 (0

.050

)25

914

(0.0

51)

2705

1 (0

.052

)32

589

(0.0

54)

Acc

epta

nce

Num

ber

c

Rev. 1.0, 01/02, page 151 of 292

The following procedures can be employed when using table 4.1:

1. Given a target lot tolerance failure rate (1) and time (t), set the P1 (an LTPD value) and anacceptance number.

2. Based on P1 and c, find a corresponding sample size n.

3. Randomly extract n samples from a lot. Perform tests for a prescribed duration. If the totalnumber of failures does not exceed the value c, the lot is considered a pass, i.e. accepted.

If the lot is a pass, it can be stated that the “failure rate of the lot at a 90% confidence level is lessthan 1”. Based on a consumer risk of = 0.1, this table gives the sample size n and the passthreshold number c that are necessary to assure a lot tolerance failure rate of 1. The followingrelationship holds between the lot tolerance failure rate and an LTPD value: 1 = P1/t(%/h). If nsamples are extracted from a lot with a lot tolerance failure rate of 1 and if the number of defectsis less than or equal to c, at a confidence level of 1 – = 90%, the following expression can beobtained from the binomial distribution:

L(λ1) = Σ nCr[F(t)]r [R(t)]n−r ≤ βr =c

r =0

If 1, t are small, by Poisson approximation,

L(λ1) = Σ exp ( λ1T) • (λ1 • T)r / r! ≤ βr =c

r =0

where T = n • t. The quantity T is referred to as the “component hour.”

In the case of an exponential distribution, the expression

F(t) = 1 – exp (– t)

holds. The number of cumulative defects during the length of time for which the product must beguaranteed will be

n × F(t) = n × (1 – e– t)= nt (1 – e– t t if t is sufficiently small)

In the exponential distribution, where the component hour is constant, doubling the number ofsamples can reduce the test duration by half. In other words, time and the number of samples canbe treated as equivalent quantities.

Rev. 1.0, 01/02, page 152 of 292

(2) Example Assuming a Weibull Distribution*1

This example shows how to extract samples assuming a Weibull distribution.

Let us consider the mean failure rate λ (t) that occurs until the end of the warranty period,assuming that the shape parameter m for Weibull distribution is known.

If the following mean failure rate holds

(t) = [F(t2) – F(t1)] (t2 – t1)

from the Weibull function, it follows that

F(t) = 1 – exp [– (t /)m]

If ( t /)m is sufficiently small,

F '(t) (t /)m

Therefore,(t) will be

(t) = [(t2

m – t1

m) /m] / (t2 – t1)= tm–1/m (from the initial period to a given time, t2 = t, t1 = 0)

The cumulative number of defects until the end of the warranty period can be expressed as

nF(t) = n λ (t) t= n(t /)m

In other words, when the problem is considered in terms of a mean failure rate, the inexponential distribution can be substituted by λ (t). Consequently, this is equal to the number ofsamples in the exponential distribution when m = 1. If t denotes the warranty time; tR, the durationof the test to be conducted; and nR, the applicable number of samples, the cumulative number ofdefects through the warranty period will be

nF(t) = nRF(tR)

n(t /)m = nR(tR/)m

nR = n(t / tR)m

Thus, if m > 1, the number of samples can be reduced by increasing the test duration.

If the warranty period is 1000h and tR = 2000h, for m = 2 the number of samples will be one-forththe number that would be required when tR = 1000h, or one-half the component hour, whichenhances the efficiency of the test. On the other hand, if the test duration is set to 500h, the

Rev. 1.0, 01/02, page 153 of 292

number of samples will quadruple, and the component hour will double, which decreases theefficiency (fig. 4.2).

The same reasoning also applies to the case where m < 1.

For example, if m = 0.5, at tR = 2000 hrs, the number of samples will be (1/2)0.5 = 0.71, and at tR =500 hrs, the number of samples will be 20.5 = 1.41, which increases the component hour by factorsof 1.42 and 0.7, respectively. This suggests that the efficiency can be increased to increase thenumber of samples, and reduce the time factor.

m = 2.0

m = 0.5

10

1

0.1

0.01

Cum

ulat

ive

Fai

lure

Rat

e F

(t)

(%

)

Test Time t tR = 200 hr

10E 1 10E 2 10E 3 10E 4 10E 5

Weibull Probability Paper

Figure 4.2 Concept of the Number of Samples Based on Weibull Distribution

For example, for m = 2.0, if the warranty period and the defect rate are 1000h and 0.1%,respectively, at tR = 2000h, F(tR) = approximately 0.4%, which reduces the number of samples toone-fourth the number that would otherwise be required.

4.2.3 Confidence Limits on the Failure Rate

The interval for reliability R is estimated so that the probability of the true value of the reliabilityR falling between the upper and lower bounds RU and RL will be 1 – . In this case, the quantity1 – is referred to as the confidence level, and as the risk rate.

There are two ways of making an interval estimate: a two-sided estimation and a one-sidedestimation. In this case, we consider a one-sided estimation in which the probability of reliabilitybeing less than or equal to the lower bound RL is . In actual practice, we estimate the one-sidedupper bound on the failure rate.

Rev. 1.0, 01/02, page 154 of 292

The lower bound RL on reliability R is determined by testing n samples of the product for which areliability R is required, and by determining the probability of a maximum of r failuresoccurring. In other words, in n sample, there are nCi possible combinations of i defects. Becausethe probability of defects is (1 – RL)

i and the probability of the remaining “pass” items is RL

n–i, thefollowing equation can be written:

Σ nCi(1 − RL)i RL

n−1 = βr

i =0

If the cumulative number of defects for a given test time is r(t) and the number of samples tested isn, the reliability and the non-reliability, respectively, will be

R(t) = 1 – r(t) / n

F(t) = r(t) / n

By substituting into the above binomial probability expression, if the probability of a maximum ofr defects occurring is = 0.1, we obtain

Σ nCi[r(t) / n] i [1 − r(t) / n]n−1 = βr

i =0

If n = 20, 50, 100, 1000, and the upper limit for the reliability r(t) that the number of defects willbe r or less is determined and the result is divided by the number r of defects, this determines theconfidence coefficient shown in table 4.3.

Thus, the coefficient to be multiplied varies with the number of samples n. If n is sufficientlylarge, approximately equal to 1000, the coefficient can be treated as a Poisson distribution (tables4.2 and 4.3).

If n is large and F(t) = r(t) /n is small, Poisson approximation is possible. The mean Poissondistribution m is

m = n × r(t) /n = r(t)

Therefore, the aforementioned binomial probability calculation can be approximated as follows:

Σ e−r(t) • [r(t)]

i/ i! = β

r

i =0

For r = 0, if = 0.1 (i.e. 1 – = 90%),

e–r ( t ) =

By taking the logarithm of the both sides,

r(t) = – ln

Rev. 1.0, 01/02, page 155 of 292

Therefore, for r = 0, the coefficient to be multiplied by the number of defects will be r = – ln =2.30. Similarly, for = 0.4(1 – = 60%), r = 0.92.

In both binomial probability and Poisson probability, the probability of r defects or less occurringcannot be obtained analytically in most cases. Therefore, the probability is solved by a computer-based successive approximation method. In the case of Poisson probability, r (t) is constant,irrespective of the value of n. By dividing the quantity r (t) by the number of defects r, we canobtain the coefficient to be multiplied by the upper limit on the confidence factor.

Table 4.2 shows confidence coefficients for reliability rates 90% and 60% corresponding withvalues of the number of failures r.

Table 4.2 Coefficient of Failure Rate Confidence Limit

Confidence Level Confidence LevelNumber ofFailures ( r ) 60% 90%

Number ofFailures ( r ) 60% 90%

0 0.92 2.30 6 1.22 1.76

1 2.02 3.89 7 1.20 1.68

2 1.55 2.66 8 1.18 1.62

3 1.39 2.23 9 1.16 1.58

4 1.31 2.00 10 1.15 1.54

5 1.26 1.85

Example: Two failures occurred when a 1000-hour life span test was conducted on 100 devices.Assuming an acceleration coefficient of 10 times, the failure rate with a 60% confidencelevel upper bound can be obtained as follows:

T = 100 × 1000 = 1 × 105 [h] r = 2

Acceleration coefficient = 10

Therefore, the Failure Rate will be

F.R. = 2 × 1.55 / (105 × 10) = 3.1 × 10–6 [h – 1]

Rev. 1.0, 01/02, page 156 of 292

Table 4.3 Dependence of the Reliability Upper Limit Coefficient of Binomial Probabilityon the Number of Samples n (case of r = 0 – 3)

rn

0 1 2 3

20 2.22 3.62 2.45 2.03

50 2.25 3.78 2.57 2.15

100 2.27 3.83 2.62 2.19

1000 2.3 3.88 2.66 2.22

4.3 Screening

4.3.1 The Purpose of Screening

With progress in LSI manufacturing process technology and improvement of quality control, thereliability of devices is improving each year, but initial or early failures (performance defects,short lifetime) still exist. The following is a list of reasons why these initial failures continue tooccur.

1. When many manufacturing processes are carried out variations in process accuracyaccumulated, producing products that are may be nearer the lower limits of quality andperformance.

2. Some devices have defects because of, for example, sub-microscopic specks of foreignmaterials adhering to them and with undesirable chemical impurities.

3. At each stage of the manufacturing process (in-process), it is difficult to remove products thatare marginal as to their mechanical and electrical characteristics.

The purpose of screening is necessary to remove products that have these deficiencies.

4.3.2 Screening Methods

Screening methods include techniques of reliability testing discussed above, that involve applyingstresses corresponding to the failure mode and failure mechanism involved. These stresses mustnot damage the device; and methods must be compatible with the various stages of themanufacturing process (in-process). An example of this is the internal visual inspection ofMIL-STD-883D.

Typical screening methods and the failure modes detected by each method are summarized intable 4.4.

As an example, consider the use of screening at burn-in.

Rev. 1.0, 01/02, page 157 of 292

When the distribution of accumulated failures in a product obeys the Weibull distribution, theshape parameter m of those failures is m < 1 in the case of the initial failure mode. When burn-in isapplied to this kind of product, as shown in fig. 4.3 the cumulative failure probability distributionafter burn-in x approaches m 1 so that the failure rate appears to be fixed. Here the burn-in timeis converted to the time under the normal environment in which the product is used. In otherwords, there is a time interval in which it is believed to correlate with the random failure region.After the time equivalent to the burn-in time has elapsed, the failure rate gradually decreases. Thisis the effect of screening. However, in the case of a product of which a low initial quality level andif the screening is inadequate, the cumulative failure probability in the market could become large.As a result, it is important to improve the initial quality level and in addition to set the appropriatescreening conditions (temperature, voltage, time). In addition to performing appropriate screening,it is necessary to consider the application of the device being screened, its construction, theprocess, and also to consider the possibility of side effects.

Note: *1 Reference: Shiomi Hiroshi “Introduction to Reliability Engineering,” 3rd RevisedEdition, Maruzen

m = 0.166667

10h

100h

1000h

10000h

Cum

ulat

ive

Fai

lure

Rat

e F

(t)

(%

)

Time (t )10E 0 10E 1 10E 2 10E 3 10E 4 10E 5

10

1

0.1

0.01

0.001

0.0001

Figure 4.3 Example of Screening Effect

The example in fig. 4.3 shows a case of an initial failure (m = 1/6, = 1 million hours) with burn-in time equivalent to market operating conditions used as a parameter (for example if theacceleration rate is 100 times, 10 hours is equivalent to 0.1 hour of burn-in).

Rev. 1.0, 01/02, page 158 of 292

Characteristics of screening by burn-in include:

1. A random failure mode occurs when m 1, which has nearly the same time duration as theburn-in time.

2. When the burn-in time is exceeded, the original curve is approached asymptotically.

3. The randomly occurring failure rate becomes lower, the more burn-in screening is done.

This is mathematically described as

= (m/) (t B/)m–1 (tB: burn-in time)

Rev. 1.0, 01/02, page 159 of 292

Table 4.4 Optimum Screening Methods for Each Failure Mode

Screening Item

Stresses AppliedClassification by

Characteristic MeasurementSpecial Tests

Failure Mode1.

Hig

h T

empe

ratu

re T

est

2.T

empe

ratu

re C

ycle

3.O

pera

tion

at H

igh

Tem

pera

ture

4.E

xces

s V

olta

ge A

pplie

d

1.C

hara

cter

istic

s M

easu

red

at N

orm

alT

empe

ratu

re

2.C

hara

cter

istic

s M

easu

red

at H

igh

Tem

pera

ture

3.C

hara

cter

istic

s M

easu

red

at L

owT

empe

ratu

re

4.F

unct

iona

l Ope

ratio

n M

onito

r

5.F

orw

ard

Dire

ctio

n V

F M

onito

r

6.M

easu

rem

ent o

f Lea

kage

Cur

rent

at

Max

imum

Rat

ed V

olta

ge

1.H

erm

etic

ity T

est

2.P

IND

Tes

t

3.X

-Ray

Pen

etra

tion

Comments

Wire BondingDefect

VF is effective for items that

can be measured.

Contamination(Mobile Ions)

Short Circuit dueto Broken Wire inAI or AU Wiring

Defective Sealing Molding voids.Visual inspection may beeffective.

Pinhole Confirm that normal (good)device is not damaged whenexcessive voltage is applied.

InsufficientBreakdownVoltage

Functional test is necessary;when there is an internaldefect.

Memory Data Loss(EPROM)

High temperature test is aneffective method forevaluation.

Temperature andVoltage MarginDefect

* * Including immobilecontamination.

Chip Cracking

Foreign MaterialsDielectric Layer

Wire Shorts Deterioration of characteristicsfrom use of strong X-rays.

AI WiringCorrosion

: Very effective

: Effective

Rev. 1.0, 01/02, page 160 of 292

4.4 Methods of Testing Reliability

Testing under actual conditions of use is believed to be the best method of reliability testing, but itis very difficult to obtain sufficiently accurate information within a limited time and at reasonablecost. Therefore, the conditions of actual use have to be simulated as much as possible. In general,the stress that is applied is limited to the amount that will not destroy the device being tested, butin some cases enough stress to destroy the device is deliberately applied so that failures can becreated quickly and analyzed. Controlling this type of stress is critical.

Reliability testing must be conducted by standardized methods so that the tests will bereproducible. These testing methods are specified in, for example, the Electronic IndustriesAssociation of Japan (EIAJ) standards, the JIS standards, the IEC standards and the MILstandards. Typical standards are the following.

EIAJ (Electronic Industries Association of Japan) standards

EIAJ ED-4701: Semiconductor device environment and durability testing methods

EIAJ ED-4702: Methods of testing the mechanical strength of surface-mountedsemiconductors

EIAJ ED-4703: Methods of evaluation and structural analysis within semiconductor devicemanufacturing processes

EIAJ EDX-4702: Static electricity destruction testing methods for semiconductor devices(device charging model)

EIAJ EDR-4701B: Semiconductor device handling guide

EIAJ EDR-4702: Table of comparison of semiconductor device quality and reliability testingmethods

IEC (International Electrotechnical Commission) standards

Publication 68: Environmental testing methods

Publication 749: Mechanical testing methods and environmental testing methods forsemiconductor devices

MIL (American Military Standards)

MIL-STD-202F: Testing methods for electrical and electronic components

MIL-STD-750C: Testing methods for discrete semiconductor devices

MIL-STD-883D: Microelectronics testing methods

These various standards are compared in the survey report EIAJ EDR-4702, to which referenceshould be made as necessary.

Next, we will outline the various tests, centering around the EIAJ standards.

Rev. 1.0, 01/02, page 161 of 292

Outline of Environmental and Durability Testing Methods

(1) Test of Ability to Withstand the Heat of Soldering (other than SMD)

The solder used has the composition Pb:Sn = 4:6; the flux used is rosin in an isopropyl alcoholor ethanol solvent (about 25%). The solder temperature and immersion time combination isselected from the following table; the leads are dipped once to a depth up to 1 to 1.5 mm fromthe main body of the sample. Normally condition A is used and the electrical characteristicsare evaluated.

Condition Solder Temperature ( C) Immersion Time (s)

A 260 5 10 1

B 350 10 3.5 0.5

(2) Test of Ability to Withstand the Heat of Soldering (SMD)

Unless otherwise specified, a humidified resin sample is baked for 24 hours at 125 ±5C in atemperature chamber.

(a) Non-vapor barrier packaging

The sample is humidified before it is heated. Unless otherwise specified, condition A isused. If the sample is stored in a location with average temperature of 30C and humidityof 70% or less, condition A is selected. If the average temperature is 30C and the humidity85% or less, condition B is selected.

If the SMD is thick and will be saturated with moisture after 168 hours, then condition Awith a time of 336 hours is selected.

Condition Temperature ( C) Relative Humidity (%) Treatment Time (hours)

A 85 2 65 5 168 24 or 336 24

B 85 2 85 5 168 24

Rev. 1.0, 01/02, page 162 of 292

(b) Vapor barrier packaging

The sample is humidified under the maximum temperature and humidity conditions thatwill exist in the vapor barrier package if the sample has been stored for a long time in it.Within four hours after the above operation, the sample is humidified under the storageconditions specified for the device after the vapor barrier package is opened. Humidify asspecified for the solder mounting method being used.

• Method 1: Infrared reflow or air reflow

Heat treatment condition

Heating Temperature(C)

Heating Time(seconds)

Peak Temperature(C)

1-A 235 5 10 1 240

1-B 220 5 10 1 225

SM

D M

ain

Bod

y S

urfa

ceT

empe

ratu

re

240°C max

235±5°C

150±10°C 150±10°C

225°C max

220±5°C

90±30s 90±30s

10±1s 10±1s

Time Time

SM

D M

ain

Bod

y S

urfa

ceT

empe

ratu

re

• Method 2: Vapor phase reflow


Heating Temperature ( C) Heating Time (seconds)

2-A 215 5 40 1

SM

D M

ain

Bod

y S

urfa

ceT

empe

ratu

re

90±30s

40±4s

Time

150±10°C

215±5°C

Rev. 1.0, 01/02, page 163 of 292

• Method 3: Immersion in wave solder tank


Heating Temperature ( C) Heating Time (seconds)

3-A 260 5 5 1

3-B 260 5 10 1

Direction of movement

Direction of movement

Dissolved solder Printed circuit board

• Method 4: Immersion of terminals in solder tank


Solder Temperature ( C) Immersion Time (seconds)

4-A 350 10 3.5 0.5

(3) Solderability Test

The flux is rosin dissolved in isopropyl alcohol or ethanol (about 25%). After the leads areimmersed in the flux for 5 to 10 seconds, they are dipped in solder to a distance of 1 to 1.5 mmfrom the main body of the sample. A condition is that solder must adhere to 95% or more ofthe portion that was immersed. As long as the leads do not reach the specified immersiontemperature, the times specified in parentheses may be used for samples of small heat capacity.

ConditionSymbol

Immersion Temperature(C)

Immersion Time(seconds)

Remarks

A 235 5 5 0.5 (2 0.2) Used for wave soldering

B 215 5 10 0.5 (3 0.3) Used for reflow soldering

(4) Thermal Shock Test

Test Condition A B C D E

High temperature side (C) 100 + 0 – 5 125 5 150 5 200 5 Tstg max 5

Low temperature side (C) 0 + 5 – 0 –55 5 –65 5 –65 5 Tstg min 5

LiquidUsed

High TemperatureSide

Pure water Suitablemedium

Suitablemedium

Suitablemedium

Suitablemedium

Low TemperatureSide

Pure water Suitablemedium

Suitablemedium

Suitablemedium

Suitablemedium

Rev. 1.0, 01/02, page 164 of 292

(a) Method 1 (case in which the mass of the sample by itself exceeds 1.5g)

High temperature side 15 seconds or more 5 cycles

Low temperature side 5 seconds or more 5 cycles

Transition must be completed within 10 seconds.

(b) Method 2 (case in which the mass of the sample by itself is 1.5g or less)

High temperature side 15 seconds or more, not more than 5 minutes, 5 cycles

Low temperature side 15 seconds or more, not more than 5 minutes, 5 cycles

The transition must be completed within 3 seconds.

(5) Temperature Cycle Test

(a) Temperature cycle holding time

Mass of the Device by Itself m (g) Stages b, d Stages a, c

m 15 5 minutes or less 10 minutes or more

15 m 150 15 minutes or less 30 minutes or more

150 m 1500 30 minutes or less 60 minutes or more

(b) Test conditions

Temperature Time

a Minimum storage temperature (Tstg min)

b 5 to 35C

c Maximum storage temperature (Tstg max)

d 5 to 35C

Select 1 condition according to themass of the device by itself.

(c) Test condition tolerances

Temperature Limits ( C) Tolerance ( C)

High Temperature Side 125 or more 5

Less than 125 53

Low Temperature Side –25 or more 35

Less than –25 5

Rev. 1.0, 01/02, page 165 of 292

a b c d

Tstg max

Tstg min

1 cycle

TN

(6) Temperature and Humidity Cycle Test

It is necessary to control the test so that the humidity does not reach 100%RH.

Stage Condition

Time a c d f 2.5 h

b e h 3.0 h

g i 1 to 4 h

Temperature TN 25 2C

TU 65 2C

TL –10 +3/–5C

Humidity a b d e g i 90 to 96% RH

c f 80 to 96% RH

h Arbitrary

a

1 cycle

b c d e f g h i

TU

TN

TL

Supplement

Rev. 1.0, 01/02, page 166 of 292

(7) Hermetic Seal Test

Method 1 (test for small leaks using radioisotope)

Method 2 (test for small leaks using helium gas)

Method 3 (test for large leaks using bubbles)

(8) Shock Test

Select shocks corresponding to the maximum acceleration and pulse period to which thedevice is expected to be subjected from the following table. Select the acceleration consideringthe material of the device and its shape. One must be careful that the test does not become ameaningless destructive test.

Note: As a rule this test is applied to cavity type packages.

Acceleration [m/s 2] Pulse Width [ms] Number of Times

A 1000 (100G) 6 3 times in each direction

B 5000 (500G) 1

C 15000 (1500G) 0.5

(9) Fixed Acceleration Test

Unless otherwise specified, the specified acceleration is to be applied in each of the X1, X2,Y1, Y2, Z1 and Z2 directions for one minute. Centrifugal force is to be increased until thespecified acceleration is reached. Then the slowdown to zero is to be done gradually, over 20seconds or more.

Note: As a rule this test is applied to cavity type packages.

Acceleration (m/s 2)

A 50000 (5000G)

B 100000 (10000G)

C 200000 (20000G)

D 300000 (30000G)

(10) Vibration Test

This test is applied mainly to cavity type packages.

Vibrations are applied in three directions, X, Y and Z. The test is conducted for equal time ineach direction.

Rev. 1.0, 01/02, page 167 of 292

Type of Vibration Frequency Variation

Frequency Range 100–2000 Hz

Total Amplitude or Acceleration 200 m/s2 (20G)

Proportion of Sweep 100–2000–100 Hz about 4 minutes

Method of Sweep Logarithmic frequency sweep or uniform sweep

Direction of Sweep 4 cycles each in the X, Y and Z directions

Test Time 48 minutes

(11) Lead Strength Test

Application of lead strength test method

Terminal Shape Tension Torsion Bending Torque

Lead Wire Terminal (can type etc.) O O O

Plate Terminal 1 (DIP, SIP, etc.) O O

Plate Terminal 2 (SOP, QFP, TSOP, etc.) O

Plate Terminal 3 (SOJ, QFJ, etc.) Not used

Stud Terminal (power diode etc.) O

Pin Terminal (PGA etc.) O

O: Indicates the test method that is used.

(a) Tension test

The specified tension is applied in the direction of the terminal, and held for 10 ±1 seconds.In the case of a device for which the terminal cross-sectional area is 0.03 mm2 or less, aseparate specification is given.

Nominal Cross-sectional AreaS (mm 2)

Nominal Wire Diameterd (mm)

Tension Force(N)

0.03 S 0.05 0.2 d 0.25 1

0.05 S 0.07 0.25 d 0.3 2.5

0.07 S 0.2 0.3 d 0.5 5

0.2 S 0.5 0.5 d 0.8 10

0.5 S 1.2 0.8 d 1.25 20

1.2 S 1.25 d 40

Rev. 1.0, 01/02, page 168 of 292

(b) Torsion test

This test is only applied to lead wire terminals.

6.0–6.5 mm

1.2±0.4 mm

Sample

Sample Holder

Rotations take about 5 seconds for each complete turn.

Symbol Turn Angle (degrees) Number of Turns

A 360 3

B 180 2

(c) Bending test

The specified load is suspended at the terminal tip for 2 to 3 seconds; during this time themain body of the device is bent 90 degrees and then returned to its original position. Thiscounts as one cycle. The main body is then bent in the opposite direction through 90degrees and returned.

Unless otherwise specified, the test is performed two cycles as described above.

Nominal Cross-sectional AreaS (mm 2)

Nominal Wire Diameterd (mm)

Tension Force(N)

0.03 S 0.05 0.2 d 0.25 0.5

0.05 S 0.07 0.25 d 0.3 1.25

0.07 S 0.2 0.3 d 0.5 2.5

0.2 S 0.5 0.5 d 0.8 5

0.5 S 1.2 0.8 d 1.25 10

1.2 S 1.25 d 20

Rev. 1.0, 01/02, page 169 of 292

(d) Screw terminal torque test

The specified torque is applied to the screw terminal in a plane at right angles to theterminal axis for 10 ±1 seconds.

Test Condition SymbolNominal Diameter of Screw(mm) A (N • m) B (N • m)

2 0.3 —

2.6 0.4 0.2

3 0.5 0.25

3.5 0.8 0.4

4 1.2 0.6

5 2 1

6 2.5 1.25

(12) Tightening Strength Test

(a) Method 1: Torque test

The specified nut(s), bolt(s) and washer(s) are used with the sample, tightened to thespecified torque and left there for 10 ±1 seconds, then removed.

Object of testing: The sample is tightened at the appropriate location(s).

(b) Method 2: Snap-fit strength test

The specified snap-fit pressure is applied uniformly to the surface of the sample to whichconnectors are snap-fitted, held there for 10 ±1 seconds and then removed.

Object of testing: Flat plate

(13) Salt Water Spray Test

Salt water at 35 ±2C is sprayed on the sample for the specified time.

Concentration: 5 ±1% (by weight)

pH: 6.5 to 7.2

Salt deposition rate: 10 to 50g/m2/d

Symbol Test Time (hours)

A 16 ± 1

B 24 ± 2

C 48 ± 4

D 96 ± 4

Rev. 1.0, 01/02, page 170 of 292

(14) Resistance to Solvents Test

This test measures the ability of the marking to withstand the solvents used to remove fluxafter soldering. The sample is completely immersed in the solvents listed in the table belowunder the specified conditions. After the sample is removed from the solvent, it is dried for aminimum of five minutes, then rubbed back and forth five times with absorbent cotton or thinpaper with a pressure of 5±0.5 N/cm2.

Types of solvent

Type of Solvent Solvent StandardSolvent Temperature

(C)Immersion Time

(minutes)

Isopropyl Alcohol JIS K 1522 or JIS K 8839 23 5 5 0.5

Distilled Water orDeionized Water

Conductivity 2 ms/m or less

Resistivity 500 m or more

55 5 5 0.5

(15) High Temperature Storage Test

Storage is to be done at the rated maximum storage temperature (Tstg max); the test time is tobe specified as appropriate for each case.

Allowable temperature in chamber

Temperature ( C) Tolerance ( C)

Less than 125 53

More than 125 5

(16) Low Temperature Storage Test

Storage is done at the maximum rated storage temperature (Tstg min). The test time isspecified as appropriate for each case.

Temperature ( C) Tolerance ( C)

Less than –25 5

More than –25 35

Rev. 1.0, 01/02, page 171 of 292

(17) Moisture Resistance Test

The sampler is placed in a tank at high temperature and high humidity. Distilled water ordeionized water is used at temperature 23C, pH 6.0 to 7.2 and resistivity 50 k • cm or more.Applied voltage and the test time are specified as appropriate in each case.

Letter Temperature ( C) Relative Humidity (%)

A 40 2 90 5

B 60 2 90 5

C 85 2 85 5

(18) Steam Pressurization Test

(a) Unsaturated test

The applied voltage is specified as appropriate in each case. If the power consumption islarge, the voltage is applied intermittently; the power supply is turned ON and OFFcyclically for specified time. The appropriate test time must be specified for each case.

Symbol Temperature ( C) Relative Humidity (%) Steam Pressure 105 (Pa)

A 110 2 85 5 1.2

B 120 2 85 5 1.7

C 130 2 85 5 2.3

(b) Saturated test (for reference)

Pressure inside chamber: 2 atmospheres (gauge, 2.03 105 Pa)

Temperature: 121C

(19) Electrostatic Discharge Test

(a) Human body model

The sample terminal to be tested is connected to a reference terminal via a test circuit. Thetest terminal is selected at random from among all of the terminals that have not beenselected as the reference terminal at that time. All of the terminals other than the testedterminal and the reference terminal are left open.

After the test voltage has been set, the capacitor is charged, the switch S1 is connected tothe test terminal and the capacitor is discharged three times. The discharges are at intervalsof one second or more; the ambient temperature is 25±5C.

Rev. 1.0, 01/02, page 172 of 292

SampleHigh VoltagePower Supply

S1

S2C(=100pF)

R1 R2(=1500Ω)

(b) Reference test (Machine model)

The test voltage (V) is specified as appropriate in each case. The same operation is repeatedwith both positive and negative pulses to make one cycle. The ambient temperature is255C. The voltage is applied for one cycle or five cycles.

The voltage tolerance is within –5 to 0 % of the specified voltage. The capacitor toleranceis within 5% of the specified value. Voltage is applied for one cycle as standard. If it isapplied for five cycles the interval between cycles is one second or more, and it is appliedto all terminals except the reference terminal. All terminals except for the referenceterminal are open. Except for the test with the human body model described above, the testis considered to be conducted with a device charging model by either the package chargingmethod or the device charging method (refer to section 3.2, Failure Modes andMechanisms).

SampleV

R1 R2

S1

C

Letter R 2 C

C 0 200 pF

D 1.5 k 100 pF

R1 = 1 M

Rev. 1.0, 01/02, page 173 of 292

(20) Latch-up Test

The conditions for test method 1 and test method 2 are specified separately.

(a) Method 1: Pulse current injection method

(Case of positive current)

Trigger Pulse Power Supply VCC

ICCMeasurement

The input terminal is connected to the power supply or GND.

Sample

GND

The output terminal is open.

−

+

Power Supply

A

−

+

(Case of negative current)

VCC

Sample

GND


ICCMeasurement

+

−

Power Supply

A


+

−

Trigger Pulse Power Supply

Test Terminal

Rev. 1.0, 01/02, page 174 of 292

(b) Method 2: Power supply excessive voltage method

VCC

Sample

GND


ICCMeasurement

+

−

Power Supply

A


+

−

Trigger Pulse Power Supply

Test Terminal

(21) Flame Resistance Test for Plastic Encapsulated Devices

Use a burner tube of length 35mm or more, inner diameter of 0.5±0.1 mm and outer diameterof 0.9 mm or less.

Outer Diameter maximum 0.9 mmInner Diameter 0.5 ±0.1 mm

Gas Supply

12 ±1 mm

35 mmor more

(22) Continuous Operation Test

Electrical stress is applied continuously for 1,000 hours at the maximum operating temperature(Topr max).

Rev. 1.0, 01/02, page 175 of 292

(a) High temperature DC test

Connect the specified input voltage V1 to the input terminal and load RL to the outputterminal.

V1

1 2

RL RL

Power Supply

(b) High temperature AC test

Connect the specified input signal to the input terminal and the specified load RL to theoutput terminal.

1 2

RL RL

Power Supply

(c) High temperature ring oscillation test

The inverter in the figure is necessary when Tn is an even number, or the circuit is a non-inverter circuit.

1 2 n

Power Supply

Inverter

For a high temperature AC test, in the case of a simple gate circuit, (c) ring oscillationoperation may be performed.

Rev. 1.0, 01/02, page 176 of 292

(23) Intermittent Operation Test (Power On—Power Off)

The input, or all or part of the power supply, is turned ON and OFF cyclically, in the samemode as in the continuous action test (22). The ambient temperature is the maximum operatingtemperature (Topr max); the test time is specified as appropriate in each case.

(24) Soft Error Test (MIL-STD-883E)

Use 241 Am or 228 Th as a radiation (normally 0.37, 3.7, 37 kBq). The chip is directlyirradiated with alpha radiation and the ability of the device to withstand alpha radiation isevaluated.

The software error rate (SER) is calculated by the following formula.

SER =EtCT

AXt4d2 × 1

P( (E: Number of ErrorsT: Test Time (min)C: Equivalent Coefficient, Equal to 2.22 1012 (min • FIT)A: Amount of Radiation per hourX: Radiation Intensity (kBq)t: Proportion of Alpha Raysd: Distance from the Device (cm)P: Radiation Amount of Entire Package (Alpha/cm2h)

Rev. 1.0, 01/02, page 177 of 292

Section 5 Reliability Prediction

Increasing integration of semiconductor devices contributes not only down sizing and theadvanced functions of electronic equipment, but also to the high reliability of the equipment byreducing the number of parts. To predict the failure rates of electronic equipment, it is necessaryto examine the failure rates of all components, such parts as semiconductor devices, resistors,capacitors and switches, and solder joints.

The prediction failure rate of semiconductor devices consist of accelerated tests and surveys of theconditions under which the failures occur in actual use. These methods are described in sections(1) and (2) below.

(1) Accelerated Tests

The tests used to predict actual lifetime in a short period are called accelerated lifetime tests.

Under JIS these are defined as, “Tests which are conducted under more severe conditions thanstandard, in order to shorten the test time.” However, during this type of testing it is essential thatthe failure mode and its cause do not change or vary. Various factors, such as temperature,moisture, applied voltage and mechanical strength, affect the lifetime of semiconductor products.For example in the case of temperature accelerated tests, by exposing semiconductor devices tothermal stress, as the accelerated factor, the main cause of failure is activated and failure isinduced in a shorter period of time, than under conditions of actual or normal use. In other words,thermal stress activates destructive, chemical and physical reactions, the main causes of devicefailure, and when they exceed certain limits, it is possible to induce failures at an accelerated rate.For example, destruction of junctions, gate insulation film and inter-layer insulation film, alsobreaks in metallization and contacts manifest the failure mechanisms. These phenomena can beexplained by the reaction theory model.

(2) Methods of Surveying Failure Conditions in the Market

When developing new products, we assess reliability design and, using various reliability tests andprocess data. We verify that reliability of the design agrees with the design specifications.Products, which pass this assessment, are mass-produced, but, unfortunately, defective productsmay still occasionally occur. We can predict failure rate and define the failure mode by collectingand processing data on defective products. Data processing is done using statistical methodsbased on statistical theory, it is complex and arduous.

The Weibull probability paper, normal probability paper, lognormal probability paper and thecumulative hazard probability paper are used as tools to do this easily. More recently it hasbecome possible to use personal computers to assist in processing this data. The most convenientand most frequently used tools are the Weibull probability paper and the cumulative hazardprobability paper. Examples of data analysis using the cumulative hazard probability paper arepresented in section 5.3.2, Failure Prediction by Aggregation of Failure Occurrence Data.

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5.1 Basic Failure Model

Substances deteriorate when the equilibrium conditions related to thermal, electrical or mechanicalstress change, or when chemical or structural changes occur. In semiconductor devices, thereaction theory model is commonly used. This model is the progression of destructive physicaland mechanical reactions, which cause failure when they exceed certain limits. In particular, forsemiconductor devices temperature is a commonly used accelerating factor for most failuremodes.

(1) Arrhenius Model

The Arrhenius model generally expresses dependence of reaction speed on stress due totemperature. According to the speed of reaction theory, to progress from the normal state(standard state) to an unfavorable state (destructive state) it is necessary to pass over an energybarrier, as shown in table 5.1. This energy is called activation energy (Ea). This energy Ea isprovided by the environment. Atoms and molecules become more excited when the supply ofenergy increases, and some of them exceed the Ea barrier. The probability of transition from thestandard state to the destructive state takes the form, exp (–Ea/kT); this is called the MaxwellBoltzmann distribution. This reaction speed is expressed as below.

Activated State

Standard State

Destructive State

Ea (Activation Energy)

Figure 5.1 Activation Energy

Reaction Speed K = exp (– Ea/ kT)

Ea: Activation Energyk: Boltzamann Constant = 8.6157 10–5(eV/K): ConstantT: Absolute Temperature K

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where, because the shorter lifetime (L) has the faster speed of reaction. Lifetime is inverselyproportional to speed of reaction, then lifetime can be expressed as

L = A exp (Ea/kT)

Further, the acceleration coefficient expresses the multiplication factor of each lifetime L1 and L2

under condition 1 (standard state) and condition 2 (accelerated state) respectively.

The acceleration coefficient for the reaction can be calculated by

Acceleration Coefficient = L1 / L2 = exp [Ea/ k • (1/T1 1/T2)]

(2) Eyring Model

The Eyring model is an extension of the Arrhenius model, which, with the exception oftemperature considers the affects of voltage and mechanical stress. The reaction speed; K; in theEyring model is expressed as below.

K = a(k • T / h) e–Ea/k • T • S

a: Constant: Coefficient Expressing Dependence of StressEa: Activation Energyk: Boltzamann Constant = 8.6157 10–5 (eV/K)h: Planck Constant = 6.626 10–34 (Jsec)S: Applied Stress (except Temperature)

For a small change in temperature, the equation above can be expressed as follows.

K = e–Ea/k • T • S

: Constant

Further, if the temperature is constant, to consider stress alone, then lifetime L, can be expressedby the equation:

ln L = A – • ln S

A: Constant

This Eyring model is often applied in accelerated tests for stress. For example, in the case of heatfatigue of plastics, if stress is taken as alternating stress and lifetime is taken as the repeatedlifetime frequency N, then if N1 and N2 are the lifetimes for the alternating stress S1, S2 respectively,then

ln (N1 / N2) = • ln (S2 / S1)

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Also, as the representative example of temperature cycle tests, if stress is represented bytemperature difference (T), and if M is the number of temperature cycles to failure, then asabove, this can be expressed as

ln (M1 / M2) = • ln (T2 /T1)

Relation of ln L to stress corresponds with ln N to ln S (S N curve) (fig. 5.2).

ln N

In N = Constant − α In S

Life

time

SL SUln S

Figure 5.2 Relation Between Repeated Lifetime and Stress

5.2 Accelerated Lifetime Test Methods

(1) Means of Acceleration

Accelerated lifetime tests are conducted under stress conditions more severe than actual conditionsof use (fundamental conditions). They are methods of physically and chemically inducing thefailure mechanisms to assess, in a short time, device lifetime and failure rates under actualconditions of use.

Means of acceleration are as follows.

Make the stress more severe (for example, high temperature, high voltage).

Increase the frequency of the applied stress.

Establish more critical criteria for judging failure (assess a limited number of samples in ashort time).

Make and evaluate test devices with structures that are more sensitive to particular failuremodes.

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(2) Applied Stress Method

Examples of how stress is applied in accelerated lifetime tests are constant stress, and step stressmethods. The constant stress method is a lifetime test where stress, such as temperature orvoltage, is held constant and the degree of deterioration of properties and time to failure lifetimedistribution are evaluated. In the step stress method, contrary to the constant stress method, thetime is kept constant and the stress is increased in steps and the level of stress causing failure isobserved. This relation is shown in fig. 5.3. In the figure, the continuously increasing stress testcan be consider as a step stress test where the constant time is extremely short.

Str

ess

Time (t )

Distribution Stress (Strength) Causing Failure f (S)

Continuously Increasing Stress Test

Constant Stress Constant Stress Test

Step Stress Test

Distribution of Time Resulting in Failure (Lifetime Distribution)

Figure 5.3 The Outline of Each Stress Tests

The constant stress method determines the lifetime distribution for a given stress and the stepstress method determines the distribution of stress resulting in failure when time is constant.Assuming the failure mechanism does not change, the results obtained from these two methodscan be expected to fall on the same straight line in a graph of the Arrhenius model or the Eyringmodel.

Representative examples of tests using the constant stress method, the step stress method, and thecyclic stress method, a variation of the constant stress method, are shown in table 5.1.

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Table 5.1 Distribution of Representative Accelerated Lifetime Tests

Applied StressMethod

Features Accelerated Test Main Cause Failure Mechanism

High TemperatureStorage Test

Temperature Junction Degradation, ImpuritiesDeposit, Ohmic ContactDegradation, Inter-metallicchemical compounds

Operating LifetimeTest

Temperature

Voltage

Current

Surface Contamination, JunctionDegradation, Mobile Ions, EMD

High Temperature-High HumidityStorage

Temperature

Moisture

Corrosion, SurfaceContamination, Pinhole

Constant StressMethod

Investigation of theeffects of constantstress on a device

High Temperature-High Humidity Bias

Temperature

Moisture

Voltage

Corrosion, SurfaceContamination, JunctionDegradation, Mobile Ions

Temperature Cycle TemperatureDifference

Duty

Cracks, Thermal Fatigue, BrokenWires and metallization

Power Cycle TemperatureDifference

Duty

Insufficient Adhesive Strength ofOhmic Contact

Cyclic StressMethod

Investigation of theeffects repeatedstress

Temperature-Humidity Cycle

TemperatureDifference

MoistureDifference

Corrosion, Pinhole, SurfaceContamination

Operating Test Temperature

Voltage

Current

Surface Contamination, JunctionDegradation, Mobile Ions, EMD

Step StressMethod

Investigation of thestress limit that adevice canwithstand

High Temperaturereverse Bias

Temperature

Voltage

Surface Contamination, JunctionDegradation, Mobile Ions, TDDB

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5.3 Examples of Failure Rate Prediction

Prediction of failure rate is important for system reliability and integrity design when usingsemiconductor devices in electronic systems.

5.3.1 Reliability Data

This section first discuss reliability data (documentation) used before going into failure rateprediction.

During the development stage of semiconductor devices internal quality certification evaluatesoverall reliability and quality, not just electrical characteristics and functions. During reliabilityevaluation, each type of test is performed (including the following stresses operating life, moistureresistance, thermal resistance, mechanical resistance, and environment resistance tests). Duringthese tests, assessment is based on pass or fail as to whether the product meets marketrequirements.

Reliability data published by Hitachi are summaries of reliability test results obtained from qualitycertification. The format of reliability data differs slightly with the type. Table 5.2 shows anexample of a microprocessor product (function: single chip microcomputer, wafer process: 0.8 mCMOS, package: PLCC).

Reliability tests include lifetime tests (an endurance tests), environment tests, and mechanicaltests. The operating life test primarily evaluates the various components, such as elements andmetallization patterning, and oxide films formed on the chip, as well as the moisture resistance ofplastic packages. The environment test mainly evaluates resistance to the thermal stress exertedduring actual use.

Test results are presented as the number of failures and the number of tested items. The failure ratefor a product can be obtained from these results. For example solderbility, in table 5.2, has a lottolerance percent defective (LTPD) of 10% pass standard, and high-temperature unbiased storagehas a lot tolerance failure rate (LTFR) of 10%/1000 h.

Further, failure rates can be estimated using the test results in reliability data. The examples givenhere use the methods described under JIS-C5003, “General Test Procedures for Failure Rate inElectronic Components.” Failure rates for the operation lifetime test results in table 5.2 can beobtained from

Failure Count (r) × Coefficient (a)Total Component Hour (T)

=

= 2.0% (1/1000 h)

= 2.0 × 10 5 (1/h)

0.9245 × 1000

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In this calculation, for failure count r = 0, a reliability standard of 60% (60% confidential level)and the coefficient of, a = 0.92 for a 60% reliability standard, were used.

The value calculated here is the failure rate obtained under accelerated test conditions. However,to obtain the failure rate for conditions of actual use, the above value is divided by the accelerationcoefficient.

In the accelerated test conditions, the accelerated factors are temperature and applied voltage.Activation energy is the parameter used to express the degree of acceleration due to temperature.This differs with the failure mechanism, but a representative value for each failure mechanism canbe obtained (see section 3).

The above failure rate calculation was obtained from the data of individual products of amicroprocessor. Since the test sample size was limited, the total component hours (Total test items Time) is small, and even if there is zero failure, the estimated value becomes comparativelylarge. However, it can be confirmed that the actual failure rate is even lower, by including datafrom other products. This is based on design standardization.

Hitachi believes that reliability design is very important to ensure semiconductor device qualityand reliability. In reliability design, standardization of design is currently on going. Throughstandardization, quality and reliability can be maintained at the same standard, even if devicecharacteristics and functions differ. The main objects of standardization are circuits, elements,modules, layout, wafer processes, structure, package design, components, and materials.

For these standardized elements, quality and reliability are evaluated and confirmed beforehandusing such methods as TEG, Test Element Group. Since the quality and reliability of individualproducts are based on these standardized elements, they can all be maintained to the samestandard.

When considering the actual reliability of individual products, it is essential to consider the testresults in conjunction with test results of other products, which have the same fundamental design(the same product family), such as the wafer process and construction. Examples ofstandardization for wafer process design include CMOS 1.3 m, 0.8 m, 0.5m, 0.35m; and thestructural design is standardized by the external configuration, such as DIP, QFP, PLCC packagedesigns. Items with the same standardized elements, including the wafer process and package, canbe treated as a single product family.

The microcomputer in table 5.2 is manufactured with a CMOS 0.8 m wafer process, using aPLCC package. Table 5.3 shows individual products which use the same wafer process.

The failure rate (0.51%/1000 h = 5.1 10–6 (1/h), Ta = 125C, reliability standard of 60%)calculated by adding the test data (not shown here) of these individual products is the estimatedfailure rate for SH7034.

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It is normal for many products, dedicated logic and microcontrollers, with different characteristicsand functions to be developed from one wafer process and package type (same family). Bycomparison, for memory products, each individual product line is usually developed from onewafer process and package. Table 5.2 is inserted as an example of reliability test results. Inpractice the reliability data submitted to customers contain test hours and number of sampleswhich differ from those shown in table 5.2.

Table 5.2 SH7034 (HD6437034) Reliability Test Results

Classification Test Item Test Conditions Results *

High temperature operation Ta = 125C, Vcc = 5.5 V, t = 1000 h 0/45

High temperature storage Ta = 150C, t = 1000 h 0/22

Low temperature storage Ta = –55C, t = 1000 h 0/22

High temperature-high humidity storage Ta = 65C, RH = 95 %, t = 1000 h 0/77

Lifetime Test

High temperature-high humidity bias Ta = 85C, RH = 85 %, Vcc = 5.0 V,t = 1000 h

0/22

Temperature cycle –55C to 150C, 200 cycles 0/45

Thermal shock 0C to 150C, 15 cycles 0/22

Solderability 230C, 5 s, rosin type flux 0/22

Solder heat resistivity infrared rays reflow 235C, 10 s 0/22

EnvironmentTest

Pressure cooker (PCT) Ta = 121C, RH = 100%, t = 100 h 0/22

Mechanical Test Lead pull strength 2.5 N, 10 s, 1 time 0/22

* Failure count/sample size

Table 5.3 Other Devices Using Same Process as SH7034

Product Product Number

Microprocessor Unit SH7034A, SH7042/43, SH7050

Microprocessor Peripheral LSI H8/2244, H8S/2246, H8S/2655, HD66330485, HD64411F

Next we will explain the general procedure for failure rate prediction of Hitachi semiconductordevices, based on reliability test data.

(1) Failure Rate Prediction Based on Temperature Accelerated Tests

Temperature accelerated tests induce failures in a shorter period of time than occur underconditions of the actual working environment. In these tests thermal stress, the accelerating factor,is applied to semiconductor devices to activate failure mechanisms (failure factors). In otherwords, thermal stress induces chemical and physical reactions and when exceeding a certain limitcauses device failure to be accelerated. For example, destruction of junction, gate insulation filmand interlayer insulation film, and breaks in metallization or contacts, develop as failuremechanisms. The reaction theory model discussed earlier can explain these kinds of phenomena.

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High temperature operation tests and high temperature storage tests are representative oftemperature acceleration test methods. The temperature acceleration factor is expressed by a unitof measurement called activation energy (Ea). This value varies according to the failuremechanism. If the Ea value is large, the temperature acceleration characteristic is large. If it issmall, the temperature acceleration characteristic is also small. When predicting failure rate fromreliability test results Ea is considered indispensable.

The failure rate under conditions of actual use can be predicted from the high temperatureoperating life test in table 5.2 SH7034 Reliability Test Results, (125C, 5.5V operating life test),as explained below.

The conditions of actual use are

Ta = 40C

VCC = 5.0 V

assuming Tj = Ta, calculated as follows. (Where Tj is the junction temperature.)

Generally activation energy (Ea) can be determined from the evaluations of the various thermalconditions, however from previously accumulated records, supposing

Ea = 0.80 eV

then, the procedure for prediction of the failure rate for conditions of actual use is as follows.

First, calculate the acceleration factor (temperature acceleration coefficient r) for conditions ofthe temperature accelerated test against conditions of actual use. The product of the temperatureacceleration coefficientr and the test time is equivalent to operating time under conditions ofactual use. In other words, if temperature accelerated test time is L(Tb), the operation time underconditions of actual use is L(Ta), then

L(Ta) r L(Tb

From the Arrhenius model, the relation between L(Ta) and L(Tb) can be expressed by

L(Ta) C • eEa/kTa

L(Tb) C • eEa/kTb

where Ta: Temperature under Conditions of Actual Use (40C)Tb: Temperature under Accelerated Conditions (125C)Ea: Activation Energy (0.80 eV)k: Boltzmann Constant (8.6157 10–5 eV/K)C: Constant

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Therefore, the acceleration factor r is

γ r = =

= [e0.80/8.6157×10−5 (273+40)] / [e0.80/8.6157×10−5 (273+125)]

= 561.8

L(Ta)L(Tb)

eEa/kTa

eEa/kTb

This shows that compared to conditions of actual use, the temperature accelerated test has anequivalent acceleration factor of approximately 560 times and time to failure is reduced by a factorof 560 times. Consequently, the operating time L(Ta) under conditions of actual use is equivalentto

L(Ta) = 560 1000 (h) = 560000 (h)

Considering reliability test data of the SH7034 product family described in the previous section,the failure rate under the temperature accelerated test is calculated:

Failure rate = 5.1 10–6 (1/h)

The failure rate under conditions of actual uses is equivalent to the failure rate under thetemperature accelerated test divided by the acceleration factor r:

Failure rate = 5.1 10–6/560= 9.1 10–9(1/h) 9(FIT)

Therefore, 9(FIT) becomes the expected value for the SH7034.

If the temperature accelerated test is 1000 hours of continuous operation, this is equivalent to560000 hours (roughly 64 years) of continuous operation under conditions of actual use.However, very few systems, equipment, or devices are used continuously for 560000 hours. If thestress during operation is larger than that while in standby, it is possible to estimate a value whichis close to the failure rate under conditions of actual use by multiplying by the reduction factor.

In temperature accelerated tests, the higher the temperature within a certain range, the shorter thetime to failure. However, for excessive temperatures, failures that would not occur in actual use,are sometimes induced (in other words, failure may be caused by a completely different failuremechanism than what will be found in actual use). Therefore certain precautions must be takenabout that. Generally, 125C is used operating life tests to minimize probability of inducingdifferent failure mechanisms.

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(2) Failure Rate Prediction Based on Voltage Accelerated Tests

Voltage (electric field) stress is applied as the acceleration factor in voltage accelerated tests.Voltage stress can induce destructive physical reactions. Failure is accelerated when exceedingcertain limits of a specific voltage level. See section 3 for details on failure mechanisms. Onerepresentative test for voltage acceleration is the TDDB test. The voltage acceleration factor () isshown the conversion factor of the electrical field strength generated by the voltage applied todevice structures as the thickness of oxides. Like activation energy, these values differ accordingto the failure mechanism. If is large, the voltage acceleration factor is large, and conversely if is small, the voltage factor is small.

The voltage acceleration coefficient expresses the dependence of time to failure on externallyapplied voltage. However, because the externally applied voltage is fixed by user requisites, thestrength of the electric field applied to internal elements has increased with the miniaturization ofsemiconductor devices. This means the more device miniaturization progresses the greater theeffect of the externally applied voltage. Therefore, it is necessary to conduct reliabilitycomparisons with a normalized voltage acceleration coefficient expressing an electric fieldstrength independent of the miniaturization process. However, field strength for each device mustbe derived from the device configuration and circuit (or circuit analysis).

The following is an example of failure rate prediction for actual use conditions.

Since gate oxide films tend to experience the most impact from electric fields, we will analyze theimpact if the thickness of the film is 10nm with the voltage applied across the oxide layer duringaccelerated tests is 6.0V and 3.3V during actual use, then

Accelerated Test Conditions and Results

Electric Field Strength: 6.0(MV/cm)

Test Ambient Temperature (Ta): 150(C)

Test Result (1000h): 0/22

Conditions of Actual Use

Electric Field Strength: 3.3(MV/cm)

Ambient Temperature (Ta): 55(C)

In this case, TDDB can be applied as a failure mode. For details of TDDB please refer tosection 3.

MTTF = A • 10–E exp (Ea/kT)

MTTF: Mean Time to FailureA: Constant: Voltage Acceleration Factor (cm/MV)E: Electric Field Strength (MV/cm)

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Ea: Activation Energy (eV)T: Absolute Temperature (K)k: Boltzmann Constant (8.6157 × 10–5 eV/K)

If for actual operation MTTF = MTTF1, and for accelerated tests MTTF = MTTF2, then

E1: Electric Field during actual use : 3.3(MV/cm)E2: Electric Field during accelerated tests : 6.0(MV/cm)T1: Temperature during actual use : 328(K)T2: Temperature during accelerated tests : 423(K)

If under the worst scenario = 1.0, Ea = 0.3, then,

from this if the lifetime of actual use is calculated from the voltage accelerated tests using theTDDB model and can be derived as follows:

where

if for actual use MTTF = MTTF1, and for accelerated test MTTF = MTTF2, then

MTTF1/MTTF2 = [10–1×3.3 exp (0.3/k × 328)] / [10–1×6.0 exp (0.3/k × 423)]= 5438 times

Further, under these conditions of use, the failure rate (Reliability standard of 60% (confidencelevel)) can be predicted by,

Failure rate = 0.92/(22 × 1000 × 5438)= 7.7 × 10–9(1/h) 8(FIT)

For voltage accelerated tests, under a certain range of conditions (voltage), we can consider thehigher the voltage, the shorter the time to failure. However, precautions must be taken whenapplying excessive voltages because failures, that would not occur under conditions of actual use,are sometimes induced. Additional caution becomes necessary when temperatures are excessivelyhigh.

(3) Failure Rate Prediction Based on Temperature Cycle Tests

Temperature cycle tests use rapidly changing temperature as an acceleration factor. Thealternating high and low temperatures generate stress in semiconductor devices. This stress canactivate failure factors that subsequently induce failures in a shorter time when compared tofailure under “actual use” conditions. In other words, the temperature cycles repeatedly cause heatrelated deformities such as warping in and between the various materials comprising thesemiconductor devices. Consequently physical and mechanical reactions are induced which inturn lead to device failure. Furthermore, by exceeding certain limit failures can rapidly occur.Example, such failures are package cracks, wire breaks, shorts failures.

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Various high and low temperature conditions are prescribed for temperature cycle tests;representative values are

–65C to 150C–55C to 150C–55C to 125C–45C to 125C 0C to 125C

Temperature cycle failure acceleration characteristics are determined by the difference betweenthe high and low temperature, the transition time from high to low and from low to hightemperatures, and the time the specimens are held at high and low temperatures. Stress S isproportional to temperature difference T. Experience shows that the Eyring model, described insection 2, forms between S and temperature cycle count N.

ln N = ln C + (– n) • ln T

where C: Constantn: Temperature Difference Factor

This shows that the full lifetime temperature cycle count N is inversely proportional totemperature difference T raised to the power n, and is expressed as

N = C T –n

The value of n differs with the failure mechanism; if the value n is large, the test conditionacceleration characteristic is large; conversely, if the value n is small, the test conditionacceleration characteristic is small. The value n is indispensable information for the prediction offailure rate from the temperature cycle test results.

The failure rate under conditions of actual use is predicted from the temperature cycle test results(temperature cycle –55C to 150C test) shown in table 5.2, SH7034 Reliability Test Results.

The temperature difference Tb under test conditions is

Tb = 150 – (–55) = 205

The temperature difference Ta under conditions of actual use is determined mainly from thedifference in emission of heat (the degree of thermal radiation) from a device or system when thepower supply is on and off. It is also essential to consider the temperature differences due to airconditioning being on and off in the room where the system is used, or the atmospherictemperature variations when the system is used outside.

Assume

Ta = 40C

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Also, assume

n = 6

Therefore, the acceleration coefficient for test conditions to conditions of actual use can becalculated as

γσ = =

= = 18120 −6

NaNb

40205

C × ∆Ta−n

C × ∆Tb−n =∆Ta−n

∆Tb−n

( )Consequently, the test conditions can shorten the full lifetime cycle count for actual use.

For the SH7034 example, the results are

–55C to 150C

200 cycles 0/45

The temperature cycle count for the actual working environment is

Cycle count = 200 18,120 = 3,624,000

If, in the actual working environment, 10 cycles of thermal stress are applied per day, the failurerate for a 60% confidence level can be predicted by

Failure rate =

= 2.4 × 10−9 (1/h)

= 2.4(FIT)

0.9245 × (3,624,000 / 10) × 24

Therefore, failure rate for the SH7043 can be predicted as approximately 3 FIT.

In temperature cycle accelerated testing, the higher or the lower the temperature within a certainrange, the shorter the number of cycles to failure. When temperatures exceed a certain criticallimit, failures that would not occur in actual operation are sometimes induced (failures due tocompletely different failure mechanisms), therefore precautions must be taken. Generally, thetemperature range between the maximum and minimum of storage Temperature can be applied.

(4) Failure Rate Prediction Based on Moisture Resistance Tests

In moisture resistance accelerated tests, humidity stress is applied as an acceleration factor. Devicefailure factors, such as destructive chemical and physical reactions are induced by humidity stress,

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and failure mode is accelerated by exceeding certain limits. These phenomena can be describedusing the Arrhenius model.

Representative of moisture resistance accelerated tests are high temperature-high humidity biastests and high temperature-high humidity unbiased tests. Typical of conditions for the former arethe 85C-85% RH bias test, and HAST (Highly Accelerated Temperature and Humidity StressTest) where the temperature is 100C or greater and the pressure is 1 atmosphere gauge or greater.Typical of conditions for the later are 65C-95% RH unbiased test. And Pressure cooker test(PCT) also unbiased, where the temperature is 100C or greater and the pressure is 1 atmospheregauge or greater.

Moisture resistance acceleration factors are humidity, temperature, and voltage acceleration.Moisture resistance lifetime is expressed by the Arrhenius model for the temperature factor, incombination with and humidity and voltage factors. This can be expressed by the equation:

L(Tb) = C • eEa/kTb • e/RH

• V–n

where, generally

L(Tb): LifetimeC: ConstantRH: Relative Humidity: Relative Humidity FactorV: Applied Voltagen: Applied Voltage Factor

The Ea, and n are indispensable in the prediction of failure rate under conditions of actual usefrom moisture resistance test results. These values, of course, differ according to the failure mode.Using table 5.2, SH7034 Reliability Test Results as an example, following is an explanation of theprocedure for predicting failure rate under conditions of actual use from results of hightemperature-high humidity bias tests. Assuming conditions of actual uses are

Ta = 30C, VCC = 5.0 V, RH = 85%

The moisture resistance test conditions are

Ta = 85C, VCC = 5.0 V, RH = 85%

The test results are

1000 hours 0/22

Using this method, following is the procedure for predicting the failure rate under conditions ofactual use. Because the test conditions for humidity and externally applied voltage are assumed tobe the same as conditions of actual use, the relative humidity coefficient and voltage coefficientn do not need to be calculated. Consequently, the only temperature acceleration characteristic

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needs to be examined. Because a failure did not occur, the activation energy cannot bedetermined. However, from existing records the activation energy Ea is assumed to be

Ea = 1.0 eV

From the Arrhenius model, L(Ta) and L(Tb) are

L(Ta) = C • eEa/kTa

L(Tb) = C • eEa/kTb

where Ta: Actual use Temperature Conditions (30C)Tb: Accelerated Temperature Conditions (85C)Ea: Activation Energy (1.0 eV)k: Boltzmann Constant (8.6157 10–5 eV/K)C: Constant

Therefore, the test condition acceleration coefficient H is obtained

Failure rate =

= 2.4 × 10−9 (1/h)

= 2.4(FIT)

0.9245 × (3,624,000 / 10) × 24

This means that for temperature accelerated tests compared to conditions of actual use, failureoccurs 359 times faster (time to failure is reduced by a factor of 359). Consequently, the operationtime L(Ta) under conditions of actual uses is equivalent to

L(Ta) = 359 1000 (h) = 359,000 (h)

Therefore, the SH7034 failure rate can be predicted for conditions of actual use as

Failure rate = 0.92 / (22 359,000)= 1.2 10–7(1/h)= 120(FIT)

In moisture resistance accelerated tests, the higher the temperature and relative humidity within acertain range, the shorter the time to failure. However, when temperature and relative humidityexceed a certain limit, failures that would not occur in actual use are sometimes induced (failuresdue to completely different failure mechanisms), therefore precautions must be taken. In tests likethe PCT, where relative humidity is close to 100%, with a temperature of 100C or greater, failuremechanisms sometimes change. For this reason individual failure analysis is essential. Further,the sample calculation shown here are examples of single (isolated) stress conditions, and with

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these calculations very long expectant lifetime values can be obtained. However, under conditionsof actual use, it is necessary that other factors also be considered.

5.3.2 Failure Prediction by Aggregation of Failure Data

By collecting and analyzing failure data from actual application, it is possible to predict the failurerate, assuming failures will occur in the future. However, for many various reasons accuratecollection of data is nearly impossible. Therefore, in this situation one applicable method is theHazard Analysis because when collecting a series of data any kind of hazard should be considered.The following is an example analysis using the Hazard Function.

Example: When using an electronic device, failure resulted from a specific cause. From the datawe obtain the shape parameter (m) and the scale parameter (). The data currentlyobtained is similar to that shown in the table below. However, two of the same devicesare mounted on a PCB and when one device fails, both are removed from the board.

Table 5.3 Data

Time to Failure ( h ) No. of Failures ( ri ) Remarks

3600 0 Total 200 electronic devices

6000 1 2 samples taken




26280 17

We can explain this using Weibull hazard probability paper. For details see section 2.

First, the Weibull probability paper has the following format.

Right Vertical Axis: ln ln 1/[R(t)] = ln ln 1/[1 – F(t)] = m ln t – m ln Top Horizontal Axis: ln (t)Left Vertical Axis: Unreliability Function F(t) on a percentage (%) scaleBottom Horizontal Axis: Time t

Therefore

Vertical Axis: Y = ln ln 1 / [1 – F(t)]

If Gradient: mHorizontal Axis: X = ln (t)Cut-off Intercept: b = –m ln

Then Y = mX + b

Rev. 1.0, 01/02, page 195 of 292

From the Cumulative Hazard Function expressed as H(t) = (t/)m

and taking the logarithm of both sides of the equation produces

ln H(t) = m (ln t – ln )

Next by plotting t and H(t) on the Weibull probability paper which has log-log scales, bothproduce a linear relationship and thereby obtaining m and . From this relationship m and canbe derived easily using spreadsheet software. See section 2 for details of the analysis procedure.Using this procedure we can produce a Cumulative Hazard Table.

Table 5.4 Cumulative Hazard Table

Time to Failure ( h ) X : ln (t )No. of

FailuresHazard Value: ( hi )

Cumulative HazardValue: H(i )

y : ln H(t )

6000 8.7 1 0.005 (1/200) 0.005 –5.298

8640 9.06 2 0.010 (2/198) 0.015 –4.12

13140 9.48 5 0.026 (5/194) 0.041 –3.194

17520 9.77 10 0.054 (10/184) 0.095 –2.354

26280 10.18 17 0.104 (17/164) 0.199 –1.614

Fig. 5.4 shows this Cumulative Hazard Table plotted on a Weibull probability paper. From thisgraph the respective values can be obtained.

y: I

n H

(t)

Cum

ulat

ive

Haz

ard

Val

ue

0

−1

−2

−3

−4

−5

−60 5 10 15

y = 2.4843X − 26.763

Time X: ln (t )

Figure 5.4 Lifetime Distribution from Weibull Cumulative Hazard Paper

Rev. 1.0, 01/02, page 196 of 292

Here from the relationship between the equation y = 2.4843X – 26.763 and ln H(t) = m(ln t – ln )the following values can be determined:

Shape Parameter (m): 2.5Scale Parameter (): 47,700

References

Hiroshi Shiomi: “Introduction to Reliability Engineering,” 3rd Revised Edition, Maruzen

Rev. 1.0, 01/02, page 197 of 292

Section 6 Important Information Regarding Use

The quality and reliability of semiconductor devices is heavily influenced not only by the qualityinherent to the devices themselves, but also by the “use” conditions, environmental conditions andby other so-called conditions where the selected circuits will be utilized by the customer.

This chapter discusses issues which should be given consideration to ensure high reliability in theuse of our semiconductor devices. These include the decisions on parts for use, during systemdesign, during assembly, mounting and other component handling, during storage, or at othertimes, including specific examples.

6.1 Warnings Regarding Device Selection

6.1.1 Maximum Ratings

Maximum ratings for semiconductor devices are defined as values which even momentarily mustnot be exceeded. If a maximum rating is exceeded even for an instant, degradation or failure mayresult. The subsequent lifetime of the device may be greatly shortened. In addition, differences inthe strength of individual products may mean that even though some products may withstand thestress imposed when exceeding a maximum rating, others may abruptly fail.

In designing an electronic circuit with semiconductor devices, devices should be selected, or thecircuit designed, such that maximum ratings specified for devices are not exceeded, even givenfluctuations in external conditions during use.

In addition to DC maximum ratings, devices should be used with voltages, currents, power, andtimes in the safe operating range at all points on the load locus curve. The power supply andground line serve as reference points for the semiconductor device operation. Special care shouldbe exercised to ensure that maximum ratings are not exceeded, including transient states.

Rev. 1.0, 01/02, page 198 of 292

6.1.2 Derating

The quality and reliability of semiconductor devices are greatly influenced by the environment ofuse. That is, products with the same quality may be less reliable in harsh environments, and morereliable when the usage environment is less harsh. Even when used within the maximum ratings. Ifa device is used under extremely stringent conditions equivalent to lifetime tests, wear-out-likefailures may result. Hence the concept of derating is extremely important.

Derating may be approached from two perspectives: derating with respect to design limits, andderating with respect to manufacturing defects.

1. Derating with respect to design limits

When usage conditions become extremely harsh, the wear-out failure range may be enteredduring the time of actual use, and if derating is not employed, it may become necessary toschedule replacement of all devices as part of maintenance after operation for a certain lengthof time in the application.

2. Derating with respect to manufacturing defects

While the wear-out failure range is not entered while in the marketplace, if conditions of useare harsh, the probability of occurrence of defects in the random failure range may no longerbe negligible.

Standard approaches to derating are described in table 6.1. In the “Temperature” row, junction parttemperatures assume intermittent use (for approximately three hours per day) over about 10 years.Conditions for high-reliability applications, shown in parentheses, assume round-the-clockoperation over approx. 10 years.

Rev. 1.0, 01/02, page 199 of 292

Table 6.1 Standard Examples of Derating Design* 1

Derating Element* 2 Diodes Transistors ICs HyICs LDs

Temperature Junctiontemperature*3

110C or lower(Tj = 60C or lower)

— 110C or lower(Tj = 60C orlower)

Deviceambienttemperature*3

Toprmin to Toprmax(Ta = 0 to 45C)

Toprmin toToprmax

Ta = individualspecifications

Other Power consumption, ambient temperature,heat-dissipation conditions Tj = Pd × ja + Ta

— —

Humidity Rel. humidity Relative humidity = 40 to 80%

Other Normally, if there is condensation due to rapid changes intemperature or for other reasons, the printed circuit board iscoated.

Nocondensation

Voltage Withstandvoltage

Maximumrating ×0.8 orless(maximumrating ×0.5 orless)

Maximumrating ×0.8 orless

Conform tocatalogrecommendedconditions

Conform to recommendeddelivery specificationconditions

Overvoltage Take measures to prevent overvoltage application, including electrostaticbreakdown

Current Averagecurrent

Ic × 0.5 or less(Ic × 0.25 orless)

Ic × 0.5 or less Ic × 0.5 or less(especiallypower ICs)


Peak current If (peak) × 0.8or less

Ic (peak) × 0.8or less

Ic (peak) × 0.8or less(especiallypower ICs)


Other — — Take fanout,loadimpedanceintoconsideration

— Take opticaloutput Pomaxintoconsideration

Power Averagepower

Maximumrating × 0.5 orless(especiallyZener diodes)

Maximumrating × 0.5 orless(especiallypowertransistors)

Maximumrating × 0.5or less(especiallypower ICs,high-frequencyICs )

Conform torecommendeddeliveryconditions

Vf × If × Duty

Pulse*4 ASO Should not exceed individual catalog maximum ratings

Surge If (surge) orless

Ic (peak) orless

Ic (peak) orless

Conform to recommendeddelivery conditions

*1 Excludes special usage conditions.

*2 These derating elements should be satisfied simultaneously wherever possible.

*3 For applications requiring particularly high reliability, the values in parentheses ( ) should be used.

*4 Generally where transient states are concerned, peak voltage including surges, current, and junctiontemperature should be below maximum ratings, and derating for reliability should be performed using theabove average values. ASO will differ with the circuit used; please consult with one of our engineers.

Rev. 1.0, 01/02, page 200 of 292

An example of derating for temperature is given in table 6.2. As the temperature rises, chemicalreactions in the materials constituting a semiconductor device are accelerated, and may result in afailure. Generally reliability estimates are performed in terms of whether wear-out failure can beguaranteed not to occur, based on the results of reliability tests and standard usage conditions inthe marketplace. Derating is performed after calculating the acceleration coefficient between thelifetime test data, which has been confirmed by assuming the activation energy for the chemicalreactions for each failure mode, and the actual conditions of use. In general, temperatureacceleration alone does not result in a sufficient acceleration rate, but is ordinarily used togetherwith voltage, humidity, and other acceleration rates. The acceleration limit for temperature mustbe carefully analyzed. This is because a mistake in judgment may be made by other failure modesgoverned by different reactions from that in the normal temperature range, such as the glasstransition temperature of plastic materials.

Table 6.2 Temperature Derating Characteristics (Example)

Example of Derating Application Temperature Derating

Stress factor Junction temperature

Failure judgmentcriteria

Deterioration ofelectrical characteristics

Failure mechanism Deterioration bychemical reactions

10000

1000

100

10

1

0.1100

0.9eV0.7eV0.5eV

0.3eV

0 200Temperature (°C)

Tim

es

Outline

The abscissa shows the reciprocal of absolutetemperature; the ordinate shows the timerequired to reach the prescribed failure rate atthat temperature.

It is believed that defects are caused by chemicalreactions of the material of which the devices aremade. In general, in order for a reaction to takeplace energy has to be supplied from outside.

Chemical reaction theory holds that this energycomes from thermal kinetic energy. Thedistribution of thermal kinetic energy follows theMaxwell-Boltzmann law:

Lifetime = constant exp (Ea/kT)

where Ea = activation energy (eV)T: absolute temperature (degrees K)k: Boltzmann constant (8.617 10–5eV/k)

The acceleration constant can be easilycalculated from this formula.

How to calculate derating

Let us find the acceleration coefficients in lifetime testswith Tj values of 150°C and 65°C. For the activation energy,the general value of 0.5 eV for dielectric breakdown of theoxidation film is used.

= exp [0.5/8.617 10–5 / (273 + 65)]exp [0.5/8.617 10–5 / (273 + 150)]

Rev. 1.0, 01/02, page 201 of 292

An example of derating for humidity is shown in table 6.3. This derating is performed primarilyfor corrosive breaking of Al wire and changes in solderability accompanying storage of packageleads. Due to advances in plastic materials, corrosion and breakage of Al wiring has improvedtremendously, and this failure mode hardly ever occurs any more in the marketplace; but eventoday, use under extremely harsh conditions may still result in wear-out failure in a finite amountof time.

Table 6.3 Humidity Derating Characteristics (Example)

Example of Derating Application Humidity Derating

Stress factor Temperature, relativehumidity

Failure judgmentcriterion

Deterioration ofelectrical characteristics

Failure mechanism Metallization corrosion

Absolute humidity (mm Hg) (Source: Rikanenpyo)

Temperature/K270280290300310320330340350360

00.4850.9921.1923.5350.4850.4850.4850.4850.4850.485

20.5621.1362.1773.9730.5620.5620.5620.5620.5620.562

40.6501.3002.4644.4570.6500.6500.6500.6500.6500.650

60.7501.4832.7844.9910.7500.7500.7500.7500.7500.750

80.8631.6893.1405.5800.8630.8630.8630.8630.8630.863

Outline

Since absolute humidity is proportional to thenumber of water molecules contained in a unitvolume, in this example we approximate thelifetime by the nth power of the stress thatgoverns the failure rate.

Lifetime = constant (absolute humidity) n

Taking the logarithms of both sides of thisequation, we obtain

log (lifetime) = n log (absolute humidity) +log (constant)

Taking the logarithm of absolute humidity as theabscissa and the logarithm of the time requiredto reach the prescribed failure rate at thatabsolute humidity as the ordinate, the resultinggraph is approximately a straight line.

Absolute humidity is a function of temperatureand relative humidity.

We assume that the following relation holds

Absolute humidity = saturation absolutehumidity relative humidity

How to calculate derating

We calculate the acceleration under typical conditions usedin tests of ability to withstand humidity (65°C/95% RH) andtypical conditions in the marketplace (Ta = 25°C/65% RH).

From the table, the saturation vapor pressure at 65°C iscalculated by the interpolation method to be 22.9 mmHgand the saturation vapor pressure at 25°C is calculated tobe 2.8 mmHg.

The absolute humidity for value for each case is calculatedby multiplying by 0.95 and 0.65, respectively.

Taking the ratio and using the typical acceleration constantn = 2 gives = (21.7/1.8)2 = 145 times.

An example of derating for temperature differences appears in table 6.4. The failure mechanismassumes thermal fatigue and failure of structural materials. This mode generally leads to wear-outfailure modes, and so adequate derating calculations are important for power devices and othercomponents. When designing thermal dissipation, the number of times heat stress is applied andthe temperature difference of the heat stress must be taken into consideration.

Voltage, current, and power derating is especially effective in preventing failure phenomena. Inparticular, these failure phenomena are closely related to temperature-difference derating, and are

Rev. 1.0, 01/02, page 202 of 292

subjects for stress-strength models in which a structural defect grows to cause weakening of thefailure strength, resulting in failure at stresses which did not initially cause failure.

In the actual marketplace, conditions of actual use are not so simple that they can be described bysingle conditions, and conditions change continuously with time. Normally worst-case conditionsare assumed when performing the derating to determine whether or not it can be used; but whenconditions cannot be combined into a single condition, conditions are converted into the followingstandard conditions (compound stress temperature-difference acceleration, cf. table 6.5; compoundstress temperature acceleration, cf. table 6.6) and derating is performed.

Table 6.4 Power Transistor Power Cycle Derating Characteristics (Example)

Example of Application of Derating Power Transistor Temperature Difference Derating

Stress factor Junction temperaturedifference


Deterioration of ch - c

Failure mechanism Solder fatigue

Example of a product havingthe ability of 10,000 cycles at ∆Tch = 90°C

Junction temperature difference (∆Tch)

No.

of a

vaila

ble

cycl

es

105

104

103

10210010 1000

n=2n=3n=4n=5

n=6

Outline

It is believed that the nth power of thetemperature difference is proportional to thepower cycle limit.

Number of cycle lifetimes = constant (temperature difference) n

Taking logarithms of both sides of this equationgives

log (number of cycle lifetimes) =n log (temperature difference) +log (constant)

Taking the logarithm of the junction temperaturedifference (Tch) at the time of power cycle ONor OFF as the abscissa and the logarithm of thelimiting number of power cycles at that time asthe ordinate, the resulting graph is approximatelya straight line.

This line of reasoning permits us to estimate thenumber of years a device will last from theconditions under which the power transistor isused.

Conversely, we can determine the powertransistor heat radiation conditions from thenumber of years the device is required to last.

How derating data are used

If we take Tc to have an actual measured value of 85°C, Pcto be 20 W and ch – c to be 1.0°C/W, Tjmax becomes 85 +20 1.0 = 105°C; the difference from Ta = 25°C is Tj =80°C.

The cycle lifetime at this time can be read from the graphand the number of cycles for which the component can beused obtained. In the case of a TO3PFM, this becomesabout 5, so the acceleration rate between the conditions forreliability test datum = 85 and the conditions of actual usecan be easily calculated.

Rev. 1.0, 01/02, page 203 of 292

Table 6.5 Compound stress Temperature-Difference Derating Characteristics (Example)

Example of Application of DeratingPower Transistor Temperature Difference Derating

(Example)





Temperature difference derating under multiple conditions

First, we find the acceleration coefficient between the marketconditions and lifetime test conditions.

1 = [(175 – 25)/90]5 = 21.4 times2 = [(125 – 25)/90]5 = 1.88 times

Letting m be the necessary number of cycles at T = 90°C,m = 50 times/year 10 years 21.4 + 365 days 10 years 5 times/day 1.88.

In a lifetime test at T = 90°C, this becomes about 45,000cycles.

Outline

Environmental variations under actual useconditions cannot necessarily be described interms of constant conditions.

For example, in the case of the temperaturedifference in an automobile engine compartment,the worst case would be immediately after theengine has been turned off in a service area afterthe car was operated at high speed on anexpressway in summer.

Let us assume that, for example, Tch in this caseis 175°C, and that on average this situationoccurs 50 times in a year.

Let us assume further that in normal use Tch is125°C, and that the engine is turned ON andOFF 5 times per day on average.

When the reliability test condition is T= 90°C,we calculate how many cycles these correspondto the reliability test condition.

Assuming that (lifetime) = (constant) (temperature difference) n, we solve for the casen = 5.

When the component is used under severe environmentalconditions, the acceleration limit becomes a problem. Insuch a case, please consult with our company’s StrategicMarketing Dept.

Rev. 1.0, 01/02, page 204 of 292

Table 6.6 Compound Stress Temperature Derating Characteristics (Example)

Example of Derating Application Compound Stress Temperature Derating (Example)





Temperature difference derating under multiple conditions

1 = exp [0.6/8.517e–5/(273 + 165)]exp [0.6/8.517e–5/(273 + 175)]

= 0.71 times

2 = exp [0.6/8.517e–5/(273 + 125)]exp [0.6/8.517e–5/(273 + 175)]

= 0.14 times

The market condition t that correspond to reliability testtimes at 175°C:

t = 0.71 10 hours/year 10 years + 0.14 365 days/year 10 years 5 hours/day

= 2620 hours

In lifetime testing it is extremely important to limit the time fortesting up to 1,000 hours to guarantee the quality.

Outline

Environmental variations under actual useconditions cannot necessarily be described interms of constant conditions.

For example, in the case of the temperaturedifference in an automobile engine compartment,the worst case would be immediately after theengine has been turned off in a service area afterthe car was operated at high speed on anexpressway in summer.

Let us assume that, for example, Tj in this caseis 165°C, and that on average this situation takes10 hours in a year. Let us assume further that innormal use Tj is 125°C, and 5 hours’ driving perday on average.

If the reliability test condition is T = 175°C, wecalculate how many hours these correspond tothe reliability test condition.

Assuming that (lifetime) = (constant) exp(Ea/kT), we solve for the case Ea = 0.6.

When the component is used under severe environmentalconditions, the acceleration limit becomes a problem. Insuch a case, please consult with our company’s StrategicMarketing Dept.

Assuming that the number of conditions that apply to practical use has been reduced to n,

ti = within the lifetime of a component, the cumulative time that the component has been used inthe market under the i th condition, and let

i = the acceleration coefficient for the standard conditions and the i th condition,

then t = ti • i

The lifetime under actual use conditions can be replaced with the test time in the acceleratedlifetime test by substituting the reliability test conditions for the standard conditions in thisformula.

Rev. 1.0, 01/02, page 205 of 292

6.1.3 Using a Device with Equivalent Function

Among semiconductor device characteristics, there are some that are listed in the catalogue andofficially guaranteed, and others that, while not listed in the catalogue, are de facto conditionsunder which the device can be used. Before taking advantage of characteristics that are not listedin the catalogue, it is recommended that you thoroughly investigate those characteristics, includingvariation among individual devices.

Examples of this kind of situation would be using a standard digital circuit as an operationalamplifier in an oscillator circuit, and using an output signal at a voltage at which operation is notguaranteed in a transient state when power is turned ON.

Example 1 Malfunction when a MOS IC is Used in an Analog Circuit

No. 1 Example Malfunction when a MOS IC is used in an analog circuit

Type of device MOS IC

Note Caution is required as to the amount of margin in a circuit when the inputleakage current fluctuates.

Outline of example/phenomenon/cause

When a MOS IC was used as an oscillator circuit or analog switch, theallowable leakage current was less than that for a digital circuit; a leakagecurrent that is too large can cause a malfunction.

Not only leakage current in the device itself, but also between terminals ofthe printed circuit board (due to adhering dust) is a problem.

A BA B

Countermeasures/checking methods

(a) Coat the printed circuit board so that dust will not adhere to it.(b) Improve the environment under which the device is used (reduce the

humidity).(c) Design the printed circuit board so that the resistance between A and

B will be 109 or more.

Reference item

Rev. 1.0, 01/02, page 206 of 292

Example 2 Erroneous Output from a Schmitt Trigger IC when Power is Turned ON

No. 2 Example Erroneous output from a Schmitt trigger IC when power is turned ON

Type of device TTL IC

Note Exercise caution with regard to transitional phenomena when power isturned ON.


If the power to a circuit using a Schmitt trigger IC is turned ON while theinput is at L level (0.8 V), even though the IC is an inverter the outputbecame L.

This phenomenon occurred because of the IC s hysteresischaracteristics; if power is turned ON while the input is within thehysteresis range (about 0.7 V to 1.6 V) the output becomes unstable andthe circuit does not operate normally.

Out

put v

olta

te

5 V

5 V0 V

VCC

0.5 V input (outside hysteresis)

0.8 V input (within hysteresis)


(a) Keep the input outside of the hysteresis range until Vcc has reached asteady state.

(b) Use a type of device that does not have hysteresis characteristics.

Reference item

This applies also to recent microcomputer devices which include mask versions, PROM versions,ZTAT and F-ZTAT versions, which have exactly the same functions but differ in the way ofprogramming. Of course there are differences in the center values and dispersions ofcharacteristics which are guaranteed on the labels, but there are differences in characteristics thatare not stated explicitly in the standards such as noise margin to prevent malfunction, noisegeneration and stability of the oscillator circuit.

Rev. 1.0, 01/02, page 207 of 292

Example 3 Difference between ZTAT Version and MASK Version in Ability to WithstandNoise

No. 3 Example Deterioration when subjected to noise, caused by changing the mask

Type of device Microprocessor

Note It is necessary to ask, is there a problem with performance characteristicswhich are not specified in the standards when a mask is changed?


In a ZTAT microcomputer, prototyping and initial mass production werecompleted and then there was a switchover to a MASK version with thesame pin layout in order to proceed to full-scale mass production.

When that was done, the level of noise generation increased, causingmalfunction of the scanning station selection function of an adjacent FMradio (noise caused the radio to judge that there was a station at afrequency at which there was not).

Adjustments were made in the printed circuit board ground wiring patternlayout and in the location of the bypass capacitor, tentatively solving theproblem, but this caused delay in the timing of mass production, and inthe meantime it was necessary to continue using the costly ZTATmicrocomputer.

Countermeasure/checking method

The MASK version functional specifications have been adjusted to thoseof the ZTAT microcomputer as much as possible, but depending on thesystem used there will be some products that differ somewhat in theirfunctions.

For example, even if the functions themselves are exactly the same, theproducts can differ in some characteristics that do not show up in officialspecifications (for example ability to withstand noise, latch-up,vulnerability to electrostatic breakdown, etc.), and these things must bechecked out in advance using the actual device.

If there are characteristics that make the device difficult to use or ifimprovements are necessary, please contact our company’s StrategicMarketing Dept.

Reference item

Rev. 1.0, 01/02, page 208 of 292

6.1.4 When a Device is Used in a Severe Environment

In particular, it is necessary to thoroughly consider the possibility that a failure may be caused bywear out. Unless derating is done correctly in the wear out region, the failure rate will increaserapidly with time when the device is actually used, causing serious trouble. This is very important.Before using a device, make certain that the test time is longer than the time in the reliability testcondition, which is calculated from the time in practical use by considering the accelerationcoefficient.

In wear failure mode, once defects start to occur the defect rate increases rapidly with time.Conversely, it is possible to keep the defect rate in the practical use very low even from a smallnumber of samples, by using the data over a much longer time (for example double the time) thanthe time that the device will be used in practice.

6.1.5 When Using a Device in an Application that Requires High Reliability

In applications that require high reliability, such as in case that whenever a singles failure occurs itis necessary to track down the cause and take the necessary steps to improve quality. It isnecessary to estimate not only the rate of defects caused by wear out also the defect rate in theregion of randomly occurring failures. When failures occur randomly, it can be expected that if theconditions of use become more severe by a factor of 2 then the failure rate will double. Forexample, even in the case of a product that has satisfied the quality requirement in the past, it ispossible that if the conditions of use become more severe it will no longer satisfy the qualityrequirement.

In many cases, the random failure region appears as a result of screening the initial failure modecaused by manufacturing defects. Effective means of decreasing this failure rate includedecreasing the density of defects in the manufacturing step, and optimizing of the screeningmethod.

Of course the ultimate quality target is zero defects, but unfortunately this has not yet beenachieved. When using a product in which the effect of a failure occurring in a component wouldbe serious, protective measures should be taken in the system.

Rev. 1.0, 01/02, page 209 of 292

Example 4 Quality Grade Selection

No. 4 Example Quality grade selection

Type of device All semiconductor devices

Note It is necessary to ask whether the semiconductor device being used issuitable for the application.


In an application in which zero defect quality is required, a semiconductordevice intended for use in ordinary household appliances was used, andconsiderable trouble was caused by the chronic occurrence of defectswhose probabilities are small.

When a complaint that the defect rate was high was lodged, it wasrecommended that the user switch to a device intended for high reliabilityapplications.

Supplementary explanation: There are two types of differences in thequality of a LSI intended for high reliability applications and an LSIintended for ordinary applications. One is a case in which the design addssome additional margin to the limiting value itself to meet therequirements of the severe environmental conditions (temperature orenvironmental stress). The other is better selection when a high failurerate results from manufacturing fluctuations, using technology such asscreening.

As we stated above the ultimate goal for devices to be used inapplications that require high reliability is zero defects, but at present thishas not been reached. We would like to have feedback from ourcustomers whenever a problem occurs so that we can work to improvequality.


(a) When there is a strong tradeoff between cost and quality, pleaseconsult in advance with our company’s Strategic Marketing Dept. sothat we can help you select the product that is best suited for yourapplication.

(b) Please take the necessary precautions in your system for fail-safeoperation in case a failure occurs in a semiconductor product.

Reference item

Rev. 1.0, 01/02, page 210 of 292

6.2 Protection of Devices from Electrostatic Discharge (ESD) Damage

Destructive defects are the most frequently occurring type of semiconductor device failure and itis very difficult to trace the cause of destruction from its aftermath. When the incidence ofdestruction is high, additional testing is conducted and specific measures are taken in an attempt tofind the conditions that reproduce the same form of destruction, but in reality, it is extremelydifficult to reproduce the forms of destruction that are exactly the same as those in the field.

This section, focusing on destruction mechanisms, summarizes the characteristics of destruction,and the approach to prevention and countermeasures. Correct, careful handling of sensitivesemiconductor devices during production processes can be expected to have a large effect on thereduction of defects during both the clients’ production processes and the period of initial failuresin the field.

6.2.1 ESD Damage

Damage due to electrostatic discharge is the most frequently occurring mode of destructivedefects. Following, we summarize the mechanisms that charge devices, the mechanism of damageand general precautions.

Damage of devices by electrostatic discharge is caused by sudden discharges resulting fromexcessive electrical voltages and excessive currents. Except for devices with extremely highfrequencies, most devices have internal protective elements against static electricity. Damage ofdevices due to electrostatic discharge will still, however, occur when static electricity exceeds thelevel of protection provided by the protective elements is applied to the device, or when a high-frequency surge exceeds the speed of the protective elements.

After installation on to a circuit board or apparatus, from the concept of distributed-constantcircuits, applied static electricity, concentrates at the point of lowest impedance to become a straycurrent, and then causing destruction at the weakest point.

The semiconductor device itself is processed and manufactured at extremely high temperatures, sodestruction will not result if the temperature rises for a short time. When, however, energyconsumed is intensely concentrated, the temperature rises locally and destruction occurs instantly.When the static electricity itself causes the destruction, the voltage is high and the amount ofenergy is comparatively low, so there is little sign of damage and, in many cases, it cannot beobserved. If static electricity is applied when the electric power is on, the resulting electrostaticdestruction will in some cases induce secondary thermal runaway and Area of Safe Operation(ASO) destruction.

Rev. 1.0, 01/02, page 211 of 292

(1) Mechanisms for the Generation of Static Electricity

Static electricity is the charging of a material by either an excess or a shortage of electrons. Whena material has an excess of electrons it is negatively charged, and when it has a shortage ofelectrons it is positively charged.

Materials generally have an electrical quality of either acquiring electrons or of giving them up(the series of frictional electrification). For this reason, when two materials rub, make contact orseparate, creating friction, one material acquires electrons while the other gives them up (fig. 6.1).When a conductive material comes into proximity with a charged material, local charging willoccur because of electrostatic induction (fig. 6.2). The size of charge in materials depends on thematerial properties, the surrounding conditions (temperature and humidity), and the conditions interms of friction. However, large charges are generally generated in chemical fibers and plastics(these materials are easily charged). Since static electricity charges the surface of a material, thematerial’s surface conductivity will also have a strong effect on charge transfer. When the surfaceconductivity is high, the charge will diffuse quickly. Table 6.7 shows examples ofelectrostatically generated voltages. Since surface conductivity increases with humidity, thehigher the relative humidity the lower the electrostatic voltage.

Insulator Insulator

Figure 6.1 Frictional Electricity

ConductingBody

(Electrically)Charged Body

Figure 6.2 Electrostatic Induction

Rev. 1.0, 01/02, page 212 of 292

Table 6.7 Examples of Typical Electrostatic Voltages

Electrostatic Voltage PotentialSource

10 to 20%RH 65 to 90%RH

A person walking on a carpet 35000 V 1500 V

A person walking on a vinyl floor 12000 V 250 V

A person working at a bench 6000 V 100 V

Vinyl covering 7000 V 600 V

Lifting a polythene bag from a bench 20000 V 1200 V

Polyurathane packed chair 18000 V 1500 V

(From DOD-HDBK-263)

(2) Charged-Device Model Mechanism

Recently the incidence of the ESD damage due to the charged-device model is increasing. Thismode of destruction occurs when a charged device model discharges to a conductor. The device-charging mechanisms that induce such discharges are described below.

(a) Frictional charging of package surfaces

Friction is often applied to a device in the manufacturing process or during assembly ofdevices into electronic instruments. Examples are friction with the rubber roller of the devicesealing machine, within the IC magazines, and device handling instruments. When friction isapplied to plastic packages, the surface of the package becomes charged. When the package ischarged, electric charge is electrostatically induced in the chip and its leads by electric fieldswithin the package, and the leads discharge when they make contact with a conductor(fig. 6.3).

(b) Device charging by electrostatic induction

In addition to the above, fig. 6.4 gives examples of charging that occurs even in the absence offriction. When a device is placed on a charged plastic board, electrostatic induction takesplace in the chip and leads fig. 6.4 (i). Then discharge occurs when tools or human bodiesmake contact with the leads fig. 6.4 (ii). If the device is charged, there is a further danger ofdischarge after it has been picked up from a board fig. 6.4 (iii).

This shows that there is a danger of device discharge when charged materials are simply broughtinto proximity with each other. The containers into which devices on completed boards areplaced, conveyor belts, and non-conductive finger cots can all cause device discharge.

Rev. 1.0, 01/02, page 213 of 292

DischargeConductor

Package Charged Surface

Figure 6.3 Internal Electrostatic Induction and Discharge when the Package Surface isCharged

Charged Plastic Board

After Removal from the Plastic Board

Conductor (e.g. pliers)

Discharge

( i ) ( i i )

( i i i )

Figure 6.4 Process of Device Charging by Electrostatic Induction

Rev. 1.0, 01/02, page 214 of 292

(3) General Precautions against ESD Damage

Caution is necessary in handling devices since they are generally susceptible to destruction due toelectrostatic discharge. The possibility of electrostatic destruction is especially high in the caseslisted below. Countermeasures, and confirmation of the conditions, are thus necessary to preventdestruction.

(a) Contact between devices and conductors

When conductors or devices are charged, discharge will occur between them. For the sake ofprotection, human bodies must be grounded through a high resistance, of 1 M or greater. Formetals, the danger of destruction is greater because of the sharp discharges. Bringing devicesinto contact with metals must be avoided as much as possible, but, when this is unavoidable,the metal must be grounded and the charge must be removed from the devices.

(b) Device subjected to friction

Packages become charged when they are subjected to friction, and when the lead pins arerubbed, the chips and lead pins also become charged. It is necessary to reduce the size ofcharge by preventing friction or changing the material that may be subjected to friction.

(c) When charged tools are brought into proximity with devices, the devices are charged byelectrostatic induction. The material of tools must therefore be exchanged for anti-staticmaterial.

(d) Drops in the humidity of surroundings

When handling devices, if the humidity in the vicinity falls, devices or tools, once charged, donot easily return to their original condition. Since static electricity is invisible, it is not easy toinstitute perfect countermeasures to the above mentioned factors (a)–(c). When executingthese countermeasures, greater effectiveness can be expected if the humidity is also controlled.

Rev. 1.0, 01/02, page 215 of 292

(4) Caution in Handling Devices

The most effective method of preventing sharp discharge of semiconductor elements is to use anti-static mats. First of all, devices will not become charged, but, if they become charged then, theywill not discharge sharply.

(a) The working environment

The occurrence of static electricity is closely related to humidity, and static electricity occursmore readily when the relative humidity drops. When there is a high-temperature area (in partof the working environment), the local level of humidity in that area will be low, and this leadsto the possibility of large amounts of static electricity. Therefore, from the aspect of chargeprevention, during handling and the mounting process when the possibility of charge is high, itis important to maintain a relative humidity of 45 to 55% by using humidifiers. When controlof humidity is difficult, an air-ionizing blower (called an ionizer) is also effective. However,over dependence on the air-ionizing blower may lead to unexpectedly high rates of defectswhen failures do occur. It is more important to take other measures to prevent charging and atthe same time continuously confirm the operation of the air-ionizing blower.

(b) Work

In the work place, easily charged insulators (especially chemical fiber and plastic products)must be avoided as much as possible, and conductive material should be used. For example,anti-static materials such as anti-static work gowns and the use of air-ionizing blowers arerecommended. Also when handling semiconductor devices, it is necessary to use materialsthat prevent static electricity or provide anti-static containers (for example, electrostatic-shielded bags, anti-static mats, etc.) during storage or transportation.

(i) Equipment and facilities

Measuring and test equipment, conveyors, work platforms, floor mats, tools and solderbaths and irons should all be thoroughly grounded to prevent electrostatic accumulation.Cover work benches and floors with earthed anti- static matting (105/ – 109/ ).

(ii) Human bodies

Ground human bodies during work. However, to prevent electric shock, always include a1 M resistor or higher connected in series, and be sure not to touch high voltage parts.Always wear gloves and do not touch devices with bare hands. Gloves and work gownsmust not be made of such easily charged materials as nylon. Shoes or sandals with aresistance of 1 M to 100 M are regarded as adequate, but such values may vary due todirt, wear, and humidity.

(iii) Work methods

Use a soldering iron for semiconductors (12 to 24 V, i.e., low-voltage type), and groundthe tip of the iron. In handling devices it is desirable to keep the frequency of handlingand the time of handling a given device to a bare minimum, as working quickly can helpto prevent destruction.

Rev. 1.0, 01/02, page 216 of 292

Example 5 ESD Damage during Measurement

No. 5 Example ESD Damage during measurement

Type of device MOS IC (plastic encapsulation)

Note Measure the size of charge after exposure to friction and takecountermeasures


Because a plastic guide rail was used to feed the IC to an automaticmeasuring device, the IC’s plastic materials became charged with staticelectricity as the IC slid along the guide rail. This charge was dischargedat the measuring head (metal), and caused destruction of the IC’s inputcircuit. This occurred at low levels of humidity, but not at high levels.


(1) Exchange the plastic guide rail for a metal one, to avoid thegeneration of electrostatic charge.

(2) GND the guide rail.(3) If these measures do not sufficiently reduce the size of the charge,

use an ionizing blower as well.

Reference item

Example 6 ESD Damage during Storage and Transportation

No. 6 Example ESD Damage during storage and transportation

Type of device MOS IC (Plastic encapsulation)

Note Substances adjacent to the device must not be allowed to charge to highvoltage.


During the device production process the IC which was perfect aftermounting onto the PCB and before integration, becomes defective.Because the PCBs were stacked during transportation or storage, acapacitor discharges the applying voltage and causes destruction of theIC.


(1) Place insulators between the PCBs during transport.(2) Discharge the condenser.(3) Separate the PCBs keeping some distance between them.

Reference item

Rev. 1.0, 01/02, page 217 of 292

6.2.2 Excess Voltage Destruction

Other than static electricity another cause of destruction is the application of excess voltage,commonly called excess voltage destruction. There are various causes and features of excessvoltage generation, but generally the form of destruction is determined by the amount ofdischarged energy and the size of the energy consuming area. When the temperature of local areasof silicon (Si) exceed 200°C the leakage current is extremely high and permanent destructionresults with a further increase in temperature. Physically it is necessary for the temperature to riseabove 500°C before fusion of the Al metallization or deformation of the Si substrate occurs. Thesize of destruction or deformed area is obviously related to the size of the surge energy involved inthe destruction.

Excess voltage surge includes extraneous surges induced by the activity and the switching on/offof other devices, unexpected lightening, and circuit-induced surges due to the activity of thedevice itself. Surges also arise during measurement and testing, procedures which are unrelated tothe normal activity of devices.

Rev. 1.0, 01/02, page 218 of 292

(1) Destruction due to External Surges

External surges are the most troublesome. Because incidence is generally extremely low, andinvestigating their causes or conducting simulation tests are difficult, to prevent the problem, it isnecessary to record in detail the conditions of operation and the surroundings at the time troubleoccurs.

Example 7 Destruction due to Voltage Surge

No. 7 Example Destruction due to voltage surge

Type of device CMOS analogue switch IC

Note Confirm the IC tolerance to input surge.


In a system collecting data as an analogue signal, as the source ofanalogue signal is far away from the analogue/digital converter, anexternal surge was induced on the connecting line. A CMOS analogueswitch with an excess voltage protection circuit was used on the analogueinput, but the surge exceeded the voltage causing destruction.

Several hundred metersCMOS Analogue Switch IC


(1) Isolation amplifier added to the input circuit.

+

−

(2) Zener diode is added to the input circuit to absorb the surge.

Reference item

Rev. 1.0, 01/02, page 219 of 292

(2) Precautions against Destruction by Self-generated Excess Voltage

Surges are sometimes self-generated within circuits. This is the case when inductive load circuitsare driven, such an applied surge is absorbed by the avalanche break down of transistors. In sucha case, reliability is maintained through absorption of energy by installing protective elements.Also by adding protective elements to the circuit derating characteristics are checked.

Example 8 A Driven Inductance Load

No. 8 Example A driven inductance load


Note Confirm the voltage and current waveform when the load circuit L isswitched on and off.


When an inductive load such as a relay is driven through a logical circuit,and when the current flowing into the coil in a relay is reversed theresulting reverse voltage is not absorbed and the device will sufferelectrical destruction. The situation is the same when transistors areused.


(1) Introduce a clamping diode.(2) Introduce a dumping circuit.

Reference item

When a condenser with a large value capacitance as the load is driven, excess voltage sometimesarise because of the inductive element of the load circuit.

Rev. 1.0, 01/02, page 220 of 292

Example 9 Reactance Driven

No. 9 Example Reactance driven

Type of device TTL, CMOSIC

Note Precautions against charging/discharging currents of capacitors


If a capacitor is connected to an IC output, a charging current flows as itslevel changes from low to high, and a discharging current flows as itslevel changes from high to low. In the former case, a currentcorresponding to IOS flows, and a voltage corresponding VOH is applied tothe VOL level output current destruction in the output transistor.

Charge

DischargeC


(1) Use a capacitor with a capacitance that is lower than the value.(2) Insert a resistor in series with the capacitor.(3) Design systems that do not use capacitive load.

Reference item

Rev. 1.0, 01/02, page 221 of 292

Example 10 Destructive Defects due to Noise from the Power Supply to the LCD Driver

No. 10 Example Destructive defects due to noise from the power supply to the LCD driver

Type of device LCD-driver microcomputer

Notes (1) Never reverse the voltage of the power supply to the LCD driver.(2) The voltage applied to the CMOS input must be between the value of

the power supply and GND.


An LCD driver which was used trouble-free at company A repeatedlyfailed, for unknown reasons, in product tests at company B. There was abig discrepancy between the defect rates of device types even of thesame lot. The defect rates also varied with the test pattern.

Defect analysis confirmed that cause of destruction was a build-up ofspiking noise in the power supply to the liquid crystal display due to acapacitor load, and the reversal of the potential difference across thepower supply. A bypass capacitor was placed across the power-supplyconnection providing a reversed-voltage to synchronize with the noise.The destruction no longer recurred.


(1) In order to avoid, for even a moment, the reversal of the voltageapplied to the power supply of a liquid-crystal display driver, use acondenser with the same phase to eliminate the noise as describedabove.

(2) Widen and shorten the patterns between power supplies, and with themost severe timing to the changes in the column signal, use a probewith a high speed of operation to confirm the waveform for existenceof reversed voltage between power supplies.

Reference item

Rev. 1.0, 01/02, page 222 of 292

(3) Precautions against Excess Voltage Destruction during Measurement

When measuring semiconductor devices, it is necessary to apply the same considerations asapplied to static electricity. In addition, particular care should also be taken with regard to thepoints listed below.

(a) Preventing destruction due to the power input sequence

If the power input sequence of semiconductor devices is faulty device destruction may arisedue to such phenomena as latchup. A power supply which has the negative features of theelectric current limitations combine with the device current to cause the voltage to drop, and asa result the device may malfunction. Refer to individual data books for details.

Even if the power input sequence for the test program is correct, the power input sequence maynot proceed correctly due to a faulty connection between the device and the socket of themeasuring instrument. The actual power input sequence may also be reversed due to acombination of the startup speeds of the power voltage and those of the input/output signal.Caution is needed.

Example 11 Destruction due to Mistiming of Power Input

No. 11 Example Destruction due to mistiming of power input

Type of device Linear IC

Note Confirm whether the power input sequence is the same as thespecifications.


When switching the mode, a malfunction of unknown cause occurred.The IC that malfunctioned operated off two power supplies. Only powersupply 1 is used in normal operation, while power supply 2 is designed toturn on and function when switching the mode.

The relevant IC is designed in such a way that unless the output signal ismuted (Mute) until power supply 2 rises to the high level (5V), pulse noiseoccurs and excessive current flows. It was confirmed that theseprecautions for use had not been followed, and as a consequence thenoise surrounding the power supplies caused the device to malfunction.


Confirm and follow the precautions for use given in the catalogue orspecifications provided with the delivery documents. In the case thatmultiple power supplies are used, be especially sure to control the timingof each on/off event.

Reference item

Rev. 1.0, 01/02, page 223 of 292

(b) Protection against voltage and current surges

Take care to ensure that surging voltages are not applied, especially from testers duringmeasurement, or use such countermeasures as adding clamping circuitry to the tester, or ensurethat abnormal voltages are not applied due to faulty connections during active currentmeasurement of the power supply.

Example 12 Destruction during Measurement

No. 12 Example Destruction during measurement


Note Beware of voltage surges when power is applied.

Outline of example/phenomena/cause

(1) When measuring the bus-driver output voltage VOL, destructionoccurred because the sink current IOL (100–300 mA) was keptconstant.

(2) When measuring the break down voltage tolerance (for an IC of 70Vor greater) with a current of 1mA, the same destruction defects (as in(1) above) occurred.

(3) When measuring the break down voltage tolerance (as in (2)), noisesuperimposed on the constant current source, entered the negativerange and caused destruction.


(1) Use methods that apply voltages rather than currents.(2) Apply voltages, within the break down voltage limit and measure the

current.(3) When a method that includes the application of a current must be

used, it is effective to check the contacts as indicated in the previoussequence.

Reference item

When capacitors, installed to prevent noise on input/output terminals, are connected carelessly,there is a chance that semiconductors will suffer electrical destruction because of peak currentsthat result from charging and discharging of the capacitor. For example, during intermediateinspections using board testers or in-circuit testers if the capacitor remains charged when the nextboard is tested destruction of semiconductor devices may result. In cases where the capacitors ona board remain charged after a test, there is also a possibility of discharge later in the storage case,so all capacitors in the tester and on the board must be completely discharged. In the samemanner, when a bypass capacitor with a large capacitance is inserted on the tester power supply,care must be taken to ensure that an unnecessary charge does not remain after the power supply isdisconnected.

Rev. 1.0, 01/02, page 224 of 292

(c) Precautions against noise and oscillation

Normally, even in circuits that operate correctly, the load capacitance increases when devicesare connected to oscilloscope probes or instruments for measurement. Noise or oscillation aregenerated and circuits malfunction, leading to the destruction of semiconductors. Therefore,caution is necessary.

(d) Prevention of conflict between semiconductor outputs and tester drivers

When measuring common I/O terminals, care is required so that the output of thesemiconductor and tester do not conflict.

(e) Precautions against leakage from electrical equipment

Adequate control of electrical equipment is required so that leakage does not occur from ACpower supplies to terminals of curve tracers, oscilloscopes, pulse generators, or stabilized DCpower supply.

(f) General precautions

When measuring, avoid the misconnection of terminals, reverse insertion, and shortingbetween terminals. When checking board (substrate) operations, check that there are no solderbridges or foreign matter bridges before switching the power on.

Example 13 Destruction during Measurement

No. 13 Example Destruction during measurement

Type of device Small Surface Mount IC

Note Beware of contact defects when taking measurements


When the semiconductor device to be measured was inserted into thetester socket at an angle, a spike surge occurred due to contact defectsbetween the pins of the device and the tester socket, resulting indestruction of the IC.


Place the contact check for the very beginning of the testing program.When contact defects are detected, the inspection should bediscontinued. In the case of reverse insertion, the inspection should alsobe halted.

Reference item

Rev. 1.0, 01/02, page 225 of 292

Example 14 Destruction due to Faulty Connections

No. 14 Example Destruction due to faulty connections


Note Ensure correct connection and clarify emergency measures against faultyconnections.


When installing a set, the GND line was open and the VCC connected, anIC failed due to a connection between its output terminals and GND. Themoment the output terminals made contact with GND, large currents weredrawn from SUB through an electrolytic capacitor between VCC and GND,causing destruction.


Place a clamping diode between the output terminals and GND.

Reference item

Example 15 Destruction Defects due to the Removal and Replacement of a Connector

No. 15 Example Destruction defects due to the removal and replacement of a connector

Type of device IC, LSI

Note The removal and replacement of live connectors is strictly prohibited. Ifthis cannot be avoided, the design must allow for this possibility.


In user processing, failures occurred frequently so that a motor did not run(average failure rate was 2 to 5%). Examination revealed that IC inputshad been destroyed. During board inspection, the customer erroneouslyremoved and replaced the connector while the DC supply was switchedon. When this procedure was discontinued, the defects did not recur.


(1) Always disconnect the power supply before connecting the board.(2) Protective resistors were inserted at the destroyed input terminals of

the IC.

Reference item

6.2.3 Latchup

In devices in which the structures have a parasitic thyristor, such as CMOS circuitry, a failuremode called latchup often occurs. Latchup is a phenomenon in which parasitic currents that flowbecause of an external surge act as a trigger and switch the parasitic thyristor on. This leads toheat-induced destruction. Such parasitic currents don’t flow as long as the potential on each signalline of the LSI is within the standard values. However, when the ground potential is floating, andthe potential between the input/output signal and the power supply is reversed, the current flows.As the thyristor itself is a normal semiconductor element, if the power supply is cut before thestructure breaks down because of heat, this does not lead to destruction. Once the thyristor has

Rev. 1.0, 01/02, page 226 of 292

been turned on, unless the power is cut the problem can not be resolved, even if the potentialreturns to normal.

Example 16 Destruction due to Latchup of LSI with Multiple Power Supplies

No. 16 Example Destruction due to latchup of LSI with multiple power supplies

Type of device CMOS LSI

Note If the proper sequence for the application of power is not followed, latchupwill result.


After an LSI that had passed the acceptance inspection had beenmounted on a printed board, the LSI suffered destruction duringexamination by an in-circuit tester.

Normally, connections are made first and tests are carried out afteradjusting the voltage in the –5V generating circuit. In this case, however,the test was erroneously performed without the connection being madefirst. Consequently, –5V was not being supplied to the LSI, latchup arose,an abnormal current flowed to ground, and the LSI suffered destruction.

When using CMOS devices, assume the worst so that even if latchupdoes occur, the circuit is made fail-safe in terms of prevention ofsecondary damage, and protective resistors installed to limit self-generated heat.

T

Power Supply

+5 V

+12 V

−5%Generated

Circuit−5 V

+5 V

+12 V

GND

LSI

−5V is lost due to failure and the LSI on the right causes latchup.

Printed Circuit Board


(1) Define the proper sequence for supplying and cutting power withmultiple power supplies LSI.

(2) Insert protective elements in anticipation latchup occurring.

Reference item

Rev. 1.0, 01/02, page 227 of 292

6.2.4 Destruction Induced by Excess Current

Destruction that occurs because of Al metallization meltdown is generically referred to as excesscurrent destruction. Al wiring has a positive temperature characteristic so its resistance isincreased by the application of large currents. As a result, more energy is consumed in the wiringcausing thermal runaway, the Al wiring exceeds Al-Si eutectic temperature and melts down.Transistors suffer destruction from excess current, also there are cases of a large current flow andgenerating excess current destruction. Alternatively, excess current causes the temperature to riseand as a result a eutectic mixture of Al and Si breaks through a junction and transistors aredestroyed. It is thus generally difficult to determine the cause of the destruction from the resultingcondition of the device.

Example 17 Destruction due to Large Value Capacitance

No. 17 Example Destruction due to large value capacitance

Type of device CMOS LSI

Note If the GND does not function properly, the LSI will suffer destruction.


During the debugging of programs, a program development device wasdestroyed for unknown reasons. Regardless of how many times deviceswere repeatedly replaced, several TTL and CMOS devices continued tobe destroyed at the same time. It was determined that latchup occurredbecause a large-valued capacitor (2000 F) was used and when thepower was turned on, the IC’s ground potential rose to half of the power-supply level.

Grounding from Electrical Surge; power supply wiring become resistive and ground potential increases.

Destroyed

InputGround

LSI

LSI

In the case of two power supplies

Output

Low Level (0.4V approx.)

2000 µF

Ground: 2.5V approx.Input: 0.4V approx.

Relative Electrical Potential

Potential of 1/2 the Power Supply


Exchange the large-valued capacitors on printed-circuit boards forsmaller-valued capacitors.

Reference item

Rev. 1.0, 01/02, page 228 of 292

6.2.5 Thermal Runaway

Thermal runaway is a thermal characteristic of any circuit where the positive feedback of powerresults in the temperature rising without limit until destruction occurs. It is no exaggeration to saythat thermal runaway is the most damaging form of destruction. In addition to those cases wherethermal runaway occurs because of local heating of a device, high-power devices have anadditional risk of thermal runaway because of their structurally inadequate thermal dissipation.Caution must therefore be exercised in terms of heat-radiation (thermal management) design.

6.2.6 ASO Destruction

ASO stands for Area of Safe Operation, and this is a destruction mode that typically occurs inbipolar devices. In theory, due to the temperature characteristic of the base emitter voltage, whenthe temperature increases, the voltage VBE falls, and the consumption of energy at the emitterincreases locally. Further, as VBE falls, local hot spots occur which lead to destruction. This isanother kind of thermal runaway.

In the case of a MOS device, since the ON resistance rises with temperature, one characteristic isthe tendency to automatically equalize the generation of heat, this then greatly expands the area ofpossible ASO destruction.

6.2.7 Destructive Avalanche

This is a failure mode which initiates an avalanche break down which in turn causes destructiondue to the applied voltage exceeding the junction break down voltage of a semiconductor device.As with destruction of insulating oxide films, when the yield energy is small, immediatedestruction does not occur. It can be considered that the destruction occurs when the amount ofenergy passing through the junction exceeds a fixed value. Except in designs where it isspecifically intended, care is required as under normal conditions using avalanche break down isprohibited by maximum ratings and other specifications.

Rev. 1.0, 01/02, page 229 of 292

6.3 Protecting Devices from Mechanical Destruction

Semiconductor devices are mainly made up of a silicon chip which forms its core to perform itsfunctions, bonding wires to carry electrical signals to and from the chip, lead wires, heat fins toreliably radiate heat away, and molded resin to hold the whole package together mechanically andprotect it from external stresses. Since the constituent elements of the device differ considerably insuch properties as hardness and thermal expansion coefficient, the mechanical strength margin isless than it would be for a device consisting of a single material. Consequently, all of the stages inmounting components—bending the lead wires, attachment to the heat radiation plate, cleaningafter mounting to the printed circuit board, correcting the bending—harbor the potential formechanical breakage.

External mechanical forces can loosen the adhesive bonding of the resin to the lead frame, andcause the subsequent deterioration of the margin for moisture resistance; transmission of the stressto the bonding wires can cause deterioration of ability to temperature-resistance cycles; and in asevere case wires can be disconnected. In addition, mechanical stresses applied to the heatradiation plate and to the whole package can lead to pellet cracking defects.

In the assembly process, caution should be exercised when mechanical stresses is applied, and theprocess should be designed so as not to permit defects caused by mechanical stresses. If it appearsthat destruction will be caused by mechanical stress during the assembly process, it is possible thatsome damage will be caused not only to the actual defective components but also to componentsthat do not qualify as defective. In this case the product might not perform reliably in the market,so caution is required.

In particular, in a type of product which is of hollow structure and bonding wires are not fixed inplace, there is danger of breakage caused by ultrasonic cleaning and vibration stress. There isdanger that narrow bonding wires will be disconnected by fatigue caused by resonance withultrasonic waves, and that wire disconnection will be caused by vibration and flow of gel resin.

6.3.1 Lead Forming

When semiconductor devices are mounted on a printed circuit board, there are cases in whichouter leads are formed and/or cut in advance; if, in such case, excessive force is applied to a lead,the semiconductor device can be broken or sealant can be damaged.

For example, if relative stress is applied between the package body and the leads of device, aninternal connection could be loosen or a gap could be produced between the package body and thelead, damaging sealant and causing loss of reliability. In the worst case, the molded resin or glasscould break. For this reason, the following precautions should be observed when the leads formingor cutting lead wires.

Rev. 1.0, 01/02, page 230 of 292

(1) When a lead is bent, fix the lead in place between the bending point and the package body sothat relative stress will not be applied between the package body and the lead. Do not touch orhold the package body when bending a lead (see fig. 6.5). When the lead forming die is usedcase, provide a mechanism of holding the outer lead in place and make sure that this outer leadpressing mechanism itself does not apply stress to the device body (see fig. 6.6).

Further, if the package body pressing mechanism is used when bending the lead, this methodsshould support the package body around its periphery as shown in fig. 6.7 to avoidconcentrating stress on the chip. t is the distance between the lead forming support point andthe chip.

Correct

Incorrect

Figure 6.5 How to Bent Package Leads with Handling

W3

W2

W1

W1

t t is the distance over which the main body, even if pulled by the force W3, is suppressed and not connected to the lead forming equipment.Presser

MechanismLeave this interval open.

Forming Mechanism

Figure 6.6 Using the Lead Forming Die

Rev. 1.0, 01/02, page 231 of 292

Lead PressMechanism

Correct

Chip

Main Body Press Mechanism

t

Incorrect

Figure 6.7 Example of the Lead Forming Die with the Package Body Holding Mechanism

(2) When the lead is bent to a right angle, it must be bent at a location at least 3 mm from thepackage body. Do not bend the outer lead more than 90 degrees (see fig. 6.8A). When bendingthe lead less than 90 degrees, bend it at a location at least 1.5 mm from the package body (seefig. 6.8B).

A

B

C

D

3.0 mm min

1.5 mm min

Correct

Correct

Incorrect

Incorrect

Figure 6.8 Locations and Directions for the Lead Forming of the Outer Lead

Rev. 1.0, 01/02, page 232 of 292

(3) Do not bend a lead more than once.

(4) Do not bend a lead in the side direction (see fig. 6.8C).

(5) A lead of device can be broken by excessive stress (such as tension) in the axial direction, sodo not apply more than the prescribed force. The prescribed stress will vary depending on thecross-sectional area of a lead.

(6) Depending on the shape of the bending jig or tool, the plated surface of a outer lead can bedamaged, so exercise caution. If the section that a lead contacts is on the order of 0.5mmR,there is no problem.

Transistors and diodes products can be supplied with preformed leads on request. If desired,please contact our company’s sales representative.

Example 18 A Pellet Crack Defect

No. 18 Example A pellet crack that formed during lead formation.

Type of device Gate array

Lesson learned When forming a lead on a surface-mounted package, check whether amechanical shock is being applied to the package body.


In a user’s process, the leads of a surface-mounted package device werecorrected before being placed on a circuit board using a lead correctionmachine. At this time, the clearance between the forming die pressing onthe base of the lead and the package body was eliminated. For thisreason, foreign matters entered between the package body and theforming die and applied a stress, as a result of which a chip crack defectoccurred.

Countermeasure/Method of checking

Set the clearance between the package body and the forming dieconsidering the size of specks of foreign matter.

Reference item

Rev. 1.0, 01/02, page 233 of 292

Example 19 Damage Caused by a Lead Forming Defect

No. 19 Example Wire break caused by a lead formation defect

Type of device Power transistor (Type TO-202)

Lesson learned A lead must be held securely.


When a transistor lead was formed, a lead forming pressing mechanismwas not used, so a disconnection defect, or break, was caused byloosening a pin.

Since the pressing was insufficient, excessive tension was applied in theX direction and an internal bonding wire was disconnected when the leadwire was bent.

×

Transistor

Presser

Presser

Bending

Lead Wire


When a lead forming, fix it in place between the main body of a transistorand the point where the lead wire is bent (see figure above).

Reference item Precautions when bending (section 6.3.1)

6.3.2 Mounting on a Printed Circuit Board

When a semiconductor device is mounted on a printed circuit board, be careful so that excessivestress is not applied to the leads of device.

The following are the principal precautions that need to be taken (see fig. 6.9).

(1) The intervals between device mounting holes on the printed circuit board should match thedistance between outer lead so that excessive stress is not applied while the device is beinginserted or after it is inserted.

(2) When a device is inserted into a printed circuit board, do not pull on the leads with excessiveforce, and prevent excessive stress from being applied between the leads and the case.

(3) Leave a suitable space between the semiconductor device and the circuit board. A good way todo this is to use a spacer.

(4) After fixing the device to the printed circuit board, avoid assembling the unit in such a waythat stress will be applied between the leads and the device package. For example, when adevice is connected to the heat radiating plate after soldering the leads to the printed circuitboard, fluctuations due to tolerances in lead length and printed circuit board dimensions canresult in stress being concentrated on the lead.Resulting in the lead being pulled out, packagedamage or a lead becoming disconnection. For this situation, solder the lead after device isfixed in place.

Rev. 1.0, 01/02, page 234 of 292

(5) When using an automatic insertion equipment, one should be especially careful so thatmechanical shock is not applied to the package body at the time of insertion. This will helpprevent cracks from forming in the package or the chip due to shock. Also, when an automaticforming device is used, one should observe the precautions given in section 6.3.1.

(6) When the component is mounted in IC socket and used under severe environmental conditionsthe contact between the IC pins and the IC socket may degrade. One should avoid using an ICsocket as much as possible. Also, when an IC socket is used to mount a multi-pin grid arraypackage device to a circuit board, the package can break or pins may bend when the package isinserted or removed. Therefore it is strongly recommended that a commercially availableinsertion/removal tool be used. One of the Orgat TX8136 series is a good choice for aninsertion and removal tool.

Semiconductor Device

A mounting technique in which stress is not applied to the bases of lead wires (arrows)


The distance between leads should be the same as the interval between printed circuit board mounting holes.

Insert the semiconductor device carefully into the printed circuit board. The lead are being pulled through with pliers.


Incorrect

Incorrect

Incorrect

The lead are being inserted into the printed circuit board in an awkward manner, so stresses are applied as shown by the arrows.

Avoid forcing the leads into the printed circuit board with improperly formed leads.The distance between holes in the printed circuit board are inappropriate for this devise.

Correct

Correct

Correct

Figure 6.9 Methods of Mounting a Semiconductor Device on a Printed Circuit Board

Rev. 1.0, 01/02, page 235 of 292

Example 20 Damage of a Package by Automatic Insertion

No. 20 Example Destruction of a package by automatic insertion

Type of device Silicon diode (DHD type)

Lesson learned Stress must not be applied to the main body of a device while a lead isbeing bent.


In automatic insertion of a DHD type diode into a printed circuit board by ahigh speed insertion machine, the package glass was broken either byexcessive pressure on the device main body or by excessive force usedto clinch leads on the rear side of the circuit board.

Lead Wire Package Glass


Presser Mechanism

Lead Clinching Mechanism

Countermeasures/Methods of checking

(1) Adjust the position of the presser mechanism (mold). Make thepresser mold of a material that can provide a buffer against shock.

(2) Keep the lead clinching force to a minimum.

Reference item

Rev. 1.0, 01/02, page 236 of 292

Example 21 Solder Defect Caused by Warping of a Printed Circuit Board

No. 21 Example Solder defect caused by warping of printed circuit board

Type of device Microcomputer

Lesson learned Be careful in correcting the warp of a circuit board by reflow.


A defect involving the peeling off of solder under a surface-mountingreflow stress occurred. No matter how many times a solderbility test wasperformed, no abnormality was detected, and the cause could not bedetermined. In the course of discussions the subject of warping followingreflow was raised; examination of the circuit board involved showed thatasymmetry of the copper pattern was the cause and that the warping wasabnormally large. It was judged that after reflow, while the circuit boardwas still hot, mechanical stress was applied to correct the warping.

In reflow, the assembly stress on surface mounted devices can be quitelarge. These can develop into high stresses on the printed circuit board. Ifthe circuit board undergoes large warping at the assembly stage which itis heated, even if the LSIs initially become bonded to the circuit board,they can become loose later. The user must keep control over the allowedamount of warping.

Countermeasures/Methods of checking

(1) The circuit board pattern and the component layout were adjusted toprevent warping.

(2) The frame material was changed to increase the mechanical strengthper pin with respect to the circuit board.

Reference item

Example 22 Die Cracking at the Time of Mounting a Component on a Circuit Board

No. 22 Example Die cracking at the time of mounting a component on a circuit board

Type of device Power transistor (DPAK), Small-signal transistor (UPAK)

Lesson learned It is necessary to determine if the exterior coating resin affects the stresson the device.


When an exterior-coating resin was used in mounting a component on acircuit board, the difference in thermal expansion coefficients between theepoxy resin in the device and the phenol resin used for the coatingcaused an excessive stress to be applied to the inside of the element,ultimately leading to formation of a die crack.

Use of such a coating can adversely affect the device, depending on thecoating material and thickness. Use caution in such cases.


When using an exterior-coating resin, apply a stress-absorbing resinbetween the coating resin and the epoxy resin in the device.

Reference item

Rev. 1.0, 01/02, page 237 of 292

6.3.3 Flux Cleaning Methods

Flux residue remaining after soldering may affects the components and circuit board wiringreliability, so as a general rule the flux must be removed. Cleaning methods include ultrasoniccleaning, immersion cleaning, spray cleaning and steam cleaning. These have the followingrespective characteristics.

(1) Ultrasonic Cleaning

The product is immersed in a solvent and ultrasonic vibrations applied. This method is suitablefor cleaning inside minute cracks, but in some cases can cause damage to the connectionsbetween components and the circuit board, so caution is necessary.

(2) Immersion Cleaning

The product is cleaned by immersion in a cleaning fluid. It is necessary for the cleaning fluidto have high purity.

(3) Spray Cleaning

A solvent is sprayed on the product under high pressure. When the clearance betweencomponents and the circuit board is small, the cleaning effectiveness can be increased byspraying at an angle.

(4) Steam Cleaning

A vaporized solvent is used for cleaning. This permits cleaning to be done with a solvent thatdoes not contain impurities, so it is often used in the final cleaning step.

Normally a combination of these methods is used. The normal flow of cleaning is shown infig. 6.10.

Ultrasonic Cleaning

Cleaning by Immersion in Hot Fluid

Cleaning by Immersion

in Cool Fluid

Spray Cleaning

Steam Cleaning

Drying

Figure 6.10 Normal Flow of Cleaning

Rev. 1.0, 01/02, page 238 of 292

One must pay attention to the following points when cleaning.

(a) One example of the conditions under which ultrasonic cleaning is performed is given below,but to prevent damage to the device, caution is needed regarding the applied frequency, power(especially the peak power), time, and preventing the device from resonating.

• Frequency: 28 to 29 kHz (the device must not resonate).

• Ultrasonic output: 15 W/liter (1 time)

• Time: 30 seconds or less

• The device and the printed circuit board must not directly contact the vibration source. Inparticular, ceramic package type QFNs (LCC) and QFPs (Ceramic) are cavity packages;when subjected to ultrasonic cleaning the connecting wires can resonate under certainconditions and become open or disconnected.

(b) When cleaning is continued for a long time, the marking may be erased, so check theconditions that will be used by running an actual test before committing large quintiles ofproducts.

(c) When a solvent is used, local standards for the environment and safety must be observed.

(d) It is recommended that the MIL standards summarized in table 6.8 be applied for the degree ofprinted circuit board cleanliness.

Table 6.8 Cleanliness Standards of a Printed Circuit Board

Item Standard

Residual Amount of CI 1 g/cm2 or less

Electrical Resistance of Extraction Solvent(after extraction)

2 106 • cm or more

Notes: 1. Circuit board area: Both sides of printed circuit board + mounted components2. Extraction solvent: Isopropyl alcohol (75vol%) + H2O (25vol%) (before extraction)

(electrical resistance of extraction solvent must be 6 106 • cm or more).

3. Extraction method: Clean both surfaces of circuit board (for 1 minute or more) with atleast 10 ml/2.54 2.54 cm2 of solvent.

4. Measurement of electrical resistance of extraction solvent: With electrical conductivitymeter

For details of the MIL standards, see MIL-P-28809A.

Rev. 1.0, 01/02, page 239 of 292

Example 23 Destruction by Ultrasonic Cleaning

No. 23 Example Trouble in ultrasonic cleaning

Type of device Ceramic package

Lesson learned When cleaning a package with a cavity ultrasonic, it is necessary to becarefully monitor the power.


After a ceramic package device was assembled, it was cleanedultrasonically; the bonding wires resonated with the ultrasonic vibrations.The bonding wires suffered fatigue and become disconnected in a shorttime.


Specify a frequency, output and time at which resonance will not occur.

Reference item

Example 24 Problem that Occurred when a Circuit Board was not Cleaned

No. 24 Name ofExample

Problem that occurred when a circuit board was not cleaned


Lesson of learned Be careful of minute leaks.


When components were soldered to a circuit board, flux adhered to thesurface of the IC package; subsequently, flux that remained on thesurface of the IC package absorbed moisture, the surface leakage currentbetween IC terminals increased, and the circuit board became defective.


After a circuit board is soldered, the flux should be cleaned off.

Reference item

6.3.4 Attachment of the Heat Radiation Plate

In a power device, a heat radiating plate can be used to radiate heat that is produced and thuslower the junction temperature. Attaching a semiconductor device to a heat radiating plate is aneffective method of removing heat. To avoid loss of reliability, it is necessary to take thefollowing precautions.

(1) The Selection of Silicone Grease

To improve heat conduction between the device and the heat radiating plate and increase theheat radiating effectiveness, silicone grease is uniformly applied in a thin layer to the surfaceof the device that contacts the heat radiating plate. Depending on the device, in some cases thedevice can absorb oil from the silicone grease causing the chip coating material to swell. Whenselecting a silicone grease, we recommend the use of G746 made by Shin-Etsu Chemical co.Ltd., or equivalent This grease has been formulated specific with an oil base that has low

Rev. 1.0, 01/02, page 240 of 292

affinity for the package resin so that it will not cause the coating material to swell. Of course,an equivalent product may be used (however it is not necessary when using a metal canpackage. ).

If a different type of grease is used, it may not be possible to guarantee product quality. Use ofa hard grease can cause resin cracking when a screw is tightened, so use caution. One shouldavoid applying more grease than necessary, since it can cause excessive stress.

(2) Use suitable torque when tightening.

If the applied torque is too low, the thermal resistance will increase, while if it is too high thedevice can deform. This can cause package damage and lead breakage. Use only appropriatetorque to tighten that is within the limits given in table 6.9. The effect on thermal resistancebetween the thickness of insulating material and tightening torque is given in figs. 6.11 and6.12.

Table 6.9 Optimum Tightening Torque for Representative Packages

Package Optimum Tightening Torque [kg • cm]

TO-3 6 to 10

TO-66 6 to 10

TO-3P 6 to 8

TO-3PFM 4 to 6

TO-220 4 to 6

TO-220FM 4 to 6

TO-126 4 to 6

TO-202 4 to 6

Power IC 4 to 8

Rev. 1.0, 01/02, page 241 of 292

The

rmal

Res

ista

nce

(incl

udin

g C

onta

ct T

herm

al R

esis

tanc

e)of

Insu

latin

g M

ater

ial

θc +

θ1

(°C

/W) 4.0

3.0

2.0

1.0

00.05 0.10 0.15 0.20

Thickness d (mm) of Insulating Material

With Silicone Oil Applied

Mylar

Mylar

Mica

Mica

Without Silicone Oil

TO-3 type(6 km • cm)

Figure 6.11 Relations between Thickness and Thermal Resistance of Insulating Material(Typical Examples)

With Silicone Oil Applied

Without Silicone Oil

TO-3 type example

Con

tact

The

rmal

Res

ista

nce

θc (

°C/W

)

1.0

0.8

0.6

0.4

0.2

0 2 4 6 8 10

Tightening Torque (kg • cm)

Figure 6.12 Relations between Tightening Torque and Contact Thermal Resistance

(3) Give adequate consideration to the flatness of the heat radiating plate. If the heat radiatingplate is not suitable, attached to the device, it will not effectively radiate heat away and cancause excessive stress. This can lead to deterioration of characteristics and package to resincracks. Consequently, the following precautions should be observed with the heat radiatingplate.

(i) Neither concave nor convex warping of the heat radiating plate should exceed 0.05 mm ina horizontal distance equal to the interval between screw holes (figs. 6.13 and 6.14). Also,the twist should not exceed 0.05 mm.

Rev. 1.0, 01/02, page 242 of 292

0.05 mm or less 0.05 mm or less

0.05 mm or less0.05 mm or less

L1 L2

L2L1

Convex Warp

Concave Warp

L1: Interval between Screw Holes (24 ± 0.22 mm), L2: Range Width (10.7 mm)

Figure 6.13 Warping of a Heat Radiating Plate—Examples of QIL and DIL Packages

0.05 mm or less 0.05 mm or less

0.05 mm or less0.05 mm or less

L2

L2

L1

L1

L1: Interval between Screw Holes (24 ± 0.3 mm), L2: Header Width (8.4 mm)

Figure 6.14 Warping of a Heat Radiating Plate—Example of an SIL Package

(ii) For the case of aluminum, copper or iron plates, verify that there are no residual burrs, andalways bevel the screw holes.

(iii) It is necessary to polish the surface that will contact the device until it is quite flat (finishing).

(iv) Make certain there is no foreign material such as cutting filings caught in the spacebetween the IC header and the heat radiating plate.

(v) Design the distance between screw holes to be the same as the interval between devicescrew holes (for example in the case of a SP-10T type power IC, 24 ± 0.3 mm). Aninterval that is either too wide or too narrow can cause resin cracking.

Rev. 1.0, 01/02, page 243 of 292

(4) Do not solder anything directly to the device heat radiation plate.

If something were soldered directly to the device heat radiation plate, a great deal of thermalenergy would be applied causing the device junction temperature to greatly exceed thetemperature at which operation is guaranteed. This would seriously affect the device,shortening its lifetime or even destroying it.

(5) Do not apply mechanical stress to the package.

When tightening, if the tool used (screwdriver, jig, etc.) hitsthe plastic package directly, notonly can cracks be produced in the package but the mechanical stress can be transmitted to theinside, accelerating fatigue of the device connection section and destroying the device orcausing wire damage. One must always use caution when applying mechanical stress.

(6) Do not attach any device to a heat radiating plate after a lead wires are soldered.

If a device is attached to a heat radiating plate after a lead are soldered to the printed circuitboard, dispersions in lead length and differences in the dimensions of printed circuit boardsand heat radiating plates can lead to excessive stress being concentrated in the leads. This cancause lead wires to be pulled out, packages to be destroyed and wires to be disconnected.Consequently, the device should be attached to the heat radiating plate first, and then the outerleads soldered.

(7) Do not mechanically process or deform a device heat radiating plate or package.

If a device heat radiating plate is cut or deformed, or a package is mechanically processed ordeformed, the thermal resistance will be increased and abnormal stress applied to the interiorof the device, causing failures to occur.

(8) When attaching a power device, use the recommended components (spacer, washer, lugterminal, screws, nuts, etc.) (see fig. 6.15).

Rev. 1.0, 01/02, page 244 of 292

Type TO-3 Type TO-220

3-mm Diameter Screw

Spacer

Chassis

Insulating Washer

Metal Washer

Lug Plate

Spring Washer

3-mm Diameter Nut

Insulating WasherMetal WasherSpring Washer

YZ033S Washer

SK16B Spacer

Heat Radiating Plate

+0.1−0.08

3-mm Diameter Sscrew

3.6 mm Hole Diameter

Metal Washer

3.3-mm Diameter

3-mm Diameter Nut

2.2-mmDiameter

Figure 6.15 Example for Attaching a Power Transistor

(9) Screws that are Used

The screws that are used to attach the device to the heat radiating plate can be classified intocap screws and self tapping screws; the following precautions are needed in using these.

(i) Use binding-cap screws conforming to the JIS-B1101 standard and screws that have headsequivalent to truss cap screws.

(ii) Absolutely do not use any flat-head screws since they will apply excessive stress to thedevice (fig. 6.16).

Rev. 1.0, 01/02, page 245 of 292

(Use any of thread screws, pan head screws, truss head screws, binding cap screws or flat head screws.)

Binding Cap Screw Truss Head Cap Screw

Recommended Screws

Flat Head Cap Screw Round Flat Head Cap Screw

Screw types that must not be used

Figure 6.16 Types of Screws to be Recommended and not be Used

(iii) When self tapping screws are used, adhere strictly to the tightening torque given above.

(iv) When using self tapping screws, do not use screws that are larger than the hole diameter inthe device attachment section. These screws tap not only the heat radiating plate but alsothe device attachment holes, which can cause trouble.

(10) Heat Radiating Plate Screw Hole Diameter

(i) If the hole is too large: Do not make the heat radiating plate hole diameter or bevelinglarger than the head diameter of the screws to be used. In particular, in a device that usescopper plating as the flange material (TO-220, power IC, etc.), the tightening torque cancause deformation of the copper plating and the plastic package.

(ii) If the hole is too small: In particular, if a self tapping screw is used, the tightening torquewill increase and exceed the recommended tightening torque that was discussed above, orelse the desired contact resistance will not be obtained.

(11) Other Precautions and Recommendations in Attaching Components to the HeatRadiating Plate

(i) If two or more devices are attached to one heat radiating plate, the thermal resistance foreach will increase (see fig. 6.17).

(ii) The heat radiating plate must be of suitable size and shape for radiating heat away. Inaddition, forced air cooling must be provided as necessary. Measure the product casetemperature under actual use conditions, calculate the junction temperature using publishedthermal resistance value.

Rev. 1.0, 01/02, page 246 of 292

Notes:1. Heat radiating plate 300 × 200 × 1.5 mm aluminum plate2. Attachment method

a. Position (figure at right)Unit: mm

b. Tightening torque 9 kg • cmc. Silicone oil is applied to the contact surface; mylar is not used.d. Natural convection, horizontal position

Junc

tion

Tem

pera

ture

Incr

ease

∆T

j (˚C

) 120

100

80

60

40

20

0 5 10 15 20 30Collector Power Consumption

per Component (W)

300

70 min

200

Case i

n whic

h 2 co

mpone

nts ar

e atta

ched

Case in

which

1 component is

attach

ed

Figure 6.17 A Case in which Two Components are Attached to One Heat Radiating Plate

Rev. 1.0, 01/02, page 247 of 292

Example 25 Package Destruction during Mounting

No. 25 Example Package destruction at time of mounting

Type of device Power transistor (type TO-220)

Lesson learned The torque used to tighten must be checked.


When a power transistor was mounted, the compressed air screwdrivertorque rose above 10 kg • cm and the mounting holes in the heat radiatingplate were too large, so the header and the plastic boundary surfacepeeled off. Depending on the type of compressed air screwdriver, thedispersion in the tightening torque can become large. If the torque risesabove 8 kg • cm, the heat radiating plate mounting holes are larger thanthe screw diameter, or if the heat radiating plate mounting holes are notsufficiently flat, the header can be deformed or separate from the plastic.


Use a torque within the recommended limits. For the type TO-220 therecommended limits are 4 to 6 kg • cm. Keep the flatness of the heatradiating plate mounting holes within 50 m, make sure that the mountingholes do not open wider than the screw head diameter, and use theaccessory metal washers (YZ033S).

Reference item

Rev. 1.0, 01/02, page 248 of 292

Example 26 Die Cracking at Time of Mounting to a Heat Radiating Plate

No. 26 Example Die cracking at time of mounting to a heat radiating plate

Type of device Power transistor (type TO-3)

Lesson learned Always check the tightening holes meet the recommended conditions.


The heat radiating plate mounting holes were of large diameter and wereexcessively beveled, so that when the transistor was mounted, one sideof the heat radiating plate tightened around the screw hole and droppedinto the beveled section and stem became inclined. When the other sidewas tightened, the entire stem deformed. The result was that at leasttwice as much of typical stress was applied to the die inside, causing theto crack.

Screw

Cap

Stem

Heat Radiating Plate

Nut

Countermeasuresand/Methods to verify

(1) Make the heat radiating plate hole diameter (including the beveledsection) smaller than the screw head diameter.

(2) Use the appropriate torque to tighten.

Reference item

6.4 To Protect the Device from Thermal Destruction

As it was stated above, because of its construction a semiconductor device is very sensitive tomechanical and thermal stresses. In addition, materials used in construction having very thermalexpansion coefficients. These differences have the potential to cause the adhesive holding thedifferent substances together to break. Repeated thermal stress on metals can cause fatiguefractures.

In particular, the recent emphasis on light, thin, short and small surface mounted devices has led toreduced margins for the following points.

(1) As the temperature rises, the mechanical strength of plastic assembly drops considerably.

(2)When the temperature exceeds 100°C, moisture in the resin vaporizes and the vapor fills gaps,causing steam explosions. This is termed the “popcorn “ effect.

One should carefully check the storage conditions and assembly conditions for each product, andmonitor them accordingly.

Rev. 1.0, 01/02, page 249 of 292

6.4.1 Soldering Temperature Profile

(1) Precautions during Soldering Attachment

In general, it is not desirable to expose a semiconductor device to a high temperature for a longtime.

Also, when soldering, whether using a soldering iron or by a reflow method, it is necessary to dothe processing at as a low temperature and in as a short time as possible to achieve the requiredattachment. The standard condition to determine the ability of a semiconductor device towithstand the heat of soldering is, to apply 260C heat at 1 to 1.5 mm from the device package,260°C for 10 seconds or 350°C for 3 seconds. The semiconductor is then examined and tested toinsure it withstood the heat exposure. When performing soldering, be careful not to exceed thesevalues.

An example of temperature increase during soldering, the increase of temperature in the jointsection when soldering is done on a low power plastic-package power transistor, is shown in fig.6.18. After heating in a soldering tank at 260°C for a specified time, the temperature of the jointsection was measured. If the soldering temperature is high and/or the time is long, the temperatureof the device increases; in some cases this can cause deterioration or breakage.

If the flux that is used for soldering is strongly acidic or alkaline, the leads can be corroded, Theuse of resin flux is recommended, but in any case the flux should be removed off thoroughly aftersoldering (see section 6.3.3).

The soldering iron that is used should either have three terminals including a ground terminal orthe secondary voltage decreased using a transformer so that there is no leakage current at the tip ofthe iron. If possible, the tip should always be grounded. In this case, one must be careful thatsecondary damage is not caused by the ground (see fig. 6.19). In addition, the soldering should bedone as far as possible from the device package.

Rev. 1.0, 01/02, page 250 of 292

200

100

200

100

Pull Up

Pull Up

Time (seconds)

Time (seconds)

Solder Tank at 260°C

Solder Tank at 350°C

In Air

In Air

1.5 mm

1.5 mm

260°C

350°C

Junc

tion

Tem

pera

ture

(°C

)Ju

nctio

n T

empe

ratu

re (

°C)

0

0 10 20 30 40 50 60

0 10 20 30

20 40 60 80 100 140 180 240 300

0 60 120Solder

Transistor

Solder

Transistor

Figure 6.18 Junction Temperature during Soldering

AC100 V C

24 V

Tip of Iron

1 MΩ

There must not be any leakage current at the tip of the soldering iron and a potential must not be produced. The tip should be grounded as far away as possible from the device as a recommended method.

Figure 6.19 Grounding of the Tip of a Soldering Iron

Rev. 1.0, 01/02, page 251 of 292

(2) Soldering a Lead Insertion Type Package in a Wave Solder Tank

In this method, the soldering is done by immersing the sections the package leads intended belowthe liquid surface in the jet flow solder tank. If the solder jet comes into contact with the devicepackage can break, so be certain sure that the solder does not come into direct contact with thedevice package.

In addition, when using a wave solder tank, the bottom surface of the substrate is heated by the hotsolder, and the temperature difference between the top and bottom surfaces can cause the substrateto warp. If soldering is done while the substrate is warped, at the time of removal from the soldertank the substrate will try to return to its original shape, causing excessive stress being applied tothe leads and the package. This in turn can cause the solder holding the joint together to crackand/or the leads and the package to break. For this reason, when a wave solder tank is used, thesubstrate should be held in place by brackets so that it will not be warped (see fig. 6.20).

Stress Stress Stress

Stress

Heating by Solder

(a) Warping of a substrate by wave solder heating

(b) Residual stress applied to the package when the substrate temperature drops

Figure 6.20 Warping of a substrate in a wave solder tank

6.4.2 Precautions in Handling a Surface-Mount Device

Here, we explain specific precautions and mounting conditions for surface-mount devices, the useof these has recently been expanding quite rapidly. A surface-mount device must be soldered fromthe side of the printed circuit board on which the parts are mounted. It is intrinsically easy for thedevice to be subjected to thermal stress during mounting. In particular, if the mounting methodinvolves heating the whole package, the following precautions should be observed duringmounting. For details please refer to our company’s publications “Hitachi Surface-Mount PackageUser’s Manual.”

(1) Absorption of Moisture by the Package

If the epoxy resin used in a plastic package is stored in a humid location, moisture absorptioncannot be avoided. If the amount of moisture absorbed is sufficiently large, it can vaporizesuddenly during soldering causing the resin to separate from the lead frame surface. In aparticularly severe case, the package can crack (see section 3.2.7). Consequently, it isimportant to store surface-mount packages in a dry atmosphere.

Rev. 1.0, 01/02, page 252 of 292

Moisture –absorption sensitive products that should be stored in vapor barrier packaging. Thisprevents moisture from being absorbed during transportation and storage. To prevent moistureabsorption after opening the storage bag the packages should be stored in the prescribedenvironment and mounted by reflow soldering within the defined storage time limit.

The required storage environment conditions and storage time limit are ranked according to theability of each product to withstand the storage temperature conditions. If a device is to bestored again in vapor barrier packaging, active silica gel t (the type with an indicator that turnsblue if moisture is absorbed) should be put inside with it. If the device has been out of vaporbarrier packaging and exposed to outside air for several days, it will return to its originalcondition after being in the new vapor barrier packaging with the silica gel for three to fivetimes the time the length time it was exposed to ambient. To remove moisture that wasabsorbed during transport, storage and handling, it is recommended that the device be bakedfor 16 to 24 hours (4 to 24 hours in the case of an ultra thin package such as a TQFP or TSOP).

In the following cases, it is necessary to bake the device at 125°C before mounting andsoldering it.

• The blue indicator in the silica gel desiccant cannot be seen at all through the desiccantbag.

• The permissible storage time after opening the package has been exceeded while theproducts are being stored under the conditions stated above.

• The attached label states that it should be baked.

(There are some products attached to an ultra thin package or an extra large chip that need tobe baked in any case.)

The magazine, tray, or tape and reel normally used in shipping cannot withstand muchtemperature, so the package typically cannot be baked as it is packed and received. Transferthe package to a heat resistant container. A tray with the words HEAT PROOF inscribed on itcan be baked as is. However, avoid baking the package while it is inside vapor barrierpackaging. Bake gradually, with the tray placed on a flat board, so that the tray will not warp.

(2) Dealing with Hygroscopicity

Surface-mount products tend to have shorter distance from the outside lead to the inside ICchip than plastic-sealed DIP products, so in some cases consideration needs to be given tohygroscopicity. For example, in devices that are to be used outdoors or in which ability towithstand moisture is particularly important, an appropriate measure such as resin coating isemployed. Coating materials include polyurethane and silicone resins. Stresses produced byhardening of the resin, contraction stress and the difference in thermal expansion coefficientsbetween the resin and substrate can cause the element to crack, the solder joint between thelead and the substrate to crack. Therefore the coating material selected and applied carefully..

Rev. 1.0, 01/02, page 253 of 292

(3) Precautions with Taped Items

In the case of a taped chip component or IC (MPAK, SOP, etc.), electrical charging caused byseparation of the cover tape or the carrier tape increases with the speed of the tape separation.To prevent the component from being damaged by static electricity, avoid rapid separation andfriction as much as possible.

The recommended separation speed = 10mm/s or less

(4) Precautions in Mounting

When relative humidity decreases, it becomes easier for objects to become charged with staticelectricity. When the humidity is excessively low. During storage one should avoid subjectingthe package being subjected friction, so that it does not becoming electrostatically charged.However, in handling and in mounting on a substrate, the relative humidity should be keptbetween 45% and 75% to minimize the possibility of ESD damage..

6.4.3 Using Reflow to Attach Surface-Mount Devices

On a pattern of a printed circuit board, to match the lead pins of the package, the specified amountof solder paste is applied. For example when using the screen printing, the package is placed ontop of that the solder pattern. The package is temporarily held in place by the surface tension ofthe solder paste. Then, when the solder is reflowed, the package leads are joined to the pattern tothe printed circuit board by both the surface tension of the melted solder and the self-aligningeffect.

The design values of the pattern to which the leads are joined on the printed circuit board differdepending on the solder paste material; that is used and the reflow conditions, As a rule, thepattern width should be 1.1 to 1.3 times that of the lead pins that will be soldered to it.

6.4.4 Recommended Conditions for Various Methods of Mounting Surface-Mount

Devices

The most widely used methods of mounting surface-mount devices are the infrared reflow, thevapor phase reflow and the flow solder methods ( wave soldering ). These mounting methods allinvolve heating the entire package. Strong thermal stress is applied to the package. From the pointof view of maintaining reliability, it is necessary to monitor the package surface temperature aswell as the temperature of the solder joint. Our company’s recommended mounting conditionsinclude the package surface temperature in the case of the reflow method; the solder temperatureand immersion time in the case of flow solder.

Rev. 1.0, 01/02, page 254 of 292

Pac

kage

Sur

face

Tem

pera

ture

Time

Peak Temperature and TimeTemperature

Gradient 2

Actual Set Condition

Preheating

Temperature Gradient 1

Figure 6.21 Example of Recommended Conditions

We will now present our thinking behind the recommended conditions, with reference to fig. 6.21.

(1) Temperature Gradient 1

When the temperature increases suddenly rapidly, the temperatures of the different parts of asurface-mount device (such as the package surface, interior and rear) become different, so thepackage warps due to the difference in thermal expansion coefficients among the differentmaterials, in some cases this leads to damaging the chip. Consequently, attention must be paidto the upper limit of the rate of temperature increase. The lower limit is determined by theoperating efficiency of the reflow device.

(2) Preheating

The temperatures of the components and the substrate are kept below the melting point of thesolder to stabilize the solder joint and lessen the thermal shock. In general, this is set near therated temperature of the surface-mount device.

(3) Temperature Gradient 2

The upper limit of the rate of temperature increase is determined as in (1) above. The lowerlimit is determined by the need to keep temperature and the time within limits specified in (4).

(4) Peak Temperature and Time

These are the most important factors requiring attention to keep any damage suffered by thepackage to a minimum. The peak temperature directly affects the drop in strength of thepackage (due to the temperature characteristics of the resin) and the water vapor pressureinside the package, so as low a temperature as practical is desired. In addition, since the watervapor pressure increases with time, so it is necessary to keep the time as short as possible. Theconditions recommended by our company are the coincident points between the aboveallowable conditions and the range in which soldering is possible. These values are upperlimits, not averages, so when setting the conditions it is necessary to be careful not to exceedthe upper limits (for example as given by the dotted line in fig. 6.21).

Rev. 1.0, 01/02, page 255 of 292

The conditions recommended by our company for the various mounting methods are given in figs.6.22 and 6.23.

Time

Pac

kage

Sur

face

Tem

pera

ture

10 seconds maximum235°C max

140 to 160°C

about 60 seconds

1 to 4°C/second

1 to 5°C/second

Figure 6.22 Recommended Conditions for Infrared Reflow and Air Reflow

about60 seconds

Time

Pac

kage

Sur

face

Tem

pera

ture

30 seconds maximum215°C

140 to 160°C

1 to 5°C/second

Figure 6.23 Recommended Conditions for Vapor Phase Reflow

Rev. 1.0, 01/02, page 256 of 292

Example 27 Die Cracks in a Surface-mount Package

No. 27 Example Die cracks in a surface-mount package

Type of device QFP package

Lesson to be learned Whether the package surface temperature satisfies the recommendedtemperature

Outline of example/phenomena/causes

When a semiconductor surface-mount package (QFP) is mounted on asubstrate by hot air reflow soldering, the transient temperature difference(TS – Ti = 60°C) that occurs inside the package during the sudden heatingapplied for reflow soldering causes the package to warp. This thenproduces a stress that can cracks the die.

Die

Hot Air Heating

TSTi

Location where temperature is measured

Lead


Change the conditions so that the temperature increase during mountingbecomes more gradual.

Reference item

Rev. 1.0, 01/02, page 257 of 292

Example 28 Reflow Mounting Defects

No. 28 Example Reflow mounting defects

Type of device Surface-mount package diode

Lesson to be learned Poor mounting balance will cause problems such as productdisplacement and float.

Outline of example/phenomena/causes

If the mounting balance is poor when a surface mounted package (URP,UFP, LLD, etc.) is mounted using reflow soldering, mounting problemscan occur such as the package becoming displaced or not fixed on thesurface.

(1) The land pattern does not have left-right symmetry.(2) The land pattern, including the wiring, does not have the same areas

on left and right sides.(3) The amount of solder cream applied is not uniform.(4) The land pattern is not centered in the left-right direction.(5) The soldered parts are not all heated at the same time.(6) If some parts are in the shadow of neighboring components, the left-

right temperature imbalance of the soldered section can becomelarge.

Countermeasure/Method of verifying

Check for the problems listed above.

Reference item Hitachi Diode Data Book

Rev. 1.0, 01/02, page 258 of 292

6.5 Protecting Devices from Malfunction

There are several types of semiconductor malfunction. The semiconductor itself can becomedamaged or degraded, making normal operation permanently impossible. In other cases, eventhough a semiconductor has a slight defect it will operate normally until a change in the conditionsof use and/or environmental conditions causes the latent defect to become critical. In the formercase, there is nothing to do except replace the damaged part, so quality is expressed in terms ofMTTF (Mean Time To Failure). In the latter case quality is expressed by a measure of thefrequency with which malfunction occurs, MTBF (Mean Time Between Failures).

MTBF expresses the frequency of malfunction in the environment in which the device is actuallyused. If the mechanism of malfunction and the conditions in which it occurs become clear, it ispossible for the operation to become 100% defective under those conditions. In this section weexplain mainly the latter case.

6.5.1 Precautions with Respect to Hardware

In our company’s 100% inspection procedure, a component’s electrical characteristics areefficiently and rigorously tested by a tester. However, for economic reasons there is a limit as tohow much time can be spent testing one component, so the test is conducted under what areexpected to be the worst case conditions. Because of the difference between the conditions of thetester test and the conditions under which the component is used in practice, there are cases inwhich malfunction occurs. Here we give specific examples of troubles that have been experiencedin the past, in the hope that this experience can be applied in the final evaluation of products.

(1) Precautions in Circuit Design

Circuits are classified into two categories, analog circuits and digital circuits.

Analog circuits, typified by PLL circuits, sacrifice gain to obtain accurate amplification factor bymeans of a feedback circuit between the input signal and the output signal. They can also generatea variety of functions. They can also use a comparison circuit to detect and integrate the phasedifference between input signals and use a voltage-frequency conversion circuit to tune the phasedifference. In all cases small differences between input signals are greatly amplified for use, so itis easy for noise that accompanies the input signal to have a considerable effect, and the output isvery sensitive to fluctuations in the electrical characteristics of constituent elements.Consequently, small changes in leakage current and changes in gain can develop into amalfunctioning condition. Therefore it is necessary to design the circuit while comprehending theworst case conditions among the electrical characteristic specifications in sensitive parts of thecircuit.

In contrast, in a digital circuit, the levels of the input signal and the output signal are standardized,and a noise margin between the two signals is set, which is advantageous with respect to

Rev. 1.0, 01/02, page 259 of 292

fluctuations in the characteristics of constituent elements. On the other hand, if a malfunction doesoccur, it has the potential to grow into very serious malfunction, depending on the meaning of thesignal that is affected. Recently, in devices which contain programs such as microprocessors, oncethe content of the program is changed, even if the immediate cause of the malfunction is removedthe original operation cannot be restored, so that the damage caused is greater than in the case ofan analog circuit. When malfunction occurs in a digital circuit, whether the input level, outputlevel and timing margin are being observed correctly are important points. In addition, particularlyduring transient periods such as when the power is turned ON or OFF, one important precaution isto design the circuit so that the effect of environmental conditions under which correct operation isnot guaranteed does not remain after regular operation starts.

Example 29 TTL-CMOS Interface

No. 29 Example TTL-CMOS interface

Type of device TTL, CMOS IC

Lesson learned Undershoot and overshoot must be within the specified range.

Summary of example/phenomenon/cause

When CMOS LSIs are driven by TTL ICs, a malfunction may occur due toundershoot noise or insufficient input level.

Undershoot is caused by reflection due to the imbalance between the lowoutput impedance of the TTL IC and the extremely high input impedanceof the CMOS LSI.

Insufficient input level is also caused by the significant difference in theinput level between TTL and CMOS. Particularly, the TTL level outputdoes not rise to Vcc level, which will cause a problem.

(1) Insert a resistor at output pins of TTL IC to prevent undershoot.(2) Attach a pull-up resistor to input pins of CMOS IC.(3) Use a special interfacing IC.

Reference items

Rev. 1.0, 01/02, page 260 of 292

Example 30 Malfunction of Power-on Reset Circuit

No. 30 Example Malfunction of power-on reset circuit


Lesson learned An appropriate type of power-on reset circuit must be used for the power-up waveform.


There are two types of power-on reset circuits, integral and differential.The integral type is vulnerable to an outrage or short-time power supplyinterruption, whereas the differential type is vulnerable to slow rises involtage. Due to this, circuits may malfunction as shown in the figurebelow.

(1) Malfunction of integral circuit

If t is too short after power is turned off, the potential at point A will not fall and a pulse will not be generated (dotted line).

tPower Supply

Reset

TimeReset

A

Power Supply

Schmitt Trigger

(2) Malfunction of differential circuit

If the rise of the power supply is too slow, the reset waveform will not reach the reset operation potential and a reset will not be effected (dotted line).

Power Supply

Reset

Time

Reset Operation VoltageReset

Power Supply

Countermeasure/measure of checking

Replace the current power-on reset circuit with the power supply voltagemonitoring IC shown in the figure below.

ResetPower Supply

Voltage MonitoringIC

Power Supply

Reference items

Rev. 1.0, 01/02, page 261 of 292

Example 31 Malfunction during Measurement

No. 31 Example Malfunction during measurement

Type of device MOS LSI

Lesson learned The impedance of measurement systems must be appropriate.


During measurement, resistors were connected to the measurementsystem (see figure below) to prevent damage. This caused cross-talkbetween adjacent input and output pins, thus resulting in a defective inputvoltage margin. A single measurement system was shared for testingproducts with different pin layouts, with a resistor connected not only tothe output pin but also to the input pin during measurement.

RΩ

RΩ

Output

Input

Input/Output Crosstalk

LSIMeasurement System


Modify the system so that the appropriate resistor for protecting themeasurement system can be selected by a relay depending on the pinspecifications (input/output) to allow selecting the 0- resistor for inputand R- resistor for output.

Reference items

Rev. 1.0, 01/02, page 262 of 292

(2) Precautions for Board Mounting

Semiconductor devices are not used alone; they are mounted and used on various boards such asprinted-circuit boards, on which other devices are also mounted. Therefore, semiconductor devicesshare a power-supply line with other devices and are continuously subject to influence byextraneous signals used for the circuits located near the semiconductor devices. Specialconsideration is thus necessary regarding positioning of the signal lines that are likely to beaffected by subtle signal waveforms.

Example 32 Linear IC Oscillation

No. 32 Example Linear IC oscillation


Lesson learned Oscillation must be checked.


If a long line is connected to an input pin of a linear IC, equivalentinductive (L) load is generated on the input pin, causing oscillation. If asmall signal line runs parallel to a large-current output line, mutualinduction is generated, also causing oscillation of the output waveform.

OutputInput

Wiring is long ("L" load).

Ci CL

GND

ROscillates.

Example of 3-pin Regulator

Countermeasures/measure of checking

(1) Make input lines as short as possible to reduce inductive (L) load onthe input.

(2) If input lines are inevitably long, monitor the waveform on the inputpins while varying the capacitance of input capacitor Ci and outputcapacitive load CL.

(3) Separate large-current lines from small signal lines.(4) In a printed-circuit board, insert a GND pattern between the signal line

patterns.

Reference items

Rev. 1.0, 01/02, page 263 of 292

Example 33 Malfunction due to Design Changes of Terminal Equipment

No. 33 Example Malfunction due to design modification of terminal equipment

Type of device MOS LSI

Lesson learned LSIs must not be operated under high voltage.


After the design of CRT display equipment had been changed, a non-repeatable runaway failure occurred abruptly. It recovered from the failureafter temporarily being left turned off. By reviewing the changes, it wasfound that the cause was a shift in a threshold voltage due to a highelectric field (anode voltage was 20 kV).

HighVoltageCircuit

HighVoltageCircuit

CRT CRT

High Electric Field

LSI

Before Design Modification After Design Modification

LSI


(1) Modify the CRT connection manner to prevent high electric fieldapplication.

(2) Shield the LSI from electric charge.

Reference items

Rev. 1.0, 01/02, page 264 of 292

Example 34 Reset Malfunction due to Hazardous Noise

No. 34 Example Reset malfunction due to hazardous noise


Lesson learned Anti-noise measures must be taken for mechanical switches.


With set 1 connected to set 2, when the reset switch of the applicationcircuit was pressed, the application circuit was not reset, and insteadmalfunctioned. Specifically, the reset signal of set 2 fell so slowly thathazardous noise was generated in the reset-input circuit in set 1, thusdisabling correct reset function.

B

A

A

Set 1

Set 2CPU

Reset PinHazardous noise is

generated.B


Modify set 1 to prevent generation of hazardous noise.

Reference items

Rev. 1.0, 01/02, page 265 of 292

Example 35 Oscillation Circuit and Patterns on a Board

No. 35 Example Oscillation circuit and patterns on a board


Lesson learned Oscillation-start time must be constant.


An intermittent failure occurred in microcomputers. The failure-occurrenceratio depended on the product model despite the fact that the productswere assembled by the same manufacturer. By analyzing the oscillationwaveforms of the products presenting the high failure-occurrence ratio, itwas found that it sometimes took so long for oscillation to start that thereset signal was cancelled before oscillation became stabilized, thuscausing malfunction.

It was also found that the difference in the failure-occurrence ratiobetween product models was caused by the difference in oscillation circuitpatterns. That is, the products presenting the high malfunction ratio hadno shield for the input pattern of the oscillation pin, and a high-speedsignal line crossed the pattern. This signal line generated cross-talk, thuspreventing stable oscillation.

Countermeasures/measure checking

(1) Oscillation circuit patterns were modified to the standard patternsrecommended by the manufacturer.

(2) Eliminating distortion of oscillation waveforms was confirmed bymonitoring the waveforms.

(3) Adequate margin of stable oscillation was confirmed by insertingseries resistors into the input.

Reference items

Rev. 1.0, 01/02, page 266 of 292

(3) Precautions against Malfunction due to Noise

Accompanying the increased speed of semiconductor device operations, the devices now generatemore noise and have become more sensitive to noise that leads to malfunction. Extraneous noise,for example, was eliminated by conventional low-speed devices acting as noise filters, thuspreventing malfunction of the subsequent devices, whereas the same noise is amplified by recenthigh-speed devices, thus increasing the incidence of malfunction.

Currently, CMOS devices capable of high-speed operation while at exceptionally low power, havesignificantly higher signal impedance and higher noise sensitivity. Furthermore, as CMOS circuitsare inevitably accompanied by a large current changes synchronized with clock pulses on thepower supply line, the power supply line may generate a lot of noise. Specifically, sine-wavesignals generate relevant frequency noise only, whereas square-wave signals generate variousharmonics as noise.

Particular components of harmonic waves can be determined by performing Fourier analysis onthe square waves.

When the original oscillation frequency is f0 and a frequency that depends on the rise/fall gradientof wave forms is f1, harmonic noise spectrum is attenuated at a rate of –10 dB/decade within thefrequency domain between f0–f1 and –20 dB/decade above f1. If harmonic signal waveforms arefurther superposed on square waveforms, still more noise in the form of harmonics will begenerated.

Example 36 Malfunction due to Cross-Talk Noise from NC Pins

No. 36 Example Malfunction due to cross-talk noise from NC pins


Lesson learned NC pins adjacent to noise-sensitive pins must be appropriately handled.


During development conducting anti-noise test for the user system, thenoise level was unsatisfactory. Several anti-noise measures were triedand it was found that grounding the NC pin was effective. Specifically, itwas found that the open NC pin was near the high-frequency signalpattern on the printed-circuit board, and the resulting cross-talk noise wasinput to the adjacent pin through the stray capacitor, thus causingmalfunction.


(1) NC pins must be grounded with an appropriate value of impedance, orconnected to the power supply.

(2) NC pins must be handled carefully because they may serve asinternal test pins.

Reference items

Rev. 1.0, 01/02, page 267 of 292

Example 37 Noise Generation

No. 37 Example Noise generation (electrical)


Lesson learned The capacitance and layout of the bypass capacitor must be appropriate.The clock waveforms must be appropriately shaped.


Noise generated by digital circuits such as microcomputers may causemalfunction of peripheral devices. The noise depends on various factorssuch as the clock waveforms and power supply current waveforms of theLSI, and the positioning of the bypass capacitor and routing of both thepower and the GND lines on the printed-circuit board.

LSI generates only a small electric waveform by itself. Power supply-related electric waveforms can be eliminated using a bypass capacitoreffectively to suppress the power supply current loop, and clock-relatedelectric waveforms can be eliminated by shaping the rising and fallingwaveforms. In other words, monitoring the clock waveforms and powersupply waveforms of the LSI mounted on the board using a spectrumanalyzer provides the means of preventing noise generation.


(1) Shape the rising and falling waveforms of the clock (tr,tf) and reducethe speed to accelerate attenuation of the harmonic waveforms. Theharmonic waveforms will be attenuated at a rate of 10 dB/decadewithin the frequency range between the original oscillation frequencyand tr (ff) and at 20 dB/decade above this.

(2) Absorb harmonic spectrum component using the bypass capacitor.Selecting an appropriate capacitor that has excellent frequencycharacteristics and is capable of absorbing the power supply current isimportant, and appropriate positioning of the bypass capacitor, whichdetermines magnitude of the power supply loop, is also important.

Reference items

Rev. 1.0, 01/02, page 268 of 292

(4) Precautions on Signal Waveforms

Along with the speed-up of semiconductor device operations, noise and distorted waveforms,which did not cause problems previously, have become likely to affect basic LSI operations.However, it becomes increasingly difficult to test the stability of device operations. This isbecause not only finding the conditions that most affect the operations is extremely difficult butalso finding the combination of samples that adversely affects the operations most in an evaluationand testing phase is also very difficult.

The best approach to effectively find and solve these issues is analyzing waveforms in detail.Recently, advanced waveform monitors incorporating glitch-detection function are available, andabnormal waveforms that were previously difficult to find can be quickly found today. However,even when abnormal waveforms are found, it is often difficult to determine how much theabnormal waveforms can affect the LSI. In such cases, please direct inquiries to the technicalsupport department of our company.

Example 38 Malfunction due to Distorted Input Waveforms

No. 38 Example Malfunction due to distorted input waveforms


Lesson learned Distortion of signals must be monitored.


When operating an IC, distorted input waveforms near the thresholdvoltage of the input waveform may cause unstable IC operation leading tomalfunction.

A certain logic product exhibited a significant propagation delay of theinput waveform shown below.

Specifically, the input waveform was distorted near the threshold voltage,which changed the input level and disturbed multi-gate operation, thuscausing the delay.

Out

put V

olta

ge

Threshold Voltage

Input Voltage

Input Waveform

Output Waveform

Long Delay

A slight fluctuation in input causes a large fluctuation in output and proneness to instability.


Add a buffer gate and shape the waveform to eliminate distorted inputwaveforms.

Reference items

Rev. 1.0, 01/02, page 269 of 292

Example 39 DRAM Malfunction due to Noise in Address Signals

No. 39 Example DRAM malfunction due to noise in address signals

Type of device DRAM

Lesson learned Signal waveform of DRAM must be appropriate.


DRAM internal circuits are designed to be triggered when the voltagelevel of the address signals becomes stable. If a large noise above thespecifications is applied to these signals, access time starts at the time ofnoise generation, thus causing malfunction. Particularly, special care forthe waveforms of these signals must be taken because they changedepending on the retained data pattern, and the word line selectedimmediately before.


(1) Find a large noise in the waveforms of various signals using the glitch-detection function and determine the worst pattern based on thedetected pattern.

(2) Shape the waveform by improving the impedance matching with thedriver, power-supply patterns, positioning of bypass capacitors.

Reference items

In some cases, the operational margin for a circuit can be confirmed by analyzing signalwaveforms in detail. For analog circuits such as oscillation circuits and PLL circuits in particular,waveform monitoring is one of the most effective means. If the phase difference between inputand output signals, amplitude, distortion, noise level, and other factors are strictly measured andthe waveforms are shaped to what it should be, malfunction frequency can be reduced and thewaveform characteristics can be improved greatly.

Rev. 1.0, 01/02, page 270 of 292

Example 40 Evaluation of Oscillation Circuit Stability

No. 40 Example Evaluation of oscillation circuit stability


Lesson learned Stability of oscillation circuits must be carefully confirmed.


Oscillation circuits are very difficult to handle and often cause intermittentfailures. This is particularly because they depend on the compatibilitybetween the LSI and the oscillator, the pattern routing on the printed-circuit board, and the combination of external capacitors, resistors, andother elements. Therefore, the stability of oscillation circuits must becarefully confirmed regarding temperature, power supply rising waveform,oscillation stabilization time, phase difference between input and output,and input /output waveforms.


(1) Confirm the temperature characteristics of the oscillation circuitbecause the circuit gain may vary depending on the temperature.

(2) Test the oscillation waveform while varying the power supply risingwaveform and confirm that the waveform is perfect and thatextraordinarily slow rise of the power-supply waveform does not affectthe oscillation waveform.

(3) Create the distribution of oscillation stabilization time and infer theprobability that oscillation will be stabilized after reset cancellation.

(4) Find the limit regarding the stability of oscillation start by insertingseries resistances into the feedback circuit.

(5) Keep in mind that distorted input/output waveforms cause nooscillation.

(6) Keep in mind that the phase difference between input and outputreflects oscillation stability.

Reference items

Rev. 1.0, 01/02, page 271 of 292

(5) Precautions with Regard to the Environmental Conditions in which the Device is Used

There is a hidden danger lurking in the event of unexpected malfunction. If enough considerationof the actual environmental conditions in which the device will be used in practice is not made,trouble can occur as a result of differing perceptions between the party that supplies the device andthe party that uses it. Normally it is difficult to detect this type of problem in advance. Inparticular, since this kind of problem is difficult to classify, only a general discussion that appliesto various cases will be given here.

The example of light illumination, even though it is considered very natural, is an example offailures that sometimes occur because of changes in package thickness and the varying abundanceof chip supply. The example of natural rubber is an example that is used carelessly as a material todampen oscillations in high impedance circuit configurations that carry a small volume of signals.We have also introduced the example of major failure that occurs when a system is started upwithout specifying the requirements of the device regarding the each timing of power ON,oscillations start and the start of operation after a reset signal.

Example 41 Decrease of the Operation Margin by Light Illumination

No. 41 Example Decrease of the operation margin by light illumination


Lesson learned For an application in which strong light is to be used, measure under theactual conditions of use.


When strong light is applied on a semiconductor, photoelectrons areproduced. If it is possible that strong light will be incident on the LSIduring use, exercise caution. Caution is particularly necessary when thepackage is thin and/or chips are purchased and assembled.


(1) When the electric characteristics of a bare chip are measured, shut offthe incoming light.

(2) For an application in which strong light is to be applied to a packagedproduct, measure the electric characteristics while applying light.

Reference items

Rev. 1.0, 01/02, page 272 of 292

Example 42 Leakage Defect Caused by Sulphide Gas Emitted by Natural Rubber

No. 42 Example Leakage defect caused by sulphide gas emitted by natural rubber


Lesson learned A substance of which sulphur is the main constituent, such as rubber,should not be in close proximity to the IC.


Malfunction of unknown origin occurred in the market; as the result of aninvestigation it was judged that a sulphide substance had crystallizedbetween LSI pins, amplifying the leakage current and causingmalfunction.

The result of the investigation further revealed that there was a buffercomponent made of a substance that had sulphur as its main constituent,such as rubber, in close proximity to the LSI; sulphide gas emitted fromthat substance crystallized in high humidity, causing the foreign chemicalsubstance to be formed between the LSI leads. In an experimentconducted to reproduce the phenomenon in a high temperature, highhumidity tank, it could not be reproduced, but when an identical rubbercomponent was inserted into a desiccator and a test was conducted athigh temperature and high humidity, it was reproduced. (This defect doesnot occur in a well ventilated location.)


Do not place or mount any substance having sulphur as its principalconstituent, such as rubber, in close proximity to an IC.

Reference items

Example 43 Malfunction Caused by Surge Current when Power is Turned ON

No. 43 Example Malfunction caused by surge current when power is turned ON


Lesson learned Is the power supply current OK between the time the power is turned ONand the start of oscillations?


After power is turned ON, until clock input, there was an indeterminatesection in the internal logic, and a current exceeding the current ratingflowed in the power supply. Part of the users system had internal circuitsto detect excess current flow; this current caused the device tomalfunction.


In an application in which it is necessary to detect excess current, thepeak power supply current, as well as the average power supply current,should be specified.

Reference items

Rev. 1.0, 01/02, page 273 of 292

6.5.2 Precautions Relating to Software

The number of products in which microprocessors are used has increased considerably in recentyears. In most cases it has become possible for the user to customize the functions with software;this is very convenient, but is also a source of problems. If a problem occurs infrequently in thefinal product and is difficult to reproduce, it can be extremely difficult to determine whether theproblem is in the LSI or in the user's program.

Typical examples include malfunctions that sometimes occur and sometimes do not depending onthe internal RAM pattern at power on, which was created by the user. This problem was extremelydifficult to track down.

There are a number of difficulties involved here from the point of maintaining security, but itappears that we are entering an age in which such functions as Error Logging and the Load and Gofor small scale programs in the RAM area should be created by hardware and software.

Example 44 Program Malfunction in Referring to an Indeterminate RAM Area

No. 44 Example Program malfunction in referring to an indeterminate RAM area


Lesson learned Contents of indeterminate RAM must not be used in a program.


In a user’s test production run in preparation for mass production, smallpercentage of operation defects occurred when power was turned ON.When only a short time elapsed between turning power OFF and turning itON again, reproducibility was very poor. When the smoothing capacitorwas shorted and completely discharged after power was turned OFF, thedefect became easy to reproduce.

As a result of analyzing the user’s program, it was found that uninitializedRAM content at a certain address was used as a branch in the program; itwas judged that sometimes when power was turned ON this RAM datawas inverted, causing the malfunction.


(1) RAM contents that are not initialized must not be used as a branchstatement.

(2) When developing a program, check operation after the RAM contentis initialized to set or reset state.

Reference items

Rev. 1.0, 01/02, page 274 of 292

6.6 Being Prepared for Possible Malfunction

In order to achieve zero defects in LSI production, strenuous efforts have continued day and night,but unfortunately this goal has not yet been achieved. Under conditions in which it is not possibleto obtain 100 % good products with the consideration of yield, the failure to achieve a 100 %testing rate means that the final product cannot be made fail-safe with respect to the possibility ofmalfunction of the semiconductor components. Such product as a relay that has certaincharacteristics as to how it behaves when it is destroyed. When the natural phenomenon of gravitycould be utilized, that characteristic could be used in system design, but unfortunately thecharacteristics of semiconductor failure are not that simple. Types of failures include broken orshorted wires, and open low stack or high stack. This fact can be used to judge that the output of ahigh or low signal level (not a fixed level) is evidence of normal operation. In addition, by usingthis type of judgment together with the watchdog function, much higher fail-safe operation can beobtained than with a relay circuit. The end user should make the necessary adustments in hissystem.

Example 45 Characteristics of Functional Defects when a Semiconductor Device isDestroyed

No. 45 Example Characteristics of functional defects when a semiconductor device isdestroyed

Type of device All semiconductor devices

Lesson learned In many cases, when a semiconductor is destroyed the output is eitherfixed or indeterminate.


We are making great efforts to achieve zero defects in semiconductorproduction, but at present we have not achieved this goal. Consequently,the system must be designed with a view of maintaining safety if asemiconductor device is destroyed.

In previous relay circuits, gravity was utilized to determine the side towhich the relay would fall in the worst case. Unfortunately, asemiconductor fault can consist of either an open or shorted circuit; thelevel itself cannot be designed for fail-safe operation. However, importantsignals can be converted to AC; using the fact that a signal at DC levelindicates that trouble has occurred, it is possible that even better fail-safeoperation can be obtained than with previous relay circuits. Using thischaracteristic together with the watchdog function provides even betterdetection of problems.


(1) The status of the system should be checked by setting importantsignals to high, short, low short or open.

(2) Also check operation when the power is shut OFF.

Reference items

Rev. 1.0, 01/02, page 275 of 292

Example 46 Watchdog and Fail Safe

No. 46 Example Watchdog and fail safe


Lesson learned Is the division of labor between hardware and software in the watchdogfunction OK?


The watchdog function is effective in maintaining the safety of a system.The watchdog function uses both hardware and software to reverse theoutput at certain pins at regular intervals; if an interval deviates from thedesign value, the problem can be detected from a separate monitoringcircuit and the system adjusted in the direction of safety to prevent theworst from happening.

It is important that the reversal of output at regular intervals not beachieved with hardware alone. If this were done, it would no longer bepossible to verify that software operation is normal.


(1) Let the program run away to test the system protective functions.(2) Degenerate the hardware signal to test the system protective

functions.

Reference items

With the development of digital processing technology including microprocessors, it has becomepossible to let this technology perform very sophisticated judgments. At the same time, thenumber of cases of completely unexpected types of malfunction has been increasing. Between thehardware manufacturer and the user who develops software, great difficulties occur whenmalfunction is intermittent. In systems in which a high degree of reliability is required, it must beconsidered that not only in cases of frequent occurrence of a fault but also in case of a fault thatoccurs infrequently and might be difficult to reproduce it in a test, an error logging function shouldbe built into the system. In the case of a microprocessor with a stored program, variable electroniccomponents such as the register and memory are where the flow of the program can be changed. Afunction should be included in the system so that when abnormal operation is detected, the datafrom these important parts will be stored and can be investigated later. This will greatly contributeto finding leads that can be followed up to solve the problem. If possible, if, in addition, there isalso a Data Load and Go function to access the RAM area, greater analysis power will beobtained.

Rev. 1.0, 01/02, page 276 of 292

Example 47 Microprocessor Intermittent Failure Analysis

No. 47 Example Analysis of intermittent failures in microprocessors


Lesson learned In analysis of intermittent defects, search for the cause starting fromdifferences in the contents of RAM and registers during normal anderroneous operation.


In a product that used a microprocessor, the program ran awayintermittently, but the cause could not be determined and efforts to solvethe problem dragged out for a long time. Since the device was being usedin single chip mode, the movement of the address line and data lineduring malfunction could not be determined; it was not possible todetermine the cause of the microprocessor running wild from only data atoutput pins.


If it is confirmed that a problem has occurred but the defect is anintermittent one that occurs very infrequently, information regarding theproblem will always remain in variable data areas. These data can also beused effectively as the information indicating that the logic of some partsoperated correctly by elimination method.

In applications that require high reliability, consideration should be givento incorporating an error logging function from the beginning ofdevelopment, and the system designed so that the cause of malfunctioncan be determined logically and appropriate action taken.

Reference items

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6.7 Failure-Detection Ratio during Test

As LSIs become faster and more complex, it becomes increasingly difficult to test theperformance of the LSI. Generally, as far as memory devices are concerned, 100% of failures canbe easily detected during test. However, it is difficult to prepare a perfect test pattern and testconditions that accurately simulate all on-board memory device operations. The difficulty arisesfrom the fact that the test pattern and test conditions depend on various factors such as input signalwaveform, timing, data patterns, and address patterns.

Typical memory test patterns are as follows:

1. All-1 or all-0 pattern

2. Checker or checker-bar pattern

3. Diagonal pattern

4. Address-decode pattern

5. Data retention test pattern

6. Marching pattern

7. Long-cycle test pattern

8. Walking pattern

9. Galloping pattern

10. Ping-pong pattern

Typical points to note are as follows:

1. Influence of adjacent bits

2. Interference between data lines

3. Interference between word lines

4. Output noise

5. Sense-amplifier switching timing and timing of input signals

6. Stability of potentials of internal signal lines

7. Switching timings of the ATD circuit and other signals

8. Input-noise sensitivity

9. Input-signal undershoot

Unlike memory devices, it is virtually impossible to test all the internal signals of microcomputerICs and application-specific digital-signal processor logic ICs because of their complex logic. Inparticular, since memory circuits have pattern dependency as described above, and devices such asmicrocomputers are combinations of large-scale logic circuits, it is impossible to eliminatemanufacture-related failures effectively unless systematic measures for achieving satisfyingdetection ratios are taken as early as in the phase of testing circuit design. When the logic is highly

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complex, the device logic must be configured such that it allows the internal RAM to be externallyand directly tested in the test mode.

Example 48 Testing Design of Devices with Internal RAM

No. 48 Example Testing design of devices with internal RAM

Type of device ASIC

Lesson learned RAM and registers must be able to be tested independently.


Malfunction occurred frequently in an ASIC/LSI with incorporated memoryelements such as RAM due to an unknown cause. It was difficult toeliminate failures using the test program.

By failure analysis, it was found that the malfunction was caused by aninternal RAM failure dependent on the data pattern. However, the RAMmodule was difficult to test because the relevant ASIC/LSI allowed theinternal RAM to be accessed only through logic paths. Although specificmeasures were taken by adding patterns against each failure, effectiveRAM testing was impossible and thus data-dependent manufacture-related failures could not be eliminated completely using the test program.Therefore, an on-board RAM test had to be implemented.


(1) Internal RAM circuits must be externally and directly accessed.(2) Failures of the devices with the internal RAM that can only be

externally accessed must be eliminated during an on-board test.

Reference items

Dielectric breakdown is one of the inevitable failure modes of MOS devices. This failure moderequires burn-in, that is, a highly costly screening method, to obtain high-quality products. As a100% failure-detection ratio can be easily achieved for memory devices, the burn-in saturation isdirectly connected to the expectant product quality on the market. However, logic ICs, for which a100% failure-detection ratio cannot be achieved due to the mechanisms involved and for economicreasons, are shipped with some logic circuits remaining to be burnt in because of the low detectionratio obtained by the burn-in pattern. In order to systematically eliminate from the market thefailures that were not detected by the test pattern, product quality must be controlled whileidentifying and relating such conditions statistically and rationally.

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Example 49 Burn-in Saturation and Detection Ratio

No. 49 Example Burn-in saturation and detection ratio


Lesson learned The appropriate burn-in pattern must be used.


Appropriate burn-in creates has a positive affect on device life time. In theWeibull distribution approximation, the virtual shape parameter mapproaches 1 with the increasing numbers of burn-ins. If the user shouldencounter any initial failure with exceptionally small m, the likely causesare as follows:

(1) The manufacturer did not perform burn-in.(2) The sections that were not subject to burn-in operation by the

manufacturer caused the failures.(3) Some novel causes of initial failures has been generated (causing

breakdown).


(1) Analyze failures and see whether or not the failed sections can bedetected by the test program.

(2) Analyze failures and see whether or not the failed sections can beoperated by the burn-in pattern.

Reference items

If the scale of logic complexity increases further despite the limited failure-detection ratio bytesting, the number of untested lines would also increase. As the undetected failure ratio isproportional to the number of untested lines, it seems that only unacceptably low quality productswill be manufactured in the near future. However, this is not the case. Specifically, if the yield inproduction processes is maintained at the appropriate level, the current undetected failure ratio canbe retained even if the logic scale increases. If the yield cannot be maintained at the appropriatelevel and defect-repairing circuits or equivalents are used to temporarily improve the yield, theuntested failure ratio will be so high that it can no longer be ignored. In short, improving the yieldis very effective in maintaining product quality.

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Example 50 Logic Scale and Undetected Failures

No. 50 Example Logic scale and undetected failures

Type of device ASIC

Lesson learned The failure ratio in the untested sections by the test program must beestimated.


It is anticipated that the increasing logic scale will lead to an increasedfailure ratio in the untested sections because the failure ratio in theuntested sections by the test program is simply proportional to thenumber of untested patterns. However, the failure ratio in the untestedsections will be the same in spite of the increasing logic scale if the yield-related production quality (quality of conformance) and the test-detection-ratio-related design quality (design quality) are maintained at the currentlevel. This is because the defect density itself decreases in spite of theincreasing logic scale as long as the yield is maintained at the same level.

It must be noted that this is true only when defects are random, and doesnot hold for system defects such as specific layout, circuit function, andperformance faults, which are not tested.


(1) Estimate the failure ratio in the untested sections based on therandom-defect ratio.

(2) Improve the production process to eliminate system defects.

Reference items

The yield usually does not correspond well to the undetected failure ratio. This may be becausemany multiple defects are contained in yield-defective products. As multiple defects exhibitmultiple failures simultaneously, the detection ratio will be exceptionally high, thus allowing theproducts to be screened out. Although defects cannot be completely eliminated, the undetectedfailure ratio can be controlled by effectively selecting single defects from yield-defective productsand exclusively controlling these single defects.

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Example 51 Single Defects, Multiple Defects, and Undetected Failures

No. 51 Example Single defects, multiple defects, and undetected failures

Type of device ASIC

Lesson learned Single defects must be separated from multiple defects.


It is anticipated that the increasing logic scale would lead to the increasedfailure ratio in the undetected sections. If the same ratio of single defectsand multiple defects are detected by the same test program, different areratios of defects missed by the test. It must be noted that almost allundetected failures are from single-defect products when the detectionratio is high.


(1) Single-defect ratio directly reflects the undetected failure ratio.(2) Single-defect ratio corresponds well to the burn-in failure ratio.

Reference items

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6.8 Other Examples

General precautions in storage and transport of electronic components can be applied directly tosemiconductor devices, but there are additional points that require caution. An explanation ofsome relevant general items is given below.

6.8.1 Precautions in Packaging

Recent semiconductor devices are of high quality and high reliability, but depending on suchfactors as handling by the user, mounting and the conditions of use, there are many factors that canlead to destruction of the device (destruction by static electricity, mechanical destruction, moistgas, etc.). First, let us discuss precautions with regard to possible destruction of devices in thestorage case and during packaging.

(1) The Storage Case

(a) Semiconductor manufacturers use storage cases (tray, magazine or tape and reel) of materialsand construction that will maintain the initial quality even under the worst environmentalconditions, so as far as possible use the storage case specified by the manufacturer.

(b) If the storage case specified by the manufacturer cannot be used, use a storage case thatsatisfies the following conditions.

• The material will not trigger a chemical reaction or emit a harmful gas.

• The construction protects the device from destruction by vibrations and shocks.

• The case material that leads of the device will contact is either electrically conducting ordoes not hold an electric charge (the surface is treated with an electrical charge preventionmaterial).

(c) When removing a device that is vulnerable to destruction by static electricity, such as a highfrequency device or an MOS device, from its storage case, discharge any electrical charge onthe body and clothing through a high resistor (about 1 M), then remove it from the storagecase using an electrically conducting finger nipple or glove.

(2) Packaging

A semiconductor device in a storage case must be further packaged to protect it from outsideeffects such as a shock, rain water and soiling. The packages used for some common products areshown in fig. 6.24.

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Carton Tape (blue)

PP BandsExterior Cardboard

Carton

Inner Box

Label Magazine

Cardboard Paper Cardboard Cardboard Tape

Stopper

Magazine orTray, Tape

ProductProduct

Magazine Product

Tray

Reel Tape

1

2

3

Figure 6.24 Example of Packaging

Opening the exterior cardboard carton reveals an inner box or boxes, inside of which is the storagecase (magazine, tray or tape and reel), inside which reside the ICs. In the case of plastic surface-mount packages which have large chips, there is also Moisture-proof packaging to preventmoisture absorption. Next, we give some precautions in packaging.

(a) To keep the shock, vibrations and moisture to which the semiconductor device is subjected to aminimum, it is necessary to give serious consideration to using packaging that has sufficientmechanical strength, ability to withstand vibrations and ability to block moisture to meet therequirements of the transport method to be used. In general, the storage case is securelywrapped in polyurethane foam or vinyl, which in turn is put into a cardboard carton withsufficient packaging material to prevent vibrations, then the carton is closed with gummedtape. Depending on the transport conditions, more secure packaging may become necessary.

(b) The outside of the cardboard carton should be labeled to indicate that the contents are fragile,must not be allowed to become wet and which direction is up.

Right side UP Fragile Do not permit to become wet

Figure 6.25 Examples of Exterior Labeling

(c) If poor environmental conditions are anticipated, as in transport by sea, it is necessary to usevacuum packaging and sealed packaging.

Rev. 1.0, 01/02, page 284 of 292

(d) The surfaces of transparent plastic magazines are treated to prevent them from becomingelectrically charged, but this surface treatment wears off over time, so these magazines shouldnot be used for storage for more than six months. Never reuse the magazines.

6.8.2 Storage of Semiconductor Devices

When storing semiconductor devices, it is necessary to protect them from environmental dangersincluding temperature, humidity, ultraviolet radiation, poisonous or contaminating gases such ashydrogen sulphide, radiation including X-rays, static electricity and strong electromagnetic fields.

(1) Environment of the Storage Location

(a) Ambient temperature and humidity

It is desirable for a location in which semiconductor devices are stored to be kept at so-callednormal temperature and humidity; Care must be taken to avoid storage under temperature andhumidity conditions that are significantly different from these. Normal temperature andhumidity means 25 to 35C and 45% to 75% RH (some products have special restrictions onstorage conditions, which should be observed). When it is very dry, such as during winter, it isnecessary to use a humidifier. If tap water is used in the humidifier the chlorine in it cancorrode leads of devices, so purified or distilled water should be used.

(b) A clean location

Avoid storage in a location with corrosive gas or a large amount of dust.

(c) A place where temperature variations are small

Sudden temperature variations can cause dew to form on devices, so avoid such anenvironment, and store devices in a location where temperature variations are small (and awayfrom direct sunlight or other strong light).

(d) Miscellaneous

Store devices in a location free of radiation, static electricity and strong electromagnetic fields.

(2) Storage Conditions

(a) In storing semiconductor devices, it is necessary to make sure that they are not subjected toheavy loads. In particular, when boxes are stacked, it is possible to subject the semiconductorsto excessive loads without realizing it. Of course it is also necessary to avoid placing heavyobjects on top of them.

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Excessive Weight on Top ×

Unstable ×

Direct Sunlight ×

Flame ×Chemicals ×

High Humidity×

Figure 6.26 Examples of Poor Storage Locations and Practices

(b) Store semiconductor devices without processing their external leads. This is to avoid degradingthe adherence of solder during mounting due, for example, to rust.

Example of Lead Processed by Bending

Unprocessed Lead

Figure 6.27 Storage Condition

(c) Place semiconductor devices only in containers that do not readily become electrostatic-charged.

(3) Long-term Storage

If a semiconductor device is stored for a long time (1 year or more), there is danger that the leadterminals can become difficult to solder, perhaps even rust, and/or can suffer deterioration ofelectrical characteristics. In particular, the following precautions are necessary.

(a) Storage environment: See (1) above.

(b) If long-term (1 year or more) storage is envisioned from the start, take such precautions asusing vacuum packaging or a sealed container into which silica gel is inserted.

(c) If a semiconductor device is stored under ordinary storage conditions and for a long time (1 to8 years) has elapsed, before using the device it is necessary to determine if it can still be easilysoldered and if it has rusted.

(d) Storage in a poor environment, or long-term storage under ordinary storage conditions

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If a semiconductor device is stored in a very poor environment, or is stored under ordinarystorage conditions and 1 year or more has elapsed, it is necessary to determine whether it canstill be easily soldered, if it has rusted, and if there has been any change in its electricalcharacteristics (for surface-mount packages, see section 6.4.2). Use TAB products within 3months.

(4) Storage of Chips and Wafers

Semiconductor chips and wafers must be stored under more strictly controlled conditions thanpackage products. Absolutely avoid storing chips and wafers in conditions in which they areexposed to the outside air.

(a) Storage of chips and wafers

Store chips and wafers in the designated types of containers, and do not open and close thecontainers any more than necessary. Normally, chip storage containers are sealed to protectchips and wafers from temperature, humidity and corrosive gases, and from vibrations andshock during transport.

(b) Do not store chips and wafers in opened containers. This is to prevent the chips and wafersfrom being oxidized or corroded due to changes in temperature and humidity, and the presenceof gases, dust and chemicals.

(c) Store chips and wafers in an atmosphere at 5 to 30ºC and 45% to 75% RH, where they will notbe affected by chemicals or volatile substances.

(d) When putting a chip into or taking it out of a storage container, handle it gently using vacuumtweezers or a vacuum collet so that the surface will not be scratched.

(e) The chip should be mounted within 5 days after the sealed storage container is opened. Whenwork is not being performed, as at night, the component should be stored in a dried nitrogenatmosphere. If the sealed storage container has been opened, the component should be storedin dried nitrogen (at or below –30ºC (dew point)) for not more than 20 days; if the storagecontainer is still sealed, it should be stored for not longer than three months.

Chip Tray

Vinyl Bag (sealed)

Nitrogen

Enlarged View of Chip Tray

1 chip in each compartment

Figure 6.28 Examples of Chip Storage Containers

Rev. 1.0, 01/02, page 287 of 292

Example 52 Solderability Defects that can Develop during Storage

No. 52 Example Solderability defects that can develop during storage

Type of device IC

Outline of example Magazines made of cardboard paper and black rubber were used for ICstorage, causing the device lead wires to become discolored and leadingto solderability defects. The lead surface material was converted tosulphide by sulphur compounds contained in the storage magazines.

Countermeasure Storage cases and magazines made of material that does not react withthe lead wires were used. In particular, sulphur compounds must beavoided.

6.8.3 Precautions in Transport

In transport of semiconductor devices and of units and subsystems which incorporatesemiconductor devices, the same precautions must be observed that are necessary for otherelectronic components; in addition, the points listed below must be considered.

(1) Handle the cardboard cartons used as the exterior packaging carefully. In particular, be carefulnot to subject them to shocks or drop them as this can damage the products inside.

(2) Be particularly careful in handling the interior boxes.

If these are dropped, stoppers can fall out of the magazines inside allowing the products to fallout and causing the leads to become deformed. Ceramic packages can be damaged, causingleakage defects.

(3) It is necessary to make sure that the products do not become wet. Be particularly careful whentransporting them through rain and/or snow (Do not permit to become a wet).

(4) Transport containers and jigs must not be easily charged and not generate electrostatic chargewhen subjected to vibrations. One effective measure is to use conducting containers oraluminum foil.

(5) To prevent components from being destroyed by electrostatic charge on the body and/orclothing, ground the body through a high resistor to discharge static electricity when handlingsemiconductor devices. The resistance should be about 1 M. It is necessary for the resistor tobe inserted into the connection between body and ground at a position relatively close to thebody to prevent danger of electrical shock.

(6) In transporting a printed circuit board with semiconductor devices mounted on it, it isnecessary to take a measure, such as shorting the lead terminals to keep them at the samepotential, to prevent them from becoming charged with static electricity. If a printed circuitboard is transported on a belt conveyor, take an appropriate measure to prevent electricalcharging by the belt rubber.

(7) When transporting a semiconductor device or printed circuit board, keep mechanical vibrationsand shocks to an absolute minimum.

Rev. 1.0, 01/02, page 288 of 292

6.8.4 Product Safety

(1) Efforts to Ensure Product Safety

Since July 1995 the Product Liability (PL) Law has been in effect in Japan, but even before thatour company considered safety an integral element of product quality and has promoted safety ofsemiconductor products as part of our efforts to improve them.

Our company’s basic philosophy on product safety and efforts to improve it are as follows.

The product safety that our company guarantees is the normal level of safety required of thesemiconductor products themselves; the user must assume full responsibility for meeting safetyrequirements connected with the way these products are used and the environment in which theyare used.

(a) Product safety measures from the beginning

In the flow of, for example, the Reliability program examples and quality certification flowrequirements for product safety are specified; safety considerations form an integral part of thedecision to use a product, development and design. The principal safety measures that aretaken in the major steps from product development through shipment are listed in table 6.11.

Table 6.11 Principal Product Safety Measures

Principal Categories Considerations (main points)

Product Development On the way the user uses the product

Determination of Specifications On the environment in which the product is used

Design On destruction mode

On malfunction mode

Manufacture Observance and clarification of manufacturing rules

Quality Assurance Quality assurance and evaluation checks at each stage ofproduction

Sales Thorough emphasis on safety in documents that are issued

(b) Documentation

In order for semiconductor products to be used safely, there are a number of documentsincluding data sheets that indicate the documented performance available. We also issues anumber of documents specifically related to product safety so that the maximum utilization canbe taken of the product specifications.

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Table 6.12 Documents Concerning Product Safety

Category Examples of Specific Documents

Documents that give product specifications Data sheets, Data books, Technical information,Delivery specifications (Purchase specifications),etc.

Documents that give precautions in use Reliability handbooks, Package manuals, etc.

Other documents (documents prepared forindividual users)

Sale agreements, Quality agreements, etc.

(c) Consultations on specifications and quality

Quality consultations are held to assist the user in using the products under conditions that areappropriate for the product specifications. As stated above, these conditions are promulgated ina variety of documents, but discussion are held in order to give more detailed conditions foruse and help the user to select the most suitable product for each application.

6.8.5 Examples of Other Categories of Problems

Finally, we introduce several examples that do not fit into any of the categories that have beenpresented thus far.

Example 53 Tape Peeling Off at High Speed in the Case of Tape and Reel Products

No. 53 Example Tape peeling off at high speed in the case of tape and reel products

Type of device Embossed taping products

Note The strength of embossed tape to being peeled off should be measuredat the actual speed to be used.


Even though no problem occurred in the embossed taping certificationtest, the tape frequently peeled off during the users mounting operations.An investigation revealed that, in the line in which the defect occurred, themost recent model of high speed mounting machine was being used, andthe tape peel-off speed was increased to * times the previous value inorder to increase the component mounting index. In a test in which thetape peel-off speed was increased, the defect was reproduced.


(1) In the embossed tape peel-off test, attention must be paid to the peel-off speed.

(2) In the embossed tape peel-off test, one must not forget to apply thestress of storage as preprocessing.

Reference item

Rev. 1.0, 01/02, page 290 of 292

Example 54 Changes in Characteristics Caused by X-ray Irradiation

No. 54 Example Changes in characteristics caused by X-ray irradiation

Type of device MOS IC (plastic sealed)

Outline of example In an X-ray penetration test, the device was irradiated with X-rays for along time, and the IC came to have defective characteristics. The IC’sMOS parameter (Vth) fluctuated, causing deterioration of characteristics.

Countermeasure The X-rays with which the device is irradiated should be kept as weak aspossible.

Example 55 Lifetime Curve Using Cp and Cpk

No. 55 Example Lifetime curve using Cp and Cpk

Type of device All semiconductors

Note The Cp and Cpk defect rate is given and used effectively in predicting thelifetime.


Cp and Cpk provide an effective means not only for PQC but also fortesting the product lifetime. When Cp and Cpk are used, it is possible todetermine the defective rate of products which do not meet the standardsat that time. That is interpreted as the defect rate at that time. If a Weibullplot of the defect rate is prepared together with the time duration of thelifetime test, then the shape parameter m and the scale parameter canbe determined even if the occurrence of defects is zero. If data are takenunder the diversified conditions, then it is even possible to find theacceleration coefficient. Always select items to measure that arecorrelated with the failure mode.


(1) Cp and Cpk indicate the defect rate.(2) Do not forget that the ability to approximate the distribution by a

normal distribution is the starting point for using Cp and Cpk.

Reference item

Rev. 1.0, 01/02, page 291 of 292

Example 56 Cp, Cpk and Screening

No. 56 Example Cp, Cpk and screening

Type of device All semiconductors

Note Cp and Cpk provide a means of assuring quality without having to testevery single device.


The concept of Cp and Cpk is convenient, but caution is particularlynecessary when making a judgment on an item on which screening hasbeen performed. Trying to predict the defect rate from data after everysingle device has been tested and defective devices removed ismeaningless.

If defective devices are removed, the devices that were removed containimportant elements. Between the values that are announced outside thecompany and the values used in the selection testing, the followingindeterminate factors are included.

(1) Measurement tolerances(2) Temperature corrections(3) Deterioration of reliability


When screening is performed, look carefully into the margin between theexternal standards applied outside the company and the selectionstandards.

Reference item

Example 57 Bonding Stress in Mounting Chips that Have Been Shipped

No. 57 Example Bonding stress in mounting chips that have been shipped

Type of device Power MOS FET

Note The oxide film below the bonding pad is destroyed by the stress ofbonding.


When the characteristics of chips that had been shipped (power MOSFETs) were tested after mounting by the user, defective dielectricconstants were found between source and gate. As a result of analysis, itwas judged that the oxide film below the gate bonding was cracked,causing the dielectric constant to deteriorate. The cause was inadequatechecking of the conditions at the time of mounting.


After the bonding conditions are set, the characteristics need to bechecked, and, at the same time, the aluminum film below the bondingshould be removed and the silicon oxide should be checked for cracking.

Reference item

Rev. 1.0, 01/02, page 292 of 292

Example 58 Leakage from Airtight Seal due to Electrolytic Corrosion

No. 58 Example Leakage from airtight seal due to electrolytic corrosion

Type of device Glass diode

Note A voltage must not be applied to a product to which moisture is adhering.


Cuprous oxide (Cu2O) that forms on the surface of the copper layer of aDumet line diffuses into the glass, bonding to form an airtightconstruction. While a reverse bias is applied, water that adheres to thediode surface is decomposed electrolytically by reverse bias, andhydrogen (H2) is generated on the anode side.

This hydrogen reduces the cuprous oxide; water penetrates where thereduction took place, producing a cavity and destroying the air tightness.Destruction of the air tightness in turn permits more moisture to penetrateinto the cavity. Moisture penetration produces a leakage current on thesurface of the pellet, increasing the reverse current (IR). If the reversebias continues to be applied while the reverse current is flowing, migrationof the silver (Ag) pellet electrode occurs.


The IR becomes large due to fluctuations in the electrical characteristics.View the inside from the glass package.

Reference item Hitachi Diode Data Book

Example 59 Signal Data Collision

No. 59 Example Signal Data collision


Outline of example For memory ICs having common input/output terminals, when data is atoutput state and an input signal with the opposite direction is applied, datacollision will occur and generate excessive current flow. The resultingsupply voltage variation may cause malfunction or device destruction.

Countermeasures (1) Timing Design should be made to prevent data collision.(2) Timing should be changed using latch.

Reliability Handbook

Publication Date: 1st Edition, January 2002Published by: Business Planning Division

Semiconductor & Integrated CircuitsHitachi, Ltd.

Edited by: Technical Documentation GroupHitachi Kodaira Semiconductor Co., Ltd.

Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.