reliability of la-silicate mos capacitors with tungsten ... presen.pdf · reliability of...
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Reliability of La-silicate MOS capacitors with tungsten carbide gate electrode
1
S. Hosoda1, K. Tuokedaerhan1, K. Kakushima2, Y. Kataoka2, A. Nishiyama2, H Wakabayashi2, N. Sugii2, K. Tsutsui2,
K. Natori1, T. Hattori1, H. Iwai1
1Frontier Research Center, Tokyo Institute of Technology2Interdisciplinary Graduate School of Science and Engineering
224th ECS Meeting
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Introduction of high-k gate dielectrics
1
0.8
0.6
0.4
0.2
EOT
[nm
]
2025202020152010Year
EOT: equivalentoxide thickness
BulkMG
FD SOIEOT=0.5nm
ITRS2011
1
0.8
0.6
0.4
0.2
EOT
[nm
]
2025202020152010Year
EOT: equivalentoxide thickness
BulkMG
FD SOIEOT=0.5nm
ITRS2011
EOT below 0.5 nm is required in near future
2
S DIL(SiO2)
Metal gatePoly-Si
substrate
High-k
High-k/Si indirect contact
S D
Metal gatePoly-Si
substrate
High-k
High-k/Si direct contact
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Reports on high-k/Si direct contact
3
K. Choi, et al., VLSI Symp. Tech. p.138 (2009).J. Huang, et al., VLSI Symp. Tech. p.34 (2009).
negativeshift
IL scavenging
Si sub.
HfO2
metalO
SiO2
O O
direct high-k/Si
Vo control
Si sub.
HfO2
metalO
O
Odirect high-k/Si
EOT=0.59nm EOT=0.55nm
High-k/Si direct contact can be obtained by control of oxygen atoms in the gate stack
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La2O3 + nSi + mO2→La(SiO4)n
La-rich Si-rich(k~20) (k~8)
(La-silicates)
・ Direct contact with Si by forming La-silicate layer・ High dielectric constant ・Wide band-gap・ Amorphous
La-silicate is one of the potential candidates for next generation
Advantage of La-silicate
La-silicate for direct contact of high-k/Si
2nm
800oC, 30min
La-silicate(k~16)
4
Supply of oxygen atoms
Small n Large n
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Concerns in reliability
5
No report on Reliability of La-silicate
Poly-Si/HfSiON/SiON/n-Si
Crupi, Felice, et al. Microelectronic engineering 80 (2005): 130-133.
EOT 0.9 nm
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La-silicate MOS capacitor with W2C gate electrode
6
Interface state density was suppressed by W2C gate electrode ( Dit< 3×1011 cm-2eV-1)
Dit
(cm
-2eV
-1)
10
×1011
0.7 0.8 0.9
W gate
W2C gate
EOT (nm)
ψs= - 0.15 eV
F.G 80030min
0.850.75
12
8
6
4
2
0
Dit
(cm
-2eV
-1)
10
×1011
0.7 0.8 0.9
W gate
W2C gate
EOT (nm)
ψs= - 0.15 eV
F.G 80030min
0.850.75
12
8
6
4
2
0n-Si
La-silicate
W Carbide
n-SiLa-silicate
W Carbide
n-SiLa-silicate
n-SiLa-silicate
W
n-SiLa-silicate
n-SiLa-silicate
W
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Purpose of this study
Investigate reliability of La-silicate MOS capacitors with tungsten carbide gate electrode
7
1. Introduction
2. W2C formation
3. Device fabrication process
4. PBTI measurement
5. Conclusion
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Stacked W/C structure
Advantage
Carbide formation
annealing
Deposition methods of carbides
8
Deposition of several sets of carbon and metal stacking
n-Si
・・・
wC
La-silicate
wC
wC
Cycle W/C layers
Layered reaction to suppress excess growth of grain size
Content of carbon can be controlled Low temperature annealing
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0
20
40
60
80
100
120
140
160
180
200
0 150 300 450 600 750 900 1050 1200
0
100
200
300
400
500
600
700
800
30 40 50 60 70 80 90
W2C
(100
)(0
02)
(101
)
(102
)
(110
)
(103
)(2
00)
(112
)(2
01)
(004
)
(202
)
2Ѳ (deg)
Inte
nsity
(Cou
nt)
Tungsten carbide formation
Grain size = 1.9nm
W2C
GIXD750oC
(due to reaction of C and SiO2)W
amorphous
Shee
t res
ista
nce
(Ω/s
q.)
10nm
Annealing temperature (oC)
750oC
9
W2C with small grain size can be obtained at 725oC~825oC
・・・
1 cycle
18 set
wCwC
wC
SiO2(400nm)
n-Si
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n-Si
Cycle W/C layers
W Carbide
Annealing
SPM,HF - treatment
TiN(10 nm), Si(100nm) capping layer by RF sputtering
Annealing in F.G ambient at 800oC (for 30 min)
Backside Al contact
Annealing in F.G ambient at 420oC(for 30 min)
capacitor
measurement
Device fabrication process
n-Si(100)
・・・
1 cycle
18 set
Gate patterning (RIE)
Si removal by TMAH
in-situ
wC
n-Si
wC
wC
W/C multi-stacking layerby RF sputtering
La2O3 e-beam evaporation (1- 4nm) at 300oC
10
La2O3
La-silicate
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TEM observation
Atomically flat metal/high-k and high-k/Si interfaces were achieved by W2C gate electrode
TiN/W/La-silicate/n-Si
TiN/W2C/La-silicate/n-Si
11
20nm
20nm
W2C
WTiN
TiN 5nm
5nm
W2C
W
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Interfaces roughness with W2C
High-k/Si and Metal/High-k interface roughness was improved with W2C gate electrode
12
Metal/High-kinterface
High-k/Siinterface
Dis
trib
utio
n
Interface height position (nm)
Dis
trib
utio
n
Interface height position (nm)0.0 0.3 0.6-0.6 -0.3 0.0 0.3 0.6-0.6 -0.3
Metal/High-kinterface
High-k/Siinterface
Dis
trib
utio
n
Interface height position (nm)
Dis
trib
utio
n
Interface height position (nm)0.0 0.3 0.6-0.6 -0.3 0.0 0.3 0.6-0.6 -0.3
W2C(Ra=0.12 nm)
W (Ra=0.36 nm)W (Ra=0.61 nm)
W2C(Ra=0.26 nm)
High-k/Si interface roughness
Metal/High-k interface roughness
W W2C
0.36 nm
0.61 nm 0.26 nm
0.12 nm
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Electrical characteristic with W2C
13
Interface state density was suppressed with W2C gate electrode
-1.5 0.0 1.0 1.5-1.0
1.5
1.0
2.0
2.5
3.5
0.0
F.G 800oC 30minEOT=0.75nm10×10µm2
100kHz
Gate Voltage (V)
Cap
acita
nce
Den
sity
(µF/
cm2 )
0.5
3.0
0.5-0.5
W
n-SiLa-silicate
W Carbide
n-SiLa-silicate
W2C Dit=2.50×1011(eV-1cm-2)W Dit=9.8×1011(eV-1cm-2)
Conductance method
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PBTI comparison
n+-polysilicon/HfO2 /SiON/Si-substrate
Si/SiO2 /Si-substrate
β≃0.32
β=1
Zafar S, Gusev E P and Cartier E 2005 IEEE Trans. Dev. Mater. Reliab. 5 45.
stress time (s)
0.0011 10 100 1000 10000
0.1
0.01
1∆
V fb(
V)
Solid lines ∆Vfb= ∆Vmax(1-exp[-(t/τ0)β])W : β≃0.28
W2C : β≃0.39
W2C Vs=1.7(V)W2C Vs=1.8(V)W2C Vs=1.9(V)
W Vs=1.7(V)W Vs=1.8(V)W Vs=1.9(V)
EOT=0.75nm
RT
14
β0.28 0.32 0.39 1
Poly-Si/SiO2W2C/La-silicateW/La-silicate Poly-Si/HfO2/SiON
Better Reliability
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Si sub.
High-k
High temperature annealing
(CTE~10-6K-1)
(CTE~10-5K-1)
(CTE~10-6K-1)
Si sub.High-k
Room temperature
Si sub.
Possible explanation
W2C
W
PBTI was improved with W2C gate electrode due to smaller mechanical strain
15
W Carbide
n-SiLa-silicate
W
n-SiLa-silicate
CTE: Coefficient Thermal Expansion
High temperature annealing
Si sub.
High-k
(CTE~10-6K-1)
(CTE~10-5K-1)
(CTE~10-6K-1)
Si sub.
High-k
slip at GB
stress release
Room temperature
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Conclusions
16
・Reliability of La-silicate with different gate electrodes (W2C, W) is measured first time by PBTI.
・Atomically flat interface of metal/high-k and high-k/Si was achieved with W2C gate electrodes.
・Better reliability was obtained presumably due to mechanical stress relaxation by nano-sized W2C gate electrode.
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Thank you for your attention
17
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Backup
18
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S D
Metal gatePoly-Si
substrate
High-k
PBTI for reliability measurement
Positive bias
n-MOSFET
PBTI (Positive Bias Temperature Instability)Threshold voltage shifts occur under positive bias in NMOS
We measure reliability of La-silicate by PBTI
Linder, Barry. 223rd ECS Meeting (May 12-17, 2013). Ecs, 2013.
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0
1000
2000
3000
4000
5000
6000
30 40 50 60 70 80 90 2θ (deg)
Inte
nsity
(Cou
nt)
W
900oC
TEM observation and XRD results for W gate electrode
10nm
W/C=1:1, 900oC
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Coefficient of Thermal expansion
21
Roylance, David. "Introduction to elasticity." Cambridge: Department of Materials Science and Engineering (2000).
W・・・4.2×10-6 K-1
WC・・・5.8×10-6 K-1
La・・・1.3×10-5 K-1
Si・・・2.6×10-6 K-1
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Deposition methods of carbides
22
1. Sputtering from carbide alloy targetDeposition methods of carbides
Carbon deficiency formation during annealing2. Sputtering with CH4 gas
3. Solid reaction of C and W layersHydrogen to produce carbon deficiency
Interface reaction and grows grains
H, Romanus, Thin solid Films 146, (2000)
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質疑①
Q1.グレインサイズが小さくなることで信頼性が上がるのなら、ゲート電極がアモルファスだったらさらに信頼性は上がる?
23
Q2.ゲート電極の厚さによる信頼性への影響はあるのか?
Q3.絶縁膜がLa-silicate以外でも、同じようにゲート電極のグレインサイズの影響は現れる?
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質疑③
24
Q2.ゲート電極の厚さによる信頼性への影響はあるのか?
A.今回の測定ではW電極・W2C電極ともに同じ膜厚のみで測定
川那子さん・来山さんによるの測定TiN/W/La2O3/n-Si
来山大祐 修士論文 (2012)
W膜厚の増加によってVfbのシフト量が増加
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質疑④
25
Q3.絶縁膜がLa-silicate以外でも、同じようにゲート電極のグレインサイズの影響は現れる?
A.ゲート電極堆積後にアニールすることでLa-silicateができるためにグレインサイズが界面に影響
Si sub.
High-k
High temperature
(CTE~10-6K-1)
(CTE~10-5K-1)
(CTE~10-6K-1)
Si sub.High-k
Room temperature
Si sub.
・・・
n-Si
La2O3
Cycle W/C layers
n-SiLa-silicate
W Carbide
Annealing
La2O3 + nSi + mO2→La(SiO4)n
La-rich Si-rich(k~20) (k~8)n小 n大
(La-silicates)
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26
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High temperature annealing
質疑②
27
Q1.グレインサイズが小さくなることで信頼性が上がるのなら、ゲート電極がアモルファスだったらさらに信頼性は上がる?
Si sub.
High-k
(CTE~10-6K-1)
(CTE~10-5K-1)
(CTE~10-6K-1)
Si sub.
High-k
slip at GB
stress release
Room temperature
W2C
Si sub.
High-k
High temperature annealing
(CTE~10-6K-1)
(CTE~10-5K-1)
(CTE~10-6K-1)
Si sub.High-k
Room temperature
Si sub.
W
A.アモルファスだと信頼性は向上すると考えられる
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TMAHについて
TMAH(水酸化テトラメチルアンモニウム水溶液)
TMAH中において
Siが水溶性のケイ酸イオンとなり、Si除去が可能
↑+→++ −−2
232 22 HSiOOHOHSi
28
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PBTIについてBTI (Bias Temperature Instability)・MOSFETへの電圧印加による閾値電圧の変動
PMOS: negative BTI (NBTI)NMOS: positive BTI (PBTI)
Linder, Barry. 223rd ECS Meeting (May 12-17, 2013). Ecs, 2013.
PBTIの方がNBTIよりも信頼性に影響
PBTIによる信頼性を測定
S DHigh-k
Metal gatePoly-Si
substrate
ストレス電圧
29
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W2C W
0(s) 0(s)3163(s) 3163(s)
Dit(
eV-1
cm-2
)
0.0
2.0
12.0
10.0
6.0
8.0
4.0
PBTIによるDitの増加
∆Dit=1.05×1011
∆Dit=1.35×1011
・両ゲート電極共に、PBTI中にDitは上昇する・PBTI中のDitの変化量はほぼ差が無い 30
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0.00E+00
5.00E-08
1.00E-07
1.50E-07
2.00E-07
2.50E-07
1.00E+00 1.00E+02 1.00E
W電極とW2C電極のDit比較F.G 800oC 30EOT=0.75nm10×10µm2
100kHzW2CDit=2.50×1011(eV-1cm-2)
WDit=9.78×1011(eV-1cm-2)
Frequency(Hz)
Gp/ω
(F/c
m2 )
×10-7
102 104 1061 10 103 105 107
2.5
2.0
1.5
1.0
0.5
0
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∆Vmax (V) τ0 β
1.7(V) 0.087 101.4 0.281.8(V) 0.099 127.9 0.261.9(V) 0.101 13.5 0.28
1.7(V) 0.042 114.5 0.401.8(V) 0.066 361.0 0.391.9(V) 0.074 210.8 0.39
W
W2C
32
PBTI fitting parameter
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33
PBTIのリカバリー
0(s) 3163(s) 測定終了後
1.7(V) Vfb=-0.24(V) Vfb=-0.16(V) Vfb=-0.21(V)1.8(V) Vfb=-0.23(V) Vfb=-0.14(V) Vfb=-0.21(V)1.9(V) Vfb=-0.23(V) Vfb=-0.13(V) Vfb=-0.19(V)
1.7(V) Vfb=-0.27(V) Vfb=-0.23(V) Vfb=-0.26(V)1.8(V) Vfb=-0.27(V) Vfb=-0.21(V) Vfb=-0.26(V)1.9(V) Vfb=-0.27(V) Vfb=-0.20(V) Vfb=-0.24(V)
W
W2C
ストレスを切った後にVfbシフトのリカバリを確認
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0.01
0.1
0.001
1
100 101 102 103 104 105
La-silicate(W)La-silicate(W2C)
1.7(V) 0.75nm
poly-Si/HfO2/IL/Si
1.5(V) 1.7nm
34
poly-Si/HfO2/IL/SiとのPBTI比較
Zafar S, Gusev E P andCartier E 2005 IEEE Trans. Dev. Mater. Reliab. 5 45.
stress time (s)
∆V f
b(V
)
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1. Sputtering from carbide alloy targetCarbideの堆積方法
アニール中にC欠損が生じる2. Sputtering with CH4 gas
3. C層とW層の固層反応Hydrogen to produce carbon deficiency
Interface reaction and grows grains
H, Romanus, Thin solid Films 146, (2000)
35
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Electrical characteristic with W2C
-1.5 0.0 1.0 1.5-1.0
1.5
1.0
2.0
2.5
3.5
0.0
F.G 800oC 30minEOT=0.75nm10×10µm2
100kHz
W2CDit=2.50×1011(eV-1cm-2)WDit=9.78×1011(eV-1cm-2)
Gate Voltage (V)
Cap
acita
nce
Den
sity
(µF/
cm2 )
0.5
3.0
0.5-0.5
3
Interface state density is lower by W2C gate electrode
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Possible explanation
Si sub.
High-k
(CTE~10-6K-1)
(CTE~10-5K-1)
(CTE~10-6K-1)
Si sub.
High-k
slip at GB
stress release
High temperature Room temperatureW2C
Si sub.
High-k
High temperature
(CTE~10-6K-1)
(CTE~10-5K-1)
(CTE~10-6K-1)
Si sub.High-k
Room temperature
Si sub.
W
PBTI was improved by W2C gate electrode due to nice interface properties
37
W Carbide
n-SiLa-silicate
W
n-SiLa-silicate
CTE: Coefficient Thermal Expansion
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0
20
40
60
80
100
120
140
160
180
200
0 150 300 450 600 750 900 1050 1200
0
100
200
300
400
500
600
700
800
30 40 50 60 70 80 90
W2C
(100
)(0
02)
(101
)
(102
)
(110
)
(103
)(2
00)
(112
)(2
01)
(004
)
(202
)
2Ѳ (deg)
Inte
nsity
(Cou
nt)
Annealing temperature for W2C
Grain size = 1.9nm
W2C
GIXD750oC
(due to reaction of SiO2)W
amorphous
SiO2(400nm)
Shee
t res
ista
nce
(Ω/s
q.)
10nm
Annealing temperature (oC)
750oC
38
n-Si
W2C with small grain size can be obtained at 725oC~825oC
・・・
1 cyclwCwC
w