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design document for:

High Voltage C-V Characterization of SiC

submitted to:

Professor Joseph PiconeECE 4522: Senior Design II

Department of Electrical and Computer EngineeringMississippi State University

Mississippi State, Mississippi 39762

May 01, 2001

submitted by:

W. Draper, R. Miller, J. Heath, and J. BurkettFaculty Advisor: Associate Professor Mike MazzolaDepartment of Electrical and Computer Engineering

Mississippi State UniversityBox 9571

Mississippi State, Mississippi 39762Tel: 662-325-2059, Fax: 662-320-8546

email: {wad1, rdm1, jwh1, jlb1}@ece.msstate.edu

High Voltage C-V Characterization of SiC

EXECUTIVE SUMMARY

As silicon carbide (SiC) microelectronics devices mature, many research hours are spent developing precisely doped, low defect density epitaxial films [1]. As Mississippi State University continues to push the envelope with their research in this area, a need has arisen for an onsite system to quantitatively evaluate thick (³ 5mm) epitaxy [2]. In order to prove research theorems and continue technological advancement, researchers must quickly determine epitaxial dopant impurity concentration. In the past, Mississippi State University has met this need with Secondary Ion Mass Spectroscopy (SIMS) [2]. However, this method is costly and cannot be done locally. Another way to measure the doping levels is through C-V characterization. High-voltage C-V characterization of epitaxy collects data that can be mathematically manipulated to reveal impurity concentration at any given depth less than 10mm [3]. The commercial unavailability of such a system presents this team with the task of creating one.

Several design constraints have been defined to guarantee this project be efficient and cost effective. Most importantly, equipment presently owned by Mississippi State University must be used to assemble the characterization system. The use of available equipment ensures that our costs are lower per sample than current characterization methods. In addition, a computer interface must be implemented to control the system, collect data, perform calculations, and graphically represent the results. This integrated system will reduce the time needed to establish the doping levels. Presently SIMS requires 7-10 days in order to characterize each sample. All data must be stored in an Access database that is already in use with other test systems. Therefore, our system must also use this database to store and catalog all results. Once assembled, system precision must be verified by comparing C-V characterization results of a reference sample with its known values.

In order to most effectively bring our system to realization, our team has elected to first verify operation of each of the individual subsystems: hardware, software input, software output, data analysis, and C-V testing structure. After verification of each subsystem is completed, work will begin to integrate software components and hardware. Extensive testing is required in order to determine if the system can consistently and accurately characterize thick epitaxial layers.

C-V characterization systems currently exist that measure doping levels up to a depth of 5 mm using 100 V [2]. However, our system will measure depths of 10 mm using up to 400 V [4]. Present systems do not automatically interpret data. Our system will use Lab View software to acquire the appropriate data measurements and then output doping levels in both graphical and tabular forms.

As SiC research continues its rapid growth, epitaxial layers will reach depths over 12 mm with lower defect densities [5]. With future improvements of the testing structure design, our system could operate up to a hardware limitation of 600V. In the future, the system could be fully automated, which would eliminate human contact with the SiC wafers.

ECE 4512 December 05, 2000

TABLE OF CONTENTS

ABSTRACT.............................................................................................11. INTRODUCTION ....................................................................................12. PROBLEM .............................................................................................13. OBJECTIVES..........................................................................................2 3.1. High-Voltage Testing Structure...................................................3 3.2. Graphical User Interface..............................................................3 3.3. Capacitance Measurement...........................................................3 3.4 Integration with Access Database...............................................3 3.5 Automation....................................................................................3 3.6. Characterization Time..................................................................3 3.7. Cost................................................................................................4 3.8. Doping Concentration Profile......................................................44. APPROACH............................................................................................4 4.1. C-V Testing Structure Simulation................................................4 4.2. C-V Testing Structure Layout......................................................10 4.3. Boonton 72BD Capacitance Meter..............................................10 4.4 Signal Input...................................................................................11 4.5 Data Interpretation........................................................................11 4.6. Software Approach.......................................................................14 5. TEST SPECIFICATIONS.........................................................................19 5.1. C-V Testing Structure Simulation................................................20 5.2. C-V Testing Structure Layout......................................................20 5.3. Boonton 72BD Capacitance Meter..............................................20 5.4 Manual Value Input.......................................................................20 5.5 Manual Calculations.....................................................................21 5.6. Keithley Input Voltages................................................................21 5.7. Probe Stand Movement................................................................21 5.8. System Testing.............................................................................21

High Voltage C-V Characterization of SiC 2 of 41

6. TEST CERTIFICATIONS.........................................................................22 6.1. C-V Testing Structure Simulation................................................22 6.2. C-V Testing Structure Layout......................................................30 6.3. Boonton 72BD Capacitance Meter..............................................31 6.4 Manual Value Input.......................................................................31 6.5 Manual Calculations.....................................................................31 6.6. Keithley Input Voltages................................................................33 6.7. Probe Stand Movement................................................................34 6.8. System Testing.............................................................................347. SUMMARY..............................................................................................388. FUTURE WORK.....................................................................................399. ACKNOWLEDGMENTS.........................................................................3910. REFERENCES.......................................................................................39



ABSTRACT

As silicon (Si) based microelectronic devices reach physical limitations, researchers are developing alternative silicon carbide (SiC) based devices [6]. Proper operation of complicated SiC devices is directly related to epitaxial impurity concentration [7]. Quantification of impurities in thick epitaxial layers can be extracted from C-V data related to the epitaxial film. Our system collects C-V data and extracts impurity concentration. In addition, calculated results are displayed to the user, thus creating a cost-effective characterization tool.

1. INTRODUCTION

Silicon carbide (SiC) is a wide-bandgap material that is physically suited for high voltage, high frequency, and high temperature electronic devices [1], [5]. Examples of such devices are diodes, field effect transistors (FETs), and bipolar junction transistors (BJTs). Currently, the only discrete SiC devices available commercially are light-emitting diodes [6]. However, many other discrete SiC devices are presently under development throughout the world [7].

Proper semiconductor device performance requires a single crystalline structure with low defect density and precision doping. Commercial unavailability of a SiC substrate that meets these requirements creates an ever-present problem for researchers in their attempts to further this rapidly advancing technology.

2. PROBLEM

SiC devices begin with a highly impure SiC bulk substrate that is currently available commercially. Onto this substrate, a single crystalline epitaxial layer is grown through a process known as chemical vapor deposition (CVD) [3], [8]. The epitaxial layer has a low defect density and can be precisely doped [8]. This layer creates the foundation required to fabricate semiconductor devices. Current technology at Mississippi State University allows the growth of SiC epitaxy up to 12 micrometers in depth.

Researchers can predict the doping levels of the epitaxy by controlling growth conditions such as pressure, gas flow and temperature. However, in order to produce reliable semiconductor devices it is necessary to measure the actual doping concentration of each epitaxial layer and compare this to expected results. This measurement insures that the process and equipment remain functioning properly during the entire growth process.

Current technology at MSU limits the measurement of doping levels to a depth of only 5 micrometers. With the advancement of our CVD technology, epitaxy is now grown in excess of 10 micrometers. Researchers at MSU are forced to determine doping concentrations in thick epitaxy using Secondary Ion Mass Spectroscopy (SIMS). This is done off campus, making it time consuming and expensive, thus creating the need for a cost effective on-campus system.



Doping concentration of epitaxy can be interpreted from capacitance-voltage (C-V) measurements. These measurements require a testing structure, such as a Schottky barrier diode. C-V data is collected by incrementing a voltage applied to the testing structure. At each voltage increment, the induced capacitance is measured and can be graphically represented with a capacitance vs. voltage plot.

By creating a system that is accessible to researchers at MSU using equipment already available, the cost and time involved in properly characterizing epitaxial layers is greatly reduced. Our characterization system decreases the turn around time and cost associated with the SIMS process thus allowing researchers to advance SiC technology more rapidly. 3. OBJECTIVES

1. High-voltage Testing Structure: Design and implement a Schottky diode for use as a C-V testing structure that can operate with an applied reverse bias of up to 400 V while maintaining a capacitance within the dynamic range of the measurement equipment [8], [9].

2. Graphical User Interface: Design and implement computerized graphical users interface using Lab View 6.0 in a Windows 95/98 environment.

3. Capacitance Measurement: Ensure capacitance measurement hardware

is capable of 2% precision at the analogue output.

4. Integration with Access database: System must export all collected and calculated data to a preexisting Access database. A excel file will be used to complete this task.

5. Automation: All data collection, calculations, and probe stand movement must be fully automated by a Lab View 6.0 routine, so that one test will be run from beginning to end without human intervention.

6. Characterization Time: Characterization time must be less than 2 minutes per C-V testing structure [10].

7. Cost: Total system cost, including all parts and labor, must not exceed $15,000.

8. Doping Concentration Profile: Doping concentration profile must be verified within 20%.

Conforming to the above design constraints will ensure that a suitable C-V characterization system is implemented.



3.1. High-voltage Testing Structure

In order to test the doping of the epitaxy, a testing structure was designed and created to withstand 400 V. The 400 V plateau is necessary to measure the doping level at the 10 –12 mm depth. Several Schottky diode geometries were simulated using Medici to maximize breakdown voltage [9]. The design chosen was and array of circular structures ranging from 500mm in radius to 350mm in radius.

3.2. Graphical User Interface

The C-V characterization system requires computerized control through a graphical user interface. The interface we have designed reduces the complexity involved in characterization and decreases the amount of training required to properly operate the system. The graphical representation of calculated results simplifies their interpretation.

3.3. Capacitance Measurement

Precise capacitance measurements are necessary to ensure overall system performance. Any error in the initial capacitance measurement is compounded during calculations. Calculations performed with inaccurate capacitance values are invalid. Therefore, initial capacitance measurement have at least a 2% precision.

3.4. Integration with Access Database

After all data has been collected and processed, the results are stored in a preexisting Access database. The Access database catalogues all SiC wafers and details regarding their fabrication. Doping impurity characterization that this system calculates is stored in an Excel file that can easily be put into the access database by the administrator.

3.5. Automation

The system is fully automated in order to allow the probing of several different points without human aid. Elimination of human contact reduces the risk of sample damage or contamination. Automation also reduces the amount of user training and decreases the number of errors due to improper operation. Automation was performed with a Lab View 6.0 routine.

3.6. Characterization Time

The time required to collect data from each C-V testing structure is less than 2 minutes. At this per structure rate, characterization of epitaxial film on one wafer takes approximately 20 minutes. Our system allows for 24 wafer characterizations per day, which exceeds previous production by 1200%.



3.7. Cost

For our system to be beneficial to current research projects at Mississippi State University, the total cost must be less than $15,000. This cost estimate must include all purchased components and production labor. Our system has a total cost of $12841. This cost is meets out cost requirement.

3.8. Doping Concentration Profile

The results produced by the system were verified by comparing C-V characterization results with low-voltage C-V Characterization for depths less than 5mm. For depths greater than 5mm, SIMS measurements were used to support the high-voltage C-V characterization. This verification was done for several different known samples. Each C-V characterization was within 20% of the known sample. This shows that the results are valid. The magnitude of the error is due to several measurements and calculations introducing small errors at each step.

4. APPROACH

4.1. C-V Testing Structure Simulation

Design of the high-voltage testing structure was performed with 1-D parallel-plate capacitor model equations. We elected to use these 1-D equations, rather than more realistic 2-D equations, in order to simplify data analysis. Using a 1-D model rather than a 2-D model brings greater difficulty to this project by requiring a comparison between the two. This comparison verified that the device has been designed in such a way that it can be modeled with reasonable accuracy using 1-D equations.

4.1.1. Space Charge Region Width

Theoretical space charge region width as a function of voltage for various dopant concentrations must was calculated. This was done in order to determine the voltage level required to characterize 10mm thick epitaxy. Theoretical voltage dependant space charge region width was calculated from the following equation:

Where,W = Space charge region widthr = Semiconductor dielectric constanto = Permittivity of free spaceA = Device areaC = Capacitance.


eq. 4.1.1.1


4.1.2. Capacitance Per Unit Area

Theoretical capacitance per unit area of the high-voltage testing structure was calculated so that the device area was determined such that the total capacitance of the structure stays within the dynamic range of the measurement equipment. Capacitance per unit area of a nickel contact on 4H SiC was calculated from he following equation:

Where,

C = CapacitanceA = Areaq = Electron charger = Semiconductor dielectric constanto = Permittivity of free spaceND = Donor doping concentrationVbi = Built-in device potentialV = Applied voltage.

4.1.3. Optimal Device Area

The optimal range for device areas was determined in order to ensure that the voltage dependent capacitance of the high-voltage testing structure remains within the dynamic range of the measurement equipment under all operating conditions. Understanding from eq. 4.1.2.1 that capacitance per unit area decreases with increases negative voltage, we will use the maximum operating voltage of –400 V to determine device area. Solving eq. 4.1.2.1 for device area yields:

Where,C = Minimum measurable device capacitanceA = Areaq = Electron charger = Semiconductor dielectric constanto = Permittivity of free spaceND = Donor doping concentrationVbi = Built-in device potentialV = Applied voltage.


eq. 4.1.2.1

eq. 4.1.3.1


4.1.4. 2-D Medici Simulation

2-D Medici simulations were performed to verify that the 3-D device could be modeled with 1-D equations. Medici input files include the maximum operation voltage, optimal device area and 4h-SiC material parameters. The results from our simulation are I-V characteristics, maximum electric field and equipotential points. The following are the Medici input files:

ASSIGN NAME=RC N.VAL=550ASSIGN NAME=RD N.VAL=700

ASSIGN NAME=TEL N.VAL=1ASSIGN NAME=TL1 N.VAL=3ASSIGN NAME=TL2 N.VAL=3ASSIGN NAME=TL3 N.VAL=4ASSIGN NAME=TBULK N.VAL=20

ASSIGN NAME=X0 N.VAL=0ASSIGN NAME=X1 N.VAL=@RCASSIGN NAME=X2 N.VAL=@RD

ASSIGN NAME=Y0 N.VAL=0ASSIGN NAME=Y1 N.VAL=@Y0+@TELASSIGN NAME=Y2 N.VAL=@Y1+@TL1ASSIGN NAME=Y3 N.VAL=@Y2+@TL2ASSIGN NAME=Y4 N.VAL=@Y3+@TL3ASSIGN NAME=Y5 N.VAL=@Y4+@TBULK

ASSIGN NAME=CL1 N.VAL=5E15ASSIGN NAME=CL2 N.VAL=5E15ASSIGN NAME=CL3 N.VAL=5E15ASSIGN NAME=CBULK N.VAL=1E19

CALL FILE="mesh"

STOP

Medici input file a

PLOT.2D BOUND FILL JUNC T.SIZE=.25PLOT.2D BOUND FILL JUNC T.SIZE=.25 grid

PLOT.1D X.ST=0 X.EN=0 Y.ST=@Y1 Y.EN=@Y5 DOPING Y.LOG LINE=3

EXTRACT EXPRESS="MAX(@FUNC;@EM)" COND="@y<@Y1" NAME=FUNCEXTRACT EXPRESS="MAX(@FUNC1;@EM)" COND="@y>@Y1" NAME=FUNC1EXTRACT EXPRESS="@x" COND="(@EM=@FUNC1)&(@y>@Y1)" NAME=xemECE 4512 December 05, 2000


EXTRACT EXPRESS="@y" COND="(@EM=@FUNC1)&(@y>@Y1)" NAME=yemEXTRACT EXPRESS="@x" COND="(@EM=@FUNC)&(@y<@Y1)" NAME=xemoEXTRACT EXPRESS="@y" COND="(@EM=@FUNC)&(@y<@Y1)" NAME=yemoEXTRACT EXPRESS="@V(BACK)" NAME=VMAX

SOLVE

PLOT.2D BOUND FILL JUNC T.SIZE=.25+ TITLE="Vmax="@VMAX", Emax(oxide)="@FUNC", Emax(bulk)="@FUNC1CONTOUR POTENTIA MIN=0 MAX=@VMAX DEL=@VMAX/50 COLOR=6CONTOUR FLOW

PLOT.2D BOUND FILL JUNC T.SIZE=.25+ TITLE="Vmax="@VMAX", x(Emax)="@xem", y(Emax)="@yemCONTOUR E.FIELD MIN=@FUNC1/2 MAX=@FUNC1 DEL=@FUNC1/22 FILL

Medic input file plot

TITLE Senior Design: C-V Testing Structure MESH OUT.FILE="cv.msh" CYL

ASSIGN NAME=K N.VALUE=1.5 X.MESH [email protected] L=@X1 H1=@RC/10 H2=@RC/10X.MESH L=@X2 H1=@RC/10 H2=@RC/10

Y.MESH [email protected] L=@Y1 N.S=3Y.MESH L=@Y2 N.S=4Y.MESH L=@Y3 N.S=4 Y.MESH L=@Y4 N.S=4Y.MESH L=@Y5 H1=@TL3/4 H2=@TBULK/4

REGION OXIDEREGION NAME=RL1 SIC POLYGON + X.POLY=(@X0,@X2,@X2,@X0) + Y.POLY=(@Y1,@Y1,@Y2,@Y2)REGION NAME=RL2 SIC POLYGON + X.POLY=(@X0,@X2,@X2,@X0) + Y.POLY=(@Y2,@Y2,@Y3,@Y3)REGION NAME=RL3 SIC POLYGON + X.POLY=(@X0,@X2,@X2,@X0) + Y.POLY=(@Y3,@Y3,@Y4,@Y4)



REGION NAME=RBULK SIC POLYGON + X.POLY=(@X0,@X2,@X2,@X0) + Y.POLY=(@Y4,@Y4,@Y5,@Y5)

ELEC NAME=SCHOTTKY POLYGON + X.POLY=(@X0,@X1,@X1,@X0) + Y.POLY=(@Y0,@Y0,@Y1,@Y1)ELEC NAME=BACK BOTTOM

PROFILE REGION=RL1 UNIFORM CONC=@CL1 N-TYPEPROFILE REGION=RL2 UNIFORM CONC=@CL2 N-TYPEPROFILE REGION=RL3 UNIFORM CONC=@CL3 N-TYPEPROFILE REGION=RBULK UNIFORM CONC=@CBULK N-TYPE

$ Material definitionCALL FILE="4h-sic"MATERIAL OXIDE PERMITTI=3.9CONTACT NAME=SCHOTTKY WORKFUNC=4.5

REGRID DOPING LOG FACTOR=1.2 PLOT.2D BOUND JUNC DEPL FILL GRID SYMB CARRIERS=0METHOD ICCG DAMPED CONT.RHS ILU.ITER=20SOLVE INI EXTRACT EXPRESS="@c(SCHOTTKY,BACK)" NAME=CAPLOG OUTFILE="results/cv.log"MODELS CONMOB FLDMOB AUGER CONSRHSYMB GUMMEL CARRIERS=1 ELECSOLVE ELEC=BACK VSTEP=0.01 NSTEPS=10

MODELS CONMOB FLDMOB AUGER CONSRH BGN IMPACT.ISYMB NEWTON CARRIERS=2SOLVE ELEC=BACK CONTINU C.VMAX=500 C.IMAX=1 C.VSTEP=1LOG CLOSE

CALL FILE="plot"

$ STOP

Medici input file mesh



ASSIGN NAME=NCOND C.VAL=" "ASSIGN NAME=BCOND C.VAL="(@X>=70)&(@X<=110)&(@Y<=.25 )"ASSIGN NAME=NITROGEN N.VAL=0ASSIGN NAME=BORON N.VAL=0ASSIGN NAME=PHOSPHOR N.VAL=0ASSIGN NAME=ALUMINUM N.VAL=0

COMMENT Parameters are taken from PHISICA STATUS SOLIDI (A) 162#1 1997

ASSIGN NAME=EG N.VALUE=3.23ASSIGN NAME=EC N.VALUE=@EG/2ASSIGN NAME=EV N.VALUE=-@EG/2

COMMENT EDB and EAB correspond to mean N state and B state respectevilyMATERIAL SIC+ EG300=@EG+ PERMITTI=10+ TAUN0=4.4E-7 TAUP0=4.4E-7+ EGALPH=3.3E-4 EGBETA=0+ A.SP.HEA=1026 B.SP.HEA=0.201 C.SP.HEA=0 D.SP.HEA=-3.66E7+ MEG=0.58 MEL=0.33+ EL.EMAS=0.39 HO.EMAS=0.82$+ AUGN=3E-29 AUGP=3E-29$+ N.ION.2=84.7556 N.ION.1=5.02E3 N.IONIZA=-4.184E6 ECN.II=2.58E6 EXN.II=1$+ P.ION.2=16.3222 P.ION.1=-3.61E4 P.IONIZA=3.1E7 ECP.II=1.9E7 EXP.II=1$ {After M. Lades, W.Kaindl, G. Wachutka} + N.ION.2=0 N.ION.1=0 N.IONIZA=1.66E6 ECN.II=1.273E7 EXN.II=1 + P.ION.2=0 P.ION.1=0 P.IONIZA=5.18E6 ECP.II=1.4E7 EXP.II=1+ EDB=0.072 EAB=0.32

MOBILITY SIC+ MUN.MIN=0 MUN.MAX=9477.+ MUP.MIN=15.9 MUP.MAX=108.1

COMMENT Nitrogen states.IF COND=(@NITROGEN>0) TRAPS N.TOT=@NITROGEN/2 [email protected] MIDGAP CHARGE1 COND=@NCOND TRAPS N.TOT=@NITROGEN/2 [email protected] MIDGAP CHARGE2 COND=@NCOND



IF.END

COMMENT Phosphorus states.IF COND=(@PHOSPHOR>0) TRAPS N.TOT=@PHOSPHOR/2 [email protected] MIDGAP CHARGE1 COND=@PCOND TRAPS N.TOT=@PHOSPHOR/2 [email protected] MIDGAP CHARGE2 [email protected]

COMMENT Boron states.IF COND=(@BORON>0) TRAPS N.TOT=-@BORON E3=@EV+0.32 MIDGAP CHARGE3 [email protected]

COMMENT Aluminum states.IF COND=(@ALUMINUM>0) TRAPS N.TOT=-@ALUMINUM E3=@EV+0.23 MIDGAP CHARGE3 [email protected]

Medici input file 4h-SiC

4.2. C-V Testing Structure Layout

Layout of the C-V testing structure was performed with the Cadence layout tool. The design rule checker function of the Cadence layout tool was not utilized because our layout has only one layer. Cadence is simply a way of graphically representing the geometry and area of the device as determined by the 1-D design equations.

4.3. Boonton 72BD Capacitance Meter

The Boonton 72BD capacitance meter was used to measure the capacitance of the test sample located on the probe stand. Through our C-V testing structure simulation, we determined the range of capacitance to be measured is between 5pf and 200pf. The Boonton 72BD Capacitance Meter should be able measure this range capacitance with an accuracy of 2%.

When the capacitance measurement is taken, the meter passes an analog value to the Data Acquisition Card (DAQ). By using the DAQ, the capacitance value read is more precise than the value on the digital display of the meter. This value is then converted into a digital signal. This digital signal is then read by the personal computer.

4.4. Signal InputECE 4512 December 05, 2000


The manual input value was use to test the operation the DAQ as well as the control program. To do this, Lab View code was written that reads a digital value from the DAQ card. A signal generator was then used to generate a know DC value. By passing this value into the A/D converter, the control program was tested. The successful completion of this test allowed the input value to be displayed to the graphical user interface and read into Lab View.

4.5. Data Interpretation

Capacitance-voltage (C-V) characterization relies on the fact that the width of a reverse-biased spaced-charge region (scr) of a semiconductor junction device depends on the applied voltage. This scr width dependence on voltage lies at the heart of the C-V profiling method.

In our experiment, we constructed a Schottky barrier diode as shown in Figure 4.5.1. The Schottky barrier diode is used because it has scr properties that are closely related to a parallel plate capacitor. The parallel plate properties are important because it allows fringing to be neglected. As a result of the relationship between the Schottky barrier diode and the parallel plate capacitor, the three-dimensional diode can be designed and analyzed with one-dimensional equations. These equations were applied to the measured capacitance values allowing the simple calculation of doping concentration and depth.

Figure 4.5.1. Schottky Barrier Diode with shown spaced-charge region

The reverse bias produces a space-charge region in the epitaxy of width W. The capacitance is defined by



where Qs is the semiconductor charge. The negative sign accounts for more negative charge in the semiconductor scr (negatively charged ionized acceptors) for increased positive voltages on the test structure. dQs may then be defined by

where q is the charge of an electron, A is the area of the testing structure and NA(W) is doping concentration as a function of depth.

The charge increment dQs is produced by a slight increase in the scr width. Combining equation 4.5.1 and 4.5.2, we find

The capacitance of a reverse-biased junction, when considered as a parallel plate capacitor, is defined as

Differentiating equation 4.5.4 with respect to voltage and substituting for dW/dV gives the following equation

Equations 4.5.4 and 4.5.5 are the key equations for doping profiling. For a Schottky barrier diode, there is no ambiguity in the scr width since it can only spread into the substrate. With this information, the doping concentration (NA(W)) was plotted on a graph versus depth (W). The user is able to extract the needed information from this graph.

This knowledge was then implemented in the Lab View environment. Voltage values and measured capacitance values were ported to the data manipulation part of the control program from the data acquisition portion in the form of an array or cluster. With these values, Lab View is used to implement equations 4.4.4 and 4.4.5 to calculation the depth of the space-charge region and the doping concentration.

Calculating the depth of the space-charge region was done with a single For loop. The For loop cycles through the capacitance array, calculating the depth by dividing the


eq. 4.5.1

eq. 4.5.2

eq. 4.5.3

eq. 4.5.4

eq. 4.5.5


product of the area, free space permittivity and the relative permittivity by each measured capacitance value. This value will then be stored in a new array representing the depth of the space-charge region.

Calculation of the doping concentration was performed through multiple For loops. The first For loop cycles through the capacitance array and calculate the inverse square for each measured capacitance value. The next For loop was used to calculate the derivative of the inverse-square capacitance with respect to voltage. The last For loop was used to calculate the doping concentration using equation 4.5.5. These doping concentration values are then stored in a new array.

With the doping concentration and the depth calculated for each measured capacitance value, Lab View was used to display to the user a graph of doping concentration versus depth profile for each measured Schottky barrier diode. A simulated example of this profile can be seen in Figure 4.5.2.

Figure 4.5.2. Depth Vs Doping Concentration


0.4 0.6 0.8 1 1.2 1.4 1.6

x 10-4

1015

1016

1017

1018

Depth (cm)

Dop

ing

Con

cent

ratio

n (c

m- 3)


From the above graph, a profile of the epitaxial layer can be determined. The overall goal of this project was to achieve a maximum error of twenty percent. One can easily see that the sample graph contains a relative amount of noise. This noise can be associated with the extreme sensitivity of the doping concentration equation. Because of this sensitivity, the team used a non-liner step size for voltage and allowed the Boonton meter to be put into auto range. This worked very effectively in reducing the amount of noise.

4.6. Software Approach

The main portion of the software involved in the high voltage C-V characterization system deals with the control of the external devices. Commands were given to a device to execute a process then data collected after it has completed its task. This was done using Lab View software by National Instruments. The controls of the devices were initiated by the user through a graphical user interface. Figure 4.6.1 describes the software flow.

Figure 4.6.1 Software Flow Diagram

4.6.1. Graphical User Interface


Accept Information From The User and Initialize Variables

Instruct Keithley Source to Apply A

Voltage

Read in Value from the

Data Acquisition Card

Instruct The Probe Stand To Move To

The Next Test

Structure

Have All Voltages Been Applied?

Store Data And Increment Counter

YesNoHave All Structures

Been Tested?

No

Perform Calculations

And Display

The Results


The graphical user interface (GUI) is the point where the software, the characterization system and the user interact. It was decided in designing the interface that only a small amount of information was to be required from the user for a characterization test to take place. The only data needed in order to initiate a test was originally the starting applied voltage, the final applied voltage and the voltage increment between applied voltages. However, this lead to a linear step size between applied voltages. It was determined that the resulting profiles would be more useful if the step size were greater at deeper depths. A non-linear step size was implemented. The user now inputs the number of data points required, the final voltage, the device size, and an ID number. Other parameters for the Keithley source are invisible to the user and set by software defaults. The system then sweeps the desired voltage range and outputs a graph of the doping concentration versus depletion region depth. The GUI was kept as simple as possible. The final version is seen in Figure 4.6.1.1. Errors were also taken into account. If the system produces an error, this appears on the user interface. The Keithley voltage source control software determines these errors and their associated codes seen in Table 4.6.1.1.

Figure 4.6.1.1. Graphical User Interface



Trigger OverrunIllegal Measure RangeIllegal Source Range

In StandbyCal. Common Mode Error

Cal. Value ErrorCal. Compliance Error

Table 4.6.1.1. Error Codes for the Keithley 237 Voltage Source

4.6.2. Keithley Control Software

The first step in the characterization process is the application of a series of voltages. These voltages are created by a Keithley 237 high voltage source. The flow diagram of the process of initializing and controlling the source is seen in Figure 4.6.2.2.

Before operation, the source is reset in order to ensure no parameters from previous tests are still in memory. This is accomplished by sending the J0X (factory default) command to the unit via the data acquisition card (DAQ) located in the PC. The Lab View program can be setup to interact with various brands of DAQ cards. Once this is done, the numerical address of the specified device on the GPIB (General purpose interface bus) is all that is needed in order to write to a specific device via the DAQ. In the case of the Keithley voltage source, this address is 16. Lab View comes with pre-written function that will write to a specified GPIB address. Any errors are recorded in the error in/out line and passed down to the next module. These errors are then checked once the device process is finished. Every module has access to this line and indicates any errors.

Next, the basic parameters are uploaded to the device. This again uses the GPIB to write to the Keithley source. These parameters are invisible to the user and are set to their default values by the programmer. The device is then set to V/I mode where it will apply a voltage and measure a current value. The compliance voltage and current levels will are set to auto, allowing the source to control the upper limit. The delay is set to 0.5 seconds between each voltage increment with a zero bias level. This is also where the user inputted values for the start voltage, the stop voltage, and the voltage step are uploaded to the device.

Once the source has been initialized, it its removed from standby mode and placed into operating mode. This is accomplished by writing a N1X string to the source via the GPIB address 16. The N0X string places the device back into standby mode. Writing a H0X command string then triggers the unit and the voltage sweep occurs. The Keithley source outputs the voltage then measure the corresponding current. The device stores these values internally until the sweep is finished. It then returns them to the Lab View control



program where they are stored in an array. The applied voltage values are then passed to the calculations portion of the software to be interpreted.

After the voltage and current readings have been read and recorded, the source is placed into standby mode by writing the N0X string to the device via the GPIB. The error out string is observed for errors. Any errors are returned to the user in the form of a numerical code placed in the error out box of the GUI. A chart of the error codes can be found in Figure 4.6.2.1.

source rangeI source / V source (auto:0)

0 .0

1

s o u rc e / m e a s u re (V / I:0 )

s te p s to p le v e l

d e la y (s e c )s ta rt le v e l

b ia s le v e l

d e v ic e d e p e n d e n t e rro rs

1

0

1

0 .0

0 .1

1 0 .00

e rro r ine rro r o u t

G P IB a d d re s s

Figure 4.6.2.1. The Initiation and Control of Keithley 237 Voltage Source

Figure 4.6.2.2. The Flow Diagram of the Voltage Sweep Software Module

4.6.3. Probe Stand Movement


Reset the GPIBSet Parameters for A Single Voltage

Application

Set Basic Parameters

Place Device in Operating Mode

and Trigger

Read Back Voltage Value From The

Source

Check For Errors On The GPIB


The probe stand was manipulated in order to reach each test structure placed on the silicon carbide wafer. A Lab View software routine was developed to control the position of the probe stand. This is incorporated into the main control program as needed. Once the wafer is placed on the stand, the probe tip is placed on the first test structure or home position. The Lab View program then runs a voltage sweep and instructs the stand to move the required distance along the x-axis and y-axis of the wafer until it reaches the next structure to be tested. Another sweep is initiated and the process repeats itself for every test structure on the wafer.

Each ‘move’ or ‘parameter set’ command to the probe stand consists of writing a string to an address on the general-purpose interface bus (GPIB), then reading a status response. The computer and probe stand are attached to this bus via the data acquisition card installed in an expansion slot of the PC. Each device attached to the GPIB has a specific hardware address. The address of the probe stand is 17. This process is seen in Figure 4.6.3.1.

The Wentworth Labs MP-1000 probe stand responds to commands in the form of a single string. A list of commonly used commands is displayed in Table 4.6.3.1. A basic ‘write a string to the device’ then ‘read the status of the device’ algorithm was written and used to set parameters and send movement commands.

The first step is to initialize the GPIB. This was done using a single function built into the Lab View library. This must be done before every instruction that is given to the probe stand. Once initialized, a device parameter or movement instruction is then transmitted to the probe stand. A GPIB write function incorporated into the Lab View library was used to send these command strings. The instruction, along with an appended carriage return character, is sent over the GPIB to address 17 using the GPIB write function. A default time out of 5000 ms is used. This determines how long the system waits for the command to execute before it considers the instruction to have failed. The write function also has a mode input. This is used to determine the character that will terminate each transmitted command string. For our purposes mode 0 was used to append an end (EOI) character as the last character of the string. Other modes append a carriage return (CR) or an LF character with the EOI, a CR or LF without an EOI, or no EOI at all.

Next, the GPIB is monitored for the response from the probe stand. The GPIB read function from the Lab View library was used to read in two bytes of information from the bus. Again, the time out is set to 5000 ms and the mode set to 0. This mode expects no EOS to be sent with the status message. The response is then be displayed in an indicator type object. A list of possible responses is displayed in Table 4.6.3.2. Each portion of the ‘write a command then read response’ process is placed in a sequence structure. This ensures that each set of commands is carried out sequentially. The entire algorithm is placed in a while loop. This loop repeats the ‘write command then read response’ process until it receives a 3 (move complete) or 7 (down limit switch) status message back from the probe stand.



Figure 4.6.3.1. Flow Diagram of the Probe Stand Movement Software Module

COMMAND MEANINGSM Set units to metricSE Set units to EnglishSXnnnn Sets x index to ‘nnnn’ inches or millimetersSynnnn Sets y index to ‘nnnn’ inches or millimetersSZnnnn Sets z index to ‘nnnn’ inches or millimetersSH Sets the present location as the home locationMH Move to the home locationMU Move to the unload locationMXI+nnnn Move + ‘nnnn’ indexes along the x axisMYI+nnnn Move + ‘nnnn’ indexes along the y axis

Table 4.6.3.1. Wentworth MP-1000 Probe Stand Commands

RESPONSE # MESSAGE0 No message1 Task complete2 Invalid command3 Move complete4 Test complete5 Test aborted6 Edge sensor7 Down limit switch8 At next position9 Group instruction complete

Table 4.6.3.2. Status Messages from the Wentworth MP-1000 Probe Stand

5. TEST SPECIFICATION


Initialize the GPIB

Read status message from the GPIB

Write the character string to address 17 (Probe Stand)

Repeat process if command not successful


Testing began with each individual component and progress to overall system testing. Medici simulations were be used to validate the design of the C-V testing structure. In addition, all system hardware was tested for proper operation and precision using a digital multi-meter. The software calculation system was tested using manually collected data to verify equations and result representation. Control system outputs were verified using a digital multi-meter. Once each component was tested and functioning properly, the entire system was tested by characterizing a reference epitaxial film with known impurity concentration.

Table 5.1. summarizes the testing scheme we used. The tests represent both component level and system wide testing. Although some tests are simple in nature, each was crucial in our success in verifying overall system operation.

REQUIREMENTS EXCEL MEDICI CADENCE DIGITAL MULTI-METER

VOLTAGE SOURCE

REFERENCE EPITAXIAL

FILM

C-V Testing Structure Simulation

C-V Testing Structure Layout

Boonton 72BD Capacitance Meter

Manual Value Input

Keithley Input Voltage

Probe Stand Movement

System Testing

Table 5.1. Proposed Testing

Our most important testing was of system components individually. After performance verification of each component, system testing was done. The following test specifications provide a thorough and systematic approach for testing on both the ECE 4512 December 05, 2000


component and system levels. Strict adherence to these specifications insured proper system operation.


Capacitance per unit area and space charge region width for several different impurity-doping concentrations were calculated using an Excel spreadsheet. The Excel calculations were performed using the parallel plate capacitor model and used to determine a range of dimensions for the Medici simulation. Medici, a 2-D semiconductor device simulator, was used to maximize the performance of the C-V testing structure. Medici simulations were used to predict expected breakdown voltage, which was maximized to allow 400-V operation thus guarantee doping characterization of up to 10mm [11]. Medici simulations were also used to optimize the device size and geometry. Size and geometry were optimized in order to ensure that the device can be modeled using the parallel plate capacitor approximation [12]. In addition, device simulation must ensure the device capacitance falls within the dynamic range of the capacitance measurement hardware over the entire applied voltage range.


Cadence, a 1-D semiconductor device layout software suite, was used to represent the geometry and size of the C-V testing structure. Cadence used parameters defined by the Medici simulation to create a physical representation of the C-V testing structure, which were then used to create a fabrication mask.


The Boonton 72BD capacitance meter was tested to ensure measurement accuracy within 2%. Measurements of a given capacitor made by a Hewlett-Packard 4280A were used as a benchmark. In addition, the analog output signal used to represent the measured capacitance was validated by estimating the output magnitude through linear interpolation.

5.4. Manual Value Input

Data acquisition of the computerized control system was also validated. This was performed by applying an analog voltage with known magnitude to the Data Acquisition Card in the computerized control system. The control system’s digitized representation of the input signal magnitude was within 2% and guarantees proper functionality.

5.5. Manual Calculations

All calculations performed by the computerized control system were validated to 2 significant digits. A sample C-V data set of 100 points representing uniform impurity ECE 4512 December 05, 2000


concentration was used in this validation. First, calculations were performed on the sample data set and an impurity concentration vs. depth graph created. Visual inspection of the generated graph ensured general validity of the calculations. However, performing calculations manually on 10 of the sample data points ensured desired accuracy.

5.6. Keithley Input Voltages

The Keithley 237 High Voltage Source was used to apply a voltage to the device under test. It was important to establish that the Lab View program coupled with the voltage source was outputting the appropriate voltage values. The Keithley Corporation has provided documentation that their equipment is accurate to within 99.97%. From a break point within the control program, the Keithley source was instructed to execute a voltage sweep with a specified increment and delay between applied voltages. During the sweep, the front panel was observed to determine if the proper values were seen. After the sweep the Keithley source returned an array containing the applied voltages, increments, delays and total sweep time. The array was viewed to ensure proper values. This portion of the test was be done using seven different ranges with varying increments and delays. In the second portion of the test a Fluke digital multi-meter was used to verify the Keithley output. The Keithley source was instructed to hold five random voltages while the values are verified with the digital multi-meter. A difference of less than 1 VDC between the desired output voltages, between the front panel display reading and the digital multi-meter reading was necessary to ensure proper operation

5.7. Probe Stand Movement

The movement from one test structure to another was automated using a Lab View module within the control program. A reference wafer with the four known test structures was placed on the probe stand and the probe tip moved to start position. The program module then moves the probe tip from the starting structure to the specified location of the next test structure on the wafer. The wafer was observed using the built-in microscope to make sure the probe tip is positioned correctly on top of the test structure. The structures were placed at 10 mm to the right, 10 mm to the left, and 20 mm below the start position. This procedure was repeated for each known test structure location. The entire test was repeated a total of three times.

5.8. System Testing

Overall-system testing requires an epitaxial film with its SIMS and low-voltage C-V characterization results to as a reference. This film was be characterized with high-voltage C-V and the results compared against the reference. The portion of the high-voltage plot below 5mm was compared with the low-voltage C-V data and was within 20%, which ensured validity. Visual inspection ensured general trend agreement between high-voltage C-V and SIMS results for all depths.

6. TEST CERTIFICATIONS




An Excel spreadsheet was constructed to determine space-charged region width with respect to voltage applied to the testing structure. This phase of the simulation ensures that the system is to characterize epitaxial films of up to 10mm. Using equation 4.1.1.1 and various doping concentrations, the following graph was created:

Figure 6.1.1. SCR Width vs. Voltage

From the above spreadsheet, we determine that an applied voltage of –400 V is necessary to evaluate 10mm epitaxy for impurity doping concentration less than 5.0e15 cm-3 which is the target impurity doping concentration for most SiC applications. All subsequent calculations were performed with –400 V as the maximum applied voltage.

Capacitance per unit area was used to determine the minimum area of the testing structure and was simulated with an Excel spreadsheet. The dynamic range of the Boonton 72BD is 5pF – 200pF; therefore, the testing structure capacitance must be within this range under all conditions. The following chart was created using equation 4.2.1.1 and various doping concentration levels:



Figure 6.1.2a. Capacitance per unit area vs. Voltage

Figure 6.1.2b. Capacitance per unit area vs. Voltage (Expanded View)

From the above graphs, it is observed that capacitance per unit area decreases as the reverse bias is increased. The region of the graph near –400 V is of most importance to our design because it is the region with the smallest capacitance per unit area. The range of testing structure device areas must be large enough to ensure that the total capacitance at –400 V is greater than or near 5 pF.



Total testing structure capacitance for a range of testing structure radii was computed using the following graphs by equation 4.3.1.1, with each graph representing a different doping concentration:

Figure 6.1.3. Capacitance vs. Voltage (Nd = 5.0e14)






From the above graphs, it was determined that a testing structure device with a radius between 500mm and 350mm is necessary such that the device capacitance remains within the desired range.

Having determined the testing structure device area and voltage to be applied in order to characterize 10mm epitaxy, the Medici simulation can be performed to predict breakdown voltage. The following graphs show results from the Medici simulation [13].ECE 4512 December 05, 2000


Figure 6.1.9. C-V Testing Structure

Figure 6.1.10. C-V Testing Structure (with mesh)



Figure 6.1.11. C-V Testing Structure impurity doping concentration vs. Depth

Figure 6.1.11. C-V Testing Structure equal potential lines



Figure 6.1.11. Electric field in C-V Testing Structure

Figure 6.1.12. I-V results for the C-V Testing Structure



Most importantly for the Medici simulation results is the final I-V graph. Figure 6.1.12. shows us that our C-V testing structure design operates correctly below 500 V. This high-voltage operation allows our system to characterize epitaxial films up to 10mm.


As previously discussed, Cadence was used to layout the C-V testing structure. Parameters calculated in the previous section were used in Cadence to ensure that the fabricated device matches the simulated device.

Figure 6.2.1. Arial view of C-V Testing Structure as represented by Cadence

From the picture, one can see that an array of nine devices is used to assure the correct device size is present and the fabrication matches the simulated device [14]. The matrix contains devices with a radius ranging from 500 um to 300 um. Due to defects in the epitaxial layer, the 500 um device might incur early breakdown. This will not happen to all devices. If the user is not satisfied with the results of the first test, they can move to a smaller device size and re-initiate the test.


The Boonton 72BD capacitance meter was tested by measuring a number of standard capacitors. At the same time, the analog signal from the Boonton 72BD was tested using ECE 4512 December 05, 2000

500um to 300um


a digital multimeter. This was done to insure that the signal increased with increased capacitance. These same capacitors were then measured using a Hewlett-Packard 4280A. The two values were compared to measure the accuracy of the Boonton 72BD. In addition, a second test was preformed in which a voltage was applied to the voltage input terminals of the Boonton 72BD. This test was preformed to ensure this applied voltage did not cause an error in the capacitance readings. Figure 6.3.1. shows the measurements taken:

CAPACITANCE RATED IN Pf

72BD w/o voltage

72BD with voltage

4280A with voltage

ANALOG SIGNAL VALUE

% ACCURACY

1 1.38 1.38 1.35 .168V 2.2

5 4.50 4.50 4.53 .484V .66

143 140 140 138 .149V 1.5

181 176 176 180 .187V 2.2

680 655 655 667 .695V 1.8

Figure 6.3.1. Boonton 72BD Test Values

In doing the above tests it was determined that the Boonton 72BD is functioning correctly. The capacitance values measured were acceptable and the analog signal is working correctly. It was determined that the magnitude of the analog signal changes as the scale of the meter changes [15]. This is important for the interpretation of data. These test also determined that the voltages used for this project are not high enough to require that the Boonton 72BD be modified.

6.4. Manual Value Input

The Data Acquisition Card was installed in the CPU. The card came with a simple program that can be used to control the card. The first test done was installing this program and applying a voltage to the DAQ. This program was then used to make sure the card was functioning properly. Once this was completed, Lab View code was written to read an input from the card calculates capacitance and output this to an array. Once again, a DC voltage was applied to the DAQ and measurements were taken with the Lab View program. This test showed that the DAQ card was functioning correctly [16].



6.5. Manual Calculations

Manual calculations of a sample data set were performed using the equations for a Schottky Barrier Diode. The data set consisted of one hundred values of applied voltages and the measured capacitance. The formulas used for these calculations are as follows:

where A is the area, o is the permittivity of free space, Ks is the relative permittivity and q is the charge of an electron. The values for these constants used in the manual calculations are as follows:

A 0.000299 CM2

Permittivity of free space 8.854 x 10-14 (F/cm)Relative permittivity 10Charge of an electron 1.6030 x 10-19 (C)

Table 6.5.1. Constants

Using these constants and equations 6.5.1. and 6.5.2., manual calculations of the first ten data sets were performed. The results are as follows:

VOLTAGE CAPACITANCE DOPING LEVEL DEPTH-4.00E+01 1.80E-12-3.96E+01 1.80E-12 1.33E+17 1.47E-04-3.92E+01 1.81E-12 4.34E+16 1.46E-04-3.88E+01 1.81E-12 3.13E+16 1.46E-04-3.84E+01 1.82E-12 1.46E+17 1.46E-04-3.80E+01 1.82E-12 5.59E+16 1.45E-04-3.76E+01 1.82E-12 6.36E+16 1.45E-04-3.72E+01 1.83E-12 1.82E+16 1.44E-04-3.68E+01 1.83E-12 1.15E+17 1.44E-04-3.64E+01 1.84E-12 7.25E+16 1.44E-04-3.60E+01 1.84E-12 -2.80E+17 1.44E-04

Table 6.5.1. Results of Manual Calculations


eq. 6.5.1

eq. 6.5.2

rea


Once these manual calculations were performed, the entire data set was used to calculate doping concentration and depth. A graph of doping concentrations vs. depth was then created for visual inspection of the graph for general validity of the calculations [17].

Figure 6.5.1 Doping Concentration vs. Depth

6.6. Keithley Input Voltages

The interaction between the Lab View control program and the Keithley voltage source was tested using seven voltage ranges and five randomly selected test voltages. In the first test, the range of values was inputted into the Lab View program and the Keithley voltage source was instructed to perform a sweep from the desired start value to the desired stop value using a specified increment and delay [18], [19]. During each voltage sweep the front panel was observed to determine if the correct voltage was being applied and the proper increment made. After the sweep, the Keithley voltage supply returned to the Lab View control program the values over which it swept, the increment, the time


0.4 0.6 0.8 1 1.2 1.4 1.6

x 10-4

1015

1016

1017

1018

Depth (cm)

Dop

ing

Con

cent

ratio

n (c

m- 3)


between increments and the total sweep time. These values were viewed to ensure proper voltages, increments, and delay times. The values seen on the front panel and within Lab View agreed with the desired voltage levels to within + 1 V. The results can be viewed in Table 6.6.1. For the second portion of the test the start voltage and the stop voltage was inputted as the same number. The delay was set to ten seconds and the voltage viewed on the front panel of the Keithley as well as on a Fluke meter attached to the output of the Keithley voltage source. Each voltage value was measured three times. In each case the viewed and measured voltage levels agreed to the desired voltage to within 0.01 V. The results of this test can be viewed in Table 6.6.2.

RANGE INCREMENT DELAY RESULTS0:100 V 1 V 0.5 sec Correct

100:300 V 1 V 0.5 sec Correct100:300 V 2 V 1 sec Correct0:-100 V 1 V 0.5 sec Correct0:-100 V 10 V 5 sec Correct0:-400 V 10 V 1 sec Correct0:-400 V 1 V 2 sec Correct

Table 6.6.1 Results of The Keithley Voltage Sweep Test

VALUE DELAYFRONT PANEL MEASURED 1 MEASURED 2 MEASURED 3

-10 V 10 sec Correct -9.99 V -9.99 V -9.99 V-150 V 10 sec Correct -150.00 V -150.00 V -150.00 V-253 V 10 sec Correct -232.99 V -232.99 V -232.99 V-339 V 10 sec Correct -339.00 V -339.00 V -339.00 V-412 V 10 sec Correct -412.01 V -412.01 V -412.01 V

Table 6.6.2. Results of The Keithley Single Voltage Test

6.7. Probe Stand Movement

The movement of the probe stand was tested using a reference paper wafer with four mock test structures drawn at known locations. The structures were drawn at a home location, 10 mm to the right of the home location, 10 mm to the left of the home location and 20 down from the home location. The Lab View program was instructed to move to each position and the microscope viewed to determine if the probe stand was placed over the correct location. The probe stand was moved to the home location and the procedure repeated three times. In each case, the stand was moved to the correct location on the wafer [20].



6.8. System Testing

The system as a whole was tested by first characterizing a thinner epitaxial layer using a test sample in which a low voltage C-V characterization was previously preformed. The results of this low voltage C-V characterization are shown in figure 6.8.1. It can be seen here that a voltage of 100V penetrates to a depth of about 4.3 microns.

Figure 6.8.1 Depth Vs Doping Low Voltage C-V Characterization

This data for this graph was taken by Dr. Los using a low voltage C-V characterization system at Mississippi State University in EMRL. This curve was used as a reference for which the data from our system was compared. Our data should stay within a range of plus or minus twenty percent.

The early tests of our system produce relatively good results at low voltages (1V – 90V). However, at higher voltages, the characterization suffered effects due to noise. This noise produced a rough jagged curve near the end of the doping versus depth graph. After analysis of these results, we discovered that the capacitance being read was not accurate enough. The noise produced on the graph was due to the differential change in capacitance.

To fix this issue we allowed the Boonton to operate in the auto range mode. Doing this required that the Boonton send a signal to the DAQ which gives the current range setting. ECE 4512 December 05, 2000


This input was then used in Lab View to determine the correct capacitance level. This allows the smaller capacitances levels to be read with more accuracy. Figure 6.8.2 illustrates this point by showing that on the 200pf range 1V represents 100pf while on the 20pf range 1V represents 10pf. This allows for greater decimal accuracy in the lower capacitance levels where we were having a problem with noise.

Figure 6.8.2 Range Explanation

This change helped our system greatly. We were now able to characterize up to 100V and still be in the accuracy range of plus or minus 20 percent. However, we were still having a problem with noise at the higher voltages (200V-400V). Upon further analysis, we discovered that the problem was still with the difference in the capacitance readings at high voltage levels being too small. In order to fix this problem we would have to initiate a non –linear step size for our voltage sweep. This would allow for greater voltage changes in the higher voltage ranges causing the capacitance values to be greater in difference.

This change smoothed out our depth versus doping graph and we were now ready to validate the operation of our system. This validation took place by comparing our low voltage C-V characterization of the same device as Dr. Los. In order to meet our design constraint we must be within plus or minus 20 percent of Dr. Los’s graph. Figure 6.8.3 shows our results compared to those of Dr. Los. It can be seen here that our results stay within the constrained area.


1 V = 100 pF

1 V = 10 pF

200 Range

20 Range


Figure 6.8.3 Validation of Results

The above results validate our systems operation. From this we can tell that the system is now operating the way in which we specified it would. However, this is just for voltages lower than 100V. In order to meet our all of our objectives our system must character higher voltages as well. This was also tested using a structure with a thicker epitaxy layer. These results are shown in Figure 6.8.4. For this graph, a final voltage of 350V incremented in a non-linear step size was used. The results of this graph show that the C-V characterization system also works for higher voltages. Here we were able to accurately characterize 7.5-micron layer.

The low voltage system and high voltage system are again compared in Figure 6.8.5. The profiles for the same device match closely. This is demonstrated in Figure 6.8.6 where error bars at +20% have been place over the profiles. The systems do not deviate by more than 20%.


1E+15

1E+16

1E+17

0.5 1.5 2.5 3.5 4.5Depth (um)

ADO699-10-2

Low Voltage

Upper Deviation

Lower Deviation


Figure 6.8.4 High Voltage C-V Characterization

Figure 6.8.5 Comparison of High Voltage and Low Voltage System



Figure 6.8.6 Comparison of Two Systems With 20% Error Bars

7. SUMMARY

As silicon (Si) microelectronic devices reach physical device limitations, it is fundamentally important for a novel semiconductor to serve as a replacement in many niche applications. Silicon carbide (SiC), a wide-band gap, compound semiconductor capable of high-temperature, high frequency operation, is poised to be that coveted material. As researchers develop and refine epitaxial growth techniques, the most fundamental step in SiC microelectronic device fabrication, it is important to have a characterization system for these films. Commercial unavailability of a characterization system that is capable of operating at the high-voltage levels necessary to characterize thick epitaxy prompted our team to undertake this project.

The most important aspect of our design has been the design of a C-V testing structure that is capable of withstanding high-voltage levels required characterizing thick epitaxial films. Using well-known 1-D parallel-plate capacitor model equations, we have designed a testing structure that we believe will operate at the necessary –400 V. Operation of this device was also verified using a 2-D device simulation tool.

Practicality of our system will be increased by the addition of automation to the data collection, data analysis, and probe stand movement of our system. This automation will require a technician to place the epitaxy on the probe stand, initiate the test, and simply wait for the results. Eliminating human interaction with the testing equipment will increase the reliability, decrease the characterization time, and decrease associated costs. ECE 4512 December 05, 2000


Upon completion of this document, our team feels that it has completed a successful project. We were successfully able to take high voltage C-V measurements and characterize the thicker layers desired by researchers. Our project, completed and fully functional, will be an asset to both Mississippi State University and the SiC research community.

8. FUTURE WORK

As researchers continue to develop the SiC used in semiconductor devices, there is no doubt that edge termination techniques will become more precise. With this future improvement of the testing structure design, our system could be modified to operate up to a hardware limitation of -600V. A new testing structure would need to be designed that took into account the lower capacitances and higher voltage values produced by this environment.

Another future improvement would be to completely automate the system, eliminating human contact with the SiC wafers. Multiple characterizations could then take place without human interaction.

9. ACKNOWLEDGMENTS

We would like to thank Dr. Mike S. Mazzola for his substantial support and feedback during the development of this project. We would also like to express our appreciation to Dr. Jeff Casady for answering our numerous questions and supplying us with information on testing structures. In addition, we would like to thank Rankin Rouse and Jana Dufrene for their advice and help in writing this paper. We also acknowledge MCASP for funding this project.



10. REFERENCES

[1] V. Shields, “What is Silicon Carbide”, http://vshields.jpl.nasa.gov/SiC.html, Jet Propulsion Laboratory, 4800 Oak Grove Drive Pasadena, California, 1995.

[2] M. Mazzola, S. Saddow, and A. Schner, "Close Compensation of 6H and 4H Silicon Carbide by Silicon-to-Carbon Ratio Control," Material Science and Engrineering B, B61-62, p. 155, Oct. 1999.

[3] S.E. Saddow, M.S. Mazzola, S.V. Rendakova, and V.A. Dmitriev, "Silicon Carbide CVD Homoepitaxy on Wafers With Reduced Micropipe Density," Material Science and Engineering B, B61-62, p. 158, Sept. 1999.

[4] D.A. Neamen, Electronic Circuit Analysis and Design. Boston, MA: McGraw-Hill, 1996, p. 13.

[5] M. Mazzola, “Research at EMRL”, http://www.ece.msstate.edu/emrl, Emerging Materials Research Lab, 216 Simrall Hall, Mississippi State University, 1999.

[6] C. Harris, “Why Silicon Carbide?”, http://www.imc.kth.se/sic/whysic.htm, International Microelectronics Center, Electrum 233, 164 40 Kista, Sweden, 1999.

[7] M.S. Mazzola, S.E. Saddow, and A. Schner, "Close Compensation of 6H and 4H Silicon Carbide by Silicon-to-Carbon Ratio Control," Material Science and Engrineering B, B61-62, p. 155, Oct. 1999.

[8] M. Bathnagar, P.McLarty, and B.J. Baliga, “Silicon carbide high-voltage (400 V) Schottky barrier diodes,” IEEE Electron Device Lett., vol. 10, p. 501, Oct. 1992.

[9] J. R. O’Connor and J. Smiltens, Silicon Carbide: A High Temperature Semiconductor. New York, NY: Pergamon Press, 1960.

[10] T.I. Chappell and C.M. Ransom, “Modification to the Boonton 72BD capacitance meter for deep-level transient spectroscopy applications,” Rev. Sci. Instrum., vol. 55, p. 200, Feb. 1983.

[11] Philip F. Kane and Graydon B. Larrabee, Characterization of Semiconductor Materials. New York, NY: McGraw-Hill, 1970.

[12] J.B. Casady and R.W. Johnson, "Status of silicon carbide as a wide bandgap semiconductor for high-temperature electronics: a review," Solid-State Electronics, Vol. 39, No. 10, pp. 1409-1422, Oct. 1996.



[13] Medici: Two-Dimensional Device Simulation Program Version 2000.2 User’s Manual. Fremont CA: Avant! Corporation, July, 2000.

[14] I, Hatirnaz, “Cadence Tutorial,” http://vlsi.wpi.edu/cds/explanations/spec.html, Worchester Polytechnic Institute, Worchester, MA, November, 1998.

[15] Instruction Manual: Model 72BD Digital Capacitance Meter. Randolph, NJ: Boonton Electronics Corporation, p.2-2 – 2-4, 1987.

[16] LabVIEW – Proven Productivity. Austin, TX: National Instruments Corporation, p. 14-17, 30 December 1997.

[17] M.N.O. Sadiku, Elements of Electromagnetics. New York, NY: Oxford Press, p. 115-118, 1995.

[18] Keithley 236/237 Source Measure Units Applications Overview. Cleveland, OH: Keithley Instruments Inc., p. 23, 1999.

[19] Keithley Model 236/237/238 Source Measure Unit Operator’s Manual. Cleveland, OH: Keithley Instruments, Inc., p.1-1 – 1-27, 3-11 – 3-92, 1999.

[20] Wentworth Labs MP-1000 Probe Stand Manual. New York, NY: Wentworth Labs Inc., 1990.


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