research article a 3.9 s settling-time fractional...

Research ArticleA 39120583s Settling-Time Fractional Spread-Spectrum ClockGenerator Using a Dual-Charge-Pump Control Technique forSerial-ATA Applications

Takashi Kawamoto1 Masato Suzuki2 and Takayuki Noto2

1Hitachi Central Research Laboratory 1-280 Higashi-Koigakubo Kokubunji-shi Tokyo 185-8601 Japan2Renesas Electronics Corporation Tokyo 185-8601 Japan

Correspondence should be addressed to Takashi Kawamoto takashikawamotohvhitachicom

Received 3 October 2014 Accepted 5 January 2015

Academic Editor John N Sahalos

Copyright copy 2015 Takashi Kawamoto et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique isdeveloped for serial-advanced technology attachment (SATA) applications The dual-CP architecture reduces a design area to 60by shrinking an effective capacitance of a loop filterMoreover the settling-time is reduced by 4120583s to charge a current to the capacitorby only main-CP in initial period in settling-time The SSCG is fabricated in a 013120583m CMOS and achieves settling time of 391 120583sfaster than 811 120583s of a conventional SSCGThe random jitter and total jitter at 250 cycles at 15 GHz are less than 32 and 107 psrmsrespectively The triangular modulation signal frequency is 315 kHz and the modulation deviation is from minus5000 ppm to 0 ppm at15 GHz The EMI reduction is 100 dB The design area and power consumption are 300times 700 120583m and 18mW respectively

1 Introduction

Serial Advanced Technology Attachment (SATA) is widelyused as a low-cost high-speed interface for external storagedevices like HDDs and optical disc drives (ODDs) such asblu-ray discs DVDs and CDs However electromagneticinterference (EMI) is a particular problemwith SATA devices[1] One approach to reducing the EMI is to apply a spread-spectrum clock generator (SSCG) to a SATA-PHY

Figure 1 shows a common block diagram of the SATA-PHY It consists of a parallel-to-serial converter (PS) aspread-spectrum clock generator (SSCG) a driver (DRV)a receiver (RCV) a clock and data recovery (CDR) circuitand a serial-to-parallel converter (SP) The SSCG generatesa transmission clock signal (119865VCO) The PS converts a trans-mission parallel data (TD) into a transmission serial data byusing the 119865VCO This transmission serial data is transmittedby the DRV The 119865VCO frequency should be modulated toreduce the EMI in accordance with the SATA specification[1] A received serial data is inputted to the CDR via theRCV The CDR generates the recovery data (DATA) and

recovery clock (CLK) from the received data The serial-to-parallel converter (SP) converts from the DATA to thereceived parallel data (RD) by using the CLK In this SATA-PHY the SSCG is applied a fractional SSCG because ofa large EMI reduction [2ndash18] The fractional SSCG shouldbe narrow loop bandwidth because the quantized noiseoriginated from a ΣΔ modulator is removed Therefore thefractional SSCG essentially has large design area and longsettling-time There were some approaches to reduce designarea in previous works [15 17 18] However those could notconsist with shrinking design area shorting settling-timeand reducing EMI and jitter Therefore we introduced acapacitance multiplication technique to the fractional SSCGand then we proposed fast-settling technique by controllingthe CP

Figure 2 depicts the states defined by the SATA specifi-cation and the SATA-PHY power consumption [1] In a syncstate a communication is successfully established between ahost and a device In the sync state the SATA-PHY operatesthe SSCG The slumber state is a standby state The SATA-PHY can stop the SSCG because allowed wake-up period

Hindawi Publishing CorporationJournal of Electrical and Computer EngineeringVolume 2015 Article ID 765485 13 pageshttpdxdoiorg1011552015765485

2 Journal of Electrical and Computer Engineering

SSCG

CDR

DRV

SP

PS

RCVCLK

DATA

TX

RX

TD

RD

SATA-PHY

FVCO

Figure 1 Block diagram of SATA-PHY

Sync Partial SyncSyncSlumberPHY state

PHY power consumptionSSCG output signal

(a) Conventional



(b) Proposed

Figure 2 Proposed low power SATA-PHY operation

from slumber to sync is a long periodThepartial state is also astandby state However allowed wake-up period from partialto sync is a short period of less than 10 120583s Thus it cannotstop the SSCG because the settling time of the SSCG is longerthan 10 120583s as shown in Figure 2(a) The SATA-PHY is set tothe partial state many times in HDD and ODD applicationsIf the SSCG can achieve a settling time less than 10 120583s theSATA-PHY can stop the SSCG in partial state as shownin Figure 2(b) This is attractive for portable applicationsbecause of saving power To achieve this operation the SSCGhas to have a settling time of less than about 4 120583s taking thewake-up time of the other blocks into consideration Thisstringent settling time requirement is far shorter than that ofa conventional SSCG

Figure 3 shows a block diagram of a conventional SSCGbased on a fractional PLL [3 4 6 10ndash20] It consists of aphase frequency detector (PFD) a charge pump (CP) a 3rdorder loop filter (LF) a voltage controlled oscillator (VCO)a multimodulus divider (MMD) a programmable counter(PGC) a ΣΔ modulator (ΣΔ) and a wave generator (WG)The WG is a logic circuit and generates a triangular waveas a spread-spectrum modulation The ΣΔ modulates thetriangular signal and then generates divide ratio (119873) thatthe average of the 119873 is modulated by the triangular wave

WG

N

PFD CPLF

VCO

MMDPGC

UP

DN

M

FVCOFREF

FB FP

ΣΔ

ICP

R1

R2

C1 C2 C3

VC

Figure 3 Conventional SSCG block diagram

The 119865VCO frequency is thus modulated by the triangularwave This SSCG can reduce EMI more substantially thanother SSCGs because the linearity of the modulation can beobtained accurately by utilizing the logic circuits [2ndash7]

This SSCGhas twomain jitter sources One is aVCO jitteroriginating from the thermal and flicker noise of the MOStransistors The other is a ΣΔ modulator jitter originatingfrom the quantization noise of the ΣΔmodulator The SSCGoutput jitter is the sum of these two jitters To remove thequantization noise that is high-pass characteristics the loopbandwidth should be designed narrow Thus the settling-time is necessarily longer and the design area is large

Several approaches have been presented for reducing thedesign areaThe high-resolution fractional divider techniqueshifts the modulator quantization noise to the higher fre-quency side and so it achieves wider bandwidth [5] Howeverit is difficult to reduce the EMI by much because spuriousjitter originating from the high-resolution fractional dividerremains in the modulation bandwidth All-digital SSCGshave been presented as a means of substantially reducingdesign area [17 18] However their output jitter is still largebecause their digitally controlled ring oscillators generatelarge jitter and it is difficult to operate them accurately if thereare PVT variationsThe capacitancemultiplication techniquehas been presented to reduce the design area as an approachin which the operation is based on that of a conventionalSSCG [2 7 20] However the settling time is necessarily longbecause the loop bandwidth is set to be narrow

To achieve a low-cost SATA-PHY suitable for portableapplications the design area settling-time power consump-tion jitter and EMI must all be reduced at the same timeTo consummate these aggressive demands we have proposedthe dual-CP SSCG architecture with fast-settling CP controltechnique

The rest of the paper is organized as follows Section 2describes the overall dual-CP SSCG architecture in detailSection 3 presents the fast-settling CP control technique wehave developed to achieve short settling time Section 4describes a CP circuit design to achieve a dual-CP architec-ture that is robust against PVT variations Section 5 describesthe VCO with high-frequency limiter Section 6 presents

Journal of Electrical and Computer Engineering 3

WG

N

PFD CPMLF

VCO

MMDPGC

CPS

UP

DN

CNT

M

ST

FVCOFREF ICPM

R1

R2

C2 C3

VC

ΣΔ

FB FP

(1 minus 120572)C1

TSVCS

VCM

ICPS =120572ICPM

Figure 4 Block diagram of the proposed dual-CP SSCG with fast-settling CP control technique

measurement results for evaluation purposes and Section 7concludes with a short summary of the key points

2 Overall Dual-CP Architecture

Figure 4 shows our dual-CP SSCG architecture with fast-settling CP control technique to reduce the design areasettling time power consumption jitter and EMI all at thesame time It includes a conventional SSCG an additional CP(CPS) and a counter (CNT) A third-order ΣΔ modulatorand a third-order low-pass loop filter are applied to reducethe ΣΔ modulator jitter The PFD compares a phase of thereference clock signal (119865REF) with that of the feedback clocksignal (119865

119861) and then generates up and down signals (UP DN)

Two CPs a main CP (CPM) and an auxiliary CP (CPS) areapplied to fulfill the need for high capacitance via the use of acapacitancemultiplierWhen theUP is generated by the PFDthe CPM charges the 119862

1by the current (119868CPM) and the CPS

discharges the 1198621by the current (119868CPS) In this architecture

the open loop transfer function of the main CP (CPM) path(119865CPM(119904)) is given by

119865CPM (119904) = (119868CPM (11986211198771) 119904 + 1)

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+ (1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(1)

The open loop transfer function of the auxiliary CP (CPS)path (119865CPS(119904)) is given by

119865CPS (119904) = 119868CPS

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+(1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(2)

If the 119868CPM = 120572 lowast 119868CPS and 120572 is less than 1 the open looptransfer function from the PFD to the VCO control voltage(119881119862) is given by

119865 (119904) = (119868CPM (11986211198771) 119904 + 119868CPM (1 minus 120572))

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+(1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(3)

The zero of the open loop transfer function is given by

119865119906 =(1 minus 120572)

11986211198771

(4)

On the other hand that of the conventional one is givenby

119865119906 =1

11986211198771

(5)

Our dual-CP technique therefore results in1198621being (1minus

120572) times smaller than that of the conventional oneThere is a key design point in this dual-CP architecture

Figure 5 shows the difference in the CP and VCO character-istics for a conventional SSCG and proposed dual-CP SSCGThe locking range which means the 119881

119862range at which the

charge current (119868CPP) is almost the same as the dischargecurrent (119868CPN) is wide because the SSCG loop has a tolerancefor the current difference ldquo119868CPP minus 119868CPNrdquo in the conventionalSSCG as shown in Figure 5(a) The SSCG does not have tolock out of the lock range which means that the CP currentdifference between the 119868CPP and the 119868CPN is large Howeverin this case the jitter originating from CP current differencebecomes large Thus the SSCG output jitter becomes largerTherefore to meet the SATA jitter specification the SSCGshould lock into the lock range In a conventional SSCG thelocking-point can thus be designed at a higher voltage area toreduce the VCO jitter because the low VCO sensitivity (119870

119881)

brings about in the low VCO jitterIn proposed dual-CP SSCG the jitter originating fromCP

is more sensitive than that of the conventional one Thus thelock range becomes narrower as shown in Figure 5(b)This isbecause the SSCG loop is affected by the current differencesldquo119868CPMP minus 119868CPSNrdquo and ldquo119868CPMN minus 119868CPSPrdquo This means that itis important for the current difference to have a sufficienttolerance for PVT variations The narrow lock range makesit possible to design the VCO sensitivity (119870

119881) to be higher

than that of the conventional oneFigure 6 shows a typical example of the open loop

transfer function As aspect of the EMI the loop bandwidthshould be designed wider because harmonic elements ofthe modulation triangle signal that fundamental frequencyis 315 kHz can pass through the loop bandwidth In ourprevious work the 15th harmonics of the triangular signalshould be passed in order to obtain the large EMI reduction[3] However as aspect of the jitter as the loop bandwidthis wider the jitter originated from ΣΔ modulator quantized


Freq

uenc

y (G

Hz)

Range VCO

Target freq

Target current Lock-point

ICPP

ICPN

CP cu

rren

t (120583

A)

VC (V)

(a) Conventional SSCG

Freq

uenc

y (G

Hz)

Range VCO

Target freq

Target current

Lock-point

ICPMP

ICPMN

ICPSPICPSN

CP cu

rren

t (120583

A)

VC (V)

(b) Proposed dual-CP SSCG

Figure 5 The explanation of CP current characteristics and VCO frequency current characteristics of the conventional SSCG (a) and theproposed dual-CP SSCG (b)

Frequency (Hz)1

Gai

n (d

B)

200

100

0

minus100

minus200

1k 1M 1G

Figure 6 SSCG open loop frequency characteristics

noise is larger And the jitter originated from the VCO phasenoise is larger as the loop bandwidth is narrower Thereforethe loop bandwidth is designed at about 650 kHz This iswide enough to meet the jitter specification and reduce theEMI but this structure cannot achieve a settling-time of lessthan 4 120583s Such a settling-time is achieved by utilizing the CPcontrol technique we describe in Section 3 It is importantfor the SSCG to have a sufficient tolerance for CP currentvariation due to PVT variation

Figure 7 shows the effects of the CP current variationon the loop design The current difference ldquo119868CPM minus 119868CPSrdquoaffects the phase margin very little as shown in Figure 7(a)Even if the current difference varies minus50 the effect on thephase margin is less than 5 as shown in Figure 7(a) On theother hand the current ldquo119868CPMrdquo or ldquo119868CPSrdquo has a huge influenceimpact on the loop bandwidth Even if the different currentvaries minus50 the phase margin is affected at less than 50 asshown in Figures 7(b) and 7(c) The CP should be designedsuch that the variation of the current difference shouldremain less than about plusmn40 taking the jitter specificationinto considerationThemain CP current (119868CPM) and auxiliaryCP current (119868CPS) have a huge impact on the loop bandwidthand phase margin The variation of the 119868CPM and 119868CPS shouldbe designed at less than plusmn20 taking the jitter specificationand loop stability into consideration A CP design that isrobust against PVT variation is presented in Section 4

3 Fast-Settling CP Control Technique

We have developed a fast-setting CP control techniqueFigure 8 shows the concept of proposed fast-settling CPcontrol technique In the conventional SSCG the settling-time is long because the large 119862

1is charged by the small CP

current as shown in Figure 8(a) [7] As shown in Figure 8(a)in this SSCG a charging speed (ΔCONV) that means a slopein the settling period is given by

Δ conv =(1 minus 120572) 119868CPM1198621

(6)

In our dual-CP SSCG architecture the 1198621is smaller than

that of the conventional one Thus in the dual-CP SSCG if acharged current is same the charging speed is faster than thatof the conventional one In the dual-CP SSCG the differentialcharge current is small however the 119868CPM is larger than thecharge current of the conventional SSCGThus the chargingspeed can be faster if the only CPM charges the119862

1 As shown

in Figure 8(b) in this case the charging speed (Δ PROP) isgiven by

Δ PROP =119868CPM1198621

(7)

The charging speed (Δ PROP) achieved with our techniqueis 1(1 minus 120572) times faster than the conventional one In this


minus40 minus20 0 20 40minus60

1200Lo

op b

andw

idth

(kH

z) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM minus ICPS ()

(a)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM ()

(b)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPS ()

(c)

Figure 7 The effect of the loop bandwidth and phase margin due to CP parameters (a) The effect by different current (119868CPM minus 119868CPS) (b) Theeffect by CPM (119868CPM) (c) The effect by CPS (119868CPS)

case the CPS activates in the middle of the settling periodIf the CPS activates at early in the settling period the effectof the boosting charge by the CPM is weak On the otherhand if the CPS activates at late in the settling period a largeovershoot may occur because the operation is unstable andsettling period is prolonged rather than shortenedMoreoverthe MMD cannot operate due to the overshoot and then theSSCG falls into a malfunction as shown in Figure 8(b) Toovercome this trade-off the VCOwith high frequency limiteris applied to the SSCG as shown in Figure 8(c) [3] When theCPS is activated the overshoot occurs However the 119865VCOfrequency cannot be more than 22GHz which is the MMDmaximumoperating frequency by the high frequency limiterTherefore even if the overshoot occurs the SSCG can belocked To reduce the settling period the CPS activation timeis as long as possible However the settling period becomeslonger due to large dumping if theCPS is activated after cross-over 15 GHz of the SSCG output signalThus the CPS shouldbe activated before cross-over 15 GHz of the SSCG outputsignal Moreover even if the CPS is activated right beforecross-over 15 GHz the large dumping might occur in thecase that the phase difference between the reference clockand the feedback clock becomes large It is difficult to controlthe phase difference at the CPS activation point Thus theCPS should activate relative less than cross over 15 GHz tohave a margin of the lock period of the phase difference Inour proposed SSCG the CPS activation time is set to 1120583s toreduce settling period when the SSCG achieves the settling

period of less than 4 120583s As shown in Figure 4 the CPS iscontrolled by the CNT The CNT is the counter that makesthe CPS activation time by counting the 119865REF As shown inFigure 8 the SSCG is activated when the standby signal (119879

119878)

is set to low At this time the CPS is not activated because the119879119878is set to high After a certain period that is made by the

CNT the 119879119878is set to low and the CPS activates

Figure 9 shows the behavior simulation results for thesettling time This simulation is not designed for a settlingtime of less than 4 120583s but designed to verify the fast settlingperiod by using the CPS control The conventional dual-CPSSCG achieves a settling time of less than about 22 120583s in thissimulation On the other hand when only the CPM operatesthe overshoot occurs and the operation is unstable Whenwe apply our CP control technique to this SSCG so that theCPS is activated at 3 120583s the settling behavior is the same asthat when only the CPM is activated before 3 120583s After theCPS is activated at 3 120583s the settling behavior deviates fromthat when only the CPM is activated and then directed tothe target frequency slowly After small overshoot occurs theSSCG becomes locked at 18120583s In this case our techniqueenables the settling time to be shortened to about 4 120583s whichis almost the same as the period during which the CPS isstopped As the CPS is stopped for as long a time as possiblethe settling time can be shortened However this techniquehas little effect when the CPS is activated after the overshootoccurs Moreover large overshoot may occur due to a smalldamping factor and the settling time may be longer than that


ST

CPS starts

Overshoot

Lock

Unlock

Time (s)

SSCG settling start

CPS starts

OvershootLock

MMD operating limit

MMD operating limit

(a) Conventional

(b) Proposal wo limiter

(c) Proposal w limiter

15GHz

15GHz

15GHz

Δprop = ICPMC1

Δprop = ICPMC1

FVCO

FVCO

FVCO

TS

TS

Δconv = (1 minus 120572)ICPMC1

4120583

Figure 8 Explanation of proposed fast-lock dual-CP SSCG settling operation of the conventional SSCG (a) and the proposed dual-CPcontrolled technique without VCO high frequency limiter (b) and with limiter (c)

0 10 20 300

20

15

10

05

Only CPM operationProposed fast-lockConventional dual-CP

Proposed settling time

Conventional settling time

Freq

uenc

y (G

Hz)

Time (120583s)

ICPMC1(1 minus 120572)ICPMC1

Figure 9 Simulation results of the conventional and proposedsettling time

without our techniquersquos function when the CPS is activatedjust before the overshoot appears Therefore the timing isset such that the CPS is activated just before the overshootoccurs This timing is made by counter that counts 119865REF Inour design the CPS is activated at about 10120583s taking the CPcurrent and filter capacitance into consideration

4 Dual-CP Circuit Design

Figure 10 shows a circuit diagram of the CPM and theCPS The PFD output signals (UP UPB DN and DNB) are

connected to the gate of the switch MOSs (M8 M21 M9M10 M16 M15 M17 and M18) The VB is connected to theband-gap reference (BGR) and the reference current (119868CP) isgenerated as M1 drain current The main CP current (119868CPMPand 119868CPMN) and the auxiliary CP current (119868CPSP and 119868CPSN) aregenerated from the 119868CP by utilizing the currentmirror and aregiven by

119868CPMP119868CP=1198821198725

1198821198723

119868CPMN119868CP=1198821198727

1198821198726

119868CPSP119868CP=11988211987213

1198821198723

119868CPSN119868CP=119882lt14

1198821198726

(8)

The transistor width is described as119882119872119873

where119873 is thetransistor number Thus the CP current ratio (120572) is given by

120572 =119868CPSP119868CPMP=11988211987213

1198821198725

=119868CPSN119868CPMN=11988211987214

1198821198727

(9)

Figure 11 shows the simulation results for the CPM andCPS chargedischarge characteristics The simulation con-ditions are that the process voltage and temperature aretypical 135 V and minus40∘C respectively The horizontal axis isthe control voltage (119881

119862) and the vertical axis is theCP current

PMOS currents (119868CPMP and 119868CPSP) appear as absolute values inthe Figure In our work the CPM current (119868CPMP and 119868CPMN)and CPS current (119868CPSP and 119868CPSN) are designed at 44 120583A and32 120583A respectivelyTherefore the designed current differencevalue is 12 120583A and 120572 is 76 In general a PMOS transistor hasaccurate saturation characteristics and a narrow saturationregion and an NMOS transistor has inaccurate saturationcharacteristics and a wide saturation region In this work


UP

DNB

VB

DNB

UP

CPSCPM

M1 M2

M3 M4

M6

M7

M5

M21

M8

M9

M10

M11

M12

M14

M13

M15

M16

M17

M18

M19

M20

UPB

DN

DN

UPB

ICPSP

ICPSN

ICPMPICP

ICPMN

VCSVCM

Figure 10 Circuit diagram of CP The CP consists of the CPM and the CPS

0 02 04 06 08 10 12 14

50

40

30

20

10

0

ICPSN

ICPMPICPMN

ICPSP

Δ 1222 120583A

Δ 953120583A

ICPMP minus ICPSN 1222 120583AICPMN minus ICPSP 953120583A

VC (V)

CP cu

rren

t (120583

A)

Design different current 1200 120583A

Figure 11 Circuit diagram of CP The CP consists of the CPM andthe CPS

these problems are resolved merely by using a simple circuitdesign because other solutions such as using an OpAmpor other additional circuits increase design area and powerconsumptionThemain reason for the difference between thedesign targets and simulation results is the channel lengthmodulation The NMOS length is designed to be long todecrease the effects of channel length modulation Figure 12shows the simulation results for the current differencebetween themain CP and the auxiliary CP Since themain CPcurrent and the auxiliary CP current are designed at 44 120583Aand 32 120583A respectively the design target for the currentdifference is 12 120583A As shown in Figure 12 the variation of thecurrent difference is designed at less than plusmn20

02468

10121416

ff fs typ sf ss

Process

Target

165Vminus40∘C165V125∘C135Vminus40∘C135V125∘C


I CPM

minusI C

PS(120583

A)

ICPMP minus ICPSN ICPMN minus ICPSP

1200 120583A

Figure 12 Simulation result of different CP current (119868CPMP minus 119868CPSN119868CPMN minus 119868CPSP) Design target current is that 119868CPM (119868CPMP and 119868CPMN)and 119868CPS (119868CPSP and 119868CPSN) are 44mA and 32mA respectively

And then this CP has offset between charge current anddischarge current This offset causes jitter There are sometechniques to overcome the offset However these techniquescause large power In our SSCG the main jitter sources areVCO and ΣΔ modulator and jitter is designed sufficientlyeven if the CP has offset Therefore the CP circuit as shownin Figure 10 is applied to prefer the power to the jitter


Delay Delay DelayVIC

CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON

Figure 13 VCO block diagram [3]

M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b

ICM = ICNT minus a lowast IMIP = ICNT minus ICM

= ICNT ICNT lt IM= (1 minus b) lowast ICNT + ab lowast IM ICNT gt IM

Figure 14 VIC circuit diagram [3]

5 VCO with High Frequency Limiter

The MMD can operate at less than 22GHz under the worstcondition If the SSCG output signal frequency exceeds22 GHz in the settling period due to the dual-CP controltechnique the SSCG falls into an unlocked state To preventthis malfunction a VCO with a high frequency limiter isapplied as shown in Figure 13 [3] This VCO consists ofa voltage-current converter (VIC) and a current-controlledoscillator (CCO) as shown in Figures 14 and 15 Figure 16shows the explanation of the VCO with the high frequencylimiter The VIC converts a control voltage (119881

119862) to a control

current (119868119875) The VIC performs a high current limiter The

CCO generates output clock signals (119865VCO and 119865VCOB) wherethe frequency is controlled by the 119868

119875Therefore this VCO can

perform the high frequency limiter In the VIC1198721 convertsthe 119881119862to an 119868CNT An 119868CM that is calculated as 119868CNT minus 119868119872 is

generated at1198724 drain nodeThe 119868119875that is a11987211 drain current

is calculated as 119868CNTminus119868CMWhen the 119868CNT smaller than the 119868119872

the 119868119875is the 119868CNT because the 119868CM is zero On the other hand

when the 119868CNT larger than the 119868119872 the 119868

119875is calculated as (1 minus

119887)lowast119868CNT+119886119887lowast119868119872 that is nearly 119886119887lowast119868119872The 119886 and 119887 are current

mirror ratios of1198723 1198725 and1198727 1198729 respectively The 119868119875is

expected constant current against the119881119862 However if the 119868CNT

that is the1198721 drain current is different from the 119868CNT that is11987210 drain current the 119868

119875may not be constant The 119868CNT that

is11987210 drain current is likely to be smaller than one of the1198721

M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON

Figure 15 Delay cell circuit diagram [3]

because the11987210 has heavier loads that are the1198729 and11987211than the1198721 In this case the 119868

119875characteristics have negative

slope against the119881119862 These negative characteristics cause that

SSCG falls into the unlock state because the SSCG loop maybe positive feedback To prevent from this malfunction thecurrent mirror ratio between the1198727 and1198729 is 1 119887 in orderthat the 119868

119875characteristics have positive slope against the 119881

119862

when the 119868CNT is larger than 119868119872


I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO

Figure 16 Explanation of the VCO with high frequency limiter [3]

0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)

SS135V125∘CTT150V25∘CFF165V0∘C

Specification 15GHz

Figure 17 Postlayout simulation result of VCO frequency-voltagecharacteristics

Figure 17 shows the postlayout simulation results forthe VCO frequency-voltage characteristics As shown inFigure 11 the locking-point should be set at the range from05V to 08V because the current differences (119868CPMP minus 119868CPSNand 119868CPMN minus 119868CPSP) are nearly equal to the design targets Themaximum frequency of the VCO output signal should be setat less than 22GHz under the worst condition As shown inFigure 17 the VCO oscillates at 15 GHz at about 08 V andthe maximum frequency is less than 19GHz under the worstcondition

Figure 18 shows the VCO phase noise characteristics inTT condition The phase noise at 1MHz offset frequency is968 dBcHz The jitter in 250-cycle is 47 psrms Main jittersources are thermal noise of the11987210 and11987211 in the VIC inFigure 14

6 Measurement Result

We fabricated our SSCG using a 013 120583m CMOS processFigure 19 shows the settling-time results with and without

1 100Offset frequency (Hz)

Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200

Simulation conditionProcess TT

10k 1M 100M 10G

Voltage 150VTemperature 25∘C

968dBcHz 1MHz-offset47psrms in 250-cycle jitter

Figure 18 Postlayout simulation result of VCO phase noise charac-teristics

the fast-settling dual-CP control technique The sample isSS In Figure 19 there are four results Figures 19(a) and19(b) show the fast settling-time setup of the SSCG withoutand with the proposed control Figure 19(b) shows 4 120583ssettling-time by using proposed control technique On theother hand Figures 19(c) and 19(d) show the same setup asFigure 9 without and with proposed control to demonstratethe silicon results of the settling-time same as the simulationresults as shown in Figure 9 The measurement condition is135 V125∘C In Figures 19(a) and 19(b) without proposedcontrol technique the settling-time was 811 120583s as shownin Figure 19(a) With it the settling-time was 391 120583s asshown in Figure 19(b) which is less than 4 120583s The CPSbegan operating at about 10 120583s Soon after an overshootappeared and the SSCG output signal frequency becamenearly 22GHz However the VCO with its high-frequencylimiter prevented it from exceeding 22GHz and leading tomalfunctions In Figures 19(c) and 19(d) that are shown tocompare between simulation results in Figure 9 and siliconresults in Figure 19 Without proposed control techniquemeasurement and simulation results are 248 120583s and 225 120583srespectively With control technique measurement and sim-ulation results are 194120583s and 182 120583s respectively In the


15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With

Figure 19 Measurement result of the proposed SSCG settling-period The sample is SS Measurement condition is 135V125∘C Withoutproposed fast-lock dual-CP function (a) settling-period could be less than 811ms With function (b) settling-period could be less than391 120583s (c) and (d) are same PLL parameter as Figure 9 Without function (c) measurement and simulation settling period are 248 120583s and225 120583s respectively With function (d) measurement and simulation settling period are 194120583s and 182 120583s respectively

settling-time measurement results are similar to simulationresults

Figure 20 shows the measurement results for the SSCGoutput signal frequency The signal was modulated by a tri-angular wave whose frequency was 315 kHzThemodulationdeviation of the 15 GHz output signal was from +50 ppmto minus4259 ppm which met the SATA specification of from+350 ppm to minus5000 ppm

Figure 21 shows the measurement results of SSCG outputsignal spectrum The EMI reduction was 100 dB with theSSC

Figure 22 shows the measurement results for RJ andTJ under various conditions the results met the SATAspecification for all PVT variations The RJ was less than32 psrms The domain jitter source was the VCO The CPjitter due to the current mismatch of the dual-CP was farsmaller than the VCO jitter

Figure 23 shows the measurement result of the VCOfrequency-voltage characteristics in worst condition The15 GHz locking frequency was achieved at 10 V The maxi-mum frequency is less than 22GHz

315 kHz

50simminus4259ppm

Figure 20 Measurement result of the output signal frequencymodulated by triangular signal Modulation frequency is 315 kHzand modulation deviation is from +50simminus4259 ppm at 15 GHz

Figure 24 shows the measurement results for the CPcurrent The CP currents were measured by using an outputpin between the CP and the LF When the 119868CPMP wasmeasured the CPM was enabled and the CPS was disabled


wo SSC w SSC

Figure 21 Measurement results of the SSCG output signal spectrum with and without SSC

Processff fs typ sf ss

60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ

135Vminus20∘C150Vminus20∘C165Vminus20∘C135V25∘C150V25∘C

165V25∘C135V125∘C150V125∘C165V125∘C

Figure 22 Measurement result of output signal jitter of RJ and TJ

and then the UP and the DN were set to high and lowrespectively The CPM currents (119868CPMP and 119868CPMN) and CPScurrent (119868CPSP and 119868CPSN) were designed at 44 120583A and 32 120583Arespectively The NMOS currents (119868CPMN and 119868CPSN) did nothave accurate saturation characteristics due to channel lengthmodulation

Figure 25 shows the measurement results for the cur-rent difference between the CPM and CPS under variousconditions The design target for the current difference was120 120583A The variation of the current difference was less thanplusmn30 Under the ldquoffrdquo and ldquofsrdquo conditions the variation waslarger than under the other conditions This was because thechannel length modulation caused the ratio of the currentmirror consisting of PMOSs to deviate from the ideal ratio

Our SSCG generated an output signal with a frequencyof 15 GHz which meets the SATA specification As summa-rized in Table 1 its EMI was reduced by 100 dB its powerconsumption was 18mW and its settling-time was less than4 120583s the latter had been unachievable with previous SSCGsthat applied to the SATA specifications [2ndash6]

Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)

Figure 23 Measurement result of VCO frequency-voltage charac-teristics in worst condition (SS135V125∘C)

0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)

Design different current 1200 120583AICPMP minus ICPSN 1600 120583AICPMN minus ICPSP 840120583A

CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP

Figure 24 Measurement result of CP current

Figure 26 shows a chipmicrophotographThe design areawas 300 times 700120583m The 391 120583s locking-time was faster thanthe other previous works The proposed SSCG can make theSATA-PHY reduce the power in the partial state because theSSCG can be disabled For portable devices a battery lifetime


Table 1 Comparison table

Item Unit [3] [5] [2] [4] Thiswork

Outputfrequency GHz 15 15 15 15 15

Random jitter 250 cycles Ps rms lt33 mdash 5 32 lt32

Total jitter 250 cycles ps rms lt36 mdash mdash 168 lt107

EMI reduction dB 100 82 mdash 98 100Locking-time 120583s 30 42 50 63 391Technology 120583m 013 013 018 018 013Power mW 30 12 27 77 18Area mm2 03570 01120 02112 03100 02100

ff fs typ sf ss02468

10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)

ICPMP minus ICPSN ICPMN minus ICPSP135V25∘C150V25∘C165V25∘C

135V25∘C150V25∘C165V25∘C

Figure 25 Measurement result of different CP current

CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ

Figure 26 Test chip microphotograph

is critical issue Our proposed low power SATA-PHY can beone of the solutions to overcome the battery issue

7 Conclusion

A fast-settling spread-spectrum clock generator (SSCG) forSerial Advanced Technology Attachment (SATA) applicationhas been developed The SSCGrsquos settling time is shortenedthrough the use of a charge-pump (CP) control techniqueA prototype of our SSCG achieved 391 120583s settling-time

300 times 700 120583m design area 18mW power consumption 32psrms random jitter and 100 dB EMI reduction A SATA-PHY with our SSCG consumes less power in the partial statein SATA applications because it can stop the SSCG Thismakes it well suited for portable applications

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] Serial ATA International Organization ldquoSerial ATA Revision26 Specificationrdquo

[2] Y-B Hsieh and Y-H Kao ldquoA new spread spectrum clockgenerator for SATA using double modulation schemesrdquo inProceedings of the IEEE Custom Integrated Circuits Conference(CICC rsquo07) pp 297ndash300 September 2007

[3] T Kawamoto T Takahashi H Inada and T Noto ldquoLow-jitter and large-EMI-reduction spread-spectrum clock gen-erator with auto-calibration for serial-ATA applicationsrdquo inProceedings of the IEEE Custom Integrated Circuits Conference(CICC rsquo07) pp 345ndash348 September 2007

[4] H-R Lee O Kim G Ahn and D-K Jeong ldquoA low-jitter5000ppm spread spectrum clock generator for multi-channelSATA transceiver in 018 120583mCMOSrdquo in Proceedings of the IEEEInternational Solid-State Circuits Conference (ISSCC rsquo05) Digestof Technical Papers pp 162ndash163 February 2005

[5] P-Y Wang and S-P Chen ldquoSpread spectrum clock generatorrdquoin Proceedings of the IEEE Asian Solid-State Circuits Conference(ASSCC rsquo07) pp 304ndash307 November 2007

[6] J-S Pan T-H Hsu H-C Chen et al ldquoFully integratedCMOS SoC for 561816 CDDVD-dualRAMapplications withon-chip 4-LVDS channel WSG and 15 Gbs SATA PHYrdquo inProceedings of the IEEE ISSCC Digest of Technical Papers pp266ndash267 February 2006

[7] YMoon G Ahn H Choi N Kim and D Shim ldquoA quad 6Gbsmultirate CMOS transceiver with TX risefall-time controlrdquo inProceedings of the Digest of Technical Papers IEEE InternationalConference on Solid-State (ISSCC rsquo06) pp 233ndash242 IEEE SanFrancisco Calif USA February 2006

[8] S Pellerano S Levantino C Samori and A L Lacaita ldquoA135-mW 5-GHz frequency synthesizer with dynamic-logicfrequency dividerrdquo IEEE Journal of Solid-State Circuits vol 39no 2 pp 378ndash383 2004

[9] H-S Li Y-C Cheng andD Puar ldquoDual-loop spread-spectrumclock generatorrdquo in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC rsquo99) Digest of TechnicalPapers pp 184ndash185 February 1999

[10] J-YMichel andCNeron ldquoA frequencymodulated PLL for EMIreduction in embedded applicationrdquo in Proceedings of the 12thAnnual IEEE International ASICSOC Conference pp 362ndash365Washington DC USA 1999

[11] M Kokubo T Kawamoto T Oshima et al ldquoSpread-spectrumclock generator for serial ATA using fractional PLL controlledby 998779Σ modulator with level shifterrdquo in Proceedings of the IEEEInternational Solid-State Circuits Conference (ISSCC rsquo05) vol 1of Digest of Technical Papers pp 160ndash590 February 2005


[12] J Shin I Seo J Kim et al ldquoA low-jitter added SSCG withseamless phase selection and fast AFC for 3rd generation serial-ATArdquo in Proceedings of the IEEE Custom Integrated CircuitsConference (CICC 06) pp 409ndash412 San Jose Calif USASeptember 2006

[13] H-HChang I-HHua and S-I Liu ldquoA spread-spectrumclockgenerator with triangular modulationrdquo IEEE Journal of Solid-State Circuits vol 38 no 4 pp 673ndash676 2003

[14] C D LeBlanc B T Voegeli and T Xia ldquoDual-loop directVCO modulation for spread spectrum clock generationrdquo inProceedings of the IEEE Custom Integrated Circuits Conference(CICC rsquo09) pp 479ndash482 September 2009

[15] Y-H Kao and Y-B Hsieh ldquoA low-power and high-precisionspread spectrum clock generator for serial advanced technologyattachment applications using two-point modulationrdquo IEEETransactions on Electromagnetic Compatibility vol 51 no 2 pp245ndash254 2009

[16] T Kawamoto T Takahashi S Suzuki T Noto and K AsahinaldquoLow-jitter fractional spread-spectrum clock generator usingfast-settling dual charge-pump technique for serial-ATA appli-cationrdquo in Proceedings of the 35th European Solid-State CircuitsConference (ESSCIRC rsquo09) pp 380ndash383 September 2009

[17] S-Y Lin and S-I Liu ldquoA 15 GHz all-digital spread-spectrumclock generatorrdquo IEEE Journal of Solid-State Circuits vol 44 no11 pp 3111ndash3119 2009

[18] D de Caro C A Romani N Petra A G M Strollo andC Parrella ldquoA 127GHz all-digital spread spectrum clockgeneratorsynthesizer in 65 nm CMOSrdquo IEEE Journal of Solid-State Circuits vol 45 no 5 pp 1048ndash1060 2010

[19] S Levantino L Romano S Pellerano C Samori and AL Lacaita ldquoPhase noise in digital frequency dividersrdquo IEEEJournal of Solid-State Circuits vol 39 no 5 pp 775ndash784 2004

[20] K Shu E Sanchez-Sinencio J Silva-Martınez and S HK Embabi ldquoA 24-GHz monolithic fractional-N frequencysynthesizer with robust phase-switching prescaler and loopcapacitance multiplierrdquo IEEE Journal of Solid-State Circuits vol38 no 6 pp 866ndash874 2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014


Active and Passive Electronic Components

Control Scienceand Engineering

Journal of



RotatingMachinery


Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics


Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks



SSCG

CDR

DRV

SP

PS

RCVCLK

DATA

TX

RX

TD

RD

SATA-PHY

FVCO

Figure 1 Block diagram of SATA-PHY



(a) Conventional



(b) Proposed

Figure 2 Proposed low power SATA-PHY operation

from slumber to sync is a long periodThepartial state is also astandby state However allowed wake-up period from partialto sync is a short period of less than 10 120583s Thus it cannotstop the SSCG because the settling time of the SSCG is longerthan 10 120583s as shown in Figure 2(a) The SATA-PHY is set tothe partial state many times in HDD and ODD applicationsIf the SSCG can achieve a settling time less than 10 120583s theSATA-PHY can stop the SSCG in partial state as shownin Figure 2(b) This is attractive for portable applicationsbecause of saving power To achieve this operation the SSCGhas to have a settling time of less than about 4 120583s taking thewake-up time of the other blocks into consideration Thisstringent settling time requirement is far shorter than that ofa conventional SSCG

Figure 3 shows a block diagram of a conventional SSCGbased on a fractional PLL [3 4 6 10ndash20] It consists of aphase frequency detector (PFD) a charge pump (CP) a 3rdorder loop filter (LF) a voltage controlled oscillator (VCO)a multimodulus divider (MMD) a programmable counter(PGC) a ΣΔ modulator (ΣΔ) and a wave generator (WG)The WG is a logic circuit and generates a triangular waveas a spread-spectrum modulation The ΣΔ modulates thetriangular signal and then generates divide ratio (119873) thatthe average of the 119873 is modulated by the triangular wave

WG

N

PFD CPLF

VCO

MMDPGC

UP

DN

M

FVCOFREF

FB FP

ΣΔ

ICP

R1

R2

C1 C2 C3

VC

Figure 3 Conventional SSCG block diagram

The 119865VCO frequency is thus modulated by the triangularwave This SSCG can reduce EMI more substantially thanother SSCGs because the linearity of the modulation can beobtained accurately by utilizing the logic circuits [2ndash7]

This SSCGhas twomain jitter sources One is aVCO jitteroriginating from the thermal and flicker noise of the MOStransistors The other is a ΣΔ modulator jitter originatingfrom the quantization noise of the ΣΔmodulator The SSCGoutput jitter is the sum of these two jitters To remove thequantization noise that is high-pass characteristics the loopbandwidth should be designed narrow Thus the settling-time is necessarily longer and the design area is large

Several approaches have been presented for reducing thedesign areaThe high-resolution fractional divider techniqueshifts the modulator quantization noise to the higher fre-quency side and so it achieves wider bandwidth [5] Howeverit is difficult to reduce the EMI by much because spuriousjitter originating from the high-resolution fractional dividerremains in the modulation bandwidth All-digital SSCGshave been presented as a means of substantially reducingdesign area [17 18] However their output jitter is still largebecause their digitally controlled ring oscillators generatelarge jitter and it is difficult to operate them accurately if thereare PVT variationsThe capacitancemultiplication techniquehas been presented to reduce the design area as an approachin which the operation is based on that of a conventionalSSCG [2 7 20] However the settling time is necessarily longbecause the loop bandwidth is set to be narrow

To achieve a low-cost SATA-PHY suitable for portableapplications the design area settling-time power consump-tion jitter and EMI must all be reduced at the same timeTo consummate these aggressive demands we have proposedthe dual-CP SSCG architecture with fast-settling CP controltechnique

The rest of the paper is organized as follows Section 2describes the overall dual-CP SSCG architecture in detailSection 3 presents the fast-settling CP control technique wehave developed to achieve short settling time Section 4describes a CP circuit design to achieve a dual-CP architec-ture that is robust against PVT variations Section 5 describesthe VCO with high-frequency limiter Section 6 presents


WG

N

PFD CPMLF

VCO

MMDPGC

CPS

UP

DN

CNT

M

ST

FVCOFREF ICPM

R1

R2

C2 C3

VC

ΣΔ

FB FP

(1 minus 120572)C1

TSVCS

VCM

ICPS =120572ICPM










119865CPM (119904) = (119868CPM (11986211198771) 119904 + 1)

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+ (1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(1)


119865CPS (119904) = 119868CPS

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+(1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(2)


119865 (119904) = (119868CPM (11986211198771) 119904 + 119868CPM (1 minus 120572))

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+(1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(3)


119865119906 =(1 minus 120572)

11986211198771

(4)


119865119906 =1

11986211198771

(5)






119881)







Freq

uenc

y (G

Hz)

Range VCO

Target freq


ICPP

ICPN

CP cu

rren

t (120583

A)

VC (V)


Freq

uenc

y (G

Hz)

Range VCO

Target freq

Target current

Lock-point

ICPMP

ICPMN

ICPSPICPSN

CP cu

rren

t (120583

A)

VC (V)



Frequency (Hz)1

Gai

n (d

B)

200

100

0

minus100

minus200

1k 1M 1G








Δ conv =(1 minus 120572) 119868CPM1198621

(6)



1 As shown


Δ PROP =119868CPM1198621

(7)




1200Lo

op b

andw

idth

(kH

z) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM minus ICPS ()

(a)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM ()

(b)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPS ()

(c)




119878)





ST

CPS starts

Overshoot

Lock

Unlock

Time (s)

SSCG settling start

CPS starts

OvershootLock

MMD operating limit

MMD operating limit

(a) Conventional



15GHz

15GHz

15GHz

Δprop = ICPMC1

Δprop = ICPMC1

FVCO

FVCO

FVCO

TS

TS


4120583


0 10 20 300

20

15

10

05




Freq

uenc

y (G

Hz)

Time (120583s)







119868CPMP119868CP=1198821198725

1198821198723

119868CPMN119868CP=1198821198727

1198821198726

119868CPSP119868CP=11988211987213

1198821198723

119868CPSN119868CP=119882lt14

1198821198726

(8)



120572 =119868CPSP119868CPMP=11988211987213

1198821198725

=119868CPSN119868CPMN=11988211987214

1198821198727

(9)





UP

DNB

VB

DNB

UP

CPSCPM

M1 M2

M3 M4

M6

M7

M5

M21

M8

M9

M10

M11

M12

M14

M13

M15

M16

M17

M18

M19

M20

UPB

DN

DN

UPB

ICPSP

ICPSN

ICPMPICP

ICPMN

VCSVCM


0 02 04 06 08 10 12 14

50

40

30

20

10

0

ICPSN

ICPMPICPMN

ICPSP

Δ 1222 120583A

Δ 953120583A


VC (V)

CP cu

rren

t (120583

A)




02468

10121416

ff fs typ sf ss

Process

Target



I CPM

minusI C

PS(120583

A)


1200 120583A





CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON


M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b






















M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON







119862



I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










WG

N

PFD CPMLF

VCO

MMDPGC

CPS

UP

DN

CNT

M

ST

FVCOFREF ICPM

R1

R2

C2 C3

VC

ΣΔ

FB FP

(1 minus 120572)C1

TSVCS

VCM

ICPS =120572ICPM










119865CPM (119904) = (119868CPM (11986211198771) 119904 + 1)

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+ (1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(1)


119865CPS (119904) = 119868CPS

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+(1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(2)


119865 (119904) = (119868CPM (11986211198771) 119904 + 119868CPM (1 minus 120572))

sdot (1199043+ (1

11986231198772

+1

11986211198771

+1

11986221198771

+1

11986221198772

) 1199042

+(1198621+ 1198622+ 1198623

11986211198622119862311987711198772

) 119904)

minus1

(3)


119865119906 =(1 minus 120572)

11986211198771

(4)


119865119906 =1

11986211198771

(5)






119881)







Freq

uenc

y (G

Hz)

Range VCO

Target freq


ICPP

ICPN

CP cu

rren

t (120583

A)

VC (V)


Freq

uenc

y (G

Hz)

Range VCO

Target freq

Target current

Lock-point

ICPMP

ICPMN

ICPSPICPSN

CP cu

rren

t (120583

A)

VC (V)



Frequency (Hz)1

Gai

n (d

B)

200

100

0

minus100

minus200

1k 1M 1G








Δ conv =(1 minus 120572) 119868CPM1198621

(6)



1 As shown


Δ PROP =119868CPM1198621

(7)




1200Lo

op b

andw

idth

(kH

z) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM minus ICPS ()

(a)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM ()

(b)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPS ()

(c)




119878)





ST

CPS starts

Overshoot

Lock

Unlock

Time (s)

SSCG settling start

CPS starts

OvershootLock

MMD operating limit

MMD operating limit

(a) Conventional



15GHz

15GHz

15GHz

Δprop = ICPMC1

Δprop = ICPMC1

FVCO

FVCO

FVCO

TS

TS


4120583


0 10 20 300

20

15

10

05




Freq

uenc

y (G

Hz)

Time (120583s)







119868CPMP119868CP=1198821198725

1198821198723

119868CPMN119868CP=1198821198727

1198821198726

119868CPSP119868CP=11988211987213

1198821198723

119868CPSN119868CP=119882lt14

1198821198726

(8)



120572 =119868CPSP119868CPMP=11988211987213

1198821198725

=119868CPSN119868CPMN=11988211987214

1198821198727

(9)





UP

DNB

VB

DNB

UP

CPSCPM

M1 M2

M3 M4

M6

M7

M5

M21

M8

M9

M10

M11

M12

M14

M13

M15

M16

M17

M18

M19

M20

UPB

DN

DN

UPB

ICPSP

ICPSN

ICPMPICP

ICPMN

VCSVCM


0 02 04 06 08 10 12 14

50

40

30

20

10

0

ICPSN

ICPMPICPMN

ICPSP

Δ 1222 120583A

Δ 953120583A


VC (V)

CP cu

rren

t (120583

A)




02468

10121416

ff fs typ sf ss

Process

Target



I CPM

minusI C

PS(120583

A)


1200 120583A





CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON


M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b






















M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON







119862



I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Freq

uenc

y (G

Hz)

Range VCO

Target freq


ICPP

ICPN

CP cu

rren

t (120583

A)

VC (V)


Freq

uenc

y (G

Hz)

Range VCO

Target freq

Target current

Lock-point

ICPMP

ICPMN

ICPSPICPSN

CP cu

rren

t (120583

A)

VC (V)



Frequency (Hz)1

Gai

n (d

B)

200

100

0

minus100

minus200

1k 1M 1G








Δ conv =(1 minus 120572) 119868CPM1198621

(6)



1 As shown


Δ PROP =119868CPM1198621

(7)




1200Lo

op b

andw

idth

(kH

z) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM minus ICPS ()

(a)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM ()

(b)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPS ()

(c)




119878)





ST

CPS starts

Overshoot

Lock

Unlock

Time (s)

SSCG settling start

CPS starts

OvershootLock

MMD operating limit

MMD operating limit

(a) Conventional



15GHz

15GHz

15GHz

Δprop = ICPMC1

Δprop = ICPMC1

FVCO

FVCO

FVCO

TS

TS


4120583


0 10 20 300

20

15

10

05




Freq

uenc

y (G

Hz)

Time (120583s)







119868CPMP119868CP=1198821198725

1198821198723

119868CPMN119868CP=1198821198727

1198821198726

119868CPSP119868CP=11988211987213

1198821198723

119868CPSN119868CP=119882lt14

1198821198726

(8)



120572 =119868CPSP119868CPMP=11988211987213

1198821198725

=119868CPSN119868CPMN=11988211987214

1198821198727

(9)





UP

DNB

VB

DNB

UP

CPSCPM

M1 M2

M3 M4

M6

M7

M5

M21

M8

M9

M10

M11

M12

M14

M13

M15

M16

M17

M18

M19

M20

UPB

DN

DN

UPB

ICPSP

ICPSN

ICPMPICP

ICPMN

VCSVCM


0 02 04 06 08 10 12 14

50

40

30

20

10

0

ICPSN

ICPMPICPMN

ICPSP

Δ 1222 120583A

Δ 953120583A


VC (V)

CP cu

rren

t (120583

A)




02468

10121416

ff fs typ sf ss

Process

Target



I CPM

minusI C

PS(120583

A)


1200 120583A





CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON


M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b






















M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON







119862



I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











1200Lo

op b

andw

idth

(kH

z) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM minus ICPS ()

(a)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPM ()

(b)


1200

Loop

ban

dwid

th (k

Hz) 1000

800

600

400

20060

70

60

50

40

30

20

Phas

e mar

gin

(∘)

ICPS ()

(c)




119878)





ST

CPS starts

Overshoot

Lock

Unlock

Time (s)

SSCG settling start

CPS starts

OvershootLock

MMD operating limit

MMD operating limit

(a) Conventional



15GHz

15GHz

15GHz

Δprop = ICPMC1

Δprop = ICPMC1

FVCO

FVCO

FVCO

TS

TS


4120583


0 10 20 300

20

15

10

05




Freq

uenc

y (G

Hz)

Time (120583s)







119868CPMP119868CP=1198821198725

1198821198723

119868CPMN119868CP=1198821198727

1198821198726

119868CPSP119868CP=11988211987213

1198821198723

119868CPSN119868CP=119882lt14

1198821198726

(8)



120572 =119868CPSP119868CPMP=11988211987213

1198821198725

=119868CPSN119868CPMN=11988211987214

1198821198727

(9)





UP

DNB

VB

DNB

UP

CPSCPM

M1 M2

M3 M4

M6

M7

M5

M21

M8

M9

M10

M11

M12

M14

M13

M15

M16

M17

M18

M19

M20

UPB

DN

DN

UPB

ICPSP

ICPSN

ICPMPICP

ICPMN

VCSVCM


0 02 04 06 08 10 12 14

50

40

30

20

10

0

ICPSN

ICPMPICPMN

ICPSP

Δ 1222 120583A

Δ 953120583A


VC (V)

CP cu

rren

t (120583

A)




02468

10121416

ff fs typ sf ss

Process

Target



I CPM

minusI C

PS(120583

A)


1200 120583A





CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON


M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b






















M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON







119862



I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










ST

CPS starts

Overshoot

Lock

Unlock

Time (s)

SSCG settling start

CPS starts

OvershootLock

MMD operating limit

MMD operating limit

(a) Conventional



15GHz

15GHz

15GHz

Δprop = ICPMC1

Δprop = ICPMC1

FVCO

FVCO

FVCO

TS

TS


4120583


0 10 20 300

20

15

10

05




Freq

uenc

y (G

Hz)

Time (120583s)







119868CPMP119868CP=1198821198725

1198821198723

119868CPMN119868CP=1198821198727

1198821198726

119868CPSP119868CP=11988211987213

1198821198723

119868CPSN119868CP=119882lt14

1198821198726

(8)



120572 =119868CPSP119868CPMP=11988211987213

1198821198725

=119868CPSN119868CPMN=11988211987214

1198821198727

(9)





UP

DNB

VB

DNB

UP

CPSCPM

M1 M2

M3 M4

M6

M7

M5

M21

M8

M9

M10

M11

M12

M14

M13

M15

M16

M17

M18

M19

M20

UPB

DN

DN

UPB

ICPSP

ICPSN

ICPMPICP

ICPMN

VCSVCM


0 02 04 06 08 10 12 14

50

40

30

20

10

0

ICPSN

ICPMPICPMN

ICPSP

Δ 1222 120583A

Δ 953120583A


VC (V)

CP cu

rren

t (120583

A)




02468

10121416

ff fs typ sf ss

Process

Target



I CPM

minusI C

PS(120583

A)


1200 120583A





CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON


M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b






















M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON







119862



I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










UP

DNB

VB

DNB

UP

CPSCPM

M1 M2

M3 M4

M6

M7

M5

M21

M8

M9

M10

M11

M12

M14

M13

M15

M16

M17

M18

M19

M20

UPB

DN

DN

UPB

ICPSP

ICPSN

ICPMPICP

ICPMN

VCSVCM


0 02 04 06 08 10 12 14

50

40

30

20

10

0

ICPSN

ICPMPICPMN

ICPSP

Δ 1222 120583A

Δ 953120583A


VC (V)

CP cu

rren

t (120583

A)




02468

10121416

ff fs typ sf ss

Process

Target



I CPM

minusI C

PS(120583

A)


1200 120583A





CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON


M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b






















M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON







119862



I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











CCO

VC

VP VP VP VPFVCO

FVCOB

IP

IN

OP

ON

IP

IN

OP

ON

IP

IN

OP

ON


M2

M1 M3

M4

M5 M6

M7

M8 M10

M11M9

VC

VP

ICNT

ICNT

IM

1 a

1 b






















M1 M2

M3 M4M7 M8

M10 VP

IP

INOP

ON







119862



I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










I P(m

A)

IM

ICNT

ICM

VC (V)

(a) VIC

FV

CO

(GH

z)

IP (mA)

(b) CCO

VC (V)

FV

CO

(GH

z)

15GHz

(c) VCO


0 05 10 15

Freq

uenc

y (G

Hz)

0

10

20

25

20

15

05

VC (V)


Specification 15GHz







Phas

e noi

se (d

BcH

z)

50

0

minus50

minus100

minus150

minus200


10k 1M 100M 10G






15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










15GHz

811 120583s

(a) Without

CPS on

Overshoot

15GHz391120583s

(b) With

15GHz248 120583s

(c) Without

CPS on

15GHz194 120583s

(d) With







315 kHz

50simminus4259ppm




wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










wo SSC w SSC



60

0

40

20

Jitte

r (ps

) 80

100

120

RJ

TJ


165V25∘C135V125∘C150V125∘C165V125∘C





Freq

uenc

y (G

Hz)

0

10

20

25

15

05

0 05 10 15 20VC (V)


0 02 04 06 08 10 12 14

50

40

30

20

10

0

60

VC (V)


CP cu

rren

t (120583

A)

ICPMP

ICPSN

ICPMN

ICPSP











10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation

















10121416

Process

Target

18

120 120583A

I CPM

minusI C

PS(120583

A)


135V25∘C150V25∘C165V25∘C


CNT

VCO

LFPRS PGCPFD

CPMCPS300120583m

700120583m

ΣΔ



7 Conclusion





References
























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation





















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









research article a 3.9 s settling-time fractional...

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