research article low-jitter 0.1-to-5.8ghz clock...

Hindawi Publishing CorporationJournal of Electrical and Computer EngineeringVolume 2013 Article ID 364982 8 pageshttpdxdoiorg1011552013364982

Research ArticleLow-Jitter 01-to-58 GHz Clock Synthesizer for Area-EfficientPer-Port Integration

Reza Molavi12 Hormoz Djahanshahi1 Rod Zavari1 and Shahriar Mirabbasi2

1 PMC-Sierra Burnaby BC Canada V5A 4V72University of British Columbia Vancouver BC Canada V6T 1Z4

Correspondence should be addressed to Reza Molavi rezaeceubcca

Received 31 December 2012 Accepted 11 June 2013

Academic Editor Chih-Wen Lu

Copyright copy 2013 Reza Molavi et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LCVCOs) are attractive in low-jitter multigigahertzapplications However inductors occupy large silicon area and moreover dense integration of multiple LC VCOs presents thechallenge of electromagnetic coupling amongst them which can compromise their superior jitter performanceThis paper presentsan analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner Basedon this study a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to58GHz is designed and implemented in a 65 nm digital CMOS process Measurement results are presented for densely integratedCSUs within a multirate multiprotocol system-on-chip PHY device

1 Introduction

The design of clock multipliers for multirate multistandardapplications involves a tradeoff between the output clockjitter and the frequency tuning range Traditionally a widerange is achieved via non-LC-based oscillators such asrelaxation or ring oscillators [1ndash3] at the cost of higherphase noise and intrinsic jitter LC VCOs are used for low-jitter multigigahertz applications but their tuning rangeis inherently small [2 4] Moreover dense integration ofmultiple LC VCOs on a silicon die poses a new challengedue to mutual coupling between inductors and the resultingfrequency pulling and induced phase jitter among adjacentoscillators In this work a low-jitter highly packable Clock-Synthesizer Unit (CSU) supporting a continuous (gapless)frequency range up to 58GHz is designed and implementedin 65 nm digital CMOS process One of the objectives of thisclock generation architecture is to close the gap between ringoscillators with wide tuning range but high phase-noise andjitter and LC oscillators with limited tuning range and lowphase noiseThe clock synthesizer architecture is described inSection 2 In Section 3 amodel is presented that describes theeffect of magnetic coupling between adjacent VCOs and the

resulting phase jitter in the PLL under test Implementationresults and conclusions are presented in Sections 4 and 5respectively

2 Architecture

The clock synthesizer unit presented in this work is intendedfor per-port integration in transceivers supporting variouswireline telecommunications and data communication stan-dards

As shown in Figure 1 the CSU receives a stable crystal-based reference clock (REFCLK) and employs two LC VCOsa programmable charge pump a high-speed fractional feed-back divider and flexible bank of post-PLL dividers (post-dividers) to multiply up the reference frequency to generatethe intended half-baud-rate clock This synthesizer employsa moderate bandwidth PLL programmable from 400 kHzto 12MHz to attenuate fractional-N spurs and the refer-ence and charge-pump noise while suppressing the VCOphase noise to comply with stringent jitter specifications ofnumerous wireline standards As shown in Figure 2 the CSUprovides complementary CMOS output clocks CLKHR andCLKHRB at half the baud rate driving one transmitter (TX)

2 Journal of Electrical and Computer Engineering

middot middot middotmiddot middot middot

0 05 1240

280

320

360

400

440

(p)

240

280

320

360

400

440

(p)

(p)

500

530

560

590

620

650

A-MOSCAP PMOS

CAP

Parallelcombination

Cp C3Cz

Vdd

Vdd

Rz

R3 Vcontrol

Vcontrol

Vcontrol

PMOSCap

AMOSvaractor

Icp

REFCLKCMOSphase-

frequencydetector(PFD)

Up

Down

Programmablecharge pump

Integratedloop filter

Icp LC VCO2

425ndash58GHz

LC VCO1

36ndash49GHz

Bank ofpostdividers

Outputclockdriver

Power controlswitches

Feedback clock

Fractional feedback divider

CMOS multimodulus divider(MMD)

Control signals

Δsum modulator

C0 (min) = 586pF

CLKHR(B)

Vcontrol (volt)

Figure 1 Block diagram of clock synthesizer unit (CSU)

Transmitserial data

Parallel-inserial-out

(PISO)TXTransmit

parallel data8b

8b

Half-baud-rate clockClock phasegeneration

ReceivedataRXTERM

Digital clockrecovery and

serial-inparallel-out

(SIPO)

Referenceclock

Recovered clockRecovered data

Fractional36ndash58GHz

clocksynthesizer

unit

Figure 2 Block diagram of one transceiver link

which transmits data on both transitions of the differentialclock (CLKHR-CLKHRB)

The large tuning range of the VCO (36GHz to 58GHz)comes from two LC tanks combined with a flexible post-divider bank implementing multiple divide ratios with 50output duty cycle which guarantees gapless frequency syn-thesis for baud rates from the VCOrsquos maximum frequency

of 58GHz down to 01 GHz Relying on the wide VCOfrequency range and the postdivider flexibility a redundantfrequencymapping is planned for critical telecom rates mostnotably 2488Gbs SONET that employs alternative VCOrate and postdivider combinations to avoid running adjacentVCOs at the same (or close) nominal rates This allowsdense integration of a large number of serializer-deserializer(SERDES) links each with a per-port frequency synthesizerwithout any significant inductor coupling amongst adjacentVCOs The CSU feedback path consists of a high-speedmultimodulus divider (MMD) running at the VCO rate thatis controlled by a ΔΣmodulator (DSM) [5 6] The 24b DSMuses a 3rd-order single-loop topology allowing frequencysynthesis resolution down to 2 parts per billion (ppb)A programmable integrated passive loop filter is used tosuppress the reference clock and the DSM quantization noisefrom the VCOrsquos control voltage A parallel combination ofaccumulationmode (AMOS) varactors and PMOS capacitorsis used to linearize the 119862-119881 characteristics of the on-chipcapacitor tomaintain optimal loop dynamics across the rangeof VCOrsquos control voltage 119881control (see Figure 1 inset)

Journal of Electrical and Computer Engineering 3

Two LC VCOs with overlapping tuning ranges eachcomprised of a cross-coupled NMOS and PMOS topologiesgenerate the required 36GHz to 58GHz tuning rangeIntegrated inductors with stacked metal for lower resistanceare used to achieve high quality factor (119876) and hence lowVCO phase noise To increase the headroom for low-voltageoperation on 1 volt supply the tail current source of theVCO is eliminated One advantage of this approach is theremoval of the tail-current noise which would otherwisefold back into the close-in phase noise of the VCO [4]Furthermore the increased oscillator swing due to the addedheadroom improves the phase noise performanceTheoverallsilicon area is reduced due to the removal of a large currentsource current mirrors and associated noise filters forbiasing

It is worth noting that since there is no tail currentsource in this design the 119892

119898of the devices and hence the

total negative resistance is solely governed by the size of theNMOS and PMOS transistors To guarantee oscillation it isnecessary that 119877

119875ge | minus 1119892

119898| across the frequency band

where 119877119875= (120596119871)

2

119877119904is the equivalent shunt resistance

of the inductorrsquos series loss resistance (119877119904) and 119892

119898is the

overall transconductance of the cross-coupled transistorsAssuming a relatively constant 119877

119904versus frequency the

minimum required transconductance for oscillation variesby a factor of (119891max119891min)

2 across the frequency range ofeach VCO Since the 119892

119898of the cross-coupled pairs has to

be large enough to guarantee the oscillation startup at thelower end of the frequency band there is a waste of powerat the higher end of the frequency range especially at fastprocess corner (FF) where the transistor threshold voltagesare smaller To alleviate this problem a set of programmableparallel switches control the total resistance to ground andhence the VCOrsquos power consumption (Figure 1 inset) Thisflexible scheme results in up to 30 power reduction forhigh-frequency settings or Fast silicon process corner Thewide tuning range of the VCO is achieved through the com-bination of coarse tuning using fixed switchable capacitorsimplemented by a stack of interdigitatedmetal capacitors andfine-tuning of the AMOS varactors via the control voltageA VCO calibration scheme which sets 119881control to one ofmultiple voltage levels at startup (nominally 119881dd2) selectsthe optimum metal capacitor for the target rate and givenprocess corner Provisions have been made for temperature-aware calibration that is to choose119881control for the calibrationbased on the calibration temperature so as to offer additionalmargin for postcalibration variations of temperature andsupply voltage

A dedicated flip-chip power bump near the VCO core isintended tominimize IR drop and power supply noise causedby other blocks in the SERDES including adjacent PLLsTo further stabilize the VCOrsquos supply a large decouplingcapacitor consisting of AMOS varactor and metal capacitorusing metal layers M1-M2 is implemented underneath thepatterned ground shield (PGS) of the VCOrsquos inductor ThePGS is implemented in a higher metal layer (M3) to allowthis implementation The incremental effect on the inductorquality factor is negligible while a large area of silicon die isreused to filter the sensitive VCO supply

3 Clock Jitter in PlesiochronousNeighboring PLLs

According to ITU standards for telecommunications (ITU-T) two signals are plesiochronous if they have the samenominal rate with any variation in rate being constrainedwithin specified limits For example two bit streams areplesiochronous if they are clocked off two independent clocksources that have the same nominal frequencies butmay havea slight frequency mismatch measured in parts per million(ppm) which would lead to a drifting phase and cycle slipsIn other words two plesiochronous signals or systems arealmost synchronous but not quite perfectly

One of the most challenging situations for noise couplingamong densely integrated SERDES links with independentrates is when adjacent links run in a plesiochronous mannerwith the line rates offset anywhere in the approximate rangeof plusmn10 to plusmn500 ppm In this case any coupling betweenthe links in general and magnetic coupling between theirrespective LC VCOs in particular can cause in-band noiseand spurs The unwanted pulling of one VCO by anotherVCO right around the bandwidth of the victimrsquos PLL provesto be problematic especially for Telecommunication stan-dards with close-in jitter specifications for example SONETOC-48 with jitter integration band specified from 12 kHz to20MHz offset from the carrier

We present a model that helps understand the behaviorof the unwanted periodic jitter in two adjacent PLLs (hereknown as aggressor and victim) when the two PLLs operate ata small frequency offset and the magnetic isolation betweentheir VCO inductors is finite

To quantify this effect consider two adjacent VCOsoperating at slightly different frequencies the victim VCO at120596119900and the aggressor VCO at 120596

119886= 120596119900+ Δ120596 separated by

small frequency offset Δ120596 The coupling factor (119896) betweenthe inductors 119871

1and 119871

2in the two VCOs is simulated using

an electromagnetic (EM) simulation tool Assuming identicalinductors used in the two VCOs in neighboring links theopen-circuit voltage 119881

119899OC(119905) induced by the aggressor on thevictim can be calculated as in (2)

11989812= 119896radic119871

11198712 1198711= 1198712= 119871 (1)

119881119899OC (119905) = 11989812

119889119868119886(119905)

119889119905 (2)

where 119868119886(119905) = 119868

119886119901119896sin120596119886119905 = 119868119886119901119896

sin(120596119900+Δ120596)119905 is the current

flowing through the aggressor inductor The noise voltageinduced in the victimrsquos inductor is then calculated as follows

Equation (2)997904997904997904997904997904997904997904997904997904rArr 119881

119899OC (119905) = 119896119871120596119886119868119886119901119896 cos (120596119886119905)

Loaded by V119894119888119905119894119898 tank997904997904997904997904997904997904997904997904997904997904997904997904997904997904997904997904rArr 119881

119899(119905) = 120572119896119871120596

119886119868119886119901119896

cos (120596119886119905)

= 119881119899119901119896

cos ((120596119900+ Δ120596) 119905)

(3)

Equation (3) indicates that when loaded by the tankimpedance of the victim VCO which also includes theimpedance of the cross-coupled pair the induced voltage


119881119899(119905) becomes smaller by a loading factor 120572 As can be seen

in Figure 3 this voltage appears as two asymmetric sidebandsin the output voltage spectrum of the victim VCO This isbecause the interference from the aggressor at some offset(Δ120596) from the victim VCO frequency that is 120596

119886= 120596119900+ Δ120596

can be modeled as the superposition of two AM and PMcomponents To explain this we express the victim VCOrsquosoutput voltage as

119881VCO (119905) = 119860 cos (120596119900119905) + 119881

119899119901119896cos ((120596

119900+ Δ120596) 119905) (4)

where the first term represents the desired VCO output volt-age oscillating at 119891

119900 while the second term is the interference

due to the aggressor VCO as expressed by (3) Using thephasor representation in Figure 4 and assuming that 119881

119899119901119896≪

119860 the victimrsquos output voltage may be rewritten as

119881VCO (119905) = 119860119881 (119905) sdot cos (120596119900119905 + 120601119881 (119905)) (5)

where

119860119881(119905) = 119860[1 + (

119881119899119901119896

119860cos (Δ120596119905))] (6)

120601119881(119905) = (

119881119899119901119896

119860sin (Δ120596119905)) (7)

The term 119860119881(119905) represents a periodic amplitude modulation

(AM) of theVCOrsquos carrierwith amodulation index of119881119899119901119896119860

at frequency Δ119891 and generates two in-phase sidebandsaround the VCO frequency The term 120601

119881(119905) represents phase

modulation (PM) with a modulation index of 119881119899119901119896119860 and

produces two opposite-phase sidebands around the VCO fre-quencyThis explains the existence of a sideband at (120596

119900minusΔ120596)

in Figure 3 that is smaller in magnitude than the sideband atthe aggressor frequency 120596

119886= (120596119900+Δ120596) The PMmodulation

of 120601V(119905) can be described by a voltage perturbation 119881119862ripple at

angular frequency Δ120596 = |120596119886minus 120596119900| on the control voltage of

the VCOrsquos varactorThis voltage wouldmodulate the varactorcapacitance hence the frequency and phase of the oscillatorand creates sideband spurs This modeling is useful since itallows us to evaluate noise-shaping behavior of the PLL onthe induced phase interference as described next

The response of a PLL to a voltage disturbance at the inputof its VCO largely depends on the dynamics of the loop andthe location of zeros and poles set for the stability of the PLLThis can be analyzed based on the closed-loop phase modelof the victim PLL as shown in Figure 5

As explained 119881119862ripple represents a small-signal voltage

perturbation referenced to the input control voltage of thevictim VCO that describes the frequencyphase modulationcaused by the magnetic coupling from the aggressor VCOThe frequency of this unwanted modulation is the difference(offset) between the two VCO frequencies The transferfunction from this ripple voltage to the output phase of the

Frequency (GHz)446 447 448 449 45

minus350

minus300

minus250

minus200

minus150

minus100

minus50

0

Out

put v

olta

ge (d

BV)

Victimrsquos oscillationfrequency (fo)

Component at fo + Δfinduced by aggressor

(AM +PM)

Component at fo minus Δf

(generated by PM)

Figure 3 The victim VCO oscillates at 119891119900= 4477GHz while an

aggressor oscillating at 119891119900+ Δ119891 = 4479GHz induces sidebands

at (4479GHzndash4477GHz) = 2MHz away from the victim VCONote that the first upper sideband (at the aggressor frequency) isexplained by constructive addition of AM and PM components andis larger in magnitude than the first lower sideband

A

AV(t)

120601V(t)

Vnpk

Δ120596

Vnpkcos(Δ120596t)

Vnpksin(Δ120596t)

Figure 4 Phasor diagram of AM and PM components in magneti-cally coupled VCOs

victim VCO (120601OUT) is calculated as

120601OUT119881119862ripple

=119870VCO119878

1198782 + ((119868CP1198771198852120587119873)119870VCO) 119878 + (119868CP2120587119862119885119873)119870VCO

(8)

120601OUT119881119862ripple

=119870VCO119878

1198782 + (120596BW) 119878 + 120596BW sdot 120596119885 (9)

where 119870VCO 119868CP and 119873 are the VCO gain charge pumpcurrent and feedback divider ratio respectively in the chargepump-based PLL 119877

119885and 119862

119885are the values of the resistor

and capacitor comprising the loop filter zero frequency Asimplied by (9) the transfer function from the unwantedcoupled spur to the output phase of the PLL has a bandpasscharacteristics with the passband extending from the zerofrequency (120596

119911) to the PLLrsquos unity-gain bandwidth frequency

(denoted by 120596BW) The transfer function versus the offsetfrequency is shown in Figure 6

This implies that plesiochronous links with rate offsetsclose to the bandwidth of the PLL have the largest impacton one another To support this analysis and key conclusionan experiment is carried out in which the frequency offsetbetween two adjacent PLLs is varied from 0 (synchronousoperation) to values larger than the bandwidth of each PLLThe total RMS jitter (TJrms) of the PLL is measured for each


1N

Feedback divider

PFD Charge pump Loop filter VCripple

REFCLK 12120587

Up

Down

Icp +RZ + 1CzS KVCO S

VCO

120601out

Figure 5 Closed-loop AC model of a charge pump-based PLL

0 025 05 075 1 125 15 175Δf (MHz)Offset frequency

minus110

minus100

minus90

minus80

minus70

minus60

minus50

Spur

tran

sfer f

unct

ion

(dB)

Figure 6 Transfer function of the spur generated at the output ofPLL

offset case and the results are plotted as in Figure 7 The PLLunder test has its zero frequency and bandwidth set to 90 kHzand 300 kHz respectively As seen in Figure 7 the total RMSjitter peaks around 200 kHz (ie near the transfer functionpeaking predicted by Figure 6) and drops off at frequenciesbelow the zero frequency and above the bandwidth of thePLL as expected from (9)

This behavior can also be explained by the PLL dynamicsThat is if the induced spur is far below the looprsquos zerofrequency the PLL response is fast enough to correct thisvariation and the jitter goes down Conversely if the spur isfar above the PLL bandwidth the VCO being an integratordoes not follow fast changes on its control voltage and hencethe output spur will be small Note that the jitter at zerooffset reaches its lowest limit that is the intrinsic jitter (akarandom jitter or RJrms) of the victim PLL In other words thelowest total jitter is achieved by synchronous operation

In synchronous operation (0 ppm offset) the total jitteris dominated by the random jitter of a standalone PLLwhich in turn depends on the noise contribution of theblocks within the PLL as well as the PLL dynamics Hencethe charge pump the VCO the feedback divider and the

0

02

04

06

08

1

12

14

16

Offset frequency (Hz)

minus15E+06

minus1E

+06

minus5E

+05

0E+00

5E+05

1E+06

15E+06

Total RMS jitterintegrated over 12kHzndash20MHz

TJ r

ms

(ps)

Figure 7 Measured total jitter of the victim CSU versus the offsetfrequency of aggressor link

Table 1 Effect of spacing on the coupling between two active links

Frequency offset(100 ppm)

Coupled spur(dBc)

Physical distance(120583m)

450 kHz minus443 560 (links 1 and 2)450 kHz minus567 1120 (links 1 and 3)

passive loop filter are designed with careful attention totheir random jitter contribution This noise optimizationas will be discussed shortly allows the use of a moderatequality low-cost reference clock for this multirate PLL Inorder to reduce the plesiochronous magnetic coupling effectseveral techniques have been proposed that may be exercisedincluding [10ndash12] In this work we propose a variation of thestraightforward solutions of spacing out the links physicallyhence lowering the mutual coupling and the induced noiseAn exercise employing this technique would be to powerup every other link (rather than all links) on the chip andmeasure the resulting spurs This is shown in Table 1 As canbe seen doubling the distance between the active links resultsin about 12 dB reduction in the aggressor spur observed at theoutput spectrumof the victim PLL which agrees with the factthatmagnetic coupling is inversely proportional to the squareof the distance between the inductors

However if an aggressor VCO operates at a frequencycorresponding to a frequency offset far above the bandwidthof the nearby victim PLL the aggressor will have very littleimpact due to 20 dBdecade suppression of the coupledspur beyond the bandwidth of the victim PLL As a resultrather than powering down every other VCO one can runthem alternately at totally different frequencies to satisfythe previously mentioned frequency offset condition Thistechnique can be implemented if the dividers followingeach VCO provide the same final half-baud-rate clocks totheir respective TX In other words the goal is to have aredundant frequency plan to achieve the same HRCLK(B)


Integration of 18 SERDES links (18 CSUs)for multiprotocol applications

Figure 8 Physical view of the single-chip multiratemultiprotocolPHY system-on-chip device

frequencies after the PLL postdividers while the VCOs runat totally different rates In practical terms every other VCOis tuned to a different frequency hence circumventing theunwanted coupling between adjacent PLLs and effectivelyincreasing the spacing between plesiochronous VCOs by afactor of two In this case one would only worry aboutthe coupling between every other link which means 12 dBimprovement in the magnitude of unwanted coupled spursThis frequency scheme virtually eliminates noise couplingamongst plesiochronous neighboring links and allows fordense placement of the links with integrated per-port clocksynthesizers

4 Implementation and Summary

Each clock synthesizer unit occupies an area of (560 times700)120583m2 integrated along with a transceiver link makingit 12mm tall thereby allowing a minimum integrationpitch of 560120583m for abutting multiple links Figure 8 showsthe die micrograph of a high-capacity single-chip multiratemultiprotocol PHY device in which 18 SERDES ports areintegrated as described This device enables the convergenceof high-bandwidth data video and voice services over opticaltransport network (OTN) and offers advanced protocolmapping and multiplexing capabilities for more efficientmultiservice integration on a single platform

The VCO and its output multiplexer and buffers draw atypical current of 11mA at 1 volt while the entire CSU drawsunder 20mA The measured tuning characteristics of thedual VCO versus coarse tuning metal capacitor settings overprocess temperature and supply voltage (PVT) variations areshown in Figure 9 Measurement results are within 0 to 2 ofthe simulations at119881control = 119881dd2The 2discrepancy occursat higher frequencies where most fixed metal capacitorsare disconnected and hence any inaccuracies in modelingvaractors and parasitic capacitors are more pronounced TheRMS jitter measured is 538 fs for 2488Gbs applications

0 10 20 30 40 50 60 70

FREQ

(Hz)

Coarse tuning metal capacitor settings

3E + 09

35E + 09

4E + 09

45E + 09

5E + 09

55E + 09

6E + 09

65E + 09

Measured tuning curves of dual VCO versus coarse tuning settings(full PVT at Vcontrol = Vdd2)

SS 095V minus40CFF 115V 125C

VCO1

VCO2

Figure 9 Measured tuning curves of dual LC VCOs across PVTcorners

Figure 10 Closed-loop phase noise and RMS jitter measurementat 1244GHz output (FVCO = 4976GHz) RJ = 538 fsrms (1 kHz to40MHz)

(integrated from 1 kHz to 40MHz) as shown in the phasenoise snapshot in Figure 10 With an integration bandwidthof 12 kHz to 20MHz based on SONET OC-48 specificationsthe RMS jitter is 046 ps (plusmn001 ps) for an isolated channel and050 ps (plusmn001 ps)with all channels active as shown inTable 2

Note that the PLLrsquos reference clock is the dominant phasenoise contributor below 1 kHz Despite the low output jitter ofthe CSU its input reference clock has fairly relaxed require-ments for most applications The reference clock comes froma low-cost 2-psrms (12 kHz to 20MHz) source enters the chipthrough a single-ended pad and is conveniently autoroutedthrough the digital core to all the links Table 2 summarizesmeasured RMS jitter of the CSUoutput for two representativesupported wireline standards Comparative measurementsare done first on an isolated link-under-test and thenwith fullactivity on all links Also both alternative configurations forodd and even channels are shown for the SONETOC-48 case


Table 2 Summary of the CSU clock jitter for selected wireline standards

Standard Data rate(Mbs)

VCO frequency(MHz)

HRCLK(B)frequency (MHz)

RJps-rms isolatedchannel

RJps-rms all channelsactive Integration band

Fibre Channel 4250 4250 2125 047 049 255MHz to2125GHz

SONET OC-48 248832 497664 124416 045 049 12 kHz to 20MHz373248 124416 047 051

Table 3 Clock synthesizer performance summary and comparison

Ref VCO output frequency(GHz)

RMS jitter (psrms)integration band Active area (mm2)

Powerconsumptionnominal supply

Process technology

[2] Ring VCO 10 to 85LC-VCO 83 to 111

099 (1MHz to 125GHz)055 (1MHz to 125GHz) 0277

Ring VCO 70mWLC-VCO 60mW

25V

45 nmSOI-CMOS

[3] 02 to 4 15(integration band not reported) not reported

15mWAnalog 18 VDigital 1 V

65 nmCMOS

[7] 229 to 275 097(10 kHz to 10MHz)

512(entire core)


035 120583mCMOS

[8] 57 to 68 056(integration band not reported) 043 25mW

Not reported013120583mCMOS

[9] 633 to 1056 13(integration band not reported)

35(entire core)

885mW15V

018120583mCMOS

This work36 to 58

(sim0 to 58Gbs baud rateusing dividers)

045 (12 kHz to 20MHz)047 (255MHz to 2125GHz)

054 (1 kHz to 40MHz)039 20mW

1V65 nmCMOS

Table 3 presents the performance summary and comparisonwith prior art

5 Conclusion

The design and integration of an array of LC-based clocksynthesizers for multiple transceiver links supporting variouswireline standards especially Telecommunication standardsrequires particular attention to the issue of electromagneticcoupling amongst LC VCOsThis paper develops a modelingtechnique that explains the behavior of a victim synthesizerPLL due to this coupling effect In addition a highly packableclock synthesizer employing redundant frequency mappingis designed and fabricated in a 65 nm digital CMOS tech-nology The measured clock jitter of this synthesizer is only05 psrms (integrated from 12 kHz to 20MHz) in SONETOC-48 application when all adjacent links are up and running ina plesiochronous manner that is the worst-case scenario fornoise coupling

Acknowledgments

The authors would like to thank anonymous reviewersfor their useful and constructive comments The authorsacknowledge the support of PMC-Sierra for the chip fabri-cation and testing The research is also supported in part by

the Natural Sciences and Engineering Research Council ofCanada (NSERC) and CMCMicrosystems

References

[1] K Maruko T Sugioka H Hayashi et al ldquoA 1296-to-5184Gbstransceiver with 24mW(Gbs) burst-mode CDR using dual-edge injection-locked oscillatorrdquo in Proceedings of IEEE Interna-tional Solid-State Circuits Conference (ISSCC rsquo10) pp 364ndash365February 2010

[2] DM Fischette A L S LokeMMOshima et al ldquoA 45nmSOI-CMOS dual-PLL processor clock system for multi-protocolIOrdquo in Proceedings of the International Solid-State CircuitsConference (ISSCC rsquo10) pp 246ndash247 February 2010

[3] S Desai P Trivedi and V Von Kanael ldquoA dual-supply 02-to-4GHz PLL clock multiplier in a 65nm dual-oxide CMOSprocessrdquo in Proceedings of the 54th IEEE International Solid-State Circuits Conference (ISSCC rsquo07) pp 308ndash605 February2007

[4] D Ham and A Hajimiri ldquoConcepts and methods in opti-mization of integrated LC VCOsrdquo IEEE Journal of Solid-StateCircuits vol 36 no 6 pp 896ndash909 2001

[5] W Lou X Yan Z Geng and N Wu ldquoA novel 072-62GHzcontinuously-tunable ΔΣ fractional-N frequency synthesizerrdquoin Proceedings of the 8th IEEE International Conference on ASIC(ASICON rsquo09) pp 1085ndash1088 October 2009

[6] Y-C Yang S-A Yu Y-H Liu T Wang and S-S Lu ldquoAquantization noise suppression technique for ΔΣ fractional-N


frequency synthesizersrdquo IEEE Journal of Solid-State Circuits vol41 no 11 pp 2500ndash2510 2006

[7] A Bonfanti D De Caro A D Grasso S Pennisi C Samoriand A G M Strollo ldquoA 25-GHz DDFS-PLL with 18-MHzbandwidth in 035-120583m CMOSrdquo IEEE Journal of Solid-StateCircuits vol 43 no 6 pp 1403ndash1413 2008

[8] R Gu A-L Yee Y Xie and W Lee ldquoA 625GHz 1V LC-PLL in013120583mCMOSrdquo in Proceedings of IEEE International Solid-StateCircuits Conference (ISSCC rsquo06) pp 594ndash595 February 2006

[9] H Zheng and H C Luong ldquoA 15 V 31 GHz-8 GHz CMOSsynthesizer for 9-band MB-OFDM UWB transceiversrdquo IEEEJournal of Solid-State Circuits vol 42 no 6 pp 1250ndash1260 2007

[10] N M Neihart D J Allstot M Miller and P Rakers ldquoTwistedinductors for low coupling mixed-signal and RF applicationsrdquoin Proceedings of IEEE Custom Integrated Circuits Conference(CICC rsquo08) pp 575ndash578 September 2008

[11] N Da Dalt and C Sandner ldquoA subpicosecond jitter PLL forclock generation in 012-120583m digital CMOSrdquo IEEE Journal ofSolid-State Circuits vol 38 no 7 pp 1275ndash1278 2003

[12] H-R Lee O Kim G Ahn and D-K Jeong ldquoA low-jitter5000ppm spread spectrum clock generator for multi-channelSATA transceiver in 018120583m CMOSrdquo in Proceedings of IEEEInternational Solid-State Circuits Conference (ISSCC rsquo05) pp162ndash590 February 2005

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014


Active and Passive Electronic Components

Control Scienceand Engineering

Journal of



RotatingMachinery


Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics


Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks



middot middot middotmiddot middot middot

0 05 1240

280

320

360

400

440

(p)

240

280

320

360

400

440

(p)

(p)

500

530

560

590

620

650

A-MOSCAP PMOS

CAP

Parallelcombination

Cp C3Cz

Vdd

Vdd

Rz

R3 Vcontrol

Vcontrol

Vcontrol

PMOSCap

AMOSvaractor

Icp

REFCLKCMOSphase-

frequencydetector(PFD)

Up

Down

Programmablecharge pump

Integratedloop filter

Icp LC VCO2

425ndash58GHz

LC VCO1

36ndash49GHz

Bank ofpostdividers

Outputclockdriver

Power controlswitches

Feedback clock

Fractional feedback divider

CMOS multimodulus divider(MMD)

Control signals

Δsum modulator

C0 (min) = 586pF

CLKHR(B)

Vcontrol (volt)

Figure 1 Block diagram of clock synthesizer unit (CSU)

Transmitserial data

Parallel-inserial-out

(PISO)TXTransmit

parallel data8b

8b

Half-baud-rate clockClock phasegeneration

ReceivedataRXTERM

Digital clockrecovery and

serial-inparallel-out

(SIPO)

Referenceclock

Recovered clockRecovered data

Fractional36ndash58GHz

clocksynthesizer

unit

Figure 2 Block diagram of one transceiver link

which transmits data on both transitions of the differentialclock (CLKHR-CLKHRB)

The large tuning range of the VCO (36GHz to 58GHz)comes from two LC tanks combined with a flexible post-divider bank implementing multiple divide ratios with 50output duty cycle which guarantees gapless frequency syn-thesis for baud rates from the VCOrsquos maximum frequency

of 58GHz down to 01 GHz Relying on the wide VCOfrequency range and the postdivider flexibility a redundantfrequencymapping is planned for critical telecom rates mostnotably 2488Gbs SONET that employs alternative VCOrate and postdivider combinations to avoid running adjacentVCOs at the same (or close) nominal rates This allowsdense integration of a large number of serializer-deserializer(SERDES) links each with a per-port frequency synthesizerwithout any significant inductor coupling amongst adjacentVCOs The CSU feedback path consists of a high-speedmultimodulus divider (MMD) running at the VCO rate thatis controlled by a ΔΣmodulator (DSM) [5 6] The 24b DSMuses a 3rd-order single-loop topology allowing frequencysynthesis resolution down to 2 parts per billion (ppb)A programmable integrated passive loop filter is used tosuppress the reference clock and the DSM quantization noisefrom the VCOrsquos control voltage A parallel combination ofaccumulationmode (AMOS) varactors and PMOS capacitorsis used to linearize the 119862-119881 characteristics of the on-chipcapacitor tomaintain optimal loop dynamics across the rangeof VCOrsquos control voltage 119881control (see Figure 1 inset)






119875ge | minus 1119892


where 119877119875= (120596119871)

2



119898is the













119886= 120596119900+ Δ120596 separated by


1and 119871




11989812= 119896radic119871

11198712 1198711= 1198712= 119871 (1)

119881119899OC (119905) = 11989812

119889119868119886(119905)

119889119905 (2)

where 119868119886(119905) = 119868

119886119901119896sin120596119886119905 = 119868119886119901119896



Equation (2)997904997904997904997904997904997904997904997904997904rArr 119881

119899OC (119905) = 119896119871120596119886119868119886119901119896 cos (120596119886119905)


119899(119905) = 120572119896119871120596

119886119868119886119901119896

cos (120596119886119905)

= 119881119899119901119896

cos ((120596119900+ Δ120596) 119905)

(3)





119886= 120596119900+ Δ120596


119881VCO (119905) = 119860 cos (120596119900119905) + 119881

119899119901119896cos ((120596

119900+ Δ120596) 119905) (4)




119899119901119896≪


119881VCO (119905) = 119860119881 (119905) sdot cos (120596119900119905 + 120601119881 (119905)) (5)

where

119860119881(119905) = 119860[1 + (

119881119899119901119896

119860cos (Δ120596119905))] (6)

120601119881(119905) = (

119881119899119901119896

119860sin (Δ120596119905)) (7)







119900minusΔ120596)









Frequency (GHz)446 447 448 449 45

minus350

minus300

minus250

minus200

minus150

minus100

minus50

0

Out

put v

olta

ge (d

BV)



(AM +PM)


(generated by PM)




A

AV(t)

120601V(t)

Vnpk

Δ120596

Vnpkcos(Δ120596t)

Vnpksin(Δ120596t)



120601OUT119881119862ripple

=119870VCO119878

1198782 + ((119868CP1198771198852120587119873)119870VCO) 119878 + (119868CP2120587119862119885119873)119870VCO

(8)

120601OUT119881119862ripple

=119870VCO119878

1198782 + (120596BW) 119878 + 120596BW sdot 120596119885 (9)


119885and 119862







1N

Feedback divider


REFCLK 12120587

Up

Down


VCO

120601out



minus110

minus100

minus90

minus80

minus70

minus60

minus50

Spur

tran

sfer f

unct

ion

(dB)





0

02

04

06

08

1

12

14

16


minus15E+06

minus1E

+06

minus5E

+05

0E+00

5E+05

1E+06

15E+06


TJ r

ms

(ps)




Coupled spur(dBc)












0 10 20 30 40 50 60 70

FREQ

(Hz)


3E + 09

35E + 09

4E + 09

45E + 09

5E + 09

55E + 09

6E + 09

65E + 09



VCO1

VCO2








VCO frequency(MHz)










Process technology




25V

45 nmSOI-CMOS



65 nmCMOS

[7] 229 to 275 097(10 kHz to 10MHz)

512(entire core)


035 120583mCMOS




35(entire core)

885mW15V

018120583mCMOS

This work36 to 58



054 (1 kHz to 40MHz)039 20mW

1V65 nmCMOS


5 Conclusion


Acknowledgments



References

















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation














119875ge | minus 1119892


where 119877119875= (120596119871)

2



119898is the













119886= 120596119900+ Δ120596 separated by


1and 119871




11989812= 119896radic119871

11198712 1198711= 1198712= 119871 (1)

119881119899OC (119905) = 11989812

119889119868119886(119905)

119889119905 (2)

where 119868119886(119905) = 119868

119886119901119896sin120596119886119905 = 119868119886119901119896



Equation (2)997904997904997904997904997904997904997904997904997904rArr 119881

119899OC (119905) = 119896119871120596119886119868119886119901119896 cos (120596119886119905)


119899(119905) = 120572119896119871120596

119886119868119886119901119896

cos (120596119886119905)

= 119881119899119901119896

cos ((120596119900+ Δ120596) 119905)

(3)





119886= 120596119900+ Δ120596


119881VCO (119905) = 119860 cos (120596119900119905) + 119881

119899119901119896cos ((120596

119900+ Δ120596) 119905) (4)




119899119901119896≪


119881VCO (119905) = 119860119881 (119905) sdot cos (120596119900119905 + 120601119881 (119905)) (5)

where

119860119881(119905) = 119860[1 + (

119881119899119901119896

119860cos (Δ120596119905))] (6)

120601119881(119905) = (

119881119899119901119896

119860sin (Δ120596119905)) (7)







119900minusΔ120596)









Frequency (GHz)446 447 448 449 45

minus350

minus300

minus250

minus200

minus150

minus100

minus50

0

Out

put v

olta

ge (d

BV)



(AM +PM)


(generated by PM)




A

AV(t)

120601V(t)

Vnpk

Δ120596

Vnpkcos(Δ120596t)

Vnpksin(Δ120596t)



120601OUT119881119862ripple

=119870VCO119878

1198782 + ((119868CP1198771198852120587119873)119870VCO) 119878 + (119868CP2120587119862119885119873)119870VCO

(8)

120601OUT119881119862ripple

=119870VCO119878

1198782 + (120596BW) 119878 + 120596BW sdot 120596119885 (9)


119885and 119862







1N

Feedback divider


REFCLK 12120587

Up

Down


VCO

120601out



minus110

minus100

minus90

minus80

minus70

minus60

minus50

Spur

tran

sfer f

unct

ion

(dB)





0

02

04

06

08

1

12

14

16


minus15E+06

minus1E

+06

minus5E

+05

0E+00

5E+05

1E+06

15E+06


TJ r

ms

(ps)




Coupled spur(dBc)












0 10 20 30 40 50 60 70

FREQ

(Hz)


3E + 09

35E + 09

4E + 09

45E + 09

5E + 09

55E + 09

6E + 09

65E + 09



VCO1

VCO2








VCO frequency(MHz)










Process technology




25V

45 nmSOI-CMOS



65 nmCMOS

[7] 229 to 275 097(10 kHz to 10MHz)

512(entire core)


035 120583mCMOS




35(entire core)

885mW15V

018120583mCMOS

This work36 to 58



054 (1 kHz to 40MHz)039 20mW

1V65 nmCMOS


5 Conclusion


Acknowledgments



References

















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation












119886= 120596119900+ Δ120596


119881VCO (119905) = 119860 cos (120596119900119905) + 119881

119899119901119896cos ((120596

119900+ Δ120596) 119905) (4)




119899119901119896≪


119881VCO (119905) = 119860119881 (119905) sdot cos (120596119900119905 + 120601119881 (119905)) (5)

where

119860119881(119905) = 119860[1 + (

119881119899119901119896

119860cos (Δ120596119905))] (6)

120601119881(119905) = (

119881119899119901119896

119860sin (Δ120596119905)) (7)







119900minusΔ120596)









Frequency (GHz)446 447 448 449 45

minus350

minus300

minus250

minus200

minus150

minus100

minus50

0

Out

put v

olta

ge (d

BV)



(AM +PM)


(generated by PM)




A

AV(t)

120601V(t)

Vnpk

Δ120596

Vnpkcos(Δ120596t)

Vnpksin(Δ120596t)



120601OUT119881119862ripple

=119870VCO119878

1198782 + ((119868CP1198771198852120587119873)119870VCO) 119878 + (119868CP2120587119862119885119873)119870VCO

(8)

120601OUT119881119862ripple

=119870VCO119878

1198782 + (120596BW) 119878 + 120596BW sdot 120596119885 (9)


119885and 119862







1N

Feedback divider


REFCLK 12120587

Up

Down


VCO

120601out



minus110

minus100

minus90

minus80

minus70

minus60

minus50

Spur

tran

sfer f

unct

ion

(dB)





0

02

04

06

08

1

12

14

16


minus15E+06

minus1E

+06

minus5E

+05

0E+00

5E+05

1E+06

15E+06


TJ r

ms

(ps)




Coupled spur(dBc)












0 10 20 30 40 50 60 70

FREQ

(Hz)


3E + 09

35E + 09

4E + 09

45E + 09

5E + 09

55E + 09

6E + 09

65E + 09



VCO1

VCO2








VCO frequency(MHz)










Process technology




25V

45 nmSOI-CMOS



65 nmCMOS

[7] 229 to 275 097(10 kHz to 10MHz)

512(entire core)


035 120583mCMOS




35(entire core)

885mW15V

018120583mCMOS

This work36 to 58



054 (1 kHz to 40MHz)039 20mW

1V65 nmCMOS


5 Conclusion


Acknowledgments



References

















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










1N

Feedback divider


REFCLK 12120587

Up

Down


VCO

120601out



minus110

minus100

minus90

minus80

minus70

minus60

minus50

Spur

tran

sfer f

unct

ion

(dB)





0

02

04

06

08

1

12

14

16


minus15E+06

minus1E

+06

minus5E

+05

0E+00

5E+05

1E+06

15E+06


TJ r

ms

(ps)




Coupled spur(dBc)












0 10 20 30 40 50 60 70

FREQ

(Hz)


3E + 09

35E + 09

4E + 09

45E + 09

5E + 09

55E + 09

6E + 09

65E + 09



VCO1

VCO2








VCO frequency(MHz)










Process technology




25V

45 nmSOI-CMOS



65 nmCMOS

[7] 229 to 275 097(10 kHz to 10MHz)

512(entire core)


035 120583mCMOS




35(entire core)

885mW15V

018120583mCMOS

This work36 to 58



054 (1 kHz to 40MHz)039 20mW

1V65 nmCMOS


5 Conclusion


Acknowledgments



References

















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation
















0 10 20 30 40 50 60 70

FREQ

(Hz)


3E + 09

35E + 09

4E + 09

45E + 09

5E + 09

55E + 09

6E + 09

65E + 09



VCO1

VCO2








VCO frequency(MHz)










Process technology




25V

45 nmSOI-CMOS



65 nmCMOS

[7] 229 to 275 097(10 kHz to 10MHz)

512(entire core)


035 120583mCMOS




35(entire core)

885mW15V

018120583mCMOS

This work36 to 58



054 (1 kHz to 40MHz)039 20mW

1V65 nmCMOS


5 Conclusion


Acknowledgments



References

















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation












VCO frequency(MHz)










Process technology




25V

45 nmSOI-CMOS



65 nmCMOS

[7] 229 to 275 097(10 kHz to 10MHz)

512(entire core)


035 120583mCMOS




35(entire core)

885mW15V

018120583mCMOS

This work36 to 58



054 (1 kHz to 40MHz)039 20mW

1V65 nmCMOS


5 Conclusion


Acknowledgments



References

















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation



















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









research article low-jitter 0.1-to-5.8ghz clock...

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