research institute of michigan - nasa · program at the environmental research institute of...

NASA CR-132465ERIM 195800-25-F

MIDAS, PROTOTYPE MULTIVARIATE INTERACTIVEDIGITAL ANALYSIS SYSTEM - PHASE I

1

Volume III: Wiring Diagrams

by

F. J. Kriegler, et_al.Infrared and Optics Division

E N V I R O N M E N T A L

RESEARCH INSTITUTEOF M I C H I G A N

FORMERLY WILLOW RUN LABORATORIES.

THE UNIVERSITY OF MICHIGAN

August 1974

prepared for

NATIONAL AERONAUTICS AND SPACE ADMINISTRATION

Langley Research CenterHampton, VA 23665

Contract No. NAS1-11979

https://ntrs.nasa.gov/search.jsp?R=19740024537 2018-07-13T08:57:14+00:00Z

TECHNICAL REPORT STANDARD TITLE PAGE

1. Report No. 2. Government Accession No.

NASACR-132465 ^ ^ -.«,* ,4. Title and Subtitle • ' ' -' i bSi«$ ¥*!"••'• ' • * • '

MIDAS, PROTOTYPE MULTIVARIATE INTERACTIVEDIGITAL ANALYSIS SYSTEM — PHASE IVOLUME III: WIRING DIAGRAMS7. Author(s)F. J. Kriegler et _al.9. Performing Organization Name and Address

Infrared and Optics DivisionEnvironmental Research Institute of MichiganP.O. Box 618Ann Arbor, MI 4810712. Sponsoring Agency Name and Address

National Aeronautics and Space AdministrationWashington D C 20546

3. Recipient's Catalog No.

;•-***' ^ -'-.\ ;._ i.u/»-'

' 5. 'Report DateAugust 1974

6. Performing Organization Code

8. Performing Organization Report No.195800-25-F

10. Work Unit No.

11. Contract or Grant No.NAS 1-11979

13. Type of Report and Period Covered

Final Report, October 1972through February 1974

14. Sponsoring Agency Code

15. Supplementary Notes

Volume III of ILL

16. Abstract

The MIDAS System is a third-generation,fast,multispectral recognition systemable to keep pace with the large quantity and high rates of data acquisition from pres-ent and projected sensors. MIDAS, for example, can process a complete ERTS framein forty seconds and provide a color map of sixteen constituent categories in a fewminutes. A principal objective of the MIDAS Program is to provide a system well in-terfaced with the human operator and thus to obtain large overall reductions in turn-around time and significant gains in throughput. This goal is elaborated in this reportas an objective of the Phase II program.

This report describes the hardware and software generated in Phase I of theoverall program. The system contains a mini-computer to control the various high-speed processing elements in the data path and a classifier which implements an all-digital prototype multivariate-Gaussian maximum likelihood decision algorithm op-erating at 2 x 105 pixels/sec. Sufficient hardware has been developed to performsignature extraction from computer-compatible tapes, compute classifier coefficientscontrol the classifier operation, and diagnose operation.

Volume I describes the MIDAS System in detail; Volume II contains the diagnos-tic programs used to test MIDAS' operation; Volume III displays the MIDAS con-struction and wiring diagrams.

n. Key words Real-time processingWirewrap MIDASA/D-D/A conversionMultispectral recognition systemMultivariate-Gaussian maximum

likelihood decision algorithm19. Security Classif. (of this report)

UNCLASSIFIED

18. Distribution Statement

Initial distribution listed at the endof this reportUnclassified-Unlimited

20. Security Classif. (of this page)

UNCLASSIFIED

21. No. of Pa lire

85

22. Price

FORMERLY WILLOW RUN LABORATORIES. THE UNIVERSITY OF MICHIGAN

PREFACE - -" • •.;.-,• .-

A comprehensive multisp~ec^ral_prb^paifi<de;votedrtb-tfiet:advancement of state-

of-the-art techniques for remote sensing of the environment has been a continuingprogram at the Environmental Research Institute of Michigan (ERIM), formerly

the Willow Run Laboratories of The University of Michigan. The basic objective

of this multidisciplinary program is to develop remote sensing as a practical tool

to provide the user with processed information quickly and economically.

The importance of providing timely information obtained by remote sensing

to such people as the farmer, the city planner, the conservationist, and .others

concerned with problems such as crop yield and disease, urban land studies and

development, water pollution, and forest management must be carefully considered

in the overall program. The scope of our program includes: (1) extending the

understanding of basic processes; (2) discovering new applications; (3) developingadvanced remote-sensing systems; (4) improving fast automatic data processing

systems to extract information in a useful form; and also (5) assisting in data collec-

tion, processing, analysis and ground truth verification. The MIDAS program

applies directly to No. (4) with its improved data processing capability.

This document is the final report for Phase I of the MIDAS program under

NASA Contract NAS1-11979 and covers the period from October 1972 through

February 1974. The contract effort was monitored by Mr. William Howie of NASA-

Langley. The overall program is guided by Mr. R. R. Legault, Vice President of

ERIM, and Director of the Infrared and Optics Division. Work on this contract was

directed by J. D. Erickson, Head of the Multispectral Analysis Section, and byF. J. Kriegler, Principal Investigator. The ERIM number for this report is 195800-

25-F.

ERIM personnel who contributed to this project and who co-authored this report

are Dempster Christenson, Michael Gordon, Roland Kistler, Seymour Lampert,

.Robert Marshall, and Rowland McLaughlin. In addition to providing the text, their in-

dividual contributions were as follows: Dempster Christenson and Michael Gordon

provided system programming and diagnostic software; Roland Kistler and Seymour

Lampert provided the detailed design and performed system checkout; Robert

Marshall aided in overall system configuration; Rowland McLaughlin organized this

report. The authors wish to acknowledge the direction provided by Mr. R. R. Legaultand Dr. J. D. Erickson. Outstanding contributions were made by the following per-

sons: John Baumler, Clyde Connell, William Juodawlkis, Robert Pierson, Gary

Wilson, and Nancy Wilson for their efforts in system construction.

iii

Page Intentionally Left Blank


CONTENTS

1. INTRODUCTION 1

2. GENERAL SYSTEM CONFIGURATION 2

3. CLASSIFIER SECTION , 6

4. CONTROL AND HYBRID SECTION : 35

5. BACKPLANE INTRA-BAY WIRING 63

6. SYSTEM CABLING 666.1 Cabling Between Hybrid and Control Bays 666.2 Cabling Between Classifier and Computer '66

DISTRIBUTION LIST 85


FIGURES

1. Block Diagram of the MIDAS System 3

2. Location of Major MIDAS Components 4

3. Block Diagram of the Quadratic Pipe 5

4. Block Diagram of the Mean Card 7

5. Block Diagram of the Variance Card 8

6. Block Diagram of the Matrix Multiplier Card . . . 9

7. Block Diagram of the Square Card 10

8. Block Diagram of the Square-Accumulator Card 11

9. Block Diagram of the Diagnostic/Output Card 12

10. Block Diagram of the Clock Card 13o

11. Block Diagram of the k Card 14

12. Block Diagram of the Recognition Card 15

13. Mean (MN) 16

14. Variance (VAR) 18

15. 8x8 Matrix Multiplier (MTX) 20

16. 9x9 Square Card (SQ) 22

17. Square-Accumulator (SA) . 24

18. Diagnostic/Output 26

19. Clock 29

20. k2 31

21. Recognition . . „ 33

22. Control Section 36

23. Hybrid Bay Cards (H (I-16) ) 37

24. Digital Input Synchronizer (C Ql.12) ) 38

25. Digital Output Synchronizer (C C13.14) ) 39

26. Digital Data Selector (H © ) 40

27. Hybrid Cards (H (1-16) ) 41

28. Input Bus and Port Decoder (H (lj) ) 42

29. Output Bus and Port Decoder (H (H) ) 43

30. Digital Data Selector (H © ) 4431. Analog Tape Recorder Control (C © ) 45

32. Analog Line-Count Decoder (C (D ) 46

33. Line-Count Start/Stop (C (§) ) 47

34. Digital Line-Count Decoder (C @ ) 48

vi

aERIMFORMERLY WILLOW RUN LABORATORIES, THE UNIVERSITY OF MICHIGAN

35. Video and Calibration Generator (C (6J) ) 49

36. A/D-D/A Clock Generator (C ® ) 50

37. D/A Line-Count Clock (C (j) ) 51

38. D/A Duty Cycle Generator (C (10) ) 52

39. Digital Input Programmer I (C (Tl) ) . 53

40. Digital Input Programmer II (C (12) ) 54

41. Digital Output Programmer I (C (ID ) 55

42. Digital Output Programmer II (C (H) ) 56

43. System Conditioner I (C (15) ) 57

44. System Conditioner II (C © ) 58

45. A/D Line-Control, Digital Transfer Control, andDR-11C Transfer Logic (C 17 ) 59

46. A/D Word Transfer (C © ) 60

47. Delay-Gate Generator (C (ig) ) 61

48. Playback Sync and Line-Count Clock Generator (C (20) ) 62

49. Backplane Intra-Bay Wiring 64

50. System-Cabling Diagram 67

51. Physical Layout of Plug Card (l-H) . 68

52. Output Connector Wiring of Plug Card Cl-H) 69

53. Wiring of Plug Card (27H) 70

54. Physical Layout of Plug Cards (2-H) and (2-Q) 71

55. Plug Card QTc) 72

56. DEC Block Layout 75

57. Wiring of Card (2^C) 76

58. Control Panel Wiring and Termination to Plug Card (3^C) 77

59. Physical Layout of Plug Card (4-C) 78

60. Wiring of Card (/Pc) 79

61. Cable Terminations for Data Transfer from Computerto Classifier 81

62. Cable Terminations for Data Transfer to Computerfrom Classifier. 82

63. Inter-Bay Wiring 83

VII

ERIMFORMERLY WILLOW RUN LABORATORIES, THE UNIVERSITY OF MICHIGAN

MIDAS, PROTOTYPE MULTIVARIATEINTERACTIVE DIGITAL ANALYSISSYSTEM—PHASEJ

Volume III: Wiring Diagrams

1. . , ..INTRODUCTION

This volume contains block diagrams and schematics detailing the construction of the

MIDAS Classifier. Their organization forms a tree structure in which the more general block

diagrams reference the more detailed block diagrams which lead to the schematics. This pro-

vides a self-explanatory set of diagrams enabling the reader to acquaint himself with system

design and circuitry to any desired level of detail.


2GENERAL SYSTEM CONFIGURATION

The Phase-I MIDAS System is most easily visualized if organized into subsystems as shown

in the block diagram of Fig. 1. The system is under complete control of the Digital Equipment

Corporation (DEC) PDP-11/45 computer system. All control inputs by an operator are made by

way of the computer keyboard. All commands are translated by computer software into code

words and sent out over interface devices to set up the hardware registers in the special-pur-

pose processor. These codes are decoded in three of the blocks shown in Fig. 1. These three

places are: (1) in the control section, (2) in the clock section, and (3) in the Diagnostic/Output

section. These codes will be described in detail in subsequent sections.

The MIDAS System is housed in one 6-foot rack. The physical location of the major compo-

nents is shown in Fig. 2. Each of the 4 quadratic pipes is housing in a wire-wrap card file con-

taining 13 wire-wrap circuit boards. The quadratic calculation is accomplished by a set of 12

boards in each bay while the other board in each bay is different as shown in Fig. 2.

High-speed mass data is transferred to and from the computer by means of (1) the A/D-D/A

(hybrid) section, (2) the clock section, and (3) Diagnostic/Output section. High-speed multichan-

nel data is transferred through the hybrid section and the quadratic computation pipes. The figure

numbers shown in each of the blocks of Fig. 3 refer to more detailed figures describing that

block.

The control bay and the hybrid bay have room for 22 circuit boards. There are 20 boards

in the control bay numbered C-l through C-20. There are 19 boards in the hybrid file numbered

H-lthrough H-19.

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3CLASSIFIER SECTION

A detailed description of the Classifier is given in Sections 4 and 6 of Volume I.

A block diagram of the quadratic pipe computation is shown in Fig. 3.

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4 1CONTROL AND HYBRID SECTION

The hybrid section of the classifier contains nineteen cards, of which sixteen are identical

printed circuit cards. These cards, located in slots H-l through H-16, perform the transfer of data

to the classifier. A block diagram of the control and hybrid section is shown in Fig. 22 and a

detailed block diagram of the hybrid cards is shown in Fig. 23. For a description of this clas-

sifier section, see Section 6 of Vol. I.

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•The wirewrap card files have backplanes with wirewrap connectors. These back-bay con-nectors have 122 pins, of which 10 are used for power and 10 for ground. Connections are

shown in Fig. 49. Signal origins are shown by arrows. The various card locations are designated

by odd numbers 1, 3, . . . , 25. ..

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6 'SYSTEM CABLING

6.1 CABLING BETWEEN HYBRID AND CONTROL BAYS

The wiring for data and control signals flows between the hybrid and control bays including

PC-board card plugs that terminate the cables interconnecting the bays. One end of each printed

circuit board accommodates cable wires at tie points (T.P.) on the card; the other end of the PC

board has a printed circuit connector that mates with a card slot in the connector housing asso-ciated with a particular bay.

The connector housings comprise two auxiliary files located at the rear of the control and

hybrid bays, respectively. In each of these files are four card slots for the card plugs of the

cables. Each slot is assigned a number (1 through 4) and a code letter (C or H) to give its posi-

tion in the file and identify that file with one of the two bays (control or hybrid). Figure 50 showsoverall system cabling; the table below lists the terminations of the cables that originate in the

two auxiliary files.

SLOT in Aux. File TERMINATION

r 1-C MIDAS CLASSIFIERControl! 2-C 2-HBay 1 3-C CONTROL PANEL

(.4-C DR-11C INTERFACE

{ 1-H DR-11B INTERFACE2-H 2-C3-H BNC CONNECTOR PANEL4-H BNC CONNECTOR PANEL

The description of the interconnecting cables to and from the bays is given in Figs. 51 to 60;

these figures detail the card plugs and also further describe the termination of the cables that

tie into the auxiliary card files. As indicated in these diagrams, certain of the signals are

buffered on the card plugs by line drivers (8T13) and line receivers (8T14). From Fig. 50 we

see that cable 1C terminates eventually at the classifier. This is via a card plug that mates

with a standard DEC block; then from the DEC block the signals are brought to the classifierusing point-to-point wirewrap. Figure 55 shows the layout of the card plugs associated with the

DEC block while Fig. 56 gives the block configuration. It may be noted that the cables originat-

ing from slots 3-H and 4-H are not detailed in this section.

6.2 CABLING BETWEEN CLASSIFIER AND COMPUTERAs indicated in the system cabling diagram (Fig. 50), a cable runs from the classifier to a

DR-11B interface; it is used to carry information (e.g., RAM load, classifier output, diagnostic

info ) to and from the classifier through the DEC block. At the classifier end, this cable termi-

nates in a card plug which connects to a DEC block (for block layout, see Fig. 56). The classifier

66


c Control"anel

DR-11CInterface

C

Douglas Board ^ \ ' '. MsAux.

Figs. 55-60 Conn- Controls File File(4 Cards)

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FIGURE 50. SYSTEM- CAB LING DIAGRAM

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connection to the computer via the DR-11B is through line drivers and receivers located on the

card plugs; these cards are detailed in Figs. 61 and 62. The classifier inter-bay wiring and

cabling to the DEC block are shown in Fig. 63.

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