Research  activity  3rd  year  &  final  report  

Research  Unit  (RU)  5  :  Integrated  Systems  for  Millimeter  Wavelength   Focus of the performed research During the third year, the research activities have been focused on the development of a complete quadrature receiver including the synthesizer for 60GHz wireless communications advanced circuit techniques for frequency generation at millimeter Waves and SubTHz. The objectives of the research are in line with the main target of the A.o.P. for the growing of the scientific and technical knowledge in the High Tech. area of Microelectronics and its field of applications for the years to come. In particular, there is more and more evidence that millimeter waves systems (at 60GHz and beyond) are drawing attention, and when integrated in low cost technologies like CMOS, will enable a large diffusion of commercial products as well as services of social utility (e.g. automotive anti-collision radar systems for safety, wireless interconnections at Gbit/sec, Imaging systems for security, industrial control and medical applications). The two research themes addressed in the last time frame of the project refer to:

- Design and realization of a complete quadrature receiver front-end & frequency synthesizer for 60GHz wireless connectivity

- Advanced circuit techniques for frequency generation at mmWave and Sub-THz frequency,

We have addressed in depth the study of ultrascaled technologies (down to 65nm), the investigation of new circuit topologies and system architectures, the design of individual blocks and functional subsystems, as essential vehicular steps toward the realization of highly integrated systems. The main design target is on power consumption saving (low-voltage, low-power) and to chip area optimization. Based on an intense collaboration between the group and STMicroelectonics (a joint laboratory is housed in the campus), several prototypes have been realized and characterized using the most advanced CMOS processes made available from ST. Achievements In the last year, the specific activities and the obtained results are listed as:

a) Development of an innovative wideband receiver front-end for 60GHz wireless communications.

In the second year of the activity, a first receiver prototype addressing 60GHz wireless communications has been realized and tested. A second version of the receiver has been developed, realized and tested in the last period of the project. This prototype employs improved circuit solutions for the low noise amplifier and mixer which make it able to fulfill all the performance requirements by ECMA and WiHD communication standards. The prototype is able to cover a very wide RF bandwidth, of more than 13GHz and can tolerate large components variations due to processing spreads.

b) Development of an innovative phase locked loop for the 60GHz wideband receiver front-end The complete frequency synthesizer for the mmWave receiver has been designed and integrated together with the front-end. The synthesizer is based on an integer-N phase locked loop and covers all the four channels of the standard. Phase noise of the local oscillator impairs significantly the bit-error rate of the communication. A detailed system study has been carried out to accurately define optimal specifications for the PLL and building blocks. The key implemented circuits are a 40GHz VCO with wide tuning range and a pair of injection locked dividers for quadrature signal generation at 20GHz. Synthesizer performances in terms of spectral purity, frequency coverage and power dissipation compare favorably against state-of-the art.

c) System analysis for the integration of the 60GHz receiver front-end with base-band interface

(filters and ADCs). A system level simulation has been carried out in order to define the specifications for the base-band building blocks which should allow the analog RF front-end to realize a complete transceiver, addressing communications at more than 6Gbit/sec. Specifications have been derived for variable gain amplifiers, low-pass filters for channel selection and analog to digital converters, assuming a wireless link based on OFDM modulation, according to suggestions of the emerging standardization activities. Specifications derived for the base-band building blocks are in line with performances of filters and ADCs realizations reported in the technical literature demonstrating the effective possibility to complete the receiver in standard CMOS technology.

d) Development of a wideband mmWave frequency divider and quadrature VCO

A very promising receiver architecture for the next generation of mmWave receivers is very likely based on direct conversion to baseband of the RF signal. The main issue which is the lack of a high performance quadrature generators at high frequency. To this extent, in the last year of the research activity, we developed a new topology of voltage controlled oscillator with low phase noise and quadrature outputs, operating at 60GHz. We also proposed a new topology of mmWave frequency divider to implement a phase locked loop, based on dynamic CML latches, which works up to 70GHz frequency without requiring inductors. Compared to state-of-the art, the realized divider is extremely compact and requires very low power dissipation.

e) Development of an integrated circuit generating wideband local oscillator signals at 115GHz

In the next future, applications in the SubTHz frequency range (beyond 100 GHz) are envisioned. One   of   the   challenges   of   such   high   frequency   systems   is   the   on-­‐chip   reference   frequency  generation.   In   this   research  project  we  developed  a  new   frequency  multiplier   circuit  which  provides   differential   output   signals   over   a   band   of  more   than   20GHz   centered   at   115GHz.    Prototypes   have   been   realized   in   a   65nm   CMOS   technology   and   characterized   with   a  mmWave  measurement  setup  purposely  developed.

The quality of the achieved results is demonstrated by 6 presentations at IEEE International Conferences, and 5 article published on IEEE Journals.

Published results A description of the journal publications related to the prototypes realized in the last year of the research project is reported in the following: A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS. High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20%, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploited inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. We designed, realized and successfully tested a complete receiver front-end based on the sliding IF architecture shown in figure 1. The RF signal is translated to a sliding IF by means of a mixer driven by a 40GHz local oscillator and then demodulated to base-band with a pair of mixers driven by quadrature local oscillators. To achieve wide-band operation, a new LNA topology with inter-stage matching network based on coupled resonators has been developed. The circuit schematic is shown in figure 2. Proper selection of the component values leads to a bandwidth much wider than with traditional interstage networks based on a single resonator, without penalty in gain. The LNA is made of three stages with inductive degeneration of the input transistor to improve the noise figure. Total gain of the LNA is 28dB over a bandwidth of 15GHz and an in-band noise figure of 5.5dB.

Fig. 1: block diagram of the sliding-IF mmWave receiver.

Fig. 2: Schematic of the mmWave Low Noise Amplifier

.

The frequency synthesizer is an integer-N type-II PLL, with a three state phase frequency detector – charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low. The block diagram of the PLL is shown in figure 3. The VCO is based on a differential-pair driving an LC resonator tuned at 40GHz. For wide-band coverage, the resonator frequency is programmable by means of switched Metal-Oxide-Metal capacitors. The high frequency dividers, generating the 20GHz quadrature signals are based on the injection locking principle. An optimized design leads to a frequency locking range wider than 16GHz.

Fig. 3. Block diagram of the frequency synthesizer.

Fig. 4. Chip photograph.

A test chip has been realized in a 65nm CMOS technology. A photomicrograph is shown in figure 4. Experiments provide: 6.5 dB maximum noise figure over 13 GHz bandwidth, 35 dB of conversion gain, 22.5 dBc integrated phase noise while consuming 84 mW.

Injection-locked CMOS Frequency Doubler for mm-wave Applications. Applications at millimeter-waves and even in the THz gap are flourishing due to the ever increasing speed of CMOS devices in ultra-scaled nodes. A major obstacle to low power transceiver implementation is due to the degradation with increasing frequency of key passive components, variable capacitors in particular. This is particularly severe in frequency synthesizers where high frequency VCOs consume large power, display relatively poor spectral purity and have limited tuning range, and PLLs prescalers require large input voltage swing and eventually burn more power than the VCO itself.

Fig. 5. Behavioural model and circuit schematic of the frequency multiplier

In this frame-work, frequency multipliers can play a key role, allowing the design of Voltage Controlled Oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this work, we developed a new topology of injection locked frequency doubler working at F-band. The proposed circuit requires limited input signal swing and provide a differential output over a broad frequency range, with very low power dissipation. A behavioural model and the schematic of the proposed multiplier are shown in figure 5. The circuit is basically a resonant (LC) oscillator with differential output which is injection locked by a push-push pair driven by the input signals at half the final output frequency. A mathematical description of the circuit allowed to derive simple and closed form expressions to guide the design. Two test chips have been realized in 65nm CMOS technology targeting a center output frequency of 115GHz. Photograph of the chips is shown in figure 6. The multiplier can be driven either off-chip, by a mmWave signal source, and on-chip from an integrate VCO running at 57GHz. Measurements on the multiplier drive off-chip proved an operation bandwidth from 106GHz to 128GHz with a peak voltage swing on each output of 330mV and a core power dissipation of 6mW only. The multiplier driven by the half-frequency on-chip VCO demonstrated an outstanding 13.1% tuning range around 115GHz.

Fig. 6. Photograph of the multiplier test-chips

A low noise Quadrature VCO based on magnetically coupled resonators and a wide-band frequency divider at mm-waves Wireless on-chip processing at mm-waves still lacks key functions: quadrature generation enabling direct conversion architectures and simplifying phased array systems, frequency division with an operating range wide enough to compensate spreads due to component variations. In this work we addresses the design of quadrature Voltage Controlled Oscillators (VCOs) and prescalers, the two most critical blocks of a mm-wave PLL, introducing new circuit solutions.

Fig. 7. Block diagram of the proposed mmWave quadrature VCO

Single phase VCOs followed by transmission lines or hybrids are suited for quadrature signal generation at high frequency. The drawback is a relatively large power consumed by the buffers interfacing VCOs to distributed passive components. We have thus investigated alternatives limiting power consumption. Conventional cross-coupled LC VCOs constitute the most suitable topology borrowed by RF solutions. But, the oscillation frequency dependence on the biasing current makes it susceptible to phase noise, close-in in particular.

The proposed solution, where the block diagram is shown in figure 7, relies on a ring of two tuned amplifiers, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. The inter-stage networks are based on two magnetically coupled resonators each one introducing 90° of phase shift at the resonant frequency. A detailed analysis of the circuit to derive equations for phase noise, phase accuracy has been carried out to guide the design phase. Prototypes of the circuit,, realized in 65nm CMOS, show 56GHz to 60.4GHz tunable oscillation frequency, phase noise better than -95dBc/Hz at 1MHz offset in the tuning range, 1.5° maximum phase error while consuming 22mA from 1V supply. Experimental results compares favorably against reported mmWave state-of-the-art quadrature generators.

Fig. 8. Block diagram of the proposed mmWave divider and typical waveforms

Frequency dividers for phase locked loops, based on traditional static CML latches, work over a wide band but power dissipation at mm-waves is extremely large. Injection locked LC dividers save power dissipation but have limited tunability and occupy large silicon area. Dividers based on injection locked ring oscillators are compact, low power and can be tuned over a wide frequency range. Many CMOS realizations have been proposed with an operating frequency up to 20GHz. Few realizations have been reported working at mm-wave but the frequency locking range is extremely narrow (less than 4%) mandating fine and frequent calibrations. Clocked differential amplifiers, working as dynamic CML latches, have been introduced in this work to realize high speed and low power mm-wave dividers. A block diagram of a mmWave frequency divider by four is shown in figure 8. Typical waveforms at the input and output of one of the latches are also reported. The divider does not need inductors to speed up the operating frequency thus leading to a very compact solution. A fair comparison against a divider based on traditional CML latches has been carried out demonstrating a 2x increase in the operating frequency for the same power dissipation. A divider by 4 realized in 65nm CMOS occupies 15µm x 30µm, features an operating frequency programmable from 20GHz to 70GHz in nine bands and consumes <6.5mW. The photographs of the divider and VCO test-chips are shown in figure 9.

Fig. 9. Photographs of the mmWave quadrature VCO and dynamic divider List of Publications [1] E.Monaco, M.Pozzoni, F.Svelto, A.Mazzanti “Injection-locked CMOS Frequency Doublers for µ-

wave and mm-wave Applications”, IEEE Journal of Solid State Circuits, vol.45 no.8, pp. 1567-1574, August 2010.

[2] A.Mazzanti, M.Vahidfar, M.Sosio, F.Svelto “A Low Phase-Noise Multi-Phase LO Generator for

Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers” IEEE Journal of Solid State Circuits, vol.45 no. 10, pp.2104-2115, October 2010.

[3] A.Mazzanti, M.Sosio, M.Repossi, F.Svelto “A 24 GHz Subharmonic Direct Conversion Receiver

in 65 nm CMOS” IEEE Transaction on Circuits and systems-I: Regular papers, Vol 58, no.1, pp. 88-97, Jan. 2011.

[4] U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti, F. Svelto, “A low noise Quadrature VCO

based on magnetically coupled resonators and a wide-band frequency divider at mm-waves”, IEEE Journal of Solid State Circuits, in press.

[5] A.Mazzanti, E.Monaco, M.Pozzoni, F.Svelto “A 13.1% Tuning Range 115GHz Frequency

Generator Based on an Injection-Locked Frequency Doubler in 65nm CMOS” IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011, San Francisco, Feb. 2010.

[6] F. Vecchi, S. Bozzola, M. Pozzoni, D. Guermandi, E. Temporiti, M. Repossi, U. Decanis, A.

Mazzanti, F. Svelto “A wide-band mm-wave CMOS Receiver for Gb/s communications employing inter-stage coupled resonators” IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011, San Francisco, Feb. 2010.

[7] E. Monaco, M. Pozzoni, F. Svelto, A. Mazzanti, "A 6mW, 115GHz CMOS Injection-Locked Frequency Doubler with Differential Output", Proceedings of the IEEE International Conference on Integrated Circuits Design and Technology (ICICDT), pp. 236-239 June 2-4, Grenoble (France) 2010. Received the “Best Student Paper” AWARD

[8] F. Vecchi, S. Bozzola, M. Pozzoni, D. Guermandi, E. Temporiti, M. Repossi, U. Decanis, A. Mazzanti, F. Svelto "A 60GHz Receiver with 13GHz Bandwidth for Gbit/s Wireless Links in 65nm CMOS", proceedings of the IEEE International Conference on Integrated Circuits Design and Technology (ICICDT), pp. 228-231 June 2-4, Grenoble (France) 2010.

[9] A. Ghilioni, U. Decanis, E. Monaco, A. Mazzanti, F. Svelto: "A 6.5mW inductorless CMOS

frequency divider-by-4 operating up to 70GHz"; IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011, San Francisco, 20-24 February 2011, pp. 282-284.

[10] U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti and F. Svelto: "A mm-Wave quadrature VCO

based on magnetically coupled resonators"; IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011, San Francisco, 20-24 February 2011, pp. 280-282