712 IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 6, JUNE 2017

Resistor-Triggered SCR Device for ESDProtection in High-Speed I/O Interface Circuits

Chun-Yu Lin, Member, IEEE, and Chun-Yu Chen

Abstract— In this letter, an on-chip electrostaticdischarge (ESD) protection device was proposed for high-speed I/O interface circuits. A resistor-triggered silicon-controlled rectifier device with improved performance wasdesigned and investigated in a nanoscale CMOS process.As verified in a 0.18-µm CMOS process, the proposeddesign exhibits a lower clamping voltage and low enoughovershoot voltage during ESD stress conditions, and lowerparasitic capacitance and low enough leakage currentduring normal circuit operating conditions. Therefore,the proposed design is suitable for ESD protection ofhigh-speed circuits in low-voltage CMOS processes.

Index Terms— Electrostatic discharge (ESD), high-speed,silicon-controlled rectifier (SCR).

I. INTRODUCTION

ELECTROSTATIC discharge (ESD) protection is a mustfor the integrated circuits realized in CMOS processes,

since the integrated circuits are very sensitive to ESD events.For high-speed I/O interface circuits, the ESD protectiondesign has been strongly requested from the IC indus-try [1], [2]. Therefore, improved ESD protection design toprotect the high-speed integrated circuits is needed. A silicon-controlled rectifier (SCR) device has been used as the effectiveESD protection device due to its high robustness, compactlayout area, low parasitic capacitance, low leakage current, andfreedom from latchup in a low-voltage environment [3], [4].The conventional SCR device in low-voltage CMOS processesconsists of P+, N-Well, P-Well, and N+. The equivalent circuitof the SCR consists of a PNP BJT (QPNP) and an NPN BJT(QNPN) [4]. As ESD zapping occurs from anode to cathode,the positive-feedback regenerative mechanism of QPNP andQNPN results in the SCR device being highly conductive, thusmaking SCR very robust against ESD stresses. However, turn-ON speed is one of the most important design considerations inusing SCR for ESD protection, especially during fast-transientpulse-like charged-device-model (CDM) stress. Several priordesigns have been presented to enhance the turn-ON speedof the SCR device with sufficiently low trigger voltage andovershoot voltage [5]–[8]. The inductor-assisted SCR devicefor high-frequency applications was designed to trigger at

Manuscript received April 5, 2017; revised April 14, 2017and April 19, 2017; accepted April 19, 2017. Date of publication April 24,2017; date of current version May 22, 2017. This work was supported inpart by the Ministry of Science and Technology, Taiwan, under ContractMOST 106-2622-E-003-001-CC2, and in part by Amazing Microelec-tronic Corp., Taiwan. The review of this letter was arranged by EditorM. Tabib-Azar. (Corresponding author: Chun-Yu Lin.)

The authors are with the Department of Electrical Engineering, NationalTaiwan Normal University, Taipei 106, Taiwan (e-mail: cy.lin@ieee.org).

Color versions of one or more of the figures in this letter are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2017.2696980

5 V [5], but it requires an additional inductor area. Thegate-bounded SCR devices use a dummy gate to shorten thedistance between the anode and cathode [6], but they requireadditional process steps to block the silicide to decrease theleakage current or to form the Schottky junction to increasethe holding voltage. Another gate-bounded SCR device usesan additional resistor–capacitor timer to control the gate [7];of course, it needs an additional area to implement the∼100 k� resistor and ∼pF capacitor. The direct-connectedSCR (DCSCR) device was designed with the same triggervoltage and holding voltage of 1.3 V [8]; in fact, the parasiticcapacitance of this device can be further reduced for high-speed applications.

In this work, an SCR device with low trigger voltage, lowleakage current, low parasitic capacitance, and which requiresno additional process step for ESD protection is proposed.This work proposes a novel SCR device that meets theserequirements, and its performance has been verified in ananoscale CMOS process.

II. CONVENTIONAL AND PROPOSED SCR DEVICE

FOR HIGH-SPEED APPLICATIONS

Figure 1(a) shows the device cross-sectional view of theconventional DCSCR device, and Fig. 2(a) shows its metalconnection. The four layers of P+, N-Well, P-Well, and N+form a typical SCR device in low-voltage CMOS processes.Putting the anode of the SCR device in the center can minimizethe parasitic capacitance seen at the anode. Besides, theN-Well and P-Well are connected together in this design. TwoESD current paths exist from anode to cathode, includinga diode stackup (P+/N-Well and P-Well/N+ diodes) and anSCR (P+, N-Well, P-Well, and N+). In the beginning of theESD stress, the diode stackup will turn on to discharge theinitial current, and then the SCR will take over to dischargethe primary current. The diode stackup also plays the role oftrigger circuit of the SCR, because the current drawn fromthe N-Well (injected into P-Well) can also trigger the QPNP(QNPN) of the SCR.

The proposed SCR device uses a small resistor as the triggerelement. Fig. 1(b) shows the proposed resistor-triggered SCR(RTSCR) device, and Fig. 2(a) shows its metal connection.The four layers of P+, N-Well, P-Well, and N+ form theSCR path, and the N-Well and P-Well are connected througha resistor (RT ) in this design. The current drawn from theN-Well (the base of QPNP), through the RT , and then injectedinto the P-Well (the base of QNPN) can trigger on the SCR.Besides, the RT can limit the large ESD current from flowingthrough the P+/N-Well and P-Well/N+ diodes, and the largeESD current can be discharged through the robust SCR path.Furthermore, the RT can also help to reduce the equivalent

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LIN AND CHEN: RTSCR DEVICE FOR ESD PROTECTION IN HIGH-SPEED I/O INTERFACE CIRCUITS 713

Fig. 1. Device cross-sectional views of: (a) conventional ESD protectiondesign of DCSCR and (b) proposed ESD protection design of theRTSCR.

Fig. 2. Metal connections of: (a) conventional ESD protection design ofDCSCR and (b) proposed ESD protection design of the RTSCR.

capacitance seen at the anode, which will be better for high-speed applications. Considering the simplified SCR model byusing junction capacitances, Eq. (1), as shown at the bottomof this page, expresses the equivalent capacitance seen at theanode of the RTSCR, in which YRTSCR denotes the admittanceof the RTSCR, and CP+/N−Well, CP−Well/N−Well(Deep N−Well),

Fig. 3. Layout top views of: (a) conventional ESD protection design ofthe DCSCR and (b) proposed ESD protection design of the RTSCR with150 Ω RT (RTSCR_150� ).

and CP−Well/N+ denote the junction capacitances. In general,the junction capacitance is ∼100 fF for an ESD protectiondevice. To simplify Eq. (1), the junction capacitance is rewrit-ten to CJ , and then the parasitic capacitance of the RTSCR canbe expressed by Eq. (2), as shown at the bottom of this page.It can be noted that the parasitic capacitance of the RTSCRcan be reduced by increasing RT . Using the more accuratemodel, one can obtain more precise results [9].

III. EXPERIMENTAL RESULTS

To compare the conventional and proposed ESD protectiondesigns in silicon, a 0.18-μm CMOS process was used.Figures 3(a) and (b) show the layout top views of the DCSCRand one RTSCR. The width of each SCR device was selectedto be 20 μm. The RT was split to be 25, 75, and 150 �.

A. ESD Stress ConditionThe clamping voltage during ESD stress must be less than

the failure voltage of ∼10 V in a 0.18-μm CMOS process [10].The I–V characteristic of each test device was evaluatedusing a transmission-line-pulsing (TLP) system. The TLP-measured I–V characteristics are shown in Fig. 4. The triggervoltage (Vt1) of the DCSCR is 1.82 V, and those of the RTSCRwith 25, 75, and 150 � RT (RTSCR_25�, RTSCR_75�,and RTSCR_150�) are 1.75, 1.69, and 1.50 V, respectively.The second breakdown currents (It2), which indicate thecurrent handling ability, of the conventional and proposed ESDprotection designs are all ∼2.1 A.

CRT SC R = Im (YRT SC R)

ω=

Im

⎛⎜⎝ 1

1jωCP+/N−Well

+ 11

RT+ jωCP−W ell/N−W ell(Deep N−W ell)

+ 1jωCP−Well/N+

⎞⎟⎠

ω(1)

CRT SC R = Im

⎛⎜⎝ 1

2jCJ

+ 11

ωRT+ jCJ

⎞⎟⎠ =

2CJ

+ ω2 R2T CJ

1+ω2 R2T C2

J(2

CJ+ ω2 R2

T CJ

1+ω2 R2T C2

J

)2

+(

ωRT1+ω2 R2

T C2J

)2 ≈ CJ

2 + 32ω2 R2

T C2J

(2)

714 IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 6, JUNE 2017

Fig. 4. TLP-measured I–V curves of conventional and proposed ESDprotection designs.

Fig. 5. VF-TLP-measured I–V curve and transient voltage waveformsof conventional and proposed ESD protection designs.

Another very fast TLP (VF-TLP) system was used toevaluate the effectiveness of the test devices in the timedomain of a CDM ESD event. Figure 5 shows the VF-TLP-measured I–V curves and the transient voltage waveforms inthe holding region of the test devices. The measurement resultsshow that the overshoot voltages of DCSCR, RTSCR_25�,RTSCR_75�, and RTSCR_150� at 0.5 A are 4.2, 4.6, 5.0,and 5.5 V, respectively. The overshoot voltages of the RTSCRdevices are low enough to protect the internal circuits fromCDM ESD damage.

B. Normal Circuit Operating Condition

The parasitic capacitance of each test device was measuredusing an S-parameter measurement system. Figure 6 showsthe extracted parasitic capacitance seen at the anode of eachtest device. Here the parasitic effects of the pads have beenremoved using a standard open/short de-embedding procedure.For 40 Gb/s applications, the parasitic capacitance at thefundamental frequency (20 GHz) of DCSCR, RTSCR_25�,RTSCR_75�, and RTSCR_150� are 39.9, 32.4, 31.9, and31.6 fF, respectively. The parasitic capacitance of the RTSCRhas ∼20% reduction compared to the DCSCR.

The leakage currents of the test devices are measured.Figure 7 shows the measured leakage currents of theconventional and proposed ESD protection designs at 100 °C.As the anode is biased from 0 V to 1 V with the grounded

Fig. 6. Measured parasitic capacitances of conventional and proposedESD protection designs.

Fig. 7. Measured leakage currents of conventional and proposed ESDprotection designs at 100 °C.

cathode, the leakage currents of all test devices are < 1μA.In fact, the bias and supply voltages of the high-speed circuitsare usually near or even lower than the threshold voltage ofthe transistor. Therefore, as the operation voltage is <1 V, theproposed ESD protection design can be used for high-speedapplications with <1 μA leakage current at 100 °C.

IV. CONCLUSION

The ESD protection device of the RTSCR has beendesigned, fabricated, and characterized in a 0.18-μm CMOSprocess. Experimental results show that the RTSCR devicecan achieve low parasitic capacitance, fast turn-ON speed,high ESD robustness, low leakage current, and a compactlayout area. In fact, the proposed design can also be usedin other low-voltage CMOS processes. Based on its goodperformance during ESD stress and normal circuit operatingconditions, the proposed design is confirmed for use in high-speed applications.

ACKNOWLEDGMENT

The authors would like to thank National Chip Implementa-tion Center (CIC), Taiwan, for the support of chip fabrication.The authors would also like to thank Prof. Ming-Dou Ker,Mr. Jie-Ting Chen, and Mr. Rong-Kun Chang in NationalChiao Tung University, Taiwan, for their great help duringESD testing.

LIN AND CHEN: RTSCR DEVICE FOR ESD PROTECTION IN HIGH-SPEED I/O INTERFACE CIRCUITS 715

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