resonant modular multilevel dc-dc converters for both high

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

Resonant Modular Multilevel DC-DC Converters for

both High and Low Step-Ratio Connections in

MVDC Distribution Systems

Xin Xiang, Member, IEEE, Yunjie Gu, Senior Member, IEEE, Yang Qiao, Xiaotian Zhang, Member, IEEE, Wuhua Li, Member, IEEE, Xiangning He, Fellow, IEEE, Timothy C. Green, Fellow, IEEE

Abstract—DC transformers based on power electronics are key

items of equipment for medium voltage dc (MVDC) distribution

systems. Both high and low step-ratio dc-dc conversions are

required to interface dc links at different voltages to form an

integrated dc distribution system. The transformer-coupled

resonant modular multilevel dc-dc converter (RMMC) is well-

suited to high step-ratio connection between a MVDC network and

a low voltage dc (LVDC) network but it is not suitable in low step-

ratio conversion for linking two MVDC networks with similar but

not identical voltages. This paper presents a circuit evolution of the

high step-ratio transformer-coupled RMMC into its low step-ratio

transformer-less RMMC counterpart. These two RMMCs share the

same structure and the same resonant process within the resonant

SM stack (RSS) giving rise to the same operational advantages. Also,

the circuit design experience can be readily transferred from one to

the other. From these two base RMMC circuits, a family of RMMCs

with further configurations is elaborated that provide a wider variety

of connection options for MVDC distribution systems. In this circuit

family, each high step-ratio transformer-coupled RMMC has a low

step-ratio transformer-less RMMC counterpart and one can be

transformed into the other via the circuit evolution process

presented. The theoretical analysis for both high and low step-

ratio RMMCs has been verified through full-scale simulations of

medium voltage examples and further verified through down-

scaled experiments on laboratory prototypes.

Index Terms—RMMC, high step-ratio, low step-ratio, MVDC

distribution systems.

NOMENCLATURE

𝐶𝑑 Double-voltage capacitance 𝐶𝑑𝑖𝑓 Differential capacitance

A preliminary version of this paper was presented at IEEE IECON 2019, Oct.

14-17, 2019 in Lisbon, Portugal [42].

This work was supported by the National Natural Science Foundation of

China (NSFC) under award 52061635101 and Engineering and Physical

Sciences Research Council of UK (EPSRC) under awards EP/T021780/1 and

EP/S000909/1. (Corresponding authors: Wuhua Li and Yunjie Gu.)

X. Xiang, W. Li and X. He are with College of Electrical Engineering,

Zhejiang University, Hangzhou, 310027, China. (e-mail: [email protected],

[email protected]; [email protected]).

Yunjie Gu is with the Department of Electronic and Electrical Engineering,

University of Bath, Bath BA2 7AY, U.K. (e-mail: [email protected])

Y. Qiao and X. Zhang are with Department of Electrical Engineering, Xi’an

Jiaotong University, Xi’an, 710049, China. (e-mail: qiaoyang888@stu.

xjtu.edu.cn; [email protected]).

T. C. Green is with the Department of Electrical and Electronic Engineering,

Imperial College London, London, SW7 2AZ, U.K. (e-mail: t.green@imperial.

ac.uk).

𝐶𝐿𝑆 Low-voltage side dc link capacitance

𝐶𝑀𝑆 Medium-voltage side dc link capacitance

𝐶𝑆𝑀 SM capacitance

𝑓𝑒 Effective frequency

𝑓𝑛 Resonant frequency during negative stage 𝑓𝑝 Resonant frequency during positive stage

𝑓𝑠 Switching frequency

𝑖𝐶𝑑 Current through the double-voltage capacitor 𝑖𝑙𝑜𝑤 Current through the SM lower switch

𝑖𝑆1,2,3,4 Current through the rectifier 𝑆1 , 𝑆2 , 𝑆3 , 𝑆4

𝑖𝑇𝑅𝑆 Transformer current on the secondary side 𝑖𝑢𝑝 Current through the SM upper switch

𝐿𝑚 Magnetizing inductance

𝐿𝑟 Resonant inductance

𝑀 Inserted SM number in positive stage

𝑁 Inserted SM number in negative stage (SM total number)

𝑛1 Transformer primary turns

𝑛2 Transformer secondary turns

𝑃𝑅 Power range

𝑅𝐻 Overall voltage ratio of high step-ratio RMMC 𝑅𝐿 Overall voltage ratio of low step-ratio RMMC

𝑟𝑇 Transformer turns-ratio

𝑉𝐵 Balanced dc voltage

𝑉𝐶𝑑 Voltage on the double-voltage capacitor

𝑣𝐶𝑗 SM capacitor voltage (𝑗 = 1,2, … , 𝑁)

𝑉𝑑𝑖𝑓 Voltage between two medium-voltage terminals

𝑉𝐹𝐵𝑅 Voltage stress on the full-bridge rectifiers

𝑉𝐻𝐵𝑅 Voltage stress on the half-bridge rectifiers

𝑣𝐿𝑚 Voltage on the magnetizing inductor

𝑣𝐿𝑚𝑁 Voltage on the magnetizing inductor during negative stage

𝑣𝐿𝑚𝑃 Voltage on the magnetizing inductor during positive stage

𝑣𝑙𝑜𝑤 Voltage on the SM lower switch

𝑉𝐿𝑆 Voltage on the low-voltage terminal

𝑉𝑀𝑆 Voltage on the medium-voltage terminal

𝑉𝑀𝑆1 Voltage on the first medium-voltage terminal

𝑉𝑀𝑆2 Voltage on the second medium-voltage terminal

𝑣𝑆𝑂𝑗 SM output voltage (𝑗 = 1,2, … , 𝑁)

𝑣𝑆𝑇 Stack voltage

𝑣𝑆1,2,3,4 Voltage on the rectifier 𝑆1 , 𝑆2 , 𝑆3 , 𝑆4

𝑣𝑇𝑅𝑆 Transformer voltage on the secondary side 𝑣𝑢𝑝 Voltage on the SM upper switch

𝛾 Maximum ripple for SM capacitor voltage

_𝐵 Subscript for bottom in derivative RMMCs

_𝐿 Subscript for left in derivative RMMCs

_𝑅 Subscript for right in derivative RMMCs

_𝑇 Subscript for top in derivative RMMCs

mailto:[email protected]





I. INTRODUCTION

The rapid development of high voltage dc (HVDC)

transmission systems for integration of large-scale renewable

energy and the promising prospect for low voltage dc (LVDC)

distribution systems for integration of small-scale distributed

renewable energy have created a strong impetus for considering

dc schemes at the medium voltage level [1]–[4]. Medium

voltage dc (MVDC) scheme can be expected to be a better

intermediate layer between HVDC transmission and LVDC distribution than the traditional medium voltage ac (MVAC)

counterpart as the use of dc becomes more common at the top

and bottom of the power systems. There is also evidence that

the better utilization of line and cable capacity and compact

footprint of MVDC systems will be attractive for urban

distribution systems [5]–[7] where the space available for

power networks is usually limited yet the load demand is

expected to rise further in the coming decade.

One of the key challenges for MVDC distribution systems is

to create dc voltage transformation equipment based on power

electronics, which should play the key role as the traditional ac

transformer for ac systems but provide more flexibility and save more physical volume [8], [9]. An integrated dc distribution

system would require both the high step-ratio dc-dc conversion

to interface MVDC and LVDC networks and the low step-ratio

dc-dc conversion to connect two MVDC networks with similar

but not identical voltages [10]–[13]. In general, high step-ratio

dc-dc conversion between lines in the different layers would

usually require an internal transformer to facilitate the large

voltage conversion ratio and provide galvanic isolation [14],

[15] whereas low step-ratio dc-dc conversion between lines in

the same layer can use a transformer-less structure which yields

better power density and power efficiency [16], [17]. Dc-dc conversion has been extensively studied at low voltage

for both high step-ratio and low step-ratio over many years [18],

[19]. However, the single switch circuit configuration and high

switching frequency that are the mainstay of low voltage

conversion does not scale up well for medium voltage

applications. The concept of using multiple circuits, or modules,

in series and parallel combinations, is a good approach to

extending the use of circuit principles from low-voltage isolated

dc-dc converters to medium voltage applications. Examples of

this are the modular dual-active-bridge (DAB) converter and

modular LLC resonant circuits with the merits of high power

efficiency and high power density [20]–[22]. However, these series-parallel arrangements would place large stress on the

insulation of the transformer windings and other components if

there exist large potential differences between the primary and

secondary sides. A further limitation is that, the failure of any

single module transformer can mean that the whole composite

converter is unable to operate and thus the system reliability

would be undermined [23]–[25]. The concept of modular

multilevel converter (MMC) [26] that uses sub-modules (SMs)

in place of switches in a single converter structure can avoid

these drawbacks because they utilize a lumped transformer, and

the arrangements of SMs in stack combines reliability advantages of modular design with the benefits of high effective

switching frequency through multilevel operation [27], [28].

Thus, the MMC-based dc-dc converters offer a new road to

MVDC systems through both the transformer-coupled front-to-

front [29]–[31] configurations for high step-ratio conversion

and transformer-less direct-chain-link configurations for low

step-ratio conversion [32]–[34]. However, these proposed MMC-based dc-dc topologies also raise many new challenges

that needs to be addressed, such as the low power device

utilization, low power density and high power losses for the

front-to-front configurations and the high current stress,

expensive filter design and complicate energy balancing for the

direct-chain-link configurations [35], [36].

In addition to the MMC-based circuits mentioned so far, the

transformer-coupled resonant modular multilevel dc-dc

converter (RMMC) [37]–[39] was proposed for connection

between MVDC and LVDC distribution networks where a high

step-ratio conversion is needed. It inherits important advantages of both the classic LLC resonant circuit and the MMC structure,

and it becomes a promising solution for MVDC distribution

systems [40]–[42]. The purpose of this paper is to present how

this RMMC can be reconfigured to bring those same benefits to

a low-step ratio converter for interfacing two MVDC networks

of similar but not identical voltages.

The operational principles of the original transformer-

coupled RMMC are introduced in Section II of this paper. The

benefits it possesses for high step-ratio and the difficulties of

applying it to low step-ratio conversion are then analysed and

examined in detail. In Section III, it presents a step-by-step circuit evolution which bridges the apparent gap between high

and low step-ratios and reconfigures the high step-ratio

transformer-coupled RMMC into a low step-ratio transformer-

less RMMC counterpart. These two RMMC circuits share the

same structure of resonant SM stack (RSS) with the same

resonant frequencies. As a result, the operational advantages

and circuit design experience can be readily transferred between

the two circuits. With these two base RMMC structures, a

family of RMMCs with further configurations is elaborated in

Section IV to provide a wider variety of connection options in

MVDC distribution systems. In this circuit family, each high

step-ratio transformer-coupled RMMC has a corresponding low step-ratio transformer-less RMMC with a common resonant

SM stack structure and a process is shown for reconfiguring one

into the other. In Section V and Section VI, full-scale

simulations of medium voltage examples and down-scaled

experiments on laboratory prototypes are provided, and through

these the theoretical analysis for both high and low step-ratio

RMMCs is verified. The simulation and experimental results

also serve to illustrate the potential use and good capability of

the RMMCs for both high and low step-ratio connections in

MVDC distribution systems.

II. HIGH STEP-RATIO RMMC

Fig. 1 shows the schematic of the proposed transformer-

coupled RMMC for MVDC and LVDC connection [37]–[39].

The medium-voltage side utilizes an SM stack of the MMC structure to replace the half-bridge or full-bridge inverter in the


classic LLC circuit. The SM stack with 𝑁 half-bridge SMs is

used to support the voltage 𝑉𝑀𝑆 at the medium voltage side, and

the modular structure provides high reliability for this system.

A lumped internal transformer with turns-ratio, 𝑟𝑇 = 𝑛1/𝑛2 ,

facilitates the high voltage ratio conversion and also avoids the

complex insulation issues of multiple transformers in modular DAB and LLC converters. The leakage inductance of the

transformer can serve as the resonant inductor 𝐿𝑟 , and the

magnetizing inductor 𝐿𝑚 appears in parallel and provides the

return path for the dc component of SM stack current. The low-

voltage side retains the structure of the classic LLC circuit and

inherit the soft-switching benefits. It uses fully controllable

IGBT devices (𝑆1,𝑆2,𝑆3,𝑆4) for bidirectional power conversion.

Fig. 1. Transformer-coupled resonant modular multilevel dc-dc converter.

Fig. 2. Extended phase-shift modulation scheme for RMMC (For each SM, red

period means its capacitor bypassed for the positive stage, black period means

its capacitor inserted for the negative stage).

The SM stack is switched so that either 𝑀 or 𝑁 SM

capacitors (1 ≤ 𝑀 < 𝑁) are inserted into the conduction path of the circuit. The two states exist for equal duration and a

symmetrical square-wave voltage 𝑣𝐿𝑚 is imposed across the

primary winding of the transformer and its magnetizing

inductor 𝐿𝑚 . The positive stage has 𝑀 SMs switched in (the

upper switch is on in each SM) and the remaining 𝑁 − 𝑀 SMs

are bypassed (the lower switch is on in each SM). This gives a

stack voltage 𝑣𝑆𝑇 which is less than 𝑉𝑀𝑆 and a positive voltage

is across 𝐿𝑚. In the negative stage, all 𝑁 SMs are switched in

and the voltage across 𝐿𝑚 is negative. The square-wave voltage

excites an energy exchange between the SM capacitors (𝐶1 to 𝐶𝑁) and the resonant inductor 𝐿𝑟 . Together, the SMs and the

resonant inductor are known as a resonant SM stack. The dc

component of the stack current passes through the magnetizing

inductor while the ac component of stack current flows into the

primary winding of transformer in which a secondary-side

current is generated through the ampere-turns balance. The

secondary-side current flows through 𝑆1 and 𝑆4 during the

positive stage and meanwhile the resonant SM stack is being

charged in this period. During the negative stage, 𝑆2 and 𝑆3

conduct and the resonant SM stack discharges in this period.

The voltage relationships derived from the positive stage and negative stage are written as (1) and (2) respectively, given the

assumptions that all of the SM capacitor voltages are well-

balanced at 𝑉𝐵 (𝑣𝐶1 = 𝑣𝐶2 = ⋯ = 𝑣𝐶𝑁 = 𝑉𝐵) and that the voltage

across 𝐿𝑟 is much smaller than medium-voltage terminal 𝑉𝑀𝑆.

𝑣𝐿𝑚𝑃 and 𝑣𝐿𝑚𝑁 are the voltage across the magnetizing inductor

𝐿𝑚 during the positive stage and negative stage. 𝑉𝑀𝑆 − 𝑀 ∙ 𝑉𝐵 = 𝑣𝐿𝑚𝑃 = 𝑟𝑇𝑉𝐿𝑆 (1)

𝑉𝑀𝑆 − 𝑁 ∙ 𝑉𝐵 = 𝑣𝐿𝑚𝑁 = −𝑟𝑇𝑉𝐿𝑆 (2)

In the positive stage, the capacitors of 𝑀 SMs join a resonant circuit with inductor 𝐿𝑟. The resonant frequency in this state, 𝑓𝑝,

is presented in (3) under the assumption that each SM

capacitance equals 𝐶𝑆𝑀, and this resonance assists the switches

of the inserted 𝑀 SMs to achieve soft-switching operation. In

the negative stage, all the 𝑁 SM capacitors are inserted into the

circuit and resonate with 𝐿𝑟, and the resonant frequency in this

state, 𝑓𝑛, is given in (4).

𝑓𝑝 =√𝑀

2𝜋 ∙ √𝐿𝑟𝐶𝑆𝑀

(3)

𝑓𝑛 =√𝑁

2𝜋 ∙ √𝐿𝑟𝐶𝑆𝑀

(4)

Based on (1) and (2), the step-ratio 𝑅𝐻 between the medium-

voltage side 𝑉𝑀𝑆 and low-voltage side 𝑉𝐿𝑆 is described in (5).

The voltage stress 𝑉𝐹𝐵𝑅 for full-bridge rectifier is given in (6).

𝑅𝐻 =𝑉𝑀𝑆

𝑉𝐿𝑆=

𝑁 + 𝑀

𝑁 − 𝑀𝑟𝑇 (5)

𝑉𝐹𝐵𝑅 = 𝑉𝐿𝑆 =𝑁 − 𝑀

𝑁 + 𝑀

𝑉𝑀𝑆

𝑟𝑇 (6)

To balance all the SM capacitor voltages in operation and

also to increase the effective frequency of the stack voltage 𝑣𝑆𝑇

and square-wave voltage 𝑣𝐿𝑚 for converter volume reduction,

an extended phase-shift modulation scheme has been developed

for this RMMC [10], [38] as shown in Fig. 2. All the upper

switches of the SMs are operated with a duty-cycle value of (𝑀 + 𝑁)/2𝑁, and each SM switching sequence keeps a phase-

shift value of 2𝜋/𝑁 with respect to the previous one (the last

SM is the reference for the first one). In this way, the SM output voltages 𝑣𝑆𝑂𝑗 (𝑗 = 1,2, ⋯ , 𝑁) forms a sequence of voltage pulses

with a phase-shift value of 2𝜋/𝑁 , which means the SM

capacitors join the circuit operation according to a preset

VMSCMS

Lr

Lm n2n1

S1

S2

S3

S4

SM

1

SM

2

SM

j

SM

N

vlowj,vSMj

vupj

vCj

Resonant SM Stack

VLSCLS

t... ...

t... ...

...

... ...

... ...

......

T=NTe=(N-M)TS=2π

0

vSM1

0

vSM2

0

0

0

vSMM

vSM(M+1)

vSMN

vC1

vC2

vCM

vC(M+1)

vCN

...

......

......

0 t

vSTNVB

MVB

......

......

Te

t

t

t

t

vLM

......vLmP

vLmN

0

t

vS2,vS3

......VLS

0

t

vS1,vS4

......VLS

0

2π/N


sequence for voltage balancing. So long as the value of 𝑀 and

𝑁 has no common factor other 1, all the SM capacitor voltages

can be inherently balanced without extra sorting and rotation,

and the value is derived from (1) and (2), shown in (7), which

is also the voltage stress for each SM switch.

𝑉𝐵 =2𝑉𝑀𝑆

𝑁 + 𝑀=

2𝑅𝐻𝑉𝐿𝑆

𝑁 + 𝑀 (7)

Also, thanks to the benefits of phase-shift modulation, the

frequency of the stack voltage 𝑣𝑆𝑇 and square-wave voltage

𝑣𝐿𝑚 will be increased to 𝑁/(𝑁 − 𝑀) times greater than that of

each SM switching frequency 𝑓𝑠, shown in (8), which reduces

the required volume of all the passive components in the circuit.

The voltage frequency of 𝑣𝑆𝑇 and 𝑣𝐿𝑚 is denoted as the effective frequency 𝑓𝑒 in this circuit, and it is normally chosen

at a value between 𝑓𝑝 and 𝑓𝑛 ( 𝑓𝑝 < 𝑓𝑒 < 𝑓𝑛 ) to trade-off

conduction losses and switching losses for the best overall

efficiency [37], [40].

𝑓𝑒 =𝑁

𝑁 − 𝑀𝑓𝑠 (8)

Based on (5) to (8), analysis for circuit performance is given

in Fig. 3 assuming the total SM number 𝑁 = 10. The values of

voltage step-ratio 𝑅𝐻 and effective frequency 𝑓𝑒 are increased

with the rise of positive stage number 𝑀, shown in Fig. 3(a),

and the voltage stresses for full-bridge rectifier and SM

switches are decreased in this process, shown in Fig. 3(b).

(a)

(b)

Fig. 3. Circuit performance analysis for the transformer-coupled RMMC in Fig.

1 (𝑁 = 10). (a) Voltage step-ratio and effective frequency. (b) Voltage stress

for full-bridge rectifier and SM switches.

It can be seen in Fig. 3 that this RMMC is well-suited to high

step-ratio connection between monopolar MVDC and LVDC

networks. It has the advantages of soft-switching operation for

SM switches, inherent balance capability for SM capacitor

voltages and high effective switching frequency for internal

resonance in the high step-ratio conversion. The highest step-ratio conversion is achieved by selecting the highest available

value for 𝑀, that is 𝑀 = 𝑁 − 1. This also guarantees inherent

voltage balance because 𝑀 and 𝑁 have no common factor other

than 1. Further, the SM switching frequency that is needed to

achieve the required effective frequency and the voltage ratings

that are required of the rectifier and SM switches are both at

their lowest in this conversion case. In addition, the ratio

between dc and ac component of stack current decreases with

the rise of overall voltage step-ratio [38], and this ratio reaches

a minimum value in the highest step-ratio conversion where

𝑀 = 𝑁 − 1. The core of the transformer should be as small as possible but must be sufficient to avoid saturation while

providing the return path for dc current component and

supporting the alternating flux. Operating with minimum dc

current will help in this regard. Considering all of these aspects,

the 𝑀 = 𝑁 − 1 case is therefore the best choice for operating

this RMMC.

Because these attractive advantages for high step-ratio

conversion, this RMMC is named as high step-ratio RMMC in

this paper to highlight its suitable applications.

It is also worth noting here that this RMMC could be used

for low step-ratio conversion [10], [38] but, as shown in Fig. 3(a), the number of SMs, 𝑀 would need to be significantly

decreased to achieve the low step-ratio value and the voltage

ratings of the SM switches and the rectifier would have to be

substantially increased as shown in Fig. 3(b) which may not be

feasible with single devices. Further, the switching frequency

would also have to be increased considerably to obtain the

required effective frequency with fewer SMs in the positive

stage. The lowest step-ratio conversion is achieved when 𝑀 =

1, which is the worst case for voltage stresses and the switching

frequency. This would pose serious design challenges for the

SM and rectifier devices.

To avoid these problems, a better approach is needed for adapting the high step-ratio RMMC for use in low step-ratio

applications. A step-by-step circuit evolution to achieve this

will be presented in the next section.

III. LOW STEP-RATIO RMMC

The high step-ratio RMMC is redrawn in Fig. 4(a) for a

clearer circuit evolution process. If its low-voltage terminal 𝑉𝐿𝑆

could be connected with the medium-voltage terminal 𝑉𝑀𝑆 in

series to form a second medium-voltage terminal 𝑉𝑀𝑆2

(𝑉𝑀𝑆2 = 𝑉𝑀𝑆 + 𝑉𝐿𝑆 ) and 𝑉𝑀𝑆 still serves as the first medium-

voltage terminal, (𝑉𝑀𝑆1 = 𝑉𝑀𝑆 ), this high step-ratio RMMC

would have the chance to be modified to its low step-ratio

RMMC counterpart and the value of 𝑉𝐿𝑆 would turn to be the voltage difference 𝑉𝑑𝑖𝑓 between the two medium-voltage

terminals (𝑉𝐿𝑆 = 𝑉𝑑𝑖𝑓 = 𝑉𝑀𝑆2 − 𝑉𝑀𝑆1).

3 4 5 7 9SM Number in Positive Stage (M)

6 821

0

5

10

15

20

25 RH with rT =1

fe / fs


6 821

0

0.2

0.4

0.6

0.8

1 VFBR / VMS with rT =1

VB / VMS


(a)

(b)

(c)

(d)

(e)

(f)

Fig. 4. Step-by-step circuit evolution of the high step-ratio RMMC into the low

step-ratio RMMC. (a) Original high step-ratio transformer-coupled RMMC. (b)

High step-ratio transformer-less RMMC. (c) High step-ratio RMMC with

positive double-voltage rectifier. (d) High step-ratio RMMC with negative

double-voltage rectifier. (e) Low step-ratio RMMC with negative structure. (f)

Low step-ratio RMMC with positive structure.

Firstly, the internal transformer in the high step-ratio RMMC

is no longer needed and can be removed in the low step-ratio conversion. Thus, the converter of Fig. 4(a) becomes a

transformer-less structure shown in Fig. 4(b). To create direct

connection point for 𝑉𝑀𝑆 and 𝑉𝐿𝑆, the full-bridge circuit in the

low voltage side is adjusted to a double-voltage rectifier circuit

with double-voltage capacitor 𝐶𝑑 , show in Fig. 4(c). In this

positive double-voltage circuit, the voltage on 𝐶𝑑 is equal to the

amplitude of 𝑣𝐿𝑚 and 𝑉𝐿𝑆 is doubled compared to the full-bridge

structure in Fig. 4(b). Point 𝐵 of medium voltage link is directly

connected to point 𝐷 of low voltage link but the potential of

point 𝐶 in Fig. 4(c) is higher than that of point 𝐵 and 𝐷, which

is not ready to form the second medium-voltage terminal. If the positive double-voltage structure is changed to a systematical

negative double-voltage counterpart, shown in Fig. 4(d), the

voltage amplitude relationships remains the same but the

voltage direction of 𝑉𝐶𝑑 and 𝑉𝐿𝑆 are changed. Compared to Fig.

4(c), the positions of 𝑆1 and 𝑆2 have been exchanged in Fig. 4(d)

so that 𝑆1 still conducts when 𝑣𝐿𝑚 is positive and 𝑆2 still

conducts when 𝑣𝐿𝑚 is negative, which is the same as the

switching sequences in Fig. 4(a) to Fig. 4(c). In this circuit, 𝑉𝐴𝐶

equals 𝑉𝑀𝑆 + 𝑉𝐿𝑆 and could become the second medium-voltage

terminal 𝑉𝑀𝑆2 for the low step-ratio conversion. 𝑉𝐴𝐵 could serve

as the first medium-voltage terminal 𝑉𝑀𝑆1 and it has the common point of 𝐴 with the second medium-voltage terminal

of 𝑉𝐴𝐶. Noting that the common point 𝐴 has the highest potential

in Fig. 4(d), this circuit can be developed for low step-ratio

connection between two negative MVDC links, as shown in Fig.

4(e). The systematical structure for interconnection of two

positive MVDC links is presented in Fig. 4(f), where the

common point 𝐴 has the lowest potential in the circuit.

The converters in Fig. 4 all need a dc link capacitor in the

MVDC side and at medium voltage (≈10 kV) they will need to

be composed of series-connected capacitors of lower voltage

rating [43], [44]. Series connection brings the risk of cascading

failure if a capacitor in the connection fails to a short circuit. This can be addressed by redundancy at the cost of increased

volume or by using metalized film capacitors with self-healing

properties. Metalized film capacitors rated at 1100 V are

practical here because the required capacitance is relatively

small considering there is no low-frequency current flow.

Voltage balancing among these series capacitors can be realized

with parallel balancing resistors [40], [41]. This solution may

not scale well to high voltage applications (>100 kV) and the

reliability would be a problem. Further, the stored energy in the

dc link at high voltage will be much larger and would present a

problem managing component failures and network faults. Through these circuit evolution steps, the high step-ratio

transformer-coupled RMMC in Fig. 4(a) has been reconfigured

into a low step-ratio transformer-less RMMC counterpart in Fig.

4(f). It is worth noting that the structure of the resonant SM

stack has not been changed through the whole evolution from

Fig. 4(a) to Fig. 4(f) and the resonant operation remains as one

Lr

Lm n2n1 VLSVMS

S1

S2

S3

S4

SM

1

SM

2

SM

j

SM

N

Resonant SM StackCMS CLS

VMSCMS

Lr

Lm

S1

S2

S3

S4

SM

1

SM

2

SM

j

SM

N

Resonant SM Stack VLSCLS

VMSCMS

Lr

Lm

VLS

S1

S2

SM

1

SM

2

SM

j

SM

N

Resonant SM Stack

A

B

C

D

+

+

Cd

+CLS

VMSCMS

A

B

+

Lm

S2

S1

+

CdLr

SM

1

SM

2

SM

j

SM

N

Resonant SM Stack

VLS

C

D+

CLS

Lm

Cdif

S1

S2

Cd

VMS2

Vdif (VLS)

B(D)

A

C

Lr

SM

1

SM

2

SM

j

SM

N

Resonant SM Stack

+

CMS1

VMS1

A

C

VMS2

Lm

CdCdif

S2

S1

Vdif (VLS) +

A

B(D)

C C

Lr

SM

1

SM

2

SM

j

SM

N

Resonant SM Stack

A

CMS1

VMS1


between the SM capacitors and resonant inductor within the SM

stack. Thus, the same resonant frequencies and circuit

parameters for the SM stack are preserved. This scheme would

have clear advantages in the circuit design over the resonant

mechanism which occurs outside the SM stack [42]. In that

evolution steps, the resonant frequencies are inevitably changed during reconfiguration from high step-ratio RMMC to low step-

ratio RMMC and redesign of the parameters of resonant SM

stack is needed for each configuration. A consequence of such

a redesign is that operational advantages in resonant SM stack

cannot be readily transferred. Also, the SM capacitors may need

to be physically large since the SM capacitance would have to

be increased to reduce the difference in resonant frequency

between the positive stage (with 𝑀 SM capacitors in circuit)

and the negative stage (with 𝑁 SM capacitors in circuit).

The resonant operation principle introduced in Section II can

be directly applied for this low step-ratio RMMC in Fig. 4(f). By switching either 𝑀 or 𝑁 SM capacitors into the circuit for

equal durations, the symmetrical square-wave voltage 𝑣𝐿𝑚 is

imposed across the magnetizing inductor 𝐿𝑚. The dc component

of the stack current goes through the magnetizing inductor

while the ac component of stack current flows into the double-

voltage capacitor branch. In the positive stage, the ac

component of stack current flows trough 𝑆1 and the double-

voltage capacitor and the resonant SM stack is being charged.

During this time the current of the second medium-voltage

terminal flows from the first medium-voltage terminal and the differential capacitor 𝐶𝑑𝑖𝑓 . In the negative stage, 𝑆2 conducts

and the double-voltage capacitor and the resonant SM stack is

discharging in this period to both medium-voltage terminals

and differential capacitor. The voltage relationships of this low

step-ratio RMMC in the positive stage and negative stage are

given in (9) and (10) respectively. The resonant frequencies in

positive stage and negative stage are the same with the

expressions in (3) and (4), and the resonance between SM

capacitors (𝐶1 to 𝐶𝑁) and the resonant inductor 𝐿𝑟 also assists

the soft-switching operation for all the SM switches. 𝑉𝑀𝑆1 − 𝑀 ∙ 𝑉𝐵 = 𝑣𝐿𝑚𝑃 = 𝑉𝐶𝑑 (9)

𝑉𝑀𝑆1 − 𝑁 ∙ 𝑉𝐵 = 𝑣𝐿𝑚𝑁 = 𝑉𝐶𝑑 − 𝑉𝑑𝑖𝑓 (10)

Noting that the 𝑣𝐿𝑚𝑃 = −𝑣𝐿𝑚𝑁 in the steady-state operation

due to the voltage-time balance principle on inductor 𝐿𝑚, the

value of 𝑉𝐶𝑑 and 𝑉𝑑𝑖𝑓 are derived in (11).

𝑉𝑑𝑖𝑓 = 2 𝑉𝐶𝑑 = 2𝑁 − 𝑀

𝑁 + 𝑀 𝑉𝑀𝑆1 (11)

Then, the step-ratio expression of this low step-ratio RMMC

is written in (12), and the voltage stress, 𝑉𝐻𝐵𝑅 , for the half-

bridge rectifier is given by (13). For a low-step ratio connection

between two MVDC links of similar but different voltages, the

rectifier switches 𝑆1 and 𝑆2 have to withstand the voltage

difference between the two links as seen in Fig. 4(f). The voltage difference will in many cases be less than 5 kV [45],

[46] and in these cases a single high voltage switch or a series

connection of up to 3 power switches with passive or active

voltage sharing [47], [48] will be sufficient. If the two dc link

voltages are such that a much larger voltage difference exists

then more sophisticated voltage sharing and press-pack devices

with fail-to-short characteristics will be needed for 𝑆1 and 𝑆2

and the cost and complexity will rise.

𝑅𝐿 =𝑉𝑀𝑆2

𝑉𝑀𝑆1=

𝑉𝑀𝑆1 + 𝑉𝑑𝑖𝑓

𝑣𝑀𝑆1=

3𝑁 − 𝑀

𝑁 + 𝑀 (12)

𝑉𝐻𝐵𝑅 = 𝑉𝑑𝑖𝑓 = 2𝑁 − 𝑀

𝑁 + 𝑀 𝑉𝑀𝑆1 (13)

Because the required symmetrical square-wave voltage

across the magnetizing inductor 𝐿𝑚 is the same as that for high

step-ratio RMMC, the extended phase-shift modulation scheme

can be also implemented directly for this low step-ratio RMMC

to balance all the SM capacitor voltages and increase the effective frequency. The detail operational waveforms of SM

output voltages, stack voltage, magnetizing inductor voltage

and rectifier voltage are the same as those in Fig. 2. So long as

the value of 𝑀 and 𝑁 are co-prime, all the SM capacitor

voltages can be inherently balanced at the value, shown in (14),

which is also the voltage stress for each SM switch in this low

step-ratio RMMC. The effective frequency of 𝑣𝑆𝑇 and 𝑣𝐿𝑚 is

also increased to 𝑁/(𝑁 − 𝑀) times greater than that of SM

switching frequency 𝑓𝑠 as the expression in (8).

𝑉𝐵 =2𝑉𝑀𝑆1

𝑁 + 𝑀=

2𝑉𝑀𝑆2

3𝑁 − 𝑀 (14)

With the analysis in (12) to (14) and (8), circuit analysis for

this low step-ratio RMMC is plotted in Fig. 5 with 𝑁 = 10. The

value of voltage step-ratio 𝑅𝐿 is decreased with the increase of

positive stage number 𝑀 while the effective frequency 𝑓𝑒 is

increased, shown in Fig. 5(a) and the voltage stresses for half-

bridge rectifier and SM switches are both decreased in this

process, shown in Fig. 5(b).

(a)

(b)


6 821

0

2

4

6

8

10 RL with rT =1

fe / fs


6 821

0

0.4

0.8

1.2

1.6

2 VHBR / VMS1

VB / VMS1


Fig. 5. Circuit performance analysis for low step-ratio RMMC (𝑁 = 10). (a)

Voltage step-ratio and effective frequency. (b) Voltage stress for half-bridge

rectifier and SM switches.

In comparison with the performance in Fig. 3 for the original

high step-ratio RMMC, this low step-ratio RMMC in Fig. 4(f)

is well-suited for the interconnection between two monopolar

MVDC networks with similar but not identical voltages. Because

the resonant SM stack has not been changed, this low step-ratio

RMMC will inherit all the circuit design experience from the high step-ratio RMMC and retain the operational advantages of

soft-switching operation, inherent balance and high effective

switching frequency that were present in high step-ratio RMMC.

Moreover, the lowest step-ratio conversion is achieved by

selecting 𝑀 = 𝑁 − 1 . The inherent voltage balance is

guaranteed, and the SM switching frequency and voltage

stresses are both the lowest in this conversion case (𝑀 = 𝑁 − 1).

The lowest step-ratio conversion corresponds to the highest

step-ratio conversion of the high step-ratio RMMC. The ratio

between dc and ac component in this low step-ratio RMMC also

reaches the minimum value in this case and the core of the

magnetizing inductor needs the smallest volume for dc current component. This is the best operating condition for this low

step-ratio RMMC and it is the same condition as for the high

step-ratio RMMC operating at its highest step-ratio.

This low step-ratio transformer-less RMMC does not have

the full capability for current blocking in the events of dc link

faults. It could block the fault current for the faults on the low-

side MVDC link (𝑉𝑀𝑆1) but in the event of a dc fault on the

high-side MVDC link (𝑉𝑀𝑆2), the low-side terminal will drive

fault current through the anti-parallel diodes of 𝑆1 and 𝑆2 in a way similar to the fault current path in the classic dc-ac MMC

[26], [27]. To overcome this inability, reverse-blocking

bidirectional switches [49], [50] could be used for 𝑆1 and 𝑆2 in

medium voltage cases. Alternatively, an MVDC circuit breaker

[51], [52] might be used.

IV. A FAMILY OF FURTHER RMMCS

The base circuits of high step-ratio and low step-ratio

RMMCs in Section II and III not only provide good solutions

for interconnections between monopolar dc systems with

relatively lower power rating they also lend themselves to being

building blocks for various further configurations that could

provide a wider variety of connection options for MVDC

distribution systems and also meet the requirements for higher

power rating conversion. These further RMMC configurations inherit all the advantages from the base circuits in these their

roles. They form a circuit family of RMMCs, in which each

high step-ratio transformer-coupled RMMC has counterpart in

the low step-ratio transformer-less RMMC format and each can

be transformed into the other via the circuit evolution laid out

in Section III.

By connecting two base circuits of high step-ratio RMMC in

series and grounding the connection points on both medium-

voltage side and low-voltage side, a bipolar configuration of

high step-ratio RMMC with separated transformers is obtained

and shown in Fig. 6(a), keeping the same overall voltage step-

ratio (𝑅𝐻) as the base circuit. The SM switches in each resonant

SM stack are modulated in the same way as the single high step-

ratio RMMC, and the switching sequences in the first and

second resonant SM stacks could set a phase-shift value of half

effective cycle (i.e., 𝜋/𝑁 ) to achieve a reduction in voltage

ripple on bipolar MVDC link ±𝑉𝑀𝑆.

(a)

(b)

(c)

Fig. 6. Series connection for bipolar configuration. (a) High step-ratio RMMC

with separated transformers. (b) High step-ratio RMMC with a lumped

transformer. (c) Low step-ratio RMMC.

VMS

C1MS

L1r

L1m n12n11

S11

S12

S13

S14

SM

11

SM

12

SM

1j

SM

1N

1st RSS

L2r

L2m n22n21

S21

S22

S23

S24

SM

21

SM

22

SM

2j

SM

2N

2nd RSS

+

VMS

C2MS

C1LS

VLS+

VLS

C2LS

VMSN VLSN

n2 VLS

S1

S2

S3

S4

LB

r

SMB1

SMB2

SMBj

SMBN

Bot (2

nd

) RS

S

LTr

SMT1

SMT2

SMTj

SMTN

Top

(1st) R

SS

n1

CTMS

CBMS

VMS+

VMS

CLS

VMSN

LTm

CTdCTdif

ST2

ST1

VTdif (VTLS) +

LTr

SM

T1

SM

T2

SM

Tj

SM

TN

Top (1st) RSS

LBm

CBdif

SB1

SB2

CBd

VBdif (VBLS)

LBrSM

B1

SM

B2

SM

Bj

SM

BN

Bot (2nd) RSS

+

CBMS1

CTMS1

VMS1+

VMS1

VMS2+

VMS2

VMS1N VMS2N


If the internal transformer and low-voltage side rectifier are

shared by the two base circuits, another bipolar configuration

of high step-ratio RMMC with a lumped transformer is

developed in Fig. 6(b). The top and bottom resonant SM stacks

have a phase-shift angle of half effective cycle. They together

support the total MVDC voltage stress of 2𝑉𝑀𝑆 and provide overall step-ratio of 2𝑅𝐻. Importantly, the dc component of the

top stack current flows via the bottom stack such that the

transformer is not the dc return path. The ac currents of the top

and bottom stacks combines to flow through the transformer

such that the transformer current is twice of the single RMMC.

The bipolar configuration of high step-ratio RMMC in Fig.

6(a) and Fig. 6(b) are suitable for the connection between

bipolar MVDC network and LVDC network with medium

power rating.

Both of the circuits can be transformed into a bipolar

configuration of low step-ratio RMMC using the circuit evolution process in Section III, as shown in Fig. 6(c). Its

overall step-ratio stays at 𝑅𝐿 as for the corresponding base

circuits in Fig. 4(e) and Fig. 4(f). The switching sequences in

the bottom resonant SM stack are also given a 𝜋/𝑁 phase shift

with respect to that in top resonant SM stack which reduces the

voltage ripple at both bipolar MVDC links ±𝑉𝑀𝑆1 and ±𝑉𝑀𝑆2.

This configuration can be used to connect two medium power

rating bipolar MVDC networks with similar voltages.

Two base circuits of high step-ratio RMMC can be also

placed in parallel to form an interleaved configuration of high

step-ratio RMMC, shown in Fig. 7(a), and the step-ratio is same as the base circuit. The switching sequences in the first and

second resonant SM stacks set a 𝜋/𝑁 phase shift to cancel the

ac current components on the MVDC link and the link capacitor

𝐶𝑀𝑆 can therefore be removed in this configuration.

(a)

(b)

(c)

(d)

Fig. 7. Parallel connection for interleaved or push-pull configuration. (a) High

step-ratio RMMC with separated transformers. (b) High step-ratio RMMC with

a lumped transformer. (c) Low step-ratio RMMC with positive structure. (d)

Low step-ratio RMMC with negative structure.

For the case of a shared transformer and low-side rectifier,

the interleaved configuration can be developed into a push-pull configuration of high step-ratio RMMC in Fig. 7(b). The

inductors 𝐿𝐿𝑚 and 𝐿𝑅𝑚 provide the return paths for the dc

components of stack currents, so the lumped transformer does

not need to provide a path for dc current, and the ac current

components are cancelled on the MVDC link. The overall

voltage step-ratio of this configuration is reduced to 0.5𝑅𝐻

because push-pull configuration has doubled the transformer

voltage compare to the base circuit.

These interleaved and push-pull configurations of high step-

ratio RMMC are suitable interconnection between monopolar

MVDC and LVDC networks with an extended high power range compared to the base circuit.

Based on the circuit evolution process in Section III, the

interleaved and push-pull configuration of high step-ratio

RMMC can be also evolved to a push-pull configuration of low

step-ratio RMMC, shown in Fig. 7(c) and Fig. 7(d) for positive

structure and negative structure respectively. The phase-shift

switching sequences for the two resonant SM stacks create a

symmetrical square-wave voltage between the mid-points of the

two half-bridge which is equivalent to use full-bridge rectifier,

and the link capacitor 𝐶𝑀𝑆1 is also not needed. The voltage step-

ratio in Fig. 7(c) and Fig. 7(d) remain the same as their base

circuits, and this is different to the corresponding push-pull configuration of high step-ratio RMMC in Fig. 7(b) because the

circuits in Fig. 7(c) and Fig. 7(d) have two symmetrical double-

voltage structures in their resonant current path.

These low step-ratio RMMC can be used to interconnect two

monopolar MVDC links with an extended high power range.

Combining the concepts of the series and parallel

connections, a bipolar interleaved configuration of high step-

ratio RMMC is derived in Fig. 8(a). The overall voltage step-

ratio stays at 𝑅𝐻 but both the MVDC and LVDC sides become

bipolar configuration. The phase-shift angle between the first

(third) and the second (fourth) resonant SM stacks is set at 𝜋/𝑁

VMS

L1r

L1m n12n11

S11

S12

S13

S14

SM

11

SM

12

SM

1j

SM

1N

1st RSS

L2r

L2m n22n21

S21

S22

S23

S24

SM

21

SM

22

SM

2j

SM

2N

2nd RSS

CLS

VLS

n2

VMS S1

S2

S3

S4

n1

LR

r

SMR1

SMR2

SMRj

SMRN

Rig

ht (1

st) RS

SLLr

SML1

SML2

SMLj

SMLN

Left (2

nd

) RS

S

LLm

LR

m

VLSCLS

+VMS2

CRdCdif

Vdif (VLS) +

LRr

SM

R1

SM

R2

SM

Rj

SM

RN

Right (1st) RSS

LLrSM

L1

SM

L2

SM

Lj

SM

LN

LRm

SR2

SR1

LLm

SL2

SL1

CLd

+

Left (2nd) RSS

+VMS1

VMS1N

VMS2N

LRm

Cdif

SR1

SR2

CRd

Vdif (VLS)

Right (1st) RSS

+

VMS2

VMS1

LLr

SM

L1

SM

L2

SM

Lj

SML

N LRrSM

R1

SM

R2

SM

Rj

SMR

N

LLm

SL1

SL2

CLd

+

Left (2nd) RSS

VMS1N

VMS2N


to offset the ac currents and avoid the MVDC link capacitor,

and the third (fourth) resonant SM stack sets a phase-shift angle

of a quarter of the effective cycle (𝜋/2𝑁) with respect to the first

(second) resonant SM stack to achieve voltage ripple reduction

on LVDC link and reduce the requirement for dc capacitor 𝐶𝐿𝑆.

If the transformer and rectifier are shared for all of these four base circuits, a full-bridge push-pull configuration of high step-

ratio RMMC is further developed in Fig. 8(b). The switching

sequences in the top right (bottom right) resonant SM stack

keep a phase-shift value of 𝜋/𝑁 to that in the top left resonant

SM stack (bottom left), and the switching sequences in the top

right (top left) and bottom right (bottom left) resonant SM

stacks also have a 𝜋/𝑁 phase shift. In this way, the dc currents

would not go through the magnetizing inductor of the

transformer and the ac current components are cancelled at the

MVDC link such that the link capacitor can be removed. Since

this high step-ratio RMMC is a combination of series bipolar and parallel push-pull configuration, the voltage doubling of the

series bipolar configuration (similar to Fig. 6(b)) and the

voltage halving of the parallel push-pull configuration (similar

to Fig. 7(b)) leave the overall step-ratio unchanged at 𝑅𝐻.

These bipolar interleaved and full-bridge push-pull

configuration of high step-ratio RMMC are very good

candidate for extremely high power rating connection between

MVDC and LVDC networks. It needs mention here they would

also face the technical issues of high voltage stress and high

switching frequency on SM devices when they are applied for

low step-ratio conversion, as the disadvantage analysis for their base circuit in Fig. 3.

(a)

(b)

(c)

Fig. 8. Series-parallel connection for bipolar interleaved or full-bridge push-

pull configuration. (a) High step-ratio RMMC with separated transformers. (b)

High step-ratio RMMC with a lumped transformer. (c) Low step-ratio RMMC.

Both of them can be also transformed to a bipolar full-bridge

push-pull configuration of low step-ratio RMMC, show in Fig.

8(c). The top right (bottom right) and top left (bottom left) resonant SM stacks maintain a 𝜋/𝑁 phase shift to create a

symmetrical square-wave voltage for the full-bridge

rectification, and the top right (top left) and bottom right

(bottom left) resonant SM stacks could set a 𝜋/2𝑁 phase shift

to reduce the voltage ripple on bipolar dc link ±𝑉𝑀𝑆2.

This low step-ratio configuration still has the step-ratio value

of 𝑅𝐿 and it could form a good solution for a large power rating

connection between two bipolar MVDC networks.

Table I provides a summary and comparison of the features

of all the further configurations in Fig. 6 to Fig. 8 derived from

the base RMMC. The table includes their paths through which the configuration was derived, their base circuits, schematic

descriptions, phase-shift angle, main benefits, voltage step-ratio,

power ratings and the type of MVDC system to which each

configuration is suited.

The circuit design experience and all the operational

advantages from each base RMMC are readily transferred to

these derivative RMMCs because although the ac currents in

these derivatives may go through more than one resonant SM

L1r

L1m n12n11

S11

S12

S13

S14

SM

11

SM

12

SM

1j

SM

1N

1st RSS

L2r

L2m n22n21

S21

S22

S23

S24

SM

21

SM

22

SM

2j

SM

2N

2nd RSS

C1LS

L3r

L3m n32n31

S31

S32

S33

S34

SM

31

SM

32

SM

3j

SM

3N

3rd RSS

L4r

L4m n42n41

S41

S42

S43

S44

SM

41

SM

42

SM

4j

SM

4N

4th RSS

C2LS

VMS+

VLS

VLS+

VMS

VMSN VLSN

n2

S1

S2

S3

S4

n1

Top

Rig

ht (1

st) RS

S

Top

Left (2

nd

) RS

S

VLSCLS

Bot R

igh

t (3rd

) RS

S

Bot L

eft (4

th) R

SS

LT

Lr

LB

Lr

LT

Rr

LB

Rr

VMS+

VMS

CTRdCTdif

VTdif (VTLS) +

LTRr

SM

TR

1

SM

TR

2

SM

TR

j

SMT

RN

Top Right (1st) RSS

LTLrSM

TL

1

SM

TL

2

SM

TL

j

SMT

LN

LTRm

STR2

STR1

LTLm

STL2

STL1

CTLd

+

Top Left (2nd) RSS

LBRm

CBdif

SBR1

SBR2

CBRd

VBdif (VBLS)

Bot Right (3rd) RSS

+

VMS2

VMS1+

VMS1

VMS2+

LBLr

SM

BL

1

SM

BL

2

SM

BL

j

SMB

LN LBRrS

MB

R1

SM

BR

2

SM

BR

j

SMB

RN

LBLm

SBL1

SBL2

CBLd

+

Bot Left (4th) RSS

VMS1N VMS2N


TABLE I.

SUMMARY AND COMPARION OF THE FAMILY OF FURTHER RMMCS

Derivation

paths

Base

circuits

Schematic

descriptions

Phase-shift angle

between stacks

Main benefits

over base circuits

Voltage

Step-ratio

Suitable power

ratings

Specific connections

in MVDC systems

Series

connection

for

bipolar

configuration

High step-

ratio RMMC

Fig. 6(a)

(separate trans.) 𝜋/𝑁(𝑇𝑒/2)

Reduced ripple on

MVDC link ±𝑉𝑀𝑆 𝑅𝐻

Medium

Bipolar MVDC

and bipolar LVDC

Fig. 6(b)

(lumped trans.) 𝜋/𝑁(𝑇𝑒/2) No dc current through

lumped trans. 2𝑅𝐻

Bipolar MVDC and

monopolar LVDC

Low step-

ratio RMMC Fig. 6(c)

𝜋/𝑁(𝑇𝑒/2) Reduced ripple on

both MVDC links

±𝑉𝑀𝑆1 and ±𝑉𝑀𝑆2

𝑅𝐿 Two bipolar MVDC

Parallel

connection

for

interleaved

or push-pull

configuration

High step-

ratio RMMC

Fig. 7(a)

(separate trans.) 𝜋/𝑁(𝑇𝑒/2)

No dc capacitor on

MVDC link 𝑉𝑀𝑆 𝑅𝐻

High

Monopolar MVDC and

monopolar LVDC Fig. 7(b)

(lumped trans.) 𝜋/𝑁(𝑇𝑒/2) No dc capacitor on

MVDC link 𝑉𝑀𝑆 0.5𝑅𝐻

Low step-

ratio RMMC

Fig. 7(c)

Fig. 7(d) 𝜋/𝑁(𝑇𝑒/2)

No dc capacitor on

MVDC link 𝑉𝑀𝑆1 𝑅𝐿 Two monopolar MVDC

Series-

parallel

connection

for

bipolar

interleaved

or full-bridge

push-pull

configuration

High step-

ratio RMMC

Fig. 8(a)

(separate trans.)

𝜋/𝑁(𝑇𝑒/2), 𝜋/2𝑁(𝑇𝑒/4)

No dc capacitor on

MVDC link ±𝑉𝑀𝑆

and reduced ripple

on LVDC link ±𝑉𝐿𝑆

𝑅𝐻

Large

Bipolar MVDC

and bipolar LVDC

Fig. 8(b)

(lumped trans.)

0 , 𝜋/𝑁(𝑇𝑒/2)

No dc capacitor on

MVDC link ±𝑉𝑀𝑆 and

no dc current through

lumped trans.

𝑅𝐻 Monopolar MVDC and

monopolar LVDC

Low step-

ratio RMMC Fig. 8(c)

𝜋/𝑁(𝑇𝑒/2), 𝜋/2𝑁(𝑇𝑒/4)

No dc capacitor on

MVDC link ±𝑉𝑀𝑆1

and reduced ripple on

MVDC link ±𝑉𝑀𝑆2

𝑅𝐿 Two bipolar MVDC

stack, their resonant frequencies are the same to those in base circuit since the product value of resonant inductance and SM

capacitance for resonance is always equal to that of base circuit.

Further, some operational disadvantages which exist in a base

RMMC are also alleviated or addressed for the series and

parallel combination in these derivative RMMCs.

V. FULL-SCALE SIMULATION VERIFICATION

To verify the circuit evolution presented in Section III and

validate the derivative family of RMMCs described in Section

IV, the bipolar configuration of high step-ratio RMMC and its

low step-ratio RMMC counterpart, seen in Fig. 6(b) and Fig.

6(c), were chosen here as examples to conduct medium voltage

full-scale simulation and explore their applications. These two

bipolar RMMCs are composed of the base circuits of high step-

ratio and low step-ratio RMMCs with the same resonant SM

stack, and they are also the important constituents in the family of further RMMCs that possess operational advantageous over

the base circuits.

For the high step-ratio connection in MVDC distribution

systems, the bipolar high step-ratio RMMC (refer to Fig. 6(b))

can serve as an interface between a bipolar MVDC network

(±𝑉𝑀𝑆(2𝑉𝑀𝑆) = ±5.5 kV(11 kV)) and a monopolar LVDC network

(𝑉𝐿𝑆 = 0.3 kV − 1.3 kV), and its circuit parameters are shown in

Table II with transformer turns ratio of 2.5:1. Each of the top

and bottom resonant SM stacks contains four SMs with one

resonant inductor. The SM capacitances were set with ± 10%

variation from the nominal capacitance to reflect manufacturing tolerances. The highest step-ratio conversion is achieved by

selecting the positive stage number 𝑀 = 𝑁 − 1 = 3. From the

parameters in Table II, the resonant frequencies of each

resonant SM stack in the positive stage and negative stage are approximately 2.8 kHz and 3.2 kHz respectively, so, for the

resonance performance, the SM switching frequency is chosen

as 750 Hz to generate an effective frequency of 3.0 kHz

between 2.8 kHz and 3.2 kHz. Further, the SM switching

sequences in the top and bottom resonant SM stacks set a phase-

shift of half the effective cycle. In this way, the top and bottom

stacks together support the total stress of the medium voltage,

2𝑉𝑀𝑆, and this also avoids dc current through the transformer.

TABLE II.

CIRCUIT PARAMETER OF BIPOLAR RMMC IN FULL-SCALE SIMULATION

Circuit Parameter Description Value

𝑃𝑅 Power Range 0–±500 kW

𝐶𝑇𝑀𝑆 𝐶𝐵𝑀𝑆 DC Link Capacitance 50 µF

𝐿𝑚 Magnetizing Inductance 460 mH

𝐿𝑇𝑟 𝐿𝐵𝑟 Resonant Inductance 25 µH

𝑁 SM Number per Stack 4

𝐶𝑆𝑀 SM Capacitance 400 µF (±10%)

𝛾 Maximum Ripple for SM

Capacitor Voltage 10%

𝑆 Power Switches Selected Type 5SNA 1500E250300

Simulation results for the highest step-ratio conversion case

are demonstrated in Fig. 9. Fig. 9(a) and Fig. 9(b) shows that

the capacitor of SMT1 is inserted into the top stack for 87.5%

period of a switching cycle (2π) before being bypassed for the

remaining 12.5% period. The inserted SM capacitors participate

in the resonance with 𝐿𝑟 and thus assist the SM switches

achieve the soft-switching operation. In Fig. 9(c), all the SM

capacitor voltages in the top stack are well-balanced around 1.6

kV without any extra voltage adjustment, and the phase-shift

angle between the adjacent ones is π/2 as expected. The stack

voltages and transformer voltage and current are shown in Fig.


(a) (b) (c) (d)

Fig. 9. Simulation results for the highest step-ratio conversion case of the bipolar high step-ratio RMMC. (a) Voltage and current of the upper switch in SMT1, 𝑣𝑇1𝑢𝑝

and 𝑖𝑇1𝑢𝑝 . (b) Voltage and current of the lower switch in SMT1, 𝑣𝑇1𝑙𝑜𝑤 and 𝑖𝑇1𝑙𝑜𝑤. (c) SM capacitor voltages in the top stack, 𝑣𝐶𝑇1, 𝑣𝐶𝑇2, 𝑣𝐶𝑇3, 𝑣𝐶𝑇4. (d) Stack

voltages, 𝑣𝑇𝑆𝑇 and 𝑣𝐵𝑆𝑇, and transformer voltage and current on the secondary side 𝑣𝑇𝑅𝑆 and 𝑖𝑇𝑅𝑆.

(a) (b) (c) (d)

Fig. 10. Simulation results for the lowest step-ratio conversion case of the bipolar low step-ratio RMMC. (a) Voltage and current of the upper switch in SMT1, 𝑣𝑇1𝑢𝑝

and 𝑖𝑇1𝑢𝑝 . (b) SM capacitor voltages in the top stack, 𝑣𝐶𝑇1, 𝑣𝐶𝑇2, 𝑣𝐶𝑇3, 𝑣𝐶𝑇4. (c) Top stack voltage 𝑣𝑇𝑆𝑇, voltage on top double-voltage capacitor 𝑣𝐶𝑇𝑑, voltage of

top half-bridge rectifier 𝑣𝑆𝑇1, current through top double-voltage capacitor 𝑖𝐶𝑇𝑑. (d) Bottom stack voltage 𝑣𝐵𝑆𝑇, voltage on bottom double-voltage capacitor 𝑣𝐶𝐵𝑑,

voltage of bottom half-bridge rectifier 𝑣𝑆𝐵1, current through bottom double-voltage capacitor 𝑖𝐶𝐵𝑑.

(a) (b) (c) (d)

Fig. 11. Simulation results for the lowest step-ratio conversion case of the bipolar low step-ratio RMMC with reverse power flow. (a) Voltage and current of the

upper switch in SMT1, 𝑣𝑇1𝑢𝑝 and 𝑖𝑇1𝑢𝑝 . (b) SM capacitor voltages in the top stack, 𝑣𝐶𝑇1, 𝑣𝐶𝑇2, 𝑣𝐶𝑇3, 𝑣𝐶𝑇4. (c) Top stack voltage 𝑣𝑇𝑆𝑇, voltage on top double-voltage

capacitor 𝑣𝐶𝑇𝑑, voltage of top half-bridge rectifier 𝑣𝑆𝑇1, current through top double-voltage capacitor 𝑖𝐶𝑇𝑑. (d) Bottom stack voltage 𝑣𝐵𝑆𝑇, voltage on bottom double-

voltage capacitor 𝑣𝐶𝐵𝑑, voltage of bottom half-bridge rectifier 𝑣𝑆𝐵1, current through bottom double-voltage capacitor 𝑖𝐶𝐵𝑑.

TABLE III. SIMULATION RESULTS OF ALL CONVERSION CASES FOR TABLE IV. SIMULATION RESULTS OF ALL CONVERSION CASES FOR

BIPOLAR HIGH STEP-RATIO RMMC BIPOLAR LOW STEP-RATIO RMMC

Operation Cases 𝑀 = 1 𝑀 = 2 𝑀 = 3

𝑉𝑀𝑆 , 𝑉𝐿𝑆 ±5.5 kV, 1.3 kV ±5.5 kV, 720 V ±5.5 kV, 310 V

𝑓𝑒 , 𝑓𝑠 3 kHz, 2.25 kHz 3 kHz, 1.5 kHz 3 kHz, 750 Hz

𝑉𝐹𝐵𝑅 1.3 kV 720 V 310 V

𝑉𝐶𝑇1, 𝑉𝐶𝑇2 𝑉𝐶𝑇3, 𝑉𝐶𝑇4

2.2 kV, 2.2 kV

2.2 kV, 2.2 kV

1.71 kV, 1.95 kV

1.71 kV, 1.95 kV

1.57 kV, 1.57 kV

1.57 kV, 1.57 kV

𝑉𝐶𝐵1 , 𝑉𝐶𝐵2 𝑉𝐶𝐵3, 𝑉𝐶𝐵4

2.2 kV, 2.2 kV

2.2 kV, 2.2 kV

1.71 kV, 1.95 kV

1.71 kV, 1.95 kV

1.57 kV, 1.57 kV

1.57 kV, 1.57 kV

9(d), and their frequency is four times of the SM switching

frequency. The top stack and bottom stack voltages have the

equal dc component of 5.5 kV while opposite ac components of

around ± 785 V. The transformer voltage on the secondary side

is about ± 310 V and so the overall step-ratio value is 35:1, and

the transformer current is a symmetrical sinusoidal waveform

without dc component. The voltage stresses for SM switches

and rectifier and the SM switching frequency for the required

effective frequency have all achieved the lowest values in this conversion case, which reaches good agreement with the

analysis in (5) to (8).

For the low step-ratio connection in MVDC distribution

systems, the bipolar low step-ratio RMMC (refer to Fig. 6(c))

with the same circuit parameters in Table II can play the

interconnection role between two bipolar MVDC networks with

similar voltages (±𝑉𝑀𝑆1(2𝑉𝑀𝑆1) = ±5.5 kV(11 kV), ±𝑉𝑀𝑆2(2𝑉𝑀𝑆2) =

±7 kV(14 kV) − ±12 kV(24 kV)). The lowest step-ratio conversion

is realized with 𝑀 = 𝑁 − 1 = 3 , and the SM switching

frequency is also set at 750 Hz to generate a 3.0 kHz effective

frequency. The switching sequences in the bottom resonant SM

stack can be also given a phase-shift angle of half effective

cycle with respect to that in the top resonant SM stack to reduce

the voltage ripple on MVDC link ±𝑉𝑀𝑆1. Simulation results for the lowest step-ratio conversion case

are shown in Fig. 10. In Fig. 10(a), the capacitor of SMT1 is

switched into the stack for resonance for 87.5% of the period

and soft-switching is also achieved. Fig. 10(b) shows that all the

SM capacitor voltages are still inherently balanced in this low

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

1.3

1.4

1.6

1.7

1.8

1.5

vCT1(kV)

vCT2(kV)

vCT3(kV)

vCT4(kV)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

2.0

0.0

4.0

6.0

8.0

2.0

vTST(kV)

vB ST(kV)

vTR S(kV)

iTR S(kA)

0.50.0 1.0 2.0 3.0 4.0 5.0

Time (ms)

0.0

1.0

1.5

2.0

0.5

vT1low(kV)

iT1low(kA)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

0.5

0.0

1.0

1.5

2.0

0.5

vT1up(kV)

iT1up(kA)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

1.3

1.4

1.6

1.7

1.8

1.5

vCT1(kV)

vCT2(kV)

vCT3(kV)

vCT4(kV)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

2.0

0.0

4.0

6.0

8.0

2.0

vTST(kV)

vCTd(kV)

vST1(kV)

iCTd(kA)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

2.0

0.0

4.0

6.0

8.0

2.0

vB ST(kV)

vCB d(kV)

vSB1(kV)

iCB d(kA)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

0.5

0.0

1.0

1.5

2.0

0.5

vT1up(kV)

iT1up(kA)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

0.5

0.0

1.0

1.5

2.0

0.5

vT1up(kV)

iT1up(kA)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

2.0

0.0

4.0

6.0

8.0

2.0

vB ST(kV)

vCB d(kV)

vSB1(kV)

iCB d(kA)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

1.3

1.4

1.6

1.7

1.8

1.5

vCT1(kV)

vCT2(kV)

vCT3(kV)

vCT4(kV)

0.0 1.0 2.0 3.0 4.0 5.0Time (ms)

2.0

0.0

4.0

6.0

8.0

2.0

vTST(kV)

vCTd(kV)

vST1(kV)

iCTd(kA)


𝑉𝑀𝑆1, 𝑉𝑀𝑆2 ±5.5 kV, ±12 kV ±5.5 kV, ±9 kV ±5.5 kV, ±7 kV

𝑓𝑒, 𝑓𝑠 3 kHz, 2.25 kHz 3 kHz, 1.5 kHz 3 kHz, 750 Hz

𝑉𝐻𝐵𝑅 6.5 kV 3.5 kV 1.6 kV


2.2 kV, 2.2 kV

2.2 kV, 2.2 kV

1.71 kV, 1.95 kV

1.71 kV, 1.95 kV

1.57 kV, 1.57 kV

1.57 kV, 1.57 kV

𝑉𝐶𝐵1 , 𝑉𝐶𝐵2 𝑉𝐶𝐵3 , 𝑉𝐶𝐵4

2.2 kV, 2.2 kV

2.2 kV, 2.2 kV

1.71 kV, 1.95 kV

1.71 kV, 1.95 kV

1.57 kV, 1.57 kV

1.57 kV, 1.57 kV


step-ratio conversion without switching pattern adjustment, and

the SM capacitor voltage waveforms exhibit the phase-shift of

π/2 between adjacent SMs. From Fig. 10(c) and Fig. 10(d), the

effective frequency for stack voltages, double-voltage capacitor

voltages and rectifier voltages have been all raised to four times

of the SM switching frequency. Further, the voltage across the double-voltage capacitors 𝐶𝑇𝑑 and 𝐶𝐵𝑑 are both about 785 V as

predicted by (11), which is half of the SM capacitor average

voltage. The amplitude voltages of the half-bridge rectifier

indicate the voltages across the differential capacitor 𝐶𝑇𝑑𝑖𝑓 and

𝐶𝐵𝑑𝑖𝑓 are both around 1.6 kV and thus the overall step-ratio in

this conversion is around 7:9 as expected from (12). The overall

efficiency in this conversion case, assessed using the PLECS

platform and with the power switches shown in Table II,

reaches a maximum of 98.89% with losses of 0.69% attributed to conduction and 0.42% to switching of all the switches. This

efficiency is higher than that in original high step-ratio RMMC

[37], [40] since it avoids the internal transformer and has a

reduced number of rectifiers, suggesting that this low step-ratio

RMMC could be a promising candidate for interconnection

between two MVDC networks.

Simulation results for the reverse power flow (from the

second medium-voltage terminal ±𝑉𝑀𝑆2 to the first medium

voltage terminal ±𝑉𝑀𝑆1) are shown in Fig. 11. Operation is seen

to be essentially the same as in Fig. 10, with the same voltage

values and resonant frequencies, but the current directions have been all reversed. It is worth noting that the waveforms of SM

capacitor voltages and stack voltages in Fig. 11(b) to Fig. 11(d)

are similar to those in Fig. 10(b) to Fig. 10(d), but the voltage

trends of each SM capacitor and stack voltage are actually in

the opposite sense due to the change of current flow direction.

The power efficiency is slightly reduced to 98.76% compared

to that in positive case because the soft-switching condition is

not fully achieved in the reverse conversion.

The results of all the conversion cases for these two bipolar

RMMCs are summarized in Table III and Table IV respectively.

It can be seen that both the high step-ratio and low step-ratio

RMMC have the best performance with the operation case of 𝑀 = 𝑁 − 1 = 3 in terms of step-ratio value, effective frequency,

rectifier stress and SM voltage stress.

The simulation results presented in Fig. 9 to Fig. 11 and in

Table III to Table IV demonstrate the efficacy of the circuit

evolution process that has been presented in Section III. The

high step-ratio RMMC and its low step-ratio RMMC

counterpart utilize the structure of resonant SM stack with the

same parameters and creating the same operational advantages

of soft-switching operation, inherent balance and high effective

switching frequency. In both high and low step-ratio cases,

operation with 𝑀 = 𝑁 − 1 is the preferred choice in the connections of MVDC distribution systems.

VI. DOWN-SCALED EXPERIMENTAL VERIFICATION

To further verify the theoretical analysis and simulation results, down-scaled prototypes of the bipolar high step-ratio

RMMC and low step-ratio RMMC were both built in the

laboratory for experimental demonstration, shown in Fig. 12.

The circuit parameters of the bipolar high step-ratio RMMC

prototype (refer to Fig. 6(b)) are shown in Table V with trans-

former turns ratio of 55:22, and this circuit is used to connect a

bipolar dc link (±𝑉𝑀𝑆(2𝑉𝑀𝑆 ) = ±350 V(700 V)) to a monopolar dc

link (𝑉𝐿𝑆 = 20 V − 80 V) for demonstration.

The experimental results for the highest step-ratio conversion case (𝑀 = 3 and 𝑁 = 4) are shown in Fig. 13. The SM switching

frequency is set at 750 Hz to generate an effective frequency of

3.0 kHz between the resonant frequencies of 2.7 kHz and 3.1

kHz in this prototype. From Fig. 13(a) and Fig. 13(b), the

capacitor of SMT1 and SMB1 is inserted into the resonant circuit

for 87.5% of one switching cycle, and they keep a phase-shift

angle of π/4. The soft-switching operation is achieved for both

upper and lower switches in SMT1 and SMB1. Further, the SM

capacitor voltages in the top stack are all inherently balanced at

about 100 V, shown in Fig. 13(c), and the effective frequency

for stack voltages and transformer voltage have been increased to 3.0 kHz in Fig. 13(d) with the SM switching frequency at 750

Hz. The dc component of the top and bottom stack voltages is

equal at 350 V while their ac components are opposite. The

transformer voltage on the low-voltage side is about ± 20 V

which indicates the overall step-ratio in this case is 35:1 as the

simulation results shown in Fig. 9(d). In addition, the

transformer current is also a symmetrical sinusoidal waveform

without dc component as expected thanks to the phase-shift

angle between top stack and bottom stack.

Fig. 12. Down-scaled experimental prototypes of bipolar RMMCs

TABLE V. CIRCUIT PARAMETER OF BIPOLAR RMMC IN DOWN-SCALED EXPERIMENT

Circuit Parameter Description Value

𝑃𝑅 Power Range 0–±500 W

𝐶𝑇𝑀𝑆 𝐶𝐵𝑀𝑆 DC Link Capacitance 550 µF

𝐿𝑚 Magnetizing Inductance 460 mH

𝐿𝑇𝑟 𝐿𝐵𝑟 Resonant Inductance 208 µH

𝑁 SM Number per stack 4

𝐶𝑆𝑀 SM Capacitance 50 µF (±10%)

𝛾 Maximum Ripple for SM

Capacitor Voltage 10%

𝑆 Power Switches Selected Type FF225R12ME4

Built with the same parameters in Table V, the bipolar low

step-ratio RMMC prototype (refer to Fig. 6(c)) is used to

connect two dc links with similar but not identical voltages

(±𝑉𝑀𝑆1(2𝑉𝑀𝑆1) = ±350 V(700 V), ±𝑉𝑀𝑆2(2𝑉𝑀𝑆2) = ±450 V(900 V) −

±750 V(1500 V)) for demonstration.


(a) (b) (c) (d)

Fig. 13. Experimental results for the highest step-ratio conversion case of the bipolar high step-ratio RMMC. (a) Voltage and current of the upper and lower switch

in SMT1, 𝑣𝑇1𝑢𝑝, 𝑖𝑇1𝑢𝑝 , 𝑣𝑇1𝑙𝑜𝑤 and 𝑖𝑇1𝑙𝑜𝑤. (b) Voltage and current of the upper and lower switch in SMB1, 𝑣𝐵1𝑢𝑝, 𝑖𝐵1𝑢𝑝, 𝑣𝐵1𝑙𝑜𝑤 and 𝑖𝐵1𝑙𝑜𝑤. (c) SM capacitor voltages

in the top stack, 𝑣𝐶𝑇1, 𝑣𝐶𝑇2, 𝑣𝐶𝑇3, 𝑣𝐶𝑇4. (d) Stack voltages, 𝑣𝑇𝑆𝑇 and 𝑣𝐵𝑆𝑇, and transformer voltage and current on the secondary side 𝑣𝑇𝑅𝑆 and 𝑖𝑇𝑅𝑆 .

(a) (b) (c) (d)

Fig. 14. Experimental results for the lowest step-ratio conversion case of the bipolar low step-ratio RMMC. (a) Voltage and current of the upper switch in SMT1,

𝑣𝑇1𝑢𝑝 and 𝑖𝑇1𝑢𝑝 . (b) SM capacitor voltages in the top stack, 𝑣𝐶𝑇1, 𝑣𝐶𝑇2, 𝑣𝐶𝑇3, 𝑣𝐶𝑇4. (c) Top stack voltage 𝑣𝑇𝑆𝑇, voltage on top double-voltage capacitor 𝑣𝐶𝑇𝑑, voltage

of top half-bridge rectifier 𝑣𝑆𝑇1, current through top double-voltage capacitor 𝑖𝐶𝑇𝑑. (d) Bottom stack voltage 𝑣𝐵𝑆𝑇, voltage on bottom double-voltage capacitor 𝑣𝐶𝐵𝑑,

voltage of bottom half-bridge rectifier 𝑣𝑆𝐵1, current through bottom double-voltage capacitor 𝑖𝐶𝐵𝑑.

(a) (b) (c) (d)

Fig. 15. Experimental results for the lowest step-ratio conversion case of the bipolar low step-ratio RMMC with reverse power flow. (a) Voltage and current of the

upper switch in SMT1, 𝑣𝑇1𝑢𝑝 and 𝑖𝑇1𝑢𝑝 . (b) SM capacitor voltages in the top stack, 𝑣𝐶𝑇1, 𝑣𝐶𝑇2, 𝑣𝐶𝑇3, 𝑣𝐶𝑇4. (c) Top stack voltage 𝑣𝑇𝑆𝑇, voltage on top double-voltage

capacitor 𝑣𝐶𝑇𝑑, voltage of top half-bridge rectifier 𝑣𝑆𝑇1, current through top double-voltage capacitor 𝑖𝐶𝑇𝑑. (d) Bottom stack voltage 𝑣𝐵𝑆𝑇, voltage on bottom double-

voltage capacitor 𝑣𝐶𝐵𝑑, voltage of bottom half-bridge rectifier 𝑣𝑆𝐵1, current through bottom double-voltage capacitor 𝑖𝐶𝐵𝑑.

TABLE VI. EXPERIMENTAL RESULTS OF ALL CONVERSION CASES FOR TABLE VII. EXPERIMENTAL RESULTS OF ALL CONVERSION CASES FOR

BIPOLAR HIGH STEP-RATIO RMMC BIPOLAR LOW STEP-RATIO RMMC


𝑉𝑀𝑆 , 𝑉𝐿𝑆 ±350 V, 80 V ±350 V, 45 V ±350 V, 20 V

𝑓𝑒 , 𝑓𝑠 3 kHz, 2.25 kHz 3 kHz, 1.5 kHz 3 kHz, 750 Hz

𝑉𝐹𝐵𝑅 80 V 45 V 20 V


139 V, 138 V

140 V, 137 V

103 V, 128 V

104 V, 127 V 101 V, 99 V

99 V, 100 V

𝑉𝐶𝐵1 , 𝑉𝐶𝐵2 𝑉𝐶𝐵3, 𝑉𝐶𝐵4

137 V, 139 V

138 V, 141 V

104 V, 128 V

103 V, 129 V 100 V, 99 V

99 V, 99 V

The results for the lowest step-ratio conversion case (𝑀 =

3 and 𝑁 = 4) are given in Fig. 14. The soft-switching operation

for SM switches and the inherent voltage balance for SM

capacitors are shown in Fig. 14(a) and Fig. 14(b) respectively.

In Fig. 14(c) and Fig. 14(d), the effective frequency has been

also quadrupled to 3.0 kHz to match the resonant frequencies in

this low step-ratio conversion. The voltages across the double-

voltage capacitors are approximately 50 V, and they are half of

the SM capacitor voltage and verify the analysis in (11) again. The half-bridge rectifier voltages imply the voltages across the

differential capacitors are around 100 V, which demonstrate the

step-ratio value in this experiment is also 7:9 as predicted from

(12). The experimental efficiency in this conversion case is 97.6%

with this down-scaled prototype, and it is still a promising result

compared to other low step-ratio prototypes [10], [30], [33].

Experimental results for the reverse power flow (from second

medium-voltage terminal ±𝑉𝑀𝑆2 to first medium-voltage

terminal ±𝑉𝑀𝑆1) are given in Fig. 15. Operating principle is the

same as that in positive power flow, but the stack current

direction and the voltage trend of each SM capacitor are in the

opposite sense as those in Fig. 14. The experimental efficiency is slightly decreased to 97.2% because the soft-switching

operation is also not fully achieved as the simulation results.

500 μs/div

vCT1

(100V/div)

vCT2

(100V/div)

vCT4

(100V/div)

vCT3

(100V/div)

vT1up

(100V/div)

vT1low

(100V/div)

iT1up

(2A/div)

iT1low

(2A/div)

500 μs/div

vB1up

(100V/div)

vB1low

(100V/div)

iB1up

(2A/div)

iB1low

(2A/div)

500 μs/div

vTST

(200V/div)

vBST

(200V/div)

vTRS

(50V/div)

iTRS

(10A/div)

500 μs/div

vBST

(200V/div)

vSB1

(100V/div)

iCBd

(2A/div)

500 μs/div

vCBd

(100V/div)

vTST

(200V/div)

vST1

(100V/div)

iCTd

(2A/div)

vCTd

(100V/div)

500 μs/div

vT1up

(100V/div)

vT1low

(100V/div)

iT1up

(2A/div)

iT1low

(2A/div)

500 μs/div

vCT1

(100V/div)

vCT2

(100V/div)

vCT4

(100V/div)

vCT3

(100V/div)

500 μs/div

vCT1

(100V/div)

vCT2

(100V/div)

vCT4

(100V/div)

vCT3

(100V/div)

500 μs/div

vT1up

(100V/div)

vT1low

(100V/div)

iT1up

(2A/div)

iT1low

(2A/div)

500 μs/div

vBST

(200V/div)

vSB1

(100V/div)

iCBd

(2A/div)

vCBd

(100V/div)

500 μs/div

vTST

(200V/div)

vST1

(100V/div)

iCTd

(2A/div)

vCTd

(100V/div)

500 μs/div


𝑉𝑀𝑆1, 𝑉𝑀𝑆2 ±350 V, ±750V ±350 V, ±575 V ±350 V, ±450 V

𝑓𝑒, 𝑓𝑠 3 kHz, 2.25 kHz 3 kHz, 1.5 kHz 3 kHz, 750 Hz

𝑉𝐻𝐵𝑅 400 V 225 V 100 V


139 V, 137 V

141 V, 139 V

103 V, 129 V

103 V, 128 V

100 V, 98 V

99 V, 101 V

𝑉𝐶𝐵1 , 𝑉𝐶𝐵2 𝑉𝐶𝐵3 , 𝑉𝐶𝐵4

138 V, 139 V

137 V, 140 V

103 V, 128 V

104 V, 128 V

101 V, 99 V

98 V, 99 V


The results of all the conversion cases for these two bipolar

RMMCs are provided in Table VI and Table VII respectively.

As was found in the simulation results in Table IIII and Table

IV, both the high step-ratio and low step-ratio RMMC achieve

best performance when operating with 𝑀 = 3.

The down-scaled experimental results in Fig. 13 to Fig. 15 and in Table VI and Table VII further validate the proposed

circuit evolution of the high step-ratio RMMC into its low step-

ratio RMMC counterpart and also provide the reassurance in

the results of the full-scale simulation.

VII. CONCLUSION

This paper introduced the operational advantages of the

originally proposed transformer-coupled RMMC for high step-

ratio connection between MVDC and LVDC networks and

identified the difficulties of applying it to low step-ratio

conversion for connection between two MVDC networks with

similar but not identical voltages. Then, a step-by-step circuit

evolution was presented that bridges the gap between high and

low step-ratios and reconfigures the high step-ratio transformer-

coupled RMMC into a low step-ratio transformer-less RMMC counterpart. These two RMMCs employ the same structure of

a resonant SM stack with the same resonant frequencies. They

therefore share all the operational advantages and the circuit

design experience can be also readily transferred from one to

the other. With these two base RMMC structures, a family of

RMMCs with further configurations was elaborated in this

paper to provide a wider variety of connection options for

MVDC distribution systems. In this circuit family, each high

step-ratio transformer-coupled has a low step-ratio transformer-

less RMMC counterpart and they can be transformed via the

proposed circuit evolution. The theoretical analysis is verified through full-scale simulations of medium voltage examples and

further verified through down-scaled experiments on laboratory

prototypes. The simulation and experimental results also

demonstrated the potential use and good capability of RMMCs

for both high and low step-ratio connections in MVDC

distribution systems.

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Xin Xiang (S’17-M’18) received the B.Sc. degree

from Harbin Institute of Technology, China in 2011,

the M.Sc. degree from Zhejiang University, China in

2014 and the Ph.D. degree from Imperial College

London, UK in 2018, all in Electrical and Electronic

Engineering. He has received the Eryl Cadwaladr

Davies Prize for the Best Ph.D. Thesis of Electrical

and Electronic Engineering Department in Imperial

College London, and he was also the recipient of the

Best Ph.D. Thesis Award from IEEE PELS UK and

Ireland Chapter. From 2018 to 2020, he was a Research Associate with Imperial

College London, UK. He is currently a Tenured-tracked Associate Professor in

the College of Electrical Engineering, Zhejiang University, China. His research

interests include the analysis and control of modular multilevel converters for

power system applications.

Yunjie Gu (M’16- SM’20) received the B.Sc. and the

Ph.D. degree in Electrical Engineering from Zhejiang

University, Hangzhou, China, in 2010 and 2015

respectively. He was a Consulting Engineer with

General Electric Global Research Centre, Shanghai,

China, from 2015 to 2016. After that, he joined

Imperial College, UK, under the sponsorship of the

UKRI Innovation Fellowship. He is currently a

Lecturer (Assistant Professor) with the University of

Bath, UK, and an Honorary Lecturer at Imperial

College. His research focuses on the fundamental theories and computational

tools for analyzing power system dynamics, as well as the algorithms and

software for power conversion control.

Yang Qiao received the B.S. degree in Electrical

Engineering from Xi’an Jiaotong University, Xi’an,

China, in 2013. He is currently working toward the

M.S. degree in Xi’an Jiaotong University. His

research interests include the design and control of

large step-ratio dc/dc converters for HVDC

transmission.

Xiaotian Zhang (S’11–M’12) received the B.S. and

M.S. degrees in electrical engineering from Xi’an

Jiaotong University, Xi’an, China, in 2006 and 2009,

respectively, and the Ph.D. degree (with honors) in

electrical engineering and electronics from the

University of Liverpool, Liverpool, U.K., in 2012.

Until 2015, he was with the Department of Electrical

Engineering, Imperial College London, U.K. He is

currently an Associate Professor in the Department of

Electrical Engineering, Xi’an Jiaotong University.

His research interests include the analysis and design of power electronics

converter.


Wuhua Li (M’09) received the B.Sc. and Ph.D.

degree in Power Electronics and Electrical

Engineering from Zhejiang University, Hangzhou,

China, in 2002 and 2008, respectively.

From 2004 to 2005, he was a Research Intern, and

from 2007 to 2008, a Research Assistant in GE Global

Research Center, Shanghai, China. From 2008 to 2010,

he joined the College of Electrical Engineering,

Zhejiang University as a Post doctor. In 2010, he was

promoted as an Associate Professor. Since 2013, he

has been a Full Professor at Zhejiang University. From 2010 to 2011, he was a

Ryerson University Postdoctoral Fellow with the Department of Electrical and

Computer Engineering, Ryerson University, Toronto, ON, Canada. He is

currently the Executive Deputy Director of the National Specialty Laboratory

for Power Electronics and the Vice Director of the Power Electronics Research

Institute, Zhejiang University. His research interests include power devices,

converter topologies and advanced controls for high power energy conversion

systems. Dr. Li has published more than 300 peer-reviewed technical papers

and holds over 50 issued/pending patents.

Due to his excellent teaching and research contributions, Dr. Li received the

2012 Delta Young Scholar from Delta Environmental & Educational

Foundation, 2012 Outstanding Young Scholar from National Science

Foundation of China (NSFC), 2013 Chief Youth Scientist of National 973

Program, 2014 Young Top-Notch Scholar of National Ten Thousand Talent

Program, 2019 Distinguished Young Scholar from National Science

Foundation of China. He serves as the Associated Editor of Journal of Emerging

and Selected Topics in Power Electronics, IET Power Electronics, CSEE

Journal of Power and Energy Systems, CPSS Transactions on Power

Electronics and Applications, Proceedings of the Chinese Society for Electrical

Engineering, Guest Editor of IET Renewable Power Generation for Special

Issue “DC and HVDC system technologies”, Member of Editorial Board for

Journal of Modern Power System and Clean Energy.

He received one National Natural Science Award and four Scientific and

Technological Achievement Awards from Zhejiang Provincial Government

and the State Educational Ministry of China. He was appointed as the Most

Cited Chinese Researchers by Elsevier since 2014.

Xiangning He (M’95--SM’96--F’10) received the

B.Sc. and M.Sc. degrees from Nanjing University of

Aeronautical and Astronautical, Nanjing, China, in

1982 and 1985, respectively, and the Ph.D. degree

from Zhejiang University, Hangzhou, China, in 1989.

From 1985 to 1986, he was an Assistant Engineer at

the 608 Institute of Aeronautical Industrial General

Company, Zhuzhou, China. From 1989 to 1991, he

was a Lecturer at Zhejiang University. In 1991, he

obtained a Fellowship from the Royal Society of U.K.,

and conducted research in the Department of Computing and Electrical

Engineering, Heriot-Watt University, Edinburgh, U.K., as a Post-Doctoral

Research Fellow for two years. In 1994, he joined Zhejiang University as an

Associate Professor. Since 1996, he has been a Full Professor in the College of

Electrical Engineering, Zhejiang University. He was the Director of the Power

Electronics Research Institute, the Head of the Department of Applied

Electronics, the Vice Dean of the College of Electrical Engineering, and he is

currently the Director of the National Specialty Laboratory for Power

Electronics, Zhejiang University. His research interests are power electronics

and their industrial applications.

Dr. He is a Fellow of The Institute of Electrical and Electronics Engineers

(IEEE) and was appointed as IEEE Distinguished Lecturer by the IEEE Power

Electronics Society 2011--2015. He is also a Fellow of the Institution of

Engineering and Technology (formerly IEE), U.K.

Timothy. C. Green (M’89–SM’02–F’19) received a

B.Sc. (Eng) (first class honours) from Imperial

College London, UK in 1986 and a Ph.D. from

Heriot-Watt University, Edinburgh, UK in 1990. He

is a Professor of Electrical Power Engineering at

Imperial College London, and Director of the Energy

Futures Lab with a role of fostering interdisciplinary

energy research across the university. His research is

focused on using the flexibility of power electronics

to further the decarbonisation of electricity systems by

easing the integrations of renewable sources and EV charging. In HVDC, he

has contributed converter designs that strike improved trade-offs between

power losses, physical size and fault handling. In distribution systems, he has

pioneered the use of soft open points and the study of stability of grid connected

inverters. Prof. Green is a Chartered Engineering in the UK and a Fellow of the

Royal Academy of Engineering.

resonant modular multilevel dc-dc converters for both high

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