reverse engineering the cognitive brain in silicon

Gert Cauwenberghs [email protected] Reverse Engineering the Cognitive Brain in Silicon

Reverse Engineering the Cognitive Brain in Silicon

Gert Cauwenberghs

Department of Bioengineering Institute for Neural Computation

UC San Diego

http://inc.ucsd.edu


BRAIN Initiative Brain Research through Advancing Innovative Neurotechnologies

–! Interdisciplinary collaborative initiative engaging broad participation in the sciences, engineering, arts, and humanities alongside neuroscientists in advancing our understanding of the circuits and function of the healthy and diseased brain

–! Initial investments with contributions from industry (NIH, NSF, Salk Institute, Allen Brain Institute, etc.)


A Nanotechnology-Inspired GrandChallenge for Future ComputingOCTOBER 20, 2015 AT 6:00 AM ET BY LLOYD WHITMAN, RANDY BRYANT, AND TOM KALIL

Summary: Today, the White House is announcing a grand challenge to develop

transformational computing capabilities by combining innovations in multiple

scientific disciplines.

In June, the Office of Science and Technology Policy issued a Request for Information

seeking suggestions for Nanotechnology-Inspired Grand Challenges for the Next Decade.After considering over 100 responses, OSTP is excited to announce the following grand

challenge that addresses three Administration priorities—the National Nanotechnology

Initiative, the National Strategic Computing Initiative (NSCI), and the BRAIN initiative:

Create a new type of computer that can proactively interpret and learn from data,solve unfamiliar problems using what it has learned, and operate with the energyefficiency of the human brain.

While it continues to be a national priority to advance conventional digital computing—

which has been the engine of the information technology revolution—current

technology falls far short of the human brain in terms of both the brain’s sensing and

problem-solving abilities and its low power consumption. Many experts predict that

fundamental physical limitations will prevent transistor technology from ever matching

these twin characteristics. We are therefore challenging the nanotechnology and

computer science communities to look beyond the decades-old approach to computing

based on the Von Neumann architecture as implemented with transistor-based

processors, and chart a new path that will continue the rapid pace of innovation beyond

the next decade.

! " #

the WHITE HOUSE

$

https://www.whitehouse.gov/blog/2015/10/15/nanotechnology-inspired-grand-challenge-future-computing


Neuromorphic Engineering “in silico” neural systems design

VLSI Microchips

Neuromorphic Engineering

Neural Systems

Learning &

Adaptation

g 1 g 0

g 2 g 0

g 0

g 2 g 2

g 1

g 1


Today’s Hottest Microchip Intel’s Itanium 2

The numbers … –! 0.5 billion transistors in

120nm CMOS –! 1.6GHz clock, 64-bit

instruction, 9MB L3 cache, 6.4GB/s I/O

–! 2553 SPECfp_base2000 (30% faster than 2.8GHz P4)

–! 130 Watts

Source: IEEE ISSCC’2002

… and what they mean Faster/cooler:

•! Scientific computing •! Database search •! Web surfing •! Video games

What about intelligence?


Chips and Brains

•! Itanium: –! 3 109 floating op/s!

•! 5 108 transistors •! 2 109 Hz clock

–! 1010 Hz memory I/O!•! 128-b data bus @ 400MHz

–! 130 Watts!

•! Human brain: –! 1015 synaptic op/s!

•! 1015 synapses •! 1 Hz average firing rate

–! 1010 Hz sensory/motor I/O!•! 108 nerve fibers

–! 25 Watts!

•! Silicon technology is approaching the raw computational power and bandwidth of the human brain.

•! However, to emulate brain intelligence with chips requires a radical paradigm shift in computation: –! Distributed representation in massively parallel architecture!

•! Local adaptation and memory •! Sensor and motor interfaces

–! Physical foundations of computing!


Analysis by Synthesis

Richard Feynman Carver Mead


Source Drain

MOSFET channel

Ene

rgy

Gat

e vo

ltage

Ion channel

Channels

Synapses

Neurons

Networks

Maps

Systems

Brain

Carriers 1 Å

10 nm

1 µm

100 µm

1 cm

1 m

Gate

Analysis Synt

hesi

s Neuromorphic Systems Engineering

Computational Systems Neuroscience

Membrane

Pre Post

VPre VPost EReversal

CMembrane

G. Cauwenberghs, “Reverse Engineering the Cognitive Brain,” PNAS, 2013

Multi-scale levels of investigation in analysis of the central nervous system (adapted from Churchland and Sejnowski 1992) and corresponding neuromorphic synthesis of highly efficient silicon cognitive microsystems. Boltzmann statistics of ionic and electronic channel transport provide isomorphic physical foundations.


Physics of Neural Computation Silicon and Lipid Membranes

Mead, 1989

Voltage-dependent p-channel –! Hole transport between source and drain –! Gate controls energy barrier for holes

across the channel –! Boltzmann distribution of hole energy

produces exponential decrease in channel conductance with gate voltage

poly Si Source

SiO2 Gate Drain

Ene

rgy

Gat

e vo

ltage

p- Si substrate

p-Channel p+ p+ n- well

Squid giant axon (Hodgkin and Huxley, 1952)

Voltage-dependent conductance –! K+/Na+ transport across lipid bilayer –! Membrane voltage controls energy barrier

for opening of ion-selective channels –! Boltzmann distribution of channel energy

produces exponential increase in K+/Na+ conductance with membrane voltage


Event-Coding Silicon Retina

–! Models coding and communication of visual events in the mammalian retina and optic nerve !•! Integrated photosensors (rods) •! On and off transient and sustained ganglia cell outputs

–! Spatiotemporal compressed coding and communication in optic nerve!–! Address-event coding of spikes!

Zaghloul and Boahen, 2006


Change Threshold Detection APS CMOS Imager

–! Event-driven video compression!•! Change detection and threshold encoding

on the focal plane –! 6T pixel combines APS and change event

coding !–! 4.3mW power at 3V and 30fps!

Chi, Mallik, Clapp, Choi, Cauwenberghs and Etienne-Cummings (2007)

90 x 90 TD-APS

Array

FIFO

DDS / Event Coding

Video Out Change Events Out

Fast Rotation Slow Rotation pos. neg.


Reconfigurable Synaptic Connectivity and Plasticity From Microchips to Large-Scale Neural Systems

Multi-Chip Systems

Address-Event Representation

Neural Systems

Synaptic Plasticity &

Wiring


Address-Event Representation (AER) Lazzaro et al., 1993; Mahowald, 1994; Deiss 1994; Boahen 2000

–! AER emulates extensive connectivity between neurons by communicating spiking events time-multiplexed on a shared data bus. !

–! Spikes are represented by two values:!•! Cell location (address) •! Event time (implicit)

–! All events within "t are “simultaneous”!


–! ‘Virtual’ synapses!•! Dynamically reconfigurable •! Wide-ranging connectivity •! Rewiring and synaptic plasticity

–! Quantal release: R = n p q•! n: multiplicity (repeat event) •! p: probability of release (toss a coin) •! q: quantity released (set amplitude)

Address-Event Synaptic Connectivity Goldberg, Cauwenberghs and Andreou, 2000

IFAT2 (2000)

transceiver (IFAT)

1

2

Sender

Receiver

(DRAM)


Hierarchical Vision and Saliency-Based Acuity Modulation Vogelstein, Mallik, Culurciello, Cauwenberghs, and Etienne-Cummings, NECO 2007

IFAT Cortical Model 4800 silicon neurons 4,194,304 synapses

Octopus Silicon Retina 80 x 60 pixels

AER spiking output

OR image Simple cell response Saliency map


Spike Timing-Dependent Plasticity

Bi and Poo, 1998


Spike Timing-Dependent Plasticity in the Address Domain

Causal Anti-Causal

Vogelstein et al, NIPS*2002


Spike Timing-Dependent Plasticity on the IFAT Vogelstein et al, NIPS*2002


Scaling of Task and Machine Complexity

Achieving (or surpassing) human-level machine intelligence will require a convergence between:!•! Advances in computing resources approaching connectivity and

energy efficiency levels of computing and communication in the brain; •! Advances in deep learning methods, and supporting data, to adaptively

reduce algorithmic complexity.

Machine Complexity

Throughput; Memory;

Power; Size

Task Complexity Search tree breadth ^ depth

[log]

[log]

Human brain 1015 synOP/s; 15W

Deep digital search Rule-based cognition

Collective analog computation Learned/habitual cognition

Neuromorphic engineering

Deep learning

G. Cauwenberghs, “Reverse Engineering the Cognitive Brain,” PNAS, 2013


Scaling and Complexity Challenges

•! Scaling the event-based neural systems to performance and efficiency approaching that of the human brain will require: –! Scalable advances in silicon integration and architecture!

•! Scalable, locally dense and globally sparse interconnectivity –! Hierarchical address-event routing!

•! High density (1012 neurons, 1015 synapses within 5L volume) –! Silicon nanotechnology and 3-D integration!

•! High energy efficiency (1015 synOPS/s at 15W power) –! Adiabatic switching in event routing and synaptic drivers!

–! Scalable models of neural computation and synaptic plasticity!•! Convergence between cognitive and neuroscience modeling •! Modular, neuromorphic design methodology •! Data-rich, environment driven evolution of machine complexity

EE NanoE Phys

Neuro CS

CogSci


Long-Range Configurable Synaptic Connectivity

Comparison of synaptic connection topologies for several recent large-scale event-driven neuromorphic systems and the proposed hierarchical address-event routing (HiAER), represented diagrammatically in two characteristic dimensions of connectivity: expandability (or extent of global

reach), and flexibility (or degrees of freedom in configurability). Expandability, measured as distance traveled across the network for a given number of hops N, varies from linear and polynomial in N for linear and mesh grid topologies to exponential in N for hierarchical tree-based

topologies. Flexibility, measured as the number of target destinations reachable from any source in the network, ranges from unity for point-to-point (P2P) connectivity and constant for convolutional kernel (Conv.) connectivity to the entire network for arbitrary (Arb.) connectivity.

MMAER: Multicasting Mesh AER; WS: Wafer-Scale.


Hierarchical Address-Event Routing (HiAER)

(a) Hierarchical neural network with ascending and descending neural projections. Physical neurons are represented by o and p, and inserted relay neurons (RN) interfacing across hierarchical partitions are denoted by q, k, l, n, m. Italic indices j and j – 1 represent levels in the hierarchy, while boldface indices i and i – 1 represent individual blocks within one level in the hierarchy. (b) The edge-vertex-dual of the hierarchical routing network. (c) Corresponding entries within the Synaptic Routing Table (SRT).

(a) (b)

SRT

RN

SRT

i-1

PRE POST PARAMETER

m ↓il dm,i:lk ↑n dk,nk ↓i-1q dk,i-1:q

(c)

Lj

i

lk

q Lj-1i-1

nm

PRE POST PARAMETER

o ↑k do,kl p wl,p

Lj-1i↑k↓il↓i-1q

↑n

po

Lj-1i

Lj

Lj-1 Lj-1

o p

Joshi et al, 2010; Park et al, 2011, 2015


(d) Example network with 16 neurons and weighted synaptic connections. (e) Example partitioning into hierarchical neural network with ascending and descending projections through inserted relay neurons. (f) Corresponding edge-vertex-dual HiAER implementation with synaptic routing tables (SRT) at each level in the hierarchy.

Joshi et al, 2010; Park et al, 2011, 2015

PRE POST PAR

1 2 w1,21 4 w1,42 ↑1 d2,12 3 w2,35 1 w5,1

PRE POST PAR

2 1 w2,12 3 w2,32 ↑2 d2,25 1 w5,15 4 w5,4

PRE POST PAR

1 2 w1,21 ↑1 d1,13 2 w3,23 4 w3,45 2 w5,2

PRE POST PAR

1 2 w1,23 2 w3,25 1 w5,15 4 w5,46 2 w6,2

5 4 w5,4

PRE POST PAR

1 ↓25 d1,2:51 ↑1 d1,12 ↑2 d2,2

PRE POST PAR

1 ↓26 d1,2:62 ↓15 d2,1:53 ↓25 d3,2:5

PRE POST PAR

1 ↓22 d1,2:2

IFAT

L1

IFAT

L1

L2

L3

IFAT

L1

IFAT

L11 2 1 2

1L2

2

1

↑1,↑2

↓25

↓22,

↑2↑1↓15

2 ↓23 d2,2:3

2 ↓15 d2,1:5

6 4 w6,45 3 w5,3

↓15↑1

↓25,

↓23

↓26

51 2 1

5 5

1

2

L11 L12 L11 L12

L21 L22

L31

6

2

3

5

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

( )1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

w1,2 w2,3

w2,5w1,4 w6,5 w6,7

w2,8

w2,10

w9,10 w11,10w11,12

w6,13

w13,14 w15,14

w9,14

w6,16

w9,16w2,12w6,3w6,1


Hierarchical Address-Event Routing (HiAER)

(a) Simplified system architecture of a HiAER node at Level 1 (leaf in the hierarchy), routing synaptic events through the Synaptic Routing Table (SRT) between physical neurons in the local Integrate-and-Fire Array Transceiver (IFAT) and relay neurons on the L1 bus. The SRT maps incoming events from any neuron onto outgoing events either to the final synaptic destination on the IFAT (along with synaptic strength w), or up the hierarchy through the L1 bus (along with timing information for axonal delay d). (b) Digital system architecture of a HiAER node at Level n > 1 (higher in the hierarchy), largely identical to Level 1 except for substitution of the IFAT with a Ln – 1 bus, and of the L1 bus with a Ln bus. In the absence of physical neurons, events are transmitted only between relay neurons higher and/or lower in the hierarchy (along with timing information for axonal delay d).

Ln-1 BUSLn-1 BUSLn-1 BUS

DD

R3 D

RAM

Integrate-and-Fire Array Transceiver (IFAT)

InputFIFO

Priority Queue(PQ)

CMDBuffer

TimeStamp

Mem

ory

cont

rolle

r IP

OutputBuffer

OutputFIFO

OutputFIFO

GlobalTimer

Level 1 HiAER node

(a) (b)

01

MSB

L1 BUS

DD

R3 D

RAM

PriorityQueue(PQ)

Priority Queue(PQ)

CMDBuffer

TimeStamp

Mem

ory

cont

rolle

r IP

OutputBuffer

OutputFIFO

OutputFIFO

GlobalTimer

Level n HiAER node

01

MSB

Ln BUS

Ln-1 BUS


m0

transceiver (IFAT)

1

2

Sender

Receiver

(DRAM)

5 m

m

5 mm

IFAT 0.13µm CMOS IFAT

IFAT IFAT

IFAT

SRT

SRT

SRT

SRT SRT

SRT

SRT

SRT

SRT SRT

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 2 HiAER

IFAT

IFAT IFAT

IFAT

SRT

SRT

SRT

SRT SRT

SRT

SRT

SRT

SRT SRT

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 2 HiAER

IFAT

IFAT IFAT

IFAT

SRT

SRT

SRT

SRT SRT

SRT

SRT

SRT

SRT SRT

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 2 HiAER

IFAT

IFAT IFAT

IFAT

SRT

SRT

SRT

SRT SRT

SRT

SRT

SRT

SRT SRT

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 1 HiAER

Level 2 HiAER

Level3 HiAER +SRT

!

!

!

!

C

C

GL GcompEL

Vm0

Vm1Erev0,1

Vτ0,1

neuroncompartment

distal

proximal

neuroncompartment

Csyn

Csyn

Vτ2,3

Erev2,3

synapse 0,1

synapse 2,3

(c)

Isyn

row 0

row 1

col 1col 0

Vu0,1

Vu2,3

(a) (b)

(c) (d) (e)

Hierarchical Address-Event Routing (HiAER) Integrate-and-Fire Array Transceiver (IFAT) for scalable and reconfigurable neuromorphic neocortical processing [Park et al, 2012; Yu et al, 2012]. (a) Dynamic reconfigurable synaptic connectivity across IFAT arrays of addressable neurons is

implemented by routing neural spike events through DRAM synaptic routing tables (SRT). (b) The IFAT neural array multiplexes and integrates (top traces) incoming spike synaptic events to produce outgoing spike neural events (bottom traces). (c) Full-size HiAER-IFAT network with 4 boards, each with 4 IFAT modules, serving 1M neurons and 1G synapses, and spanning 4 levels in connection hierarchy. (d) Each IFAT chip

module comprises a 65k-neuron Tezzaron 130nm CMOS IFAT microchip, Xilinx Spartan-6 FPGA (Level 1 HiAER), and two 2Gb DDR3 SDRAM SRTs serving 65M synapses. (e) Each neural cell models conductance based membrane dynamics in proximal and distal compartments for

synaptic input with programmable axonal delay, conductance, and reversal potential. IFAT chip measured energy consumption is 48 pJ per spike event, several orders of magnitude more efficient than emulation on CPU/GPU platforms.


IFAT Thermodynamics of Neural Excitability Yu, Park, Joshi, Maier, Cauwenberghs, BioCAS 2012


Large-Scale Reconfigurable Neuromorphic Computing

J. Park et al, “A 65k-Neuron 73-Mevents/s 22-pJ/event Asynchronous Micro-Pipelined Integrate-and-Fire Array Transceiver”, Proc. IEEE BioCAS 2014.

–! Integrate-and-fire array transceiver (IFAT) as digitally programmable analog neural supercomputer

–! Biophysical detail in neural and synaptic continuous-time dynamics

–! Record high density: 65k two-compartment neurons with 65M reconfigurable conductance-based synapses

–! Record low energy: 22 pJ per synaptic event

–! Real-time at 73M spikes per second

20 40 60 80

1

2 Power Linear Fit of Power

Pow

er (m

W)

Event rate (Mevents/s)

transceiver (IFAT)

1

2

Sender

Receiver

(DRAM)


Large-Scale Reconfigurable Neuromorphic Computing Technology and Performance Metrics

Stromatias 2013 SpiNNaker Manchester

Merolla 2014 SyNAPSE TrueNorth

IBM

Schemmel 2010 FACETS/BrainScaleS

Heidelberg

Benjamin 2014 NeuroGrid Stanford

Park 2014 IFAT

UCSD

Technology (nm) 130 28 180 180 90

Die Size (mm2) 102 430 50 168 16

Neuron Type Digital Arbitrary

Digital Accumulate & Fire

Analog Conductance

Integrate & Fire

Analog Shared-Dendrite Conductance I&F

Analog 2-Compartment

Conductance I&F

# Neurons 5216 1 1M 2 512 65k 65k

Neuron Area (µm2) N/A 1 3325 (14) 2 1500 1800 140

Peak Throughput (Events/s) 5M 1G 65M 91M 73M

Energy Efficiency (J/SynEvent) 8n 26p N/A 31p 22p

1 Software-instantiated neuron model 2 Time-multiplexed neuron (256x)

Benjamin, B., P. Gao, E. McQuinn, S. Choudhary, A. Chandrasekaran, J. Bussat, R. Alvarez-Icaza, J. Arthur, P. Merolla, and K. Boahen, “Neurogrid: A mixed analog-digital multichip system for large-scale neural simulations,” Proc. IEEE, 102(5):699–716, 2014.

Merolla, P.A., J.V. Arthur, R. Alvarez-Icaza, A S. Cassidy, J. Sawada, F. Akopyan, B.L. Jackson, N. Imam, C. Guo, Y. Nakamura, B. Brezzo, I. Vo, S.K. Esser, R. Appuswamy, B. Taba, A. Amir, M.D. Flickner, W.P. Risk, R. Manohar, and D. S. Modha, “A million spiking-neuron integrated circuit with a scalable communication network and interface,” Science, 345(6197):668–673, 2014.

Park, J., S. Ha, T. Yu, E. Neftci, and G. Cauwenberghs, “65k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver,” Proc. 2014 IEEE Biomedical Circuits and Systems Conf. (BioCAS), 2014.

Schemmel, J., D. Bruderle, A. Grubl, M. Hock, K. Meier, and S. Millner, “A waferscale neuromorphic hardware system for large-scale neural modeling,” Proc. 2010 IEEE Int. Symp. Circuits and Systems (ISCAS), 1947–1950, 2010.

Stromatias, E., F. Galluppi, C. Patterson, and S. Furber, “Power analysis of largescale, real-time neural networks on SpiNNaker,” Proc. 2013 Int. Joint Conf. Neural Networks (IJCNN), 2013.


(a) (b) (c)

(d) (e) (f)

Phase Change Memory (PCM) Nanotechnology

Intel/STmicroelectronics (Numonyx) 256Mb multi-level phase-change memory (PCM) [Bedeschi et al, 2008]. Die size is 36mm2 in 90nm CMOS/Ge2Sb2Te5, and cell size is 0.097µm2. (a) Basic storage element schematic, (b)

active region of cell showing crystalline and amorphous GST, (c) SEM photograph of array along the wordline direction after GST etch, (d) I-V characteristic of storage element, in set and reset states, (e) programming

characteristic, (f) I-V characteristic of pnp bipolar selector.

–! Scalable to high density and energy efficiency!•! < 100nm cell size in 32nm CMOS •! < pJ energy per synapse operation


Hybridization and nanoscale integration of CMOS neural arrays with phase change memory (PCM) synapse crossbar arrays. (a) Nanoelectronic PCM synapse with spike-timing dependent plasticity (STDP) [Kuzum et al, 2011]. Each PCM element implements a synapse with conductance modulated through phase transition as controlled by timing of voltage pulses. (b) CMOS IFAT array vertically interfacing with nanoscale PCM

synapse crossbar array by interleaving via contacts to crossbar rows. The integration of IFAT neural and PCM synapse arrays externally interfacing with HiAER neural event communication combines the advantages of highly flexible and reconfigurable HiAER-IFAT neural

computation and long-range connectivity with highly efficient (fJ/synOP range energy cost) local synaptic transmission.

I&F Element(3M CMOS)

Standard Via

GST/TiN “Via”

M4Output Lines

M5

M3

Input Lines

PCM Crossbar

Vk

AERIN

AEROUT

wijVj

Vi

I&Fi

I&Fi

(a)

(b)

Kuzum, Jeyasingh, Lee, and Wong (ACS Nano, 2011)


Deep Learning in Spike-Based Neuromorphic Systems

• Neural Sampling: Integrate & Fire (I&F) neurons can perform MCMC

sampling of a Boltzmann distribution

•Restricted Boltzmann Machines can be trained using STDP

!3!

"##$%&

'()&&$*+

,-./

0 %+%

•92% accuracy on MNIST hand-written digit recognition task

E. Neftci et al, “Event-driven contrastive divergence for spiking neuromorphic systems”, Frontiers in Neuroscience, doi: 10.3389/fnins.2013.00272, 2014


Neural Sampling with Noisy Integrate-and-Fire Neurons


!"#$%&'"($)*+,-./0#1

23.$/00.1"$#11.$"(#1'

–! We identified conditions under which spike trains from general integrate-and-fire neurons in the presence of noise generate Monte-Carlo Markov Chain (MCMC) samples from a Boltzmann distribution

–! This framework provides

the foundation for event-driven on-line stochastic learning using contrastive divergence in Boltzmann machines


Event-Driven Contrastive Divergence On-line Training of Boltzmann Machines Using STDP

–! Emulates contrastive divergence (CD) for training standard Restricted Boltzmann Machines (RBMs) using neural sampling with integrate-and-fire neurons.!

–! On-line spike event-driven training using spike-timing dependent plasticity (STDP)!•! Temporally symmetric form produces the correlations <vh> in on-line form•! Modulation g(t) controls wake-sleep phases (data vs. reconstruction)


CD training with standard RBM eCD on-line training with I&F RBM


Event-Driven Contrastive Divergence Learning a Model of MNIST Hand-Written Digits

–! MNIST hand-written digit recognition accuracy:!•! CD with standard RBM: 93.6% •! eCD with neural sampling: 91.9%

–! Extends to deep learning across multiple RBM layers for greater accuracy!


Visible(784 neurons)

Hidden(500 neurons)

Class (40 neurons)

Data Layer784+40 neurons


Event-Driven Contrastive Divergence Inference, Generation, and Cue Integration

–! Generative power of the Boltzmann machine model:!•! Bottom-up: Classification of incoming data •! Top-down: Generation of prototypical data for a class label •! Hybrid: Cue integration with missing data based on class label priors



Spiking Synaptic Sampling Machine (S3M) Biophysical Synaptic Stochasticity in Inference and Learning

–! Stochastic synapses for spike-based Monte Carlo sampling!•! Models biophysical origins of noise in neural systems •! Activity dependent noise: multiplicative synaptic sampling rather than additive neural

sampling

–! Online unsupervised learning with STDP!•! Biophysical model of spike-based learning •! Event-driven contrastive divergence

Emre O. Neftci, Bruno U. Pedroni, Siddharth Joshi, Maruan Al-Shedivat, Gert Cauwenberghs, “Unsupervised Learning in Synaptic Sampling Machines,” arXiv (http://arxiv.org/abs/1511.04484), 2015.

Time-varying Bernoulli random masking of weights

Synaptic stochasticity as biophysical model of continuous DropConnect

The S3M requires fewer synaptic operations (SynOps) than the equivalent Restricted

Boltzmann Machine (RBM) requires multiply-accumulate (MAC) operations at

the same accuracy.


Spike-Timing Dependent Eligibility Reinforcement Learning by Reward Modulation of STDP

–! Spike timing-dependent eligibility (STDE):!•! Variant on biologically inspired spike timing-dependent plasticity (STDP) •! Quantifies the sensitivity of post-synaptic spiking probability, conditioned on timed pre-

synaptic spike input, to synaptic strength •! Direct replacement for input activity term in Hebb-type incremental outerproduct update

rules for gradient-based learning in rate-based ANNs –! Temporal-difference reinforcement learning!

•! STDE-based Dopamine modulation of reward P. Frady et al, SfN 2009

Spike timing-dependent eligibility (STDE)

STDE-based temporal-difference reinforcement learning of the game of Tic-Tac-Toe

27 input neurons!(board positions)!

200 hidden neurons!

Value (V)!

Temporal!difference!

Dopamine!

STDE-!modulated!

reinforcement!

!


Silicon Learning Machines for Embedded Sensor Adaptive Intelligence

ASP A/D Sensory Features

Digital Analog

Large-Margin Kernel Regression Class Identification

Kerneltron: massively parallel support vector “machine” (SVM) in silicon (JSSC 2007)

MAP Forward Decoding Sequence Identification

Sub-microwatt speaker verification and phoneme recognition (NIPS’2004)

GiniSVM


•! 1.2 TMACS / mW –! adiabatic resonant clocking

conserves charge energy!–! energy efficiency on par with human

brain (1015 SynOP/S at 15W)!

Kerneltron: Adiabatic Support Vector “Machine” Karakiewicz, Genov and Cauwenberghs , 2007

Karakiewicz, Genov, and Cauwenberghs, VLSI’2006; CICC’2007

x i

x SIGN

! i MVM

SUPPORT VECTORS

INPUT y

KE

RN

EL K

(x ,x i )

)),((sign bKyySi

iii += !"

xx#

Classification results on MIT CBCL face detection data

resonance

capacitive load


Silicon support vector machine (SVM) and forward decoding kernel machine (FDKM)

x s

x NORMALIZATION

! i1 s

14 24x24

30x24 30x24

1 2 24

" j[n-1] " i[n] 24

MVM MVM

SUPPORT VECTORS

INPUT f i1 (x)

24 FORWARD DECODING

P i1 P i2 4 K

ER

NE

L K(x,x s )

24x24

Forward decoding MAP sequence estimation Biometric verification

840 nW power

Sub-Micropower Analog VLSI Adaptive Sequence Decoding Chakrabartty and Cauwenberghs , 2004

GiniSVM

X[n] X[n-1] X[n+1]

j

i

6 X 4 GiniSVMs

INPU

T ST

AG

E

30

14

24

PROGRAMMING REGISTERS

OUTPUT BUS

PRO

GR

AM

MIN

G

REG

ISTE

RS

–! Subthreshold translinear MOS circuits –! Programmable with floating-gate non-

volatile analog storage


Closing the Loop: Interactive Neural/Artificial Intelligence

MicropowerMixed-Signal

VLSI Neuro

Bio

Neurosystems Engineering

Biosensors,

Neural Prostheses and Brain Interfaces

Adaptive Sensory Feature

Extraction and Pattern Recognition

Neuromorphic Engineering

Learning &

Adaptation


G. Cauwenberghs, K. Kreutz-Delgado, T.P. Jung, S. Makeig, H. Poizner, T. Sejnowski, M. Arnold, F. Broccard, Y.M. Chi, J. Iversen, C. Maier, E. Neftci, D. Peterson,

A. Akinin, S. Das, N. Govil, S. Hsu, T. Mullen, A. Ojeda, C. Stevenson

Distributed Brain Dynamics of Human Motor Control

METRIC fitness function Q

MIMO parameters !

thalamocortical/BG model

EE

G

EM

G, k

inet

ics,

gaz

e

force

PD markers

MoBI

MoCap

synaptic plasticity

Force Feedback

PNS

PNS

PNS PNS

CNS

CNS

CNS

adaptive control

MoCap

Computational modeling

EEG brain dynamics and Parkinson’s

Force feedback

Neuromorphic emulation of brain dynamics in motor control

MoBI

NSF EFRI-1137279: Mind, Machines and Motor Control (M3C)


Real-Time Estimation and 3D Visualization of Source Dynamics and Connectivity Using Wearable EEG

Mullen, T., Kothe, C., Chi, Y. M., Ojeda, A., Kerth, T., Makeig, S., Cauwenberghs, G., Jung, T-P., EMBC & Asilomar BCI, 2013


Mobile Dry EEG Brain-Body Activity Imaging

Mobile dry EEG ASR and SIFT video demonstration

Cognionics 64-channel wireless dry EEG system http://www.cognionics.com

$

$UCSD SCCN SIFT and ASR http://sccn.ucsd.edu/wiki/SIFT


180 !m

Minute 0 Minute 12 Minute 30 Minute 60

CMOS Imaging in Awake Behaving Rats Murari, Etienne-Cummings, Cauwenberghs, and Thakor (2010)

–! First simultaneous behavioral and cortical imaging from untethered, freely-moving rats.!


Integrated Systems Neuroengineering

Silicon Microchips

Neural Systems

Neuromorphic/ Neurosystems

Engineering

Learning &

Adaptation

Environment Human/Bio Interaction

Sensors and Actuators

reverse engineering the cognitive brain in silicon

Documents