review article advances in microelectronics for implantable medical...

Review ArticleAdvances in Microelectronics for Implantable Medical Devices

Andreas Demosthenous

Department of Electronic and Electrical Engineering University College London Torrington Place London WC1E 7JE UK

Correspondence should be addressed to Andreas Demosthenous ademosthenousuclacuk

Received 2 December 2013 Accepted 18 February 2014 Published 29 April 2014

Academic Editor Sebastian Hoyos

Copyright copy 2014 Andreas Demosthenous This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis Overthe years the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronicselectrode technology packaging and signal processing techniques Many of todayrsquos implantable devices use wireless technology tosupply power and provide communication There are many challenges when creating an implantable device Issues such as reliableand fast bidirectional data communication efficient power delivery to the implantable circuits low noise and low power for therecording part of the system and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges facedby the microelectronics circuit designer This paper provides a review of advances in microelectronics over the last decade or sofor implantable medical devices and systems The focus is on neural recording and stimulation circuits suitable for fabrication inmodern silicon process technologies and biotelemetry methods for power and data transfer with particular emphasis on methodsemploying radio frequency inductive couplingThepaper concludes by highlighting some of the issues thatwill drive future researchin the field

1 Introduction

Neuroengineering the application of engineering techniquesto understand repair replace enhance or otherwise exploitthe properties of neural systems is a topic that is currentlygenerating considerable interest in the research communityThe nervous system is a complex network of neurons andglial cells It comprises the central nervous system (brain andspinal cord) and the peripheral nervous system Injuries ordiseases that affect the nervous system can result in some ofthemost devastatingmedical conditions Conditions such asstroke epilepsy spinal cord injury and Parkinsonrsquos diseaseto name but a few as well as more general symptoms suchas pain and depression have been shown to benefit fromimplantablemedical devicesThese devices are used to bypassdysfunctional pathways in the nervous system by applyingelectronics to replace lost function

The first implantable medical devices were introducedin the late 1950s with the advent of the heart pacemaker[1 2] and subsequently the cochlear implant [3 4] Both haverestored functionality for hundreds of thousands of patientsA pacemaker uses electronics and sensors to continuously

monitor the heartrsquos electrical activity and when arrhythmiais detected electrical stimulus is applied to the heart (viaelectrodes) to regulate its speed A cochlear implant useselectronics to detect and encode sound and then stimulatethe auditory nerve to enable deaf individuals to hear Thanksto remarkable advances in microelectronics electrode tech-nology packaging and biomedical signal processing activeimplantable medical devices have developed into advancedsystems employing wireless telemetry for transmission ofdata and sometimes power

The success of cochlear implants has inspired the develop-ment of implantable devices for restoring other basic humansensations Visual prosthesis translates camera input intoelectrical stimulation to the visual nervous system to createpixelized vision [5 6] while vestibular prosthesis connectsmotion sensors to vestibular nerves to restore balance sen-sation [7 8] Another example is deep brain stimulation(DBS) that has been shown to provide therapeutic benefits forotherwise treatment-resistant neurological disorders such asParkinsonrsquos disease tremor and dystonia [9] In current clin-ical DBS systems high frequency stimulation (gt100Hz) pro-duced by a pulse generator (stimulator) is continuously

Hindawi Publishing CorporationAdvances in ElectronicsVolume 2014 Article ID 981295 21 pageshttpdxdoiorg1011552014981295

2 Advances in Electronics

applied via deep brain electrodes to the targeted tissue area inthe brain (Figure 1) The characteristics of these pulses (egfrequency pulse duration and intensity) are programmedinto the stimulator (implanted in the chest area) and adjustedvia an external programmer DBS emerged from heart pace-maker technology and hence is also called a brain pacemakerCurrent developments are focused on the design of cranial-mounted inductively-poweredDBS systems [10] to reduce thelength of the leads from the stimulator to the electrodes andnovel stimulation techniques using high-density segmentedelectrodes which can enable current-steering and electricfield shaping capability [11 12] In addition recent papershave reported the development of prototype closed-loop (iesense and stimulate) neuroprosthetic devices for applicationssuch as vestibular prosthesis [13] and epilepsy [14 15] In thecase of epilepsy the device uses implantable multielectrodearrays and amplifiers to record electrical signals fromneuronsin the brain The recorded data is then processed to extractimportant events which for example predict the onset ofan epileptic seizure and electrical stimulation is applied toinhibit the attack

This paper provides a review of advances in microelec-tronics for implantable medical devices and systems Thefocus is limited to neural recording and stimulation circuitssuitable for fabrication in modern silicon process technolo-gies and biotelemetry methods for power and data transferAfter this introductory part Section 2 reviews several tech-niques and circuit topologies for neural recording includingmethods for on-chip data reduction to reduce the bandwidthrequirements of the wireless transmission link Section 3covers advances in neural stimulation circuits and Section 4discusses biotelemetrymethods includingwireless power anddata transmission by inductive coupling Finally conclusionsare drawn in Section 5 including some suggestions for futureresearch

2 Neural Amplifiers

Neural signals are low frequency and low amplitude sig-nals For example the amplitude of the electroneurogram(ENG) recorded with implanted cuff electrodes [16 17] istypically in the region of 1120583V with most energy concen-trated between 300Hz and 5 kHz Even when recordingneural activity with penetrating microelectrodes such as theUtah Electrode Array [18 19] or the NeuroNexus penetrat-ing probes (httpwwwneuronexustechcom) the recordedneural action potentials often have amplitudes of only a fewtens of microvolts Hence circuits for neural signal amplifi-cationmust have low noise performance and additionally lowpower consumption so that battery life is prolonged espe-cially in implantable systems (eg implantable loop recorderfor long-term monitoring of the heartrsquos electrical activity[20]) In addition front-end neural amplifiers are required toreject electrode offsets or common-mode interference Bothclock-based and continuous-time techniques have been usedin the design of neural amplifiers

21 Clock-Based Techniques The noise in CMOS transistorsis usually dominated by flicker (1119891) noise up to relatively

Pulse generator

DBS electrode

Figure 1 A DBS implant typically consists of an implantedpulse generator which generates electrical pulses for stimulationa set of connection cables and an electrode rod which deliversthe stimulation pulses to the brain target area Image sourcehttpcdnphysorgcom

Ids + Inoise

m(t)

m(t)

Ibias

Iout + Inoise

VDD

V+in Vminus

in

Figure 2 Cycling ofMOS gate bias (left) and application to anOTA

high frequencies of the order of several tens of kHz [21] Thisis particularly troublesome for the design of low frequencylow noise analog circuits Typically p-channel transistorshave less 1119891 noise than n-channel transistors Various clock-based techniques have been developed to reduce the effectsof 1119891 noise Noise reduction based on physical effects(switched biasing) chopper modulation and autozeroing areamongst these techniques

The switched biasing technique (Figure 2) reduces the1119891 noise of a MOS transistor by cyclically increasing anddecreasing its gate bias so that the device alternates betweenstrong inversion and accumulation [22] The transistor noiseismodulated by the switching signalThe switching operationis represented as a multiplication of the 1119891 noise current

Advances in Electronics 3

BPF LPFAmpVin

m(t)

Vout

Figure 3 Block diagram of a chopper amplifier

(119868noise) with the switching signal 119898(119905) For a square-wavesignal with 50 duty cycle

119898(119905) =

1

2

+

2

120587

sin (2120587119891119904119905) +

2

3120587

sin (6120587119891119904119905)

+

2

5120587

sin (10120587119891119904119905) + sdot sdot sdot

(1)

where 119891119904is the switching frequency If 119891

119904is set sufficiently

high the baseband noise reduces by half and any modulationeffects represented by the sine terms in (1) remain outsidethe bandwidth of interest and can be removed by filteringSwitched biasing improves noise performance at low frequen-cies but requires a high speed clock applied to the gate (orbulk) of the transistor with potential problems due to chargefeedthrough and additional noise originating from the drivercircuit In addition to reducing the intrinsic 1119891 noise theswitched biasing technique reduces power consumption [22]A switched biasing amplifier demonstrating input-referrednoise reduction at low frequencies (lt100Hz) is described in[23] It uses two operational amplifiers (opamps) configuredas buffers linked via resistorsThe first stage of each opamp isan operational transconductance amplifier (OTA) circuit ofthe type shown in Figure 2 where switched biasing is appliedto the p-channel transistor supplying the tail current 119868biasFurther noise reduction could be achieved by cycling the volt-age bias applied to the bulk terminals of the differential pairinput transistors

The chopper technique is also based on signal modula-tion The technique enables the design of amplifiers withhigh common-mode rejection ratio (CMRR) performance Ablock diagram of the chopper amplifier is shown in Figure 3[24] Before amplification the amplifier input signal ismodulated by a square-wave signal of frequency 119891

119904that is

much higher than the baseband frequencies of interest Thechopping signal may be represented as in (1) The upcon-verted signal is then amplified and bandpass filtered Themodulated signal spectrum is located at frequencies higherthan the 1119891 noise corner After amplification the signal isconverted back to baseband by multiplication with the samemodulation waveform used for upconversion Lowpass filter-ing restores the desired signal The technique reduces both1119891 noise and amplifier dc offset voltages but the noiseperformance is ultimately limited by the noise floor of theamplifier In addition practical nonidealities including thefinite amplifier bandwidth can lead to signal distortion

OTA

Chopper

m(t) m(t)

m(t)

Vout

+

minus

+

minusIA

R1

R2

Vel offset

Figure 4 Amplifier with 1119891 noise reduction and electrode offsetelimination [28]

Several integrated neural amplifiers employing the chop-per technique have been described for recording from bothimplanted and surface electrodes [25ndash30] The design in[28] employs an ac-coupled chopping technique to rejectelectrode offsets and achieve low noise performance Theconcept of this technique is shown in Figure 4 The systemconsists of a feedforward stage and a feedback stage Tosuppress the 1119891 noise of the instrumentation amplifier(IA) the feedforward stage employs an input chopper andan output chopper To eliminate the electrode offset thefeedback stage employs a lowpass OTA stage followed by achopper stage The operation of the circuit is as follows Theinput differential electrode offset (119881el offset) is modulated bythe input chopper and appears across resistor 119877

1 By action

of the current-feedback the current through 1198771is copied

to 1198772and defines the output voltage after demodulation by

the output chopper The lowpass OTA stage filters the dccomponent of the output and converts it into current TheOTA output current is in turn modulated by a chopperstage In the steady state the current supplied by the OTAis 119881el offset1198771 As a result no current is supplied by the IAand the current passing through 119877

2is zero so the output

(119881out) is zero The neural amplifier in [29] uses choppermodulation and switched-capacitor techniques to reduce the1119891noise and achieve frequency tuningThe circuit is capableof simultaneous recording of extracellular unit spikes (actionpotentials) and local field potentials (low frequency signalsin the 1Hz to 100Hz range) Another publication applieschopper stabilization with a distortion cancelling techniqueto the design of a front-end transimpedance amplifier forcurrent-mode biosensors [30] It achieves both low noise andlow distortion performance at minimum current consump-tion The cancellation technique reduces the distortion andcombinedwith chopping substantially reduces the 1119891noiseFor a current consumption of 50 120583A it is shown that theinput-referred noise density without cancelling and choppingat 10Hz is 29 pAradic(Hz) and reduces to 3 pAradic(Hz) whenboth techniques are employedThe total harmonic distortionfor a peak current of 1 120583A is minus55 dB


Vout

++

minus

minusVinΣ

1206011

1206012

1206011

1206012

1206011 sample1206012 hold

SampH

Figure 5 Autozero amplifier

The autozeroing technique is shown in Figure 5 Duringsampling phase (120601

1) the amplifier is configured as a unity

gain buffer and the input noise is sampled During theamplification phase (120601

2) the noise sample is subtracted from

the instantaneous amplifier input noise As the samplingfrequency chosen is higher than the 1119891 noise frequency thesample is highly correlated to the instantaneous noise andthe low frequency noise is cancelled A detailed analysis ofthe autozeroing technique is given in [31] A drawback of thetechnique is that high frequency white noise is undersam-pled and folded back into the baseband where it increasesthe noise floor A bandpass micropower neural amplifieremploying autozeroing and featuring variable-gain capabilityis presented in [32] An interesting design of a low voltagelow noise amplifier combining autozeroing and choppingstabilization is described in [33]

22 Continuous-Time Techniques The noise reduction tech-niques described above require a clock generation circuitand thus suffer from potential problems associated with highfrequency interference and clock feedthrough In additionhigh frequency switching circuits can increase the complexityand power consumption of the design As an alternativecontinuous-time techniques have been extensively used inthe design of neural amplifiers The classic circuit is the ac-coupledOTA-based neural amplifierwith capacitive feedbackshown in Figure 6 [34] The circuit is built around a singlestage OTA in CMOS technology The ratio of capacitors 119862

1

and 1198622sets the midband gain of the bandpass response The

input is capacitively coupled through 1198621 so any dc offset

from the electrode-tissue interface is removed (1198621should

be made much smaller than the electrode impedance tominimize signal attenuation) Transistors119872

119886ndash119872119889implement

MOS pseudoresistors with an extremely large incrementalresistance (gt1012Ω) This allows the cutoff frequency of theinput high-pass filters (ie ac-coupled stage) to be set tothe millihertz region The lower cutoff frequency is set bythe product of 119862

2and the MOS pseudoresistor implemented

by 119872119886and 119872

119887 The upper cutoff frequency is a function

of the load capacitance (119862119871) the OTA transconductance

(119866119898) and the midband gain (119862

11198622) To reduce the effect

of 1119891 noise the OTA input transistors should be p-channel

OTA

MOS pseudoresistor

Vout

+

minusVin

Vref

C2

C2

C1

C1

Ma Mb

CL

Md

Mc

Figure 6 OTA-based amplifier with capacitive feedback [34]

devices with large gate areas Numerous designs of neuralamplifier based on the circuit in Figure 6 or with somevariations (eg in the realization of the pseudoresistors useof fully-differential topology with one or two stage OTAs useof current-reuse techniques to double the transconductanceand so forth [35ndash39]) have been reported in the literatureincluding commercial amplifier chips by Intan Technolo-gies LLC (httpwwwintantechcom)Methods for effectiveoptimization of a recording channel in terms of its powerconsumption input-referred voltage noise silicon areaand technology used are discussed in [40] The design ofnanopower OTAs with enhanced linearity is presented in[41]

In the case of recording from a multielectrode arraythe total power consumption of the amplifier array (as wellas the silicon area) may be reduced by using the partialOTA sharing structure proposed in [42] In this techniqueeach of the 119899 amplifiers in the array share the componentscorresponding to the reference electrode (ie pseudoresistors119872119888and 119872

119889and capacitors 119862

1and 119862

2connected to 119881ref in

the amplifier in Figure 6) The silicon area is reduced as abenefit of sharing the bulky capacitor 119862

1 The improvement

factor in terms of silicon area depends on the number ofshared amplifiers In general for an electrode array size of119899 the OTA sharing technique allows an area saving of (119899 minus

1)(2119899) times 100 a power saving of (119899 minus 1)(2119899) times 100and an improvement in noise efficiency factor (NEF) of[1 minus radic(119899 + 1)2119899] times 100 compared to the conventionalarchitecture (ie using 119899 neural amplifiers) The NEF is adimensionless figure of merit (noise-power tradeoff) used tocompare different neural amplifier designs It is defined as[43]

NEF = 119881inrmsradic2 sdot 119868tot

120587 sdot 119880119879sdot 4119896119879 sdot BW

(2)


MOS pseudoresistor

Vout+

minusVin

Vref

C2

C2C2

C2

C1

C1

Ma Mb

CL

MdMc

VSS

VSS

VDD

VDDD2

D4D3

D1

N times C2

OTA

Figure 7 Capacitive feedback amplifier with low input capacitance[44]

where 119881inrms represents the integrated input-referred noise119868tot is the total power consumed by the amplifier 119880

119879is the

thermal voltage 119896 is Boltzmannrsquos constant 119879 is the absolutetemperature in Kelvin and BW is the minus3 dB bandwidth ofthe amplifier To include the supply voltage119881DD themodifiedmetric NEF2 times 119881DD is used [37]

To achieve low noise performance a large neural ampli-fier gain is usually required The conventional ac-coupledneural amplifier (Figure 6) often presents a large input loadcapacitance (typically 10ndash20 pF for a midband gain of around40 dB) to the neural signal source hence occupying a largesilicon area It suffers from the unavoidable tradeoff betweeninput capacitance and chip area versus the amplifier gainIn the amplifier in Figure 7 [44] this tradeoff is limited byreplacing the feedback capacitor with a clamped T-capacitornetwork The diodes are used for discharge purposes Com-pared to the conventional circuit this amplifier can achievea given midband gain with less input capacitance a higherinput impedance and smaller silicon area For a midbandgain of 381 dB a neural amplifier employing the topology inFigure 7 used a 16 pF input capacitance and a total siliconarea of 0056mm2 in 035-120583m CMOS technology [44]

Electrode offset removal may also be implemented bymeans of active feedback loops An example neural amplifiertopology with active feedback for dc rejection is shownin Figure 8 [45] It consists of a low noise OTA (OTA

1)

with an active feedback circuit implemented by a secondOTA (OTA

2) configured as a Miller integrator The time-

constant of the integrator is set by capacitor 1198621and the

MOS pseudoresistor comprising 119872119886and 119872

119887 The midband

gain of the amplifier is the same as the gain of OTA1 The

dominant pole of OTA1sets the amplifierrsquos lowpass cutoff

and the common-mode voltage is set by voltage119881ref Anotherexample of a neural amplifier with an active feedback loop to

MOSpseudoresistor

Vout+

+

minus

minus

Vin

Vref

C1

Ma

Mb

CL

OTA1

OTA2

Figure 8 Amplifier with active dc rejection [45]

BPF

Vout

+

minusVin

Vref

Vref

C2

C1

VSS

VDD

M1 M2M3 M4 M5

M6

M7

M8

M9R1

R2

Q1 Q2

Q3

Q4

(12)Ib1 Ib1

Ib2

Ib3

Figure 9 A BiCMOS low noise amplifier [47]

bypass any dc offset current generated by the electrode-tissueinterface is described in [46] It predominantly makes use ofcurrent-mode circuit techniques

A low noise neural amplifier for implanted cuff electrodesis described in [47] The circuit schematic is shown inFigure 9 It consists of an input BiCMOS OTA (119876

1 1198762 1198721

and 1198722) terminated in the load resistor 119877

1 followed by a

first-order bandpass filter (for bandwidth restriction) Theupper cutoff frequency is set by the combination of resistor1198772and capacitor 119862

1 while the lower cutoff frequency is set

by capacitor 1198622with the series combination of transistors

1198726and 119872

7 the latter transistor pair forming a high value

(sim20MΩ) active resistor In addition to eliminating lowfrequencies below the pass-band of the input neural signalthe high-pass section of the bandpass filter also removes someof the low frequency flicker noise voltage tail and ensures a dcoffset-free amplifier output (119881out) The dc bias voltages of1198726and 119872

7are provided by the diode-connected transistors

1198728and 119872

9 respectively which are in turn biased by the

dc current sources 1198681198872

and 1198681198873 Circuitry is also included

(1198723ndash1198725and 119876

3-1198764) to cancel the base currents of 119876

1

and 1198762 This neural amplifier achieved a measured input-

referred root mean square noise voltage of only 290 nV (noisebandwidth of 1Hzndash10 kHz) A variant of this circuit in CMOStechnology using lateral bipolar devices for 119876

1and 119876

2is

possible [48] In general for a given target noise specificationthe use of lateral pnp bipolar devices (available as parasiticdevices in CMOS technology) tends to require a larger siliconarea compared to using standard npn bipolar transistors in


Vout

+

minusVin

Vref

C2

VSS

VDD

M3 M4M5 M6

R1 R2

I1 I2 I3 I4

A B

Mi1Mi2 Mo1

Mo2

Figure 10 A current feedback instrumentation amplifier [51]

BiCMOS technology (but BiCMOS technology might incurhigher manufacturing costs) A bipolar transistor structurein CMOS technology featuring high matching characteristicsis described in [49]

For biomedical front-ends requiring high CMRR per-formance and accurate gain setting the use of an IA isdesirable An IA may be realized using the classic three-opamp topology However the CMRR of the three-opampIA depends on the matching of the resistors and the needfor low output impedance amplifiers can increase powerconsumption Another technique for IA design is to employswitched-capacitor circuits [50] but the fold over of noiseabove the Nyquist frequency can be a major limitation Apopular IA topology for integrated circuits is the currentfeedback technique In a current feedback IA the gain isaccurately set by the ratio of two resistors and the CMRRdoes not rely on thematching of resistors Figure 10 shows thesimplified circuit schematic of a current feedback IA [51]Theinput transconductor stage uses a simple current mirror loadand current sink biasing The sensing amplifier 119860 serves toexactly balance the drain currents of transistors119872

1198941and119872

1198942

by adjusting the complementary currents 1198681and 1198682 A direct

result of this is that the input differential voltage 119881in is forcedacross resistor 119877

1and hence 119872

1198941and 119872

1198942of the input stage

essentially act as a unity-gain buffer Similarly the high gainamplifier 119861 balances the drain currents of transistors 119872

1199001

and 1198721199002

in the output transconductor stage Since currents1198683and 1198684are exact copies of 119868

1and 1198682 respectively the output

voltage 119881out appears across resistor 1198772 Hence the dc gain ofthe IA is given by the ratio 119877

21198771 Placing capacitor 119862

2in

parallel with1198772creates a dominant pole which sets the minus3 dB

bandwidth of the IA The CMRR and noise analysis of thecircuit are described in [51] The IA in [52] used the currentfeedback technique to achieve aCMRRof 99 dB and an input-referred noise of 068 120583V rms It was developed to recordneural signals from electrodes on the lumbo-sacral nerveroots which can be used to restore lower-body function topatients with paraplegia after spinal cord injury

Table 1 compares various integrated neural amplifiersreported in the literature From the table it is observed that

Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filterPGA

Mul

tiple

xer

ADC

Dig

ital

proc

essin

g

(a)

Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filter PGA

ADC Dig

ital

proc

essin

g

(b)

Figure 11 Topologies for multichannel neural recording systems

there is a relationship between current demand and input-referred noise In general the lower the noise performancethe higher the current consumptionThere is a wide variationin the silicon area used

23 Data Reduction Techniques for Multichannel NeuralRecording Front-Ends Front-end neural recording interfacesfor multichannel (multielectrode) systems are typically basedon the two types of architecture in Figure 11 [53] In theapproach in Figure 11(a) the analog front-end circuits whichamplify and filter the neural signal acquired from each ofthe electrodes are grouped in an array of channels Eachof these channels comprises a low noise amplifier (LNA) ofthe type described in Sections 21 and 22 and a bandpassfilter followed by a programmable gain amplifier (PGA) tomaximize the output swing The analog outputs from allthe channels are then multiplexed in time and convertedinto digital words by an analog-to-digital converter (ADC)The generated time-multiplexed data frames can be eitherdigitally processed to compress them or sent directly tothe output as raw data In the approach in Figure 11(b)instead of sharing the ADC between the analog outputs ofthe channels an ADC is embedded in each channel Thena common digital processor manages the digitized signalsfrom the channels classifies (or reduces) the data and sendsit to the output This solution requires a higher silicon areathan the approach in Figure 11(a) but it has some merits interms of power consumption because of themuch lower sam-pling rate requirement at the digitization stage In additionthe system in Figure 11(b) has the advantage that is easilyscalable by replicating the channels A very compact circuitimplementation for the topology in Figure 11(b) is describedin [35] requiring a silicon area of only 0054mm2 per channelin a 130-nm CMOS process technology

Bandwidth limitation is a key issue for wireless biomed-ical devices Wireless transmission of raw data is a majorchallenge for high channel count recording front-ends For


Table1Com

paris

onof

integrated

neuralam

plifiers

Parameter

[34]

[109]

[45]

[110]

[111]

[112]

[29]

[42]

[35]

[37]

[44]

[40]

[39]

[46]

[36]

Year

2003

2004

2007

2009

2009

2010

2010

2011

2012

2012

2013

2013

2013

2013

2013

Fully

differential

No

No

No

No

Yes

Yes

Yes

No

Yes

Yes

No

No

No

No

Yes

CMOSprocess(120583m)

05

15018

035

013

035

018

018

013

013

035

018

018

018

018

Area(

mm

2 )016

0107

005

NA

NA

002

NA

0063

0054

0072

0065

0065

NA

076

016

Supp

lyvoltage

(V)

53

181

13

1618

121

318

118

112

Supp

lycurrent(120583A)

163827

467

126

125

28

4312

44

16121

261

1213

036

Gain(dB)

395

393

4952

457

383

33191375

394

475

40375

4860

548609

445559

26Ba

ndwidth

(Hz)

25mndash72k

0ndash91

k984ndash91k023ndash78k

23mndash115

k10ndash5

k100ndash

8k10ndash72k

167ndash69k

50mndash105k

1ndash10k

03ndash9k

038ndash51k

1ndash10k

80ndash15k

Inpu

t-referredno

ise(120583V

rms)

22

7856

443

195

608

236

35

38

22

106

54

44lowast

81

Noise

band

width

(Hz)

NA

01ndash10k

1ndash91

k1ndash12k

01ndash256k

10ndash5

k1ndash8k

10ndash100

k1ndash100k

01ndash105k

1ndash10k

1ndash8k

1ndash8k

03ndash10k

NA

CMRR

(dB)

ge83

NA

5268

58gt63

6079

701

8380

7448

gt60

NA

gt60

PSRR

(dB)

ge85

NA

5193

40gt63

NA

62638

70ge80

5555

gt70

NA

gt80

THD

Inpu

trange

(mV

pp)

1 167

11 5

1 24

053

52

1 1NA

NA

1 57

1 31

1 11 24

12 11 163

103

lowastlowast

005

10NEF

4194

49

216

248

555

668

335

216

29

578

46

19545

152

NEF2

timesV

DD

801129

4322

453

615

9241

7139

2020

559

841

10022

3808

361

297

277

lowast

Referred

totheinp

utno

deof

thee

lectrode

lowastlowast

Thea

mplitu

derangeo

fthe

inpu

tcurrent

is20

nApp


example a neural interface with 100 channels a 30 kHz sam-pling frequency per channel and an 8-bit sample resolutionwould generate raw data at 24Mbps For a 1024-channelsystem (for cortical neural sensing) the data rate wouldincrease to a massive 250Mbps This data rate is beyond thetransmission capabilities of existing (wideband) implantablewireless transmitters [54ndash56] In the case of extracellularlyrecorded action potentials (spikes) spike sorting [57] is anefficient process to achieve on-chip data reduction therebyenabling lower data rate wireless transmission and lowpower consumption Neural recording microsystems withdata reduction capability typically employ some sort ofthresholding to detect and extract the neural information[58 59] Within this scheme detection occurs when thespikersquos amplitude crosses a specified thresholdThe thresholddetector can be implemented with analog or digital circuitsFor applications where a more detailed classification of mul-tiunit activity into single-unit activity is required techniquesthat extract specific biosignal features (eg peak-to-peakamplitude duration peak-to-zero-crossing time etc) areemployed Most spike sorting methods rely on the assump-tion that each neuron produces a different distinct shape (asseen by the electrode) that remains constant throughout arecording windowThe first step in such techniques is featureextraction in which spikes are transformed into a certain setof features that emphasizes the differences between spikesfrom different neurons as well as the differences betweenspikes and noise Then dimensionality reduction takes placeinwhich feature coefficients that best separate spikes are iden-tified and stored for subsequent processing while the rest arediscarded Finally using clustering spikes are classified intodifferent groups corresponding to different neurons basedon the extracted feature coefficients Implantable spike sort-ing hardwaremust be lowpower and low areaThe algorithmsimplemented in the hardware must be accurate automaticreal-time and computationally efficient A detailed reviewand comparison of spike sorting algorithms are providedin [57 60] An ultra-low power spike sorting digital chipthat can perform detection alignment and feature extractionsimultaneously for 64 channels is described in [61] The chipwas implemented in a 90 nm CMOS process and has a powerdensity of 30 120583Wmm2 which is significantly lower thanthe power density (800 120583Wmm2) known to damage braincells [62]

Spike sorting can potentially reduce the data rate by sev-eral orders of magnitude compared to transmitting raw dataHowever the data in the segments without spikes (whichcontains useful information on the neuronal activities) is lostTo preserve these activities one solution is to use the discretewavelet transform to process the data before transmission[63] This allows the retention of almost all of the data but atthe cost of chip area and power consumption An alternativeis the emerging field of compressive sensing [64] Com-pressive sensing enables signal reconstruction from a smallnumber of nonadaptively acquired sample measurementscorresponding to the information content of the signal ratherthan to its bandwidth It has simple compression steps andtakes advantage of the signalrsquos sparseness allowing the signal

to be determined from relatively few measurements Energy-efficient compressive sensingmethods for implantable neuralrecording is a topic of current research [65 66]

Table 2 compares various multichannel neural recordingsystems with wireless transmission capability The designin [55] has the highest number of channels (128) and datarate (90Mbps) The design in [67] has the lowest powerconsumption per channel

3 Neural Stimulators

Electrical stimulus applied to nerves can trigger action poten-tials At least two electrodes are required in order to producecurrent flow The electrodes are commonly arranged inmonopolar or bipolar configuration In both cases the active(working) electrode is placed near the nerve to be stimulatedIn monopolar stimulation the indifferent electrode is placedaway from the active electrode whilst in bipolar stimulationthe reference electrode is placed near the active electrode

There are two main modes of stimulation namelycurrent-mode and voltage-mode as shown in Figure 12although charge-mode stimulation also exists [68] Current-mode stimulation (Figure 12(a)) is extensively used inimplantable stimulators Active current sources (and sinks)are used to supply the stimulus current to the load (tissue-electrode impedance) For current sources with high outputimpedance the stimulus current amplitude is not affectedby changes in the load Examples of integrated current-mode stimulators in CMOS technology for various applica-tions such as nerve root stimulation for spinal cord injuryvestibular prosthesis for balance disorders and deep brainstimulation for severe movement disorders are described in[11 69ndash73] The current amplitude range is from 1mA to16mA

In voltage-mode stimulation (Figure 12(b)) the stimu-lator output is a voltage and therefore the magnitude ofthe current delivered to the tissue is dependent on theinter-electrode impedance Thus it is difficult to control theexact amount of charge supplied to the load because ofimpedance variations In the system described in [74] thestimulator drives the electrodes with a sequence of voltagesteps charging the electrode metal-fluid capacitance Thisapplies a voltage waveform that is an approximation of thewaveform that would appear at the electrode if a currentpulse was applied (see Figure 12(a)) Since the charge isdelivered to the electrode directly from the capacitors itavoids the (substantial) power in the current sources of itscurrent-mode counterpart as well as providing large voltagecompliance However this method requires large capacitors(which act as voltage sources) that are difficult to implementon-chip The design in [74] has five 1 120583F capacitors for a15-electrode stimulation system which will increase withmore electrodes It is also difficult to achieve fine resolutioncompared to current-mode stimulation since voltage-modeis an approximate method of producing a current pulse andincreasing the resolution requires more capacitors Anothervoltage-mode stimulator is described in [75] Its architecturefeatures energy recovery enabling power savings of 53


Table2Com

paris

onof

wire

lessmultichann

elneuralrecordingsyste

ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)

Figure 12 (a) Current-mode stimulation circuit (b) Voltage-mode stimulation circuit

Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)

Figure 13 Stimulus waveforms (a) Monophasic (b) Biphasic withactive cathodic and active anodic phases (c) Biphasic with activecathodic phase and passive anodic phase (exponential decay)

to 66 (depending on the load) compared to traditionalcurrent-mode stimulator designs

Common stimulation waveforms are either monophasicor biphasic (Figure 13) A monophasic stimulus consists of arepeating unidirectional cathodic pulse (this type of stimulusis common in surface electrode stimulation) A biphasicwaveform consists of a repeating current pulse that has acathodic (negative) phase followed by an anodic (positive)phase The cathodic phase depolarizes nearby axons andtriggers the action potential The succeeding anodic phasereverses the potentially damaging electrochemical processesthat can occur at the electrode-tissue interface during thecathodic phase by (ideally) neutralizing the charge accumu-lated in the cathodic phase allowing stimulation withouttissue damageThe application of charge-balancedwaveforms

is very important especially for implanted electrodes Usuallythe stimulus for the cathodic phase is rectangular supplied byactive circuits while the stimulus for the anodic phase couldbe either square or exponentially decaying The rectangularsecondary phase is also known as active discharging and theexponentially decaying phase as passive discharging

31 Charge-Balanced Stimulation Charge imbalance can becaused by many reasons including semiconductor failureleakage currents due to crosstalk between adjacent stimulat-ing channels (sites) and cable failure A blocking capacitorin series with each electrode is used for electrical safetyagainst single-fault conditions [76] The blocking capacitoris also used to achieve (passive) charge balance Figure 14shows three current-mode stimulator configurations eachemploying a blocking capacitor [69] (a) dual supplies withboth active phases (b) single supply with both active phasesand (c) single supply with active cathodic phase and passiveanodic phase The programmable current sink 119868stimC andcurrent source 119868stimA generate the cathodic and anodic cur-rents respectivelyThese currents are driven through the loadby the control of switches 119878

1and 1198782Whenonly a single supply

is available (Figure 14(b)) the anodic and cathodic currentsare generated from a single current sink (119868stim) by reversingthe current paths by switch 119878

2 Both configurations in Figures

14(a) and 14(b) are (ideally) designed to be charge-balancedto avoid charge accumulation However achieving exactlyzero net charge after each stimulation cycle is not possibledue to mismatch or timing errors and leakage from adjacentstimulating sites Therefore it is important to include switch1198783to periodically remove the residual charge by providing

an extra passive discharge phase in which the voltage on theblocking capacitor drives current through the electrodes tofully discharge them Given the necessity for the third phasein the circuits in Figures 14(a) and 14(b) it is possible touse the passive discharge phase as the main anodic phase asshown in the circuit in Figure 14(c) and the correspondingwaveform in Figure 13(c) Note that the use of capacitive


Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)

Figure 14 Current-mode stimulator circuits with blocking capacitor (a) dual supplies with active cathodic and active anodic phases(b) Single supply with active cathodic and active anodic phases (c) single supply with active cathodic phase and passive anodic phase

electrodes may also drive the passive discharge phase How-ever blocking capacitors may still be deemed necessary toensure that dc current cannot flow into the electrodes inthe event of semiconductor failure due to breakdown voltageor leakage current Due to the large value required for theblocking capacitors (which can be a few microfarads in thecase of stimulators for lower-body applications) they aretypically realized as off-chip surface-mount components Formultichannel stimulation implants a single blocking capac-itor per channel may not be sufficient to guarantee safetydue to a single-fault failure [77]

For applications where the use of blocking capacitorsis not possible due to physical size limitations (eg retinalimplants with several hundreds of stimulating electrodes)other methods for (active) charge balancing exist (Figure 15)

(1) Dynamic current balancing [78] In the circuit inFigure 15(a) a current sink is used to generate thecathodic phase and a pMOS transistor (119872

1) to gen-

erate the anodic phase Before generating a biphasiccurrent pulse 119878cathodic and 119878anodic are open and thetwo sampling switches 119878samp are closed When thecircuit settles the amplitude of the drain currentof 1198721is the same as the current sink (due to the

feedback) and the resulting bias voltage (119881bias) onthe gate of 119872

1is sampled and held Then the two

119878samp switches open and 119878cathodic closes to form thecathodic current Following this 119878cathodic opens and119878anodic closes Because the gate voltage of1198721 is held at119881bias an anodic current equal to the amplitude of the(cathodic) sink current passes through 119878anodic to theload By optimizing the SampH circuit to reduce errorsdue to charge effects a residual dc current error of6 nA is claimed [78]

(2) Active charge balancer [79] In the circuit inFigure 15(b) the residual voltage after a biphasic pulseis measured and compared to a safe reference voltage

If the electrode voltage exceeds the safe windowadditional short stimulation current pulses areapplied to steer the electrode voltage towards abalanced condition The charge balancer is typicallyactivated for less than 5 of the operation time Thismethod has the advantage of providing feedbackinformation on the electrode condition afterstimulation

(3) H-bridge with multiple current sinks [80] Thisapproach assumes an asymmetric biphasic waveformBy way of example consider the H-bridge circuitin Figure 15(c) During the high-amplitude cathodicphase identical current sinks 119868

1 1198682 119868

119873act in par-

allel to pass current through the electrodes for a time119879 Then during the low-amplitude anodic phase oneof the119873 current sinks is used to pass current throughthe electrodes (in the reverse direction) for a time119873 sdot 119879 On a single stimulation cycle this would giveinaccurate charge balance as in practice the currentsinks would not be perfectly matched However ifthe current sink that is active in the anodic phase issequentially changed after each stimulus waveformthen after 119873 cycles each sink would have been activefor the same amount of time during the cathodicand anodic phases yielding accurate charge balanceThe method is claimed to achieve a maximum chargemismatch of 045 [80]

(4) Multiphase compensation [71] The multiphase com-pensation technique is illustrated by the waveformin Figure 15(d) To generate an asymmetric biphasicpulse the width of the anodic phase is extended to119873 times the cathodic width 119879 Ideally the anodiccurrent amplitude should be 119873 times smaller thanthe cathodic amplitudeThe amplitude of the currentsis controlled through an ADC Due to the finiteresolution of the ADC the amplitude of the cathodic


VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)

Figure 15 Techniques for charge balancing (a) Dynamic current balancing [78] (b) active charge balancer [79] (c) H-bridge with multiplecurrent sinks [80] (d) multiphase compensation approach [71]

current 119860119888 may not be an integer multiple of 119873

where 119860119888= 119872 + 120572 and 119872 is the integer multiple

of 119873 that is the closest to 119860119888 Thus there will be

charge balance error between the two phases equal to(120572119873) sdot119873 sdot119879 = 120572 sdot119879 In the multiphase compensationtechnique an additional shorter anodic pulse ofwidth119879 and amplitude 120572 is initiated after the anodic phaseto compensate for the error Subsequently a passivedischarge phase can be applied to further reduce anyremaining charge imbalance The method is claimedto achieve a residual dc current error of 45 nA [71]

32 Other Stimulator Circuits A stimulator circuit that is fail-safewith no off-chip blocking capacitors is shown in Figure 16[72]The circuit generates an active stimulation phase by highfrequency current switching (HFCS) followed by a passivedischarge phase During the active stimulation phase current119868stim (generated by a current generator circuit) is switchedalternately through the left and right branches of the chargetransfer block (Figure 16(b)) This high frequency switchingmechanism allows the size of the blocking capacitors 119862

1and

1198622to be significantly reduced The circuit operation is as

follows During the low-state of the control signal Φstim leftswitch 119872

1is closed and 119872

3is open In this phase diode 119863

1

is reverse biased diode 1198632is forward biased and current

1198681198781

flows and charges up 1198621 In the same phase on the

right branch of the charge transfer block the control signalΦstim right is high and hence switch 119872

2is open and 119863

3 1198622

and1198724form a closed pathwhich discharges119862

2to one-diode-

drop voltage During the high-state of Φstim left Φstim rightis turned low which causes 119862

2to be charged up and 119862

1

to be discharged The complementary high frequency cur-rents 119868

1198781and 119868

1198782generated during the stimulation phase

are summed at the anode of the electrode-tissue loadAfter the stimulation phase the load is passively dis-charged via an ac-coupled discharge switch (Figure 16(c))using depletion-mode transistors 119872

5ndash1198727(connected in

parallel for redundancy) which conduct most of the timeThe operation of this circuit is as follows At each neg-ative edge of the control pulse Φdischarge negative chargeis injected into capacitors 119862

3and 119862

4 On the following

positive edge diode 1198635is reverse biased so the charge on


VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3

Nerve ElectrodesA = anodeC = cathode

Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation

5V logic-level signals

Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim

Figure 16 Stimulator circuits [72] (a) configuration with large off-chip blocking capacitor (b) HFCS charge transfer block (c) isolateddischarge switch (119872

5ndash1198727are depletion transistors) (d) isolated cathode switchThe combination of (b) (c) and (d) provides a safe stimulator

circuit with no off-chip blocking capacitors

1198624is retained (apart from the leakage via resistor 119877

1)

and positive charge is injected into 1198623balancing out the

injected negative charge on 1198623 When a second negative

charge arrives it adds to the charge in 1198624and the cycle is

repeated After a couple of cycles enough negative chargeis built up on 119862

4to switch off 119872

5ndash1198727 While the pulses

continue the gate-source voltage of 1198725ndash1198727remains nega-

tive so they are held off When the pulses cease the negativecharge decays via 119877

1 An ac-coupled switch is also used for

the cathode as shown in Figure 16(d) Its operation is exactlythe same as described above except now it is the positiveedge that provides the charge to 119862

6 Implementation of the

HFCS technique requires silicon-on-insulator (SOI) technol-ogy which features fully-isolated active and passive devicesThe design in [72] used the X-FAB XT06 process technology(httpwwwxfabcom) which has trench isolation HFCS issuitable for stimulus current amplitudes up to about 1mA

The technique can be employed to greatly reduce the size ofhigh-reliability multichannel stimulator implants sited closeto the target nervous tissue (eg in the spinal canal or on thebrain surface)

There is a demand for high efficiency stimulators inapplications which have limited power availability Thebasic current-mode stimulator is inherently inefficient andattempts have been made to increase stimulator efficiencyA design is described in [81] which achieves a 2x to 3xreduction in energy consumption compared with the basiccurrent-mode stimulator It is based on a dc-dc buck voltageconverter efficiently providing a variable output for biphasicpulses The voltage output drive is adjusted by feedbackfrom a sensor detecting the current in the electrode soproviding a controlled current independent of the value of theload impedance The conventional series resistor employedfor current sensing wastes energy and is not used At the


output of the dc-dc converter there is a smoothing capacitorwhich is in parallel with the electrode load This capacitor istemporarily disconnected from the converter and the rate ofdecay of voltage across the capacitor due to the current in theelectrode load is detected and used in feedback This sensingmethod avoids wasting energy The system has appreciablesawtooth noise superimposed on the current pulse Biphasic400 120583A current pulses with widths of 1ms and rise timesof about 100120583s are shown Components external to theintegrated circuit control unit include an inductor (39120583H)and capacitors (up to 10 120583F)

Another example of minimizing power dissipation whileretaining the basic current-mode generator is presented in[82] It assumes the use of a high frequency (1MHz) inductivepower link On its secondary coil zero voltage switching andadjustment of the conduction angle provide a variable voltagesupply to the electrode load and current generator Feedbackadjusts the variable voltage supply so that the current gener-ator operates at just above its compliance limit minimizingthe power it uses The biphasic current is generated usinga single sink current generator with switches similar toFigure 15(c) The supply voltage update is near real-timeso the quality of the current pulses is high irrespective ofhow the load changes during stimulation Depending onload conditions 20 to 75 power saving compared to aconventional current-mode stimulator is claimed In a proto-type design stimulation currents of 20 120583A to 1mAwith pulsewidths of 20120583s to 200120583s are quoted

Where cross-coupling between closely spaced simulta-neously operated stimulating sites must be avoided floatingpower supplies are needed A successful example designcapable of supporting parallel stimulation to electrodeson three semicircular canals for vestibular prosthesis isdescribed in [83]

4 Delivery of Power and Data to Implants

The requirements imposed on medical devices operating inthe body are application specific but there are a commonset of constraints in size power and functionality Theinterplay between these constraints determines the availableprocessing bandwidth for the electronics the operating time(in the case of battery operated devices such as pacemakers)and the communication range and bandwidth of the wirelesstelemetry link In addition the location of the device in thebody data rate frequency and regulatory standards influencethe design complexity and power dissipation of telemetrylinks

Long range telemetry links (typically greater than 2meters) are mainly battery-operated and must conform tostrict regulatory standardsThey require both high sensitivityreceivers and high output power transmitters both of whichresult in high power dissipation In addition unlike mostnear-field (short range) inductive links (discussed below)where a stable reference clock can be extracted from theexternal carrier frequency long range telemetry links requirestable crystal references and frequency synthesizers to gen-erate a local carrier with good frequency stability These

transceivers are typically operated in dedicated frequencybands such as the US federal communications commission(FCC) approved 402ndash405MHz for medical implant commu-nication service (MICS) band (eg the ZL70102 Microsemitransceiver) This band has a 300 kHz maximum bandwidthand a maximum output power of minus16 dBm [84] and the datarate is limited to about 200 kbpsThe industrial scientific andmedical (ISM) radio bands are also frequently used for med-ical telemetry transmitters These include the 902ndash928MHz24ndash24835GHz and 5725ndash5875GHz frequency bands andhave transmission ranges up to 10 meters Lower frequenciesrequire larger antennas while higher frequencies have higherlosses due to tissue absorptionThe optimum frequency bandfor wireless transmitters located in the body is reported to beapproximately 900MHz [85] Ultra wideband (UWB) is analternative wireless data transmission method used at verylow energy levels for short range high bandwidth communi-cations Recently UWB communication in the 31ndash106GHzband was used to develop low power wireless transmitters inCMOS technology for implantable medical devices [15 5556] for high date rate (10ndash90Mbps) transmission from theimplant to the external device Modulation schemes such asonoff keying (OOK) and pulse position modulation (PPM)are used to generate the short pulses

For short range links (typically up to a few centimetres)low frequency inductive links are used for both powersupply and bidirectional data transmission Examples includecochlear and vestibular implants [3 86] These near-fieldsystems can bemade small and highly integratedModulationschemes such as OOK amplitude shift keying (ASK) andfrequency shift keying (FSK) are often used for data transmis-sion from the external unit to the implanted device [87 88]To minimize radio frequency heating due to tissue absorp-tion these systems are typically operated below 15MHz withan achievable data rate up to a few Mbps Transferred powerto the implant typically ranges from 10mW to 125mW [89ndash91] The power transmitted through the tissue should complywith safety standards

A basic block diagram of a typical architecture fortransmitting powerdata to an implant via an inductive linkis shown in Figure 17 The external transmitter typicallyconsists of a class D or class E power amplifier capable ofproviding large currents in the tuned primary coil (119871

1) from a

relatively low voltage In the implant the induced voltage thatappears across the secondary coil (119871

2 tuned by a capacitor)

is rectified and regulated to provide a power supply for theelectronics The data link from the external transmitter tothe implant (the downlink) is often achieved by modulat-ing the envelope of the power carrier to create detectablechanges across the secondary coil The data link from theimplant to the external circuit (the uplink) is commonlyimplemented by load modulation techniques These tech-niques utilize the property of the coupled coils in which achange in the load of the secondary circuit is reflected backas changing impedance in the primary through their mutualinductance119872 Examples ofmodulation techniques for uplinkand downlink data transmission are discussed later

The basic equivalent circuit of the inductive link is shownin Figure 18 [92 93] The primary circuit (119877

1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier

modulatorUplinkdemodulator

Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator

Figure 17 Architecture of a wireless inductive telemetry system to transmit power to an implant and data to and from the implant using asingle pair of coils

Vs

R1

C1

L1

M

C2L2 R2 V2

Primary circuit Secondary circuit

Figure 18 Equivalent circuit of the inductive link with a load (1198772)

tuned in series in order to provide a low impedance loadto the driving transmitter Resistor 119877

1includes the loss of

the inductor 1198711and the output resistance of the voltage

source119881119904(representing the transmitter driver) At resonance

the voltages related with 1198621and 119871

1cancel each other and

thus the primary circuit requires small voltage swings at itsinputs Thus the primary circuit loads the secondary circuitwith a small load The topology of the secondary circuit (119871

2

1198622 1198772) is tuned in parallel in order to amplify sufficiently

the induced voltage to drive a nonlinear (rectifier) loadResistor 119877

2includes the loss of the inductor 119871

2and the load

resistance of the implant circuits Both RLC circuits are tunedto the same resonant frequency The gain factor of the link atresonance is [93]

10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)

((119896crit119896) + (119896119896crit)) 119896crit = radic

11986211198771

11986221198772

(3)

where 119896 is the coupling coefficient and 119896crit is the criticalcoupling coefficient The relative dimensions of the coils andthe air gap cause a low coupling coefficient (119896 lt 01) Inaddition the inductances of the primary 119871

1and secondary

1198712coils are small and can be generated using coils with a few

turns The typical variations of the gain factor are illustratedin Figure 19 The gain factor is not constant with respect tocoupling variationsThe link transfersmaximumpowerwhenthe resistance in the primary is equivalent to the reflectedsecondary resistance assuming that reactive components are

1

Gai

n fa

ctor

kcrit

Coupling (k)

Figure 19 Gain factor versus coupling when the primary andsecondary circuits are tuned to the same frequency

being cancelled It can be shown that efficiency (120578) at criticalcoupling is equal to 50 (Figure 20) [93] For the purposesof data transfer the link behaves as a narrow-band bandpassfilter At resonance and assuming that the coils have the samequality factor 119876 the bandwidth of the link is 119861 = radic2(119891

119888119876)

where 119891119888is the carrier frequency [87]

Power transfer (gain factor) optimization and data trans-fer (bit rate) optimization have contradicting requirementsTo illustrate this the circuit in Figure 18 was simulated inAdvanced Design System (Agilent EEsof EDA) with (119877

1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871

2= 1 120583H) tuned to 1MHz

by 1198621and 119862

2 respectively [94] The relationships between

gain factor (power transfer) carrier frequency and couplingcoefficient are plotted in Figure 21 The optimum gain factoris at the resonant frequency (1MHz) and coupling coeffi-cient (119896) of around 005 The gain factor can be improvedby increasing the quality factorsThe bandwidth of the induc-tive link can be increased by lowering the quality factors


1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()

Figure 20 Efficiency of the inductive link versus coupling when theprimary and secondary circuits are tuned to the same frequency

001

0203

04

08

1

12

140

5

10

15

Carrier frequency (Hz)

times106

Coupling coefficient (k)

Gai

n fa

ctor

(V2V

s)

Figure 21 Inductive link gain factor versus coupling coefficient andcarrier frequency simulated in ADS for the equivalent circuit modelof Figure 18

It also increases as the coupling coefficient increases(ie the gap between the coils decreases) In practicethe inductive link should be designed to account for thepotentially wide variation in the gap between the coilsCoupling compensation techniques (incorporating feedback)regulate the voltage across the secondary coil [95ndash97] Powerand data links can use separate sets of coils because thisallows independent optimization to maximize performance[98] However using separate coils has the drawbacks ofan increase in the implant footprint and electromagneticinterference The latter requires the use of complex modula-tion techniques to minimize its effects and increases systemcomplexity

The most commonly used technique for uplink datatransmission is passive signalling [99] also known as loadshift keying (LSK) [100] This modulation is based on

Vs

R1

C1

L1

M

C2L2 R2

Data

Figure 22 Implementation of LSK modulation

the reflection of the implantrsquos load to the transmitter viathe inductive link A typical implementation is shown inFigure 22 The binary Data stream shorts the implant coiland the change in impedance is reflected in the transmitterbecause the implant load is much larger than the on-resistance of the switch transistor Where only two coils areused (for both power and data) there is a risk of disruptionin power delivery if the short is applied for too long to theimplant coil When communication is in idle mode the linkshould be optimized formaximum power transferThe band-width of LSK is limited by the coupling factor the parametersof the coils and the transient response of the inductive linkMultilevel LSK may be used to increase the data rate [101]An alternative communication technique for uplink is passivephase shift keying (PPSK) [102]Unlike LSK the switch acrossthe secondary coil (Figure 22) closes synchronously with thecarrier for half the carrier cycle The transient response inthe primary coil current is detected as a logic ldquo1rdquo signalAn integrated implementation of PPSK in CMOS technologyis presented in [103] The circuit was designed to work at1356MHzwith a single set of coils for both data transmissionand power delivery The link can reach a data rate of upto 116 of the carrier frequency that is 8475 kbps in thiscase making it the fastest data rate achieved by a singlewireless (inductively coupled) link used simultaneously forpower delivery and communication for implantable devicesAnother method for uplink transmission is pulse harmonicmodulation (PHM) It achieves a data rate of 20Mbps for 1 cmcoil separation using a carrier frequency of 667MHz [104]A pattern of very narrow pulses with specific time delays andamplitude is used whichminimizes intersymbol interferenceacross the receiver coil PHM is one of the fastest data trans-mission methods currently known via inductively coupledcoils Unfortunately to implement it a separate power linkis required as this method is carrier-less

For downlink data transmission various digital mod-ulation schemes are used The most common are binaryamplitude shift keying (BASK) binary frequency shift keying(BFSK) and binary phase shift keying (BPSK) The simplestin implementation is BASK but it is sensitive to amplitudefluctuation and the bit rate is typically limited to about 10of the carrier frequency [87 88] In BFSK the binary datais represented by constant amplitude using two differentfrequencies where logic ldquo1rdquo is assigned to one frequencyand logic ldquo0rdquo to the other Compared to BASK BFSK canprovide higher data-rate-to-carrier-frequency ratio [105] butit requires a wide passband in the inductive link to allow


for the different frequencies which limits power transferThe advantage of BPSK over BASK and BFSK is the use of acarrier with fixed amplitude and fixed frequencies [106]enabling efficient and stable power transfer However BPSKrequires a complicated demodulator implemented by somekind of phase-locked loop usually a Costas loop [87] A com-prehensive survey and comparison of modulation techniquesis presented in [88]

5 Conclusion and Future Directions

Since the 1950rsquos remarkable efforts have been undertakenin the development of implantable medical devices Initiallymost of the successful applications focused on cardiac rhythmmanagement Todayrsquos implantable medical devices providetherapy to treat numerous health conditions Exciting newapplications for example in electrical neuromodulation canbe used to treat Parkinsonrsquos disease epilepsy bladder con-trol gastrointestinal disorders and numerous psychologicaldisorders such as obsessive-compulsive disorder Implantablemedical devices can now provide a range of pharmacologicaltherapies enabling precise dosage and interval delivery ofdrugs to more effectively treat patientsrsquo conditions whileminimizing side effects

There are many challenges when creating an implantablemedical device These include microelectronic design elec-trode technology packaging and biomedical signal process-ingThis paper has focused on the advances inmicroelectron-ics over the last decade or so for implantable medical devicesand systems Several examples of neural amplifiers featuringlow noise and low power to monitor the small electricalpotentials produced from living neurons via electrodes havebeen discussed Both clock-based and continuous-time tech-niques are used in the design of neural amplifiers Nowadaysimplantable neural recording devices include sophisticatedsignal processing functions on-chip for data compressionsuch as spike sorting Analog and mixed analogdigital cir-cuits are used in their implementation New advanced tech-niques to further reduce the power and bandwidth require-ments of the wireless data transmission link for examplebased on the concept of compressive sensing will continueto emerge

Neural stimulation is a key function performed byimplantable medical devices for many applications Somecommon principles and design techniques for neural stimu-lators have been presented including new techniques whichavoid the need for off-chip blocking capacitors and methodsfor achieving charge balancing There is a need for energy-efficient stimulator circuits to reduce power consumption(two such examples have been discussed) and further devel-opments in this area are anticipated particularly for applica-tions requiringmany stimulation sites (eg retinal prosthesisfor the blind)

Wireless power and data operation of implantable med-ical devices are important because they avoid the need forimplantable batteries and offer more flexibility to patientsAlthough major advances have been achieved in the field ofwireless communications andwireless powering for implantsfurther improvements in terms of new techniques that allow

better optimization of the entire system are anticipated Thebasic principles of inductively coupled telemetry links com-monly used to wirelessly power implants and to provide themwith a medium for bidirectional communication have beendiscussed Recent developments include the introductionof advanced modulation schemes (eg PHM) that allowwideband transmission of data over inductively coupled coilsIn addition transceivers based on conventional widebandwireless radio technology are emerging These are expectedto continue to offer improved performance in terms of anincrease in output data rate with lower power consumptionrequirements as smaller geometry silicon process technolo-gies are used for the implementation of the implantablecircuits On the subject of providing power to implantablemedical devices it is expected that systems using energy har-vested from outside and inside the human body will evolveAn example of such a system that uses the cochlear in theinner ear as a battery source to supply a 24GHz radio trans-mitter is described in [107] For such systems ultra-low powercircuits are essential

An important research topic involves closed-loop senseand stimulate systems which will continue to develop pos-sibly combining both sensing of electrical and chemicalresponses for applications such as DBS epilepsy and otherneurological conditions Such systems will allow better man-agement of the clinical condition allowing systems to adaptto the varying pathological characteristics In addition whennew highly miniaturized implantable neural interfaces aredeveloped a step change in micropackaging techniques willbe needed to protect the active area of the integrated circuitfrom hostile environments experienced in the body As anexample a recent publication describes a technique for inte-grated circuit micropackages dedicated to neural interfacesbased on gold-silicon wafer bonding [108]

The expectation of longer life and a progressively increas-ing knowledge basewill place further dependence onmodernhealthcare technologies to improve the quality of life of avery large number of patients (both young and old)This willundoubtedly provide a fertile ground for future research

Conflict of Interests

The author declares that there is no conflict of interestsregarding the publication of this paper

References

[1] C Ward S Henderson and N H Metcalfe ldquoA short history onpacemakersrdquo International Journal of Cardiology vol 169 no 4pp 244ndash248 2013

[2] P E Vardas E N Simantirakis and E M Kanoupakis ldquoNewdevelopments in cardiac pacemakersrdquo Circulation vol 127 pp2343ndash2350 2013

[3] F G Zeng S Rebscher W V Harrison X Sun and H FengldquoCochlear implants systemdesign integration and evaluationrdquoIEEE Reviews in Biomedical Engineering vol 1 pp 115ndash1422008

[4] B S Wilson and M F Dorman ldquoCochlear implants a remark-able past and a brilliant futurerdquo Hearing Research vol 242 no


1-2 pp 3ndash21 2008[5] J M Ong and L da Cruz ldquoThe bionic eye a reviewrdquo Clinical amp

Experimental Ophthalmology vol 40 pp 6ndash17 2012[6] T Guenther N H Lovell and G J Suaning ldquoBionic vision sys-

tem architecturesmdasha reviewrdquo Expert Review of Medical Devicesvol 9 no 1 pp 33ndash48 2012

[7] CWall IIIDMMerfeld SD Rauch andFO Black ldquoVestibu-lar prostheses the engineering and biomedical issuesrdquo Journalof Vestibular Research Equilibrium and Orientation vol 12no 2-3 pp 95ndash113 2002-2003

[8] G Y Fridman and C C Della Santina ldquoProgress toward devel-opment of a multichannel vestibular prosthesis for treatment ofbilateral vestibular deficiencyrdquo Anatomical Record vol 295 pp2010ndash2029 2012

[9] S Miocinovic S Somayajula S Chitnis and J L Vitek ldquoHis-tory applications and mechanisms of deep brain stimulationrdquoJAMA Neurology vol 70 no 2 pp 163ndash171 2013

[10] HM Lee H Park andM Ghovanloo ldquoA power-efficient wire-less system with adaptive supply control for deep brain stimu-lationrdquo IEEE Journal of Solid-State Circuits vol 48 no 9 pp2203ndash2216 2013

[11] V Valente A Demosthenous and R Bayford ldquoA tripolarcurrent-steering stimulator ASIC for field shaping in deep brainstimulationrdquo IEEE Transactions on Biomedical Circuits andSystems vol 6 no 3 pp 197ndash207 2012

[12] V Valente A Demosthenous and R Bayford ldquoOutput stageof a current-steering multipolar and multisite deep brainstimulatorrdquo in Proceedings of the IEEE Biomedical Circuits andSystems Conference (BiOCAS rsquo13) pp 85ndash88 Rotterdam TheNetherlands October-November 2013

[13] J DiGiovanna W Gong C Haburcakova et al ldquoDevelopmentof a closed-loop neural prosthesis for vestibular disordersrdquoJournal of Automatic Control vol 20 pp 27ndash32 2010

[14] A Berenyi M Belluscio D Mao and G Buzsaki ldquoClosed-loopcontrol of epilepsy by transcranial electrical stimulationrdquo Sci-ence vol 337 pp 735ndash737 2012

[15] K Abdelhalim H M Jafari L Kokarovtseva J L PerezVelazquez and R Genov ldquo64-channel UWB wireless neuralvector analyzer SOC with a closed-loop phase synchrony-triggered neurostimulatorrdquo IEEE Journal of Solid-State Circuitsvol 48 no 10 pp 2494ndash2515 2013

[16] G E Loeb and R A Peck ldquoCuff electrodes for chronic stim-ulation and recording of peripheral nerve activityrdquo Journal ofNeuroscience Methods vol 64 no 1 pp 95ndash103 1996

[17] R B Stein D Charles L David J Jhamandas AMannard andT R Nichols ldquoPrinciples underlying new methods for chronicneural recordingrdquo Canadian Journal of Neurological Sciencesvol 2 no 3 pp 235ndash244 1975

[18] C T Nordhausen E M Maynard and R A Normann ldquoSingleunit recording capabilities of a 100 microelectrode arrayrdquo BrainResearch vol 726 no 1-2 pp 129ndash140 1996

[19] A S Dickey A Suminski Y Amit and N G HatsopoulosldquoSingle-unit stability using chronically implanted multielec-trode arraysrdquo Journal of Neurophysiology vol 102 no 2 pp1331ndash1339 2009

[20] S Mittal E Pokushalov A Romanov et al ldquoLong-term ECGmonitoring using an implantable loop recorder for the detectionof atrial fibrillation after cavotricuspid isthmus ablation inpatients with atrial flutterrdquo Heart Rhythm vol 10 no 11 pp1598ndash1604 2013

[21] Y Nemirovsky I Brouk and C G Jakobson ldquo1f noise inCMOS transistors for analog applicationsrdquo IEEE Transactionson Electron Devices vol 48 no 5 pp 921ndash927 2001

[22] E A M Klumperink S L J Gierkink A P van derWel and BNauta ldquoReducing MOSFET 1f noise and power consumptionby switched biasingrdquo IEEE Journal of Solid-State Circuits vol35 no 7 pp 994ndash1001 2000

[23] Y-J Min C-K Kwon H-K Kim C Kim and S-W Kim ldquoACMOSmagnetic hall sensor using a switched biasing amplifierrdquoIEEE Sensors Journal vol 12 no 5 pp 1195ndash1196 2012

[24] C C Enz E A Vittoz and F Krummenacher ldquoA CMOS chop-per amplifierrdquo IEEE Journal of Solid-State Circuits vol 22 no3 pp 335ndash342 1986

[25] A Uranga X Navarro and N Barniol ldquoIntegrated CMOSamplifier for ENG signal recordingrdquo IEEE Transactions onBiomedical Engineering vol 51 no 12 pp 2188ndash2194 2004

[26] T Denison K Consoer W Santa A-T Avestruz J Cooley andA Kelly ldquoA2120583w 100 nVrtHz chopper-stabilized instrumenta-tion amplifier for chronic measurement of neural field poten-tialsrdquo IEEE Journal of Solid-State Circuits vol 42 no 12 pp2934ndash2945 2007

[27] Y Tseng Y Ho S Kao and C N I S Su ldquoA 009 120583Wlow powerfront-end biopotential amplifier for biosignal recordingrdquo IEEETransactions on Biomedical Circuits and Systems vol 6 no 5pp 508ndash516 2012

[28] R F Yazicioglu P Merken R Puers and C van Hoof ldquoA60 120583W 60 nVradicHz readout front-end for portable biopotentialacquisition systemsrdquo IEEE Journal of Solid-State Circuits vol 42no 5 pp 1100ndash1110 2007

[29] J Lee M Johnson and D Kipke ldquoA tunable biquad switched-capacitor amplifier-filter for neural recordingrdquo IEEE Transac-tions on Biomedical Circuits and Systems vol 4 no 5 pp 295ndash300 2010

[30] V Balasubramanian P F Ruedi Y Temiz A Ferretti CGuiducci and C C Enz ldquoA 018 120583m biosensor front-end basedon 1f noise distortion cancelation and chopper stabilizationtechniquesrdquo IEEE Transaction on Biomedical Circuits and Sys-tems vol 7 no 5 pp 660ndash673 2013

[31] C C Enz and G C Temes ldquoCircuit techniques for reducingthe effects of Op-Amp imperfections autozeroing correlateddouble sampling and chopper stabilizationrdquo Proceedings of theIEEE vol 84 no 11 pp 1584ndash1614 1996

[32] C-H Chan J Wills J LaCoss J J Granacki and J ChomaJr ldquoA novel variable-gain micro-power band-pass auto-zeroingCMOS amplifierrdquo in Proceedings of the IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo07) pp 337ndash340May 2007

[33] Y Masui T Yoshida M Sasaki and A Iwata ldquo06 V supplycomplementary metal oxide semiconductor amplifier usingnoise reduction technique of autozeroing and chopper stabiliza-tionrdquo Japanese Journal of Applied Physics vol 46 no 4B pp2252ndash2256 2007

[34] R R Harrison and C Charles ldquoA low-power low-noise CMOSamplifier for neural recording applicationsrdquo IEEE Journal ofSolid-State Circuits vol 38 no 6 pp 958ndash965 2003

[35] A Rodrıguez-Perez J Ruiz-Amaya M Delgado-Restituto andA Rodrıguez-Vazquez ldquoA low-power programmable neuralspike detection channel with embedded calibration and datacompressionrdquo IEEE Transaction on Biomedical Circuits andSystems vol 6 no 4 pp 87ndash100 2012


[36] S SongM J Rooijakkers PHarpe et al ldquoA 430 nW64nVradicHzcurrent-reuse telescopic amplifier for neural recording appli-cationsrdquo in Proceedings of the IEEE Biomedical Circuits andSystems Conference (BiOCAS rsquo13) pp 322ndash325 Rotterdam TheNetherlands October-November 2013

[37] F Zhang J Holleman andB POtis ldquoDesign of ultra-lowpowerbiopotential amplifiers for biosignal acquisition applicationsrdquoIEEE Transactions on Biomedical Circuits and Systems vol 6no 4 pp 344ndash355 2012

[38] S Song M J Rooijakkers P Harpe et al ldquoA 430nW 64nVradicHzcurrent-reuse telescopic amplifier for neural recording appli-cationsrdquo in Proceedings of the IEEE Biomedical Circuits andSystems Conference (BiOCAS rsquo13) pp 322ndash325 Rotterdam TheNetherlands October-November 2013

[39] X Zou L Liu J H Cheong et al ldquoA 100-channel 1-mWimplantable neural recording ICrdquo IEEE Transactions on Circuitsand Systems I Regular Papers vol 60 no 10 pp 2584ndash25962013

[40] P Kmon and P Grybos ldquoEnergy efficient low-noise multichan-nel amplifier in submicron CMOS processrdquo IEEE Transactionson Circuits and Systems I Regular Papers vol 60 no 7 pp 1764ndash1775 2013

[41] J Gak M R Miguez and A Arnaud ldquoNanopower OTAs withimproved linearity and low input offset using bulk degener-ationrdquo IEEE Transactions on Circuits and Systems I RegularPapers vol 61 no 3 pp 689ndash698 2014

[42] V Majidzadeh A Schmid and Y Leblebici ldquoEnergy efficientlow-noise neural recording amplifier with enhanced noiseefficiency factorrdquo IEEE Transactions on Biomedical Circuits andSystems vol 5 no 3 pp 262ndash271 2011

[43] M S J Steyaert andWM C Sansen ldquoAmicropower low-noisemonolithic instrumentation amplifier for medical purposesrdquoIEEE Journal of Solid-State Circuits vol 22 no 6 pp 1163ndash11681987

[44] K A Ng and Y P Xu ldquoA compact low input capacitance neuralrecording amplifierrdquo IEEE Transaction on Biomedical Circuitsand Systems vol 7 no 5 pp 610ndash620 2013

[45] B Gosselin M Sawan and C A Chapman ldquoA low-powerintegrated bioamplifier with active low-frequency suppressionrdquoIEEE Transactions on Biomedical Circuits and Systems vol 1 no3 pp 184ndash192 2007

[46] C Y Wu W M Chen and L T Kuo ldquoA CMOS power-efficient low-noise current-mode front-end amplifier for neuralsignal recordingrdquo IEEE Transaction on Biomedical Circuits andSystems vol 7 no 2 pp 107ndash114 2013

[47] A Demosthenous and I F Triantis ldquoAn adaptive ENG amplifierfor tripolar cuff electrodesrdquo IEEE Journal of Solid-State Circuitsvol 40 no 2 pp 412ndash420 2005

[48] R Rieger M Schuettler D Pal et al ldquoVery low-noise ENGamplifier system using CMOS technologyrdquo IEEE Transactionson Neural Systems and Rehabilitation Engineering vol 14 no 6pp 427ndash437 2006

[49] Y J Jung B S Park H M Kwon et al ldquoA novel BJT structureimplemented using CMOS processes for high-performanceanalog circuit applicationsrdquo IEEE Transactions on Semiconduc-tor Manufacturing vol 25 no 4 pp 549ndash554 2012

[50] M Degrauwe E Vittoz and I Verbauwhede ldquoA micropowerCMOS instrumentation amplifierrdquo IEEE Journal of Solid-StateCircuits vol 20 no 3 pp 805ndash807 1985

[51] A Worapishet A Demosthenous and X Liu ldquoA CMOSinstrumentation amplifier with 90-dB CMRR at 2-MHz using

capacitive neutralization analysis design considerations andimplementationrdquo IEEE Transactions on Circuits and Systems IRegular Papers vol 58 no 4 pp 699ndash710 2011

[52] A Demosthenous I Pachnis D Jiang and N Donaldson ldquoAnintegrated amplifier with passive neutralization of myoelectricinterference from neural recording tripolesrdquo IEEE SensorsJournal vol 13 no 9 pp 3236ndash3248 2013

[53] A Rodrıguez-Perez M Delgado-Restituto and F Medeiro ldquoA515 nW 0ndash18 dB programmable gain analog-to-digital converterfor in-channel neural recording interfacesrdquo IEEE Transactionson Biomedical Circuits and Systems 2013

[54] YMing D A Borton J AcerosW R Patterson and A V Nur-mikko ldquoA 100-channel hermetically sealed implantable devicefor chronic wireless neurosensing applicationsrdquo IEEE Trans-actions on Biomedical Circuits and Systems vol 7 no 2 pp 115ndash128 2013

[55] M S Chae Z Yang M R Yuce L Hoang and W Liu ldquoA 128-channel 6 mW wireless neural recording IC with spike featureextraction and UWB transmitterrdquo IEEE Transactions on NeuralSystems and Rehabilitation Engineering vol 17 no 4 pp 312ndash321 2009

[56] H Gao R M Walker P Nuyujukian et al ldquoHermesE a 96-channel full data rate direct neural interface in 013120583mCMOSrdquoIEEE Journal of Solid-State Circuits vol 47 no 4 pp 1043ndash10552012

[57] S Gibson J W Judy and D Markovic ldquoSpike sorting the firststep in decoding the brain the first step in decoding the brainrdquoIEEE Signal ProcessingMagazine vol 29 no 1 pp 124ndash143 2012

[58] R R Harrison R J Kier C A Chestek et al ldquoWireless neu-ral recording with single low-power integrated circuitrdquo IEEETransactions on Neural Systems and Rehabilitation Engineeringvol 17 no 4 pp 322ndash329 2009

[59] AM Sodagar G E Perlin Y Yao KNajafi andKDWise ldquoAnimplantable 64-channel wireless microsystem for single-unitneural recordingrdquo IEEE Journal of Solid-State Circuits vol 44no 9 pp 2591ndash2604 2009

[60] SGibson JW Judy andDMarkovic ldquoTechnology-aware algo-rithm design for neural spike detection feature extraction anddimensionality reductionrdquo IEEETransactions onNeural Systemsand Rehabilitation Engineering vol 18 no 5 pp 469ndash4782010

[61] V Karkare S Gibson and DMarkovic ldquoA 130-120583W 64-channelneural spike-sorting DSP chiprdquo IEEE Journal of Solid-StateCircuits vol 46 no 5 pp 1214ndash1222 2011

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[64] D L Donoho ldquoCompressed sensingrdquo IEEE Transactions onInformation Theory vol 52 no 4 pp 1289ndash1306 2006

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[66] Y Suo J Zhang R Etienne-Cummings T D Tran and SChin ldquoEnergy-efficient two-stage compressed sensing methodfor implantable neural recordingsrdquo in Proceedings of the IEEEBiomedical Circuits and Systems Conference (BiOCAS rsquo13) pp150ndash153 RotterdamTheNetherlandsOctober-November 2013

[67] A Rodrıguez-Perez J Masuch J A Rodrıguez-Rodrıguez MDelgado-Restituto and A Rodrıguez-Vazquez ldquoA 64-channelinductively-powered neural recording sensor arrayrdquo in Proceed-ings of the IEEE Biomedical Circuits and Systems Conference(BiOCAS rsquo12) pp 228ndash231 Hsinchu Taiwan November 2012

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[69] X Liu A Demosthenous and N Donaldson ldquoAn inte-grated implantable stimulator that is fail-safe without off-chipblocking-capacitorsrdquo IEEE Transactions on Biomedical Circuitsand Systems vol 2 no 3 pp 231ndash244 2008

[70] P J Langlois A Demosthenous I Pachnis and N DonaldsonldquoHigh-power integrated stimulator output stages with floatingdischarge over a wide voltage range for nerve stimulationrdquo IEEETransactions on Biomedical Circuits and Systems vol 4 no 1 pp39ndash48 2010

[71] D Jiang A Demosthenous T Perkins X Liu and N Don-aldson ldquoA stimulator ASIC featuring versatile management forvestibular prosthesesrdquo IEEE Transactions on Biomedical Circuitsand Systems vol 5 no 2 pp 147ndash159 2011

[72] X Liu A Demosthenous and N Donaldson ldquoAn integratedstimulator with DC-isolation and fine current control forimplanted nerve tripolesrdquo IEEE Journal of Solid-State Circuitsvol 46 no 7 pp 1701ndash1714 2011

[73] X Liu A Demosthenous A Vanhoestenberghe D Jiang andN Donaldson ldquoActive Books the design of an implantablestimulator that minimizes cable count using integrated circuitsvery close to electrodesrdquo IEEE Transactions on BiomedicalCircuits and Systems vol 6 no 3 pp 216ndash227 2012

[74] S K Kelly and J L Wyatt Jr ldquoA power-efficient voltage-basedneural tissue stimulator with energy recoveryrdquo in Proceedingsof the IEEE Solid-State Circuits Conference (ISSCC rsquo04) SanFrancisco Calif USA February 2004

[75] S K Kelly and J L Wyatt Jr ldquoA power-efficient neural tissuestimulator with energy recoveryrdquo IEEE Transactions on Bio-medical Circuits and Systems vol 5 no 1 pp 20ndash29 2011

[76] X Liu A Demosthenous and N Donaldson ldquoImplantablestimulator failures causes outcomes and solutionsrdquo inProceed-ings of the 29th Annual International Conference of the IEEEEngineering in Medicine and Biology Society (EMBC rsquo07) pp5786ndash5789 Lyon France August 2007

[77] A Nonclercq L Lonys A Vanhoestenberghe A Demos-thenous and N Donaldson ldquoSafety of multi-channel stimu-lation implants a single blocking capacitor per channel is notsufficient after single-fault failurerdquo Medical amp Biological Engi-neering amp Computing vol 50 no 4 pp 403ndash410 2012

[78] J-J Sit and R Sarpeshkar ldquoA low-power blocking-capacitor-free charge-balanced electrode-stimulator chip with lesst than6 nA DC error for 1-mA full-scale stimulationrdquo IEEE Transac-tions on Biomedical Circuits and Systems vol 1 no 3 pp 172ndash183 2007

[79] M Ortmanns A Rocke M Gehrke and H-J Tiedtke ldquoA 232-channel epiretinal stimulator ASICrdquo IEEE Journal of Solid-StateCircuits vol 42 no 12 pp 2946ndash2959 2007

[80] I Williams and T G Constandinou ldquoAn energy-efficientdynamic voltage scaling neural stimulator for a proprioceptiveprosthesisrdquo IEEE Transactions on Biomedical Circuits and Sys-tems vol 7 no 2 pp 129ndash139 2013

[81] S K Arfin and R Sarpeshkar ldquoAn energy-efficient adia-batic electrode stimulator with inductive energy recycling andfeedback current regulationrdquo IEEE Transactions on BiomedicalCircuits and Systems vol 6 no 1 pp 1ndash14 2012

[82] U Cilingiroglu and S Ipek ldquoA zero-voltage switching techniquefor minimizing the current-source power of implanted stimula-torsrdquo IEEE Transactions on Biomedical Circuits and Systems vol7 no 4 pp 469ndash479 2013

[83] D Jiang A Demosthenous T Perkins D Cirmirakis X Liuand N Donaldson ldquoAn implantable 3-D vestibular stimulatorwith neural recordingrdquo in Proceedings of the 38th EuropeanSolid-State Circuits Conference (ESSCIRC rsquo12) pp 277ndash280Bordeaux France September 2012

[84] P Bradley ldquoWireless medical implant technologymdashrecentadvances and future developmentsrdquo in Proceedings of the 37thEuropean Solid-State Circuits Conference (ESSCIRC rsquo11) pp 54ndash58 Helsinki Finland September 2011

[85] H Yu C-M Tang and R Bashirullah ldquoAn asymmetric RFtagging IC for ingestible medication compliance capsulesrdquo inProceedings of the IEEE Radio Frequency Integrated CircuitsSymposium (RFIC rsquo09) pp 101ndash104 Boston Mass USA June2009

[86] D Cirmirakis D Jiang A Demosthenous N Donaldson andT Perkins ldquoA telemetry operated vestibular prosthesisrdquo in Pro-ceedings of the 19th International Conference on ElectronicsCircuits and Systems (ICECS rsquo12) pp 576ndash578 Seville SpainDecember 2012

[87] M Sawan Y Hu and J Coulombe ldquoWireless smart implantsdedicated to multichannel monitoring and microstimulationrdquoIEEE Circuits and Systems Magazine vol 5 no 1 pp 21ndash392005

[88] MAHannan SMAbbas S A Samad andAHussain ldquoMod-ulation techniques for biomedical implanted devices and theirchallengesrdquo Sensors vol 12 no 1 pp 297ndash319 2012

[89] K M Silay C Dehollain and M Declercq ldquoInductive powerlink for a wireless cortical implant with biocompatible pack-agingrdquo in Proceedings of the 9th IEEE Sensors Conference(SENSORS rsquo10) pp 94ndash98 Kona Hawaii USA November 2010

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[93] N Donaldson and T A Perkins ldquoAnalysis of resonant coupledcoils in the design of radio frequency transcutaneous linksrdquoMedical amp Biological EngineeringampComputing vol 21 no 5 pp612ndash627 1983

[94] D Cirmirakis Novel telemetry system for closed loop vestibularprosthesis [PhD thesis] University College London LondonUK 2013

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insensitive gainrdquo IEEE Transactions on Biomedical Engineeringvol 34 no 4 pp 265ndash275 1987

[96] G Wang W Liu M Sivaprakasam and G A Kendir ldquoDesignand analysis of an adaptive transcutaneous power telemetryfor biomedical implantsrdquo IEEE Transactions on Circuits andSystems I Regular Papers vol 52 no 10 pp 2109ndash2117 2005

[97] P Si A P Hu S Malpas and D Budgett ldquoA frequency controlmethod for regulating wireless power to implantable devicesrdquoIEEETransactions on Biomedical Circuits and Systems vol 2 no1 pp 22ndash29 2008

[98] G Simard M Sawan and D Massicotte ldquoHigh-speed OQPSKand efficient power transfer through inductive link for biomed-ical implantsrdquo IEEE Transactions on Biomedical Circuits andSystems vol 4 no 3 pp 192ndash200 2010

[99] N Donaldson ldquoPassive signalling via inductive couplingrdquoMedicalampBiological EngineeringampComputing vol 24 no 2 pp223ndash224 1986

[100] Z Tang B Smith J H Schild and P H Peckham ldquoData trans-mission from an implantable biotelemeter by load-shift keyingusing circuit configuration modulatorrdquo IEEE Transactions onBiomedical Engineering vol 42 no 5 pp 524ndash528 1995

[101] W Xu Z Luo and S Sonkusale ldquoFully digital BPSK demodula-tor and multilevel LSK back telemetry for biomedical implanttransceiversrdquo IEEE Transactions on Circuits and Systems IIExpress Briefs vol 56 no 9 pp 714ndash718 2009

[102] L Zhou and N Donaldson ldquoA fast passive data transmissionmethod for ENG telemetryrdquo Neuromodulation vol 6 no 2 pp116ndash121 2003

[103] D Cirmirakis D Jiang A Demosthenous N Donaldson andT Perkins ldquoA fast passive phase shift modulator for inductivelycoupled implanted medical devicesrdquo in Proceedings of the 38thEuropean Solid-State Circuits Conference (ESSCIRC rsquo12) pp 301ndash304 Bordeaux France September 2012

[104] M Kiani andM Ghovanloo ldquoA 20-Mbs pulse harmonic mod-ulation transceiver for wideband near-field data transmissionrdquoIEEE Transactions on Circuits and Systems II Express Briefs vol60 no 7 pp 382ndash386 2013

[105] M Ghovanloo and K Najafi ldquoA wideband frequency-shift key-ing wireless link for inductively powered biomedical implantsrdquoIEEE Transactions on Circuits and Systems I Regular Papers vol51 no 12 pp 2374ndash2383 2004

[106] Z Luo and S Sonkusale ldquoA novel BPSK demodulator forbiological implantsrdquo IEEE Transactions on Circuits and SystemsI Regular Papers vol 55 no 6 pp 1478ndash1484 2008

[107] P P Mercier A C Lysaght S Bandyopadhyay A P Chan-drakasan and K M Stankovic ldquoEnergy extraction from thebiologic battery in the inner earrdquo Nature Biotechnology vol 30no 12 pp 1240ndash1243 2012

[108] N Saeidi M Schuettler A Demosthenous and N DonaldsonldquoTechnology for integrated circuit micropackages for neu-ral interfaces based on gold-silicon wafer bondingrdquo Journalof Micromechanics and Microengineering vol 23 Article ID075021 12 pages 2013

[109] P Mohseni and K Najafi ldquoA fully integrated neural recordingamplifier with DC input stabilizationrdquo IEEE Transactions onBiomedical Engineering vol 51 no 5 pp 832ndash837 2004

[110] W S Liew X D Zou L B Yao and Y Lian ldquoA 1-V 60120583W16-channel interface chip for implantable neural recordingrdquo inProceedings of the 31st IEEE Custom Integrated Circuits Confer-ence (CICC rsquo09) pp 507ndash510 San Jose Calif USA September2009

[111] S Rai J Holleman J N Pandey F Zhang and B Otis ldquoA500120583Wneural tag with 2120583Vrms AFE and frequency-multiplyingMICSISM FSK transmitterrdquo in Proceedings of the IEEE Inter-national Solid-State Circuits Conference (ISSCC rsquo09) vol 1 pp212ndash213 San Francisco Calif USA February 2009

[112] F Shahrokhi K Abdelhalim D Serletis P L Carlen and RGenov ldquoThe 128-channel fully differential digital integratedneural recording and stimulation interfacerdquo IEEE Transactionson Biomedical Circuits and Systems vol 4 no 3 pp 149ndash1612010

[113] R R Harrison P T Watkins R J Kier et al ldquoA low-powerintegrated circuit for a wireless 100-electrode neural recordingsystemrdquo IEEE Journal of Solid-State Circuits vol 42 no 1 pp123ndash133 2007

[114] A Bonfanti M Ceravolo G Zambra et al ldquoA multi-channellow-power IC for neural spike recording with data compressionand narrowband 400-MHz MC-FSK wireless transmissionrdquo inProceedings of the 36th European Solid-State Circuits Conference(ESSCIRC rsquo10) pp 330ndash333 Seville Spain September 2010

[115] S B Lee H-M Lee M Kiani U-M Jow and M GhovanlooldquoAn inductively powered scalable 32-channel wireless neu-ral recording system-on-a-chip for neuroscience applicationsrdquoIEEETransactions on Biomedical Circuits and Systems vol 4 no6 pp 360ndash371 2010

[116] K Abdelhalim L Kokarovtseva J L P Velazquez and RGenov ldquo915-MHz FSKOOK wireless neural recording SoCwith 64 mixed-signal FIR filtersrdquo IEEE Journal of Solid-StateCircuits vol 48 no 10 pp 2478ndash2493 2013

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014


Active and Passive Electronic Components

Control Scienceand Engineering

Journal of



RotatingMachinery


Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics


Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks



applied via deep brain electrodes to the targeted tissue area inthe brain (Figure 1) The characteristics of these pulses (egfrequency pulse duration and intensity) are programmedinto the stimulator (implanted in the chest area) and adjustedvia an external programmer DBS emerged from heart pace-maker technology and hence is also called a brain pacemakerCurrent developments are focused on the design of cranial-mounted inductively-poweredDBS systems [10] to reduce thelength of the leads from the stimulator to the electrodes andnovel stimulation techniques using high-density segmentedelectrodes which can enable current-steering and electricfield shaping capability [11 12] In addition recent papershave reported the development of prototype closed-loop (iesense and stimulate) neuroprosthetic devices for applicationssuch as vestibular prosthesis [13] and epilepsy [14 15] In thecase of epilepsy the device uses implantable multielectrodearrays and amplifiers to record electrical signals fromneuronsin the brain The recorded data is then processed to extractimportant events which for example predict the onset ofan epileptic seizure and electrical stimulation is applied toinhibit the attack

This paper provides a review of advances in microelec-tronics for implantable medical devices and systems Thefocus is limited to neural recording and stimulation circuitssuitable for fabrication in modern silicon process technolo-gies and biotelemetry methods for power and data transferAfter this introductory part Section 2 reviews several tech-niques and circuit topologies for neural recording includingmethods for on-chip data reduction to reduce the bandwidthrequirements of the wireless transmission link Section 3covers advances in neural stimulation circuits and Section 4discusses biotelemetrymethods includingwireless power anddata transmission by inductive coupling Finally conclusionsare drawn in Section 5 including some suggestions for futureresearch

2 Neural Amplifiers

Neural signals are low frequency and low amplitude sig-nals For example the amplitude of the electroneurogram(ENG) recorded with implanted cuff electrodes [16 17] istypically in the region of 1120583V with most energy concen-trated between 300Hz and 5 kHz Even when recordingneural activity with penetrating microelectrodes such as theUtah Electrode Array [18 19] or the NeuroNexus penetrat-ing probes (httpwwwneuronexustechcom) the recordedneural action potentials often have amplitudes of only a fewtens of microvolts Hence circuits for neural signal amplifi-cationmust have low noise performance and additionally lowpower consumption so that battery life is prolonged espe-cially in implantable systems (eg implantable loop recorderfor long-term monitoring of the heartrsquos electrical activity[20]) In addition front-end neural amplifiers are required toreject electrode offsets or common-mode interference Bothclock-based and continuous-time techniques have been usedin the design of neural amplifiers

21 Clock-Based Techniques The noise in CMOS transistorsis usually dominated by flicker (1119891) noise up to relatively

Pulse generator

DBS electrode

Figure 1 A DBS implant typically consists of an implantedpulse generator which generates electrical pulses for stimulationa set of connection cables and an electrode rod which deliversthe stimulation pulses to the brain target area Image sourcehttpcdnphysorgcom

Ids + Inoise

m(t)

m(t)

Ibias

Iout + Inoise

VDD

V+in Vminus

in

Figure 2 Cycling ofMOS gate bias (left) and application to anOTA

high frequencies of the order of several tens of kHz [21] Thisis particularly troublesome for the design of low frequencylow noise analog circuits Typically p-channel transistorshave less 1119891 noise than n-channel transistors Various clock-based techniques have been developed to reduce the effectsof 1119891 noise Noise reduction based on physical effects(switched biasing) chopper modulation and autozeroing areamongst these techniques

The switched biasing technique (Figure 2) reduces the1119891 noise of a MOS transistor by cyclically increasing anddecreasing its gate bias so that the device alternates betweenstrong inversion and accumulation [22] The transistor noiseismodulated by the switching signalThe switching operationis represented as a multiplication of the 1119891 noise current


BPF LPFAmpVin

m(t)

Vout



119898(119905) =

1

2

+

2

120587

sin (2120587119891119904119905) +

2

3120587

sin (6120587119891119904119905)

+

2

5120587


(1)





119904that is


OTA

Chopper

m(t) m(t)

m(t)

Vout

+

minus

+

minusIA

R1

R2

Vel offset



1 By action







Vout

++

minus

minusVinΣ

1206011

1206012

1206011

1206012

1206011 sample1206012 hold

SampH








1








by 119872119886and 119872






OTA

MOS pseudoresistor

Vout

+

minusVin

Vref

C2

C2

C1

C1

Ma Mb

CL

Md

Mc





1and 119862



1 The improvement




120587 sdot 119880119879sdot 4119896119879 sdot BW

(2)


MOS pseudoresistor

Vout+

minusVin

Vref

C2

C2C2

C2

C1

C1

Ma Mb

CL

MdMc

VSS

VSS

VDD

VDDD2

D4D3

D1

N times C2

OTA



119879is the




1)





119887 The midband




MOSpseudoresistor

Vout+

+

minus

minus

Vin

Vref

C1

Ma

Mb

CL

OTA1

OTA2


BPF

Vout

+

minusVin

Vref

Vref

C2

C1

VSS

VDD

M1 M2M3 M4 M5

M6

M7

M8

M9R1

R2

Q1 Q2

Q3

Q4

(12)Ib1 Ib1

Ib2

Ib3




1 1198762 1198721


1 followed by a




1198726and 119872




1198728and 119872




(1198723ndash1198725and 119876


1



1and 119876

2is



Vout

+

minusVin

Vref

C2

VSS

VDD

M3 M4M5 M6

R1 R2

I1 I2 I3 I4

A B

Mi1Mi2 Mo1

Mo2




1198941and119872

1198942



1and hence 119872

1198941and 119872



1199001

and 1198721199002





2in




Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filterPGA

Mul

tiple

xer

ADC

Dig

ital

proc

essin

g

(a)

Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filter PGA

ADC Dig

ital

proc

essin

g

(b)






Table1Com

paris

onof

integrated

neuralam

plifiers

Parameter

[34]

[109]

[45]

[110]

[111]

[112]

[29]

[42]

[35]

[37]

[44]

[40]

[39]

[46]

[36]

Year

2003

2004

2007

2009

2009

2010

2010

2011

2012

2012

2013

2013

2013

2013

2013

Fully

differential

No

No

No

No

Yes

Yes

Yes

No

Yes

Yes

No

No

No

No

Yes


05

15018

035

013

035

018

018

013

013

035

018

018

018

018

Area(

mm

2 )016

0107

005

NA

NA

002

NA

0063

0054

0072

0065

0065

NA

076

016

Supp

lyvoltage

(V)

53

181

13

1618

121

318

118

112

Supp

lycurrent(120583A)

163827

467

126

125

28

4312

44

16121

261

1213

036

Gain(dB)

395

393

4952

457

383

33191375

394

475

40375

4860

548609

445559

26Ba

ndwidth

(Hz)

25mndash72k

0ndash91


23mndash115

k10ndash5

k100ndash

8k10ndash72k

167ndash69k

50mndash105k

1ndash10k

03ndash9k

038ndash51k

1ndash10k

80ndash15k

Inpu

t-referredno

ise(120583V

rms)

22

7856

443

195

608

236

35

38

22

106

54

44lowast

81

Noise

band

width

(Hz)

NA

01ndash10k

1ndash91

k1ndash12k

01ndash256k

10ndash5

k1ndash8k

10ndash100

k1ndash100k

01ndash105k

1ndash10k

1ndash8k

1ndash8k

03ndash10k

NA

CMRR

(dB)

ge83

NA

5268

58gt63

6079

701

8380

7448

gt60

NA

gt60

PSRR

(dB)

ge85

NA

5193

40gt63

NA

62638

70ge80

5555

gt70

NA

gt80

THD

Inpu

trange

(mV

pp)

1 167

11 5

1 24

053

52

1 1NA

NA

1 57

1 31

1 11 24

12 11 163

103

lowastlowast

005

10NEF

4194

49

216

248

555

668

335

216

29

578

46

19545

152

NEF2

timesV

DD

801129

4322

453

615

9241

7139

2020

559

841

10022

3808

361

297

277

lowast

Referred

totheinp

utno

deof

thee

lectrode

lowastlowast

Thea

mplitu

derangeo

fthe

inpu

tcurrent

is20

nApp











Table2Com

paris

onof

wire

lessmultichann


ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










BPF LPFAmpVin

m(t)

Vout



119898(119905) =

1

2

+

2

120587

sin (2120587119891119904119905) +

2

3120587

sin (6120587119891119904119905)

+

2

5120587


(1)





119904that is


OTA

Chopper

m(t) m(t)

m(t)

Vout

+

minus

+

minusIA

R1

R2

Vel offset



1 By action







Vout

++

minus

minusVinΣ

1206011

1206012

1206011

1206012

1206011 sample1206012 hold

SampH








1








by 119872119886and 119872






OTA

MOS pseudoresistor

Vout

+

minusVin

Vref

C2

C2

C1

C1

Ma Mb

CL

Md

Mc





1and 119862



1 The improvement




120587 sdot 119880119879sdot 4119896119879 sdot BW

(2)


MOS pseudoresistor

Vout+

minusVin

Vref

C2

C2C2

C2

C1

C1

Ma Mb

CL

MdMc

VSS

VSS

VDD

VDDD2

D4D3

D1

N times C2

OTA



119879is the




1)





119887 The midband




MOSpseudoresistor

Vout+

+

minus

minus

Vin

Vref

C1

Ma

Mb

CL

OTA1

OTA2


BPF

Vout

+

minusVin

Vref

Vref

C2

C1

VSS

VDD

M1 M2M3 M4 M5

M6

M7

M8

M9R1

R2

Q1 Q2

Q3

Q4

(12)Ib1 Ib1

Ib2

Ib3




1 1198762 1198721


1 followed by a




1198726and 119872




1198728and 119872




(1198723ndash1198725and 119876


1



1and 119876

2is



Vout

+

minusVin

Vref

C2

VSS

VDD

M3 M4M5 M6

R1 R2

I1 I2 I3 I4

A B

Mi1Mi2 Mo1

Mo2




1198941and119872

1198942



1and hence 119872

1198941and 119872



1199001

and 1198721199002





2in




Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filterPGA

Mul

tiple

xer

ADC

Dig

ital

proc

essin

g

(a)

Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filter PGA

ADC Dig

ital

proc

essin

g

(b)






Table1Com

paris

onof

integrated

neuralam

plifiers

Parameter

[34]

[109]

[45]

[110]

[111]

[112]

[29]

[42]

[35]

[37]

[44]

[40]

[39]

[46]

[36]

Year

2003

2004

2007

2009

2009

2010

2010

2011

2012

2012

2013

2013

2013

2013

2013

Fully

differential

No

No

No

No

Yes

Yes

Yes

No

Yes

Yes

No

No

No

No

Yes


05

15018

035

013

035

018

018

013

013

035

018

018

018

018

Area(

mm

2 )016

0107

005

NA

NA

002

NA

0063

0054

0072

0065

0065

NA

076

016

Supp

lyvoltage

(V)

53

181

13

1618

121

318

118

112

Supp

lycurrent(120583A)

163827

467

126

125

28

4312

44

16121

261

1213

036

Gain(dB)

395

393

4952

457

383

33191375

394

475

40375

4860

548609

445559

26Ba

ndwidth

(Hz)

25mndash72k

0ndash91


23mndash115

k10ndash5

k100ndash

8k10ndash72k

167ndash69k

50mndash105k

1ndash10k

03ndash9k

038ndash51k

1ndash10k

80ndash15k

Inpu

t-referredno

ise(120583V

rms)

22

7856

443

195

608

236

35

38

22

106

54

44lowast

81

Noise

band

width

(Hz)

NA

01ndash10k

1ndash91

k1ndash12k

01ndash256k

10ndash5

k1ndash8k

10ndash100

k1ndash100k

01ndash105k

1ndash10k

1ndash8k

1ndash8k

03ndash10k

NA

CMRR

(dB)

ge83

NA

5268

58gt63

6079

701

8380

7448

gt60

NA

gt60

PSRR

(dB)

ge85

NA

5193

40gt63

NA

62638

70ge80

5555

gt70

NA

gt80

THD

Inpu

trange

(mV

pp)

1 167

11 5

1 24

053

52

1 1NA

NA

1 57

1 31

1 11 24

12 11 163

103

lowastlowast

005

10NEF

4194

49

216

248

555

668

335

216

29

578

46

19545

152

NEF2

timesV

DD

801129

4322

453

615

9241

7139

2020

559

841

10022

3808

361

297

277

lowast

Referred

totheinp

utno

deof

thee

lectrode

lowastlowast

Thea

mplitu

derangeo

fthe

inpu

tcurrent

is20

nApp











Table2Com

paris

onof

wire

lessmultichann


ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Vout

++

minus

minusVinΣ

1206011

1206012

1206011

1206012

1206011 sample1206012 hold

SampH








1








by 119872119886and 119872






OTA

MOS pseudoresistor

Vout

+

minusVin

Vref

C2

C2

C1

C1

Ma Mb

CL

Md

Mc





1and 119862



1 The improvement




120587 sdot 119880119879sdot 4119896119879 sdot BW

(2)


MOS pseudoresistor

Vout+

minusVin

Vref

C2

C2C2

C2

C1

C1

Ma Mb

CL

MdMc

VSS

VSS

VDD

VDDD2

D4D3

D1

N times C2

OTA



119879is the




1)





119887 The midband




MOSpseudoresistor

Vout+

+

minus

minus

Vin

Vref

C1

Ma

Mb

CL

OTA1

OTA2


BPF

Vout

+

minusVin

Vref

Vref

C2

C1

VSS

VDD

M1 M2M3 M4 M5

M6

M7

M8

M9R1

R2

Q1 Q2

Q3

Q4

(12)Ib1 Ib1

Ib2

Ib3




1 1198762 1198721


1 followed by a




1198726and 119872




1198728and 119872




(1198723ndash1198725and 119876


1



1and 119876

2is



Vout

+

minusVin

Vref

C2

VSS

VDD

M3 M4M5 M6

R1 R2

I1 I2 I3 I4

A B

Mi1Mi2 Mo1

Mo2




1198941and119872

1198942



1and hence 119872

1198941and 119872



1199001

and 1198721199002





2in




Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filterPGA

Mul

tiple

xer

ADC

Dig

ital

proc

essin

g

(a)

Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filter PGA

ADC Dig

ital

proc

essin

g

(b)






Table1Com

paris

onof

integrated

neuralam

plifiers

Parameter

[34]

[109]

[45]

[110]

[111]

[112]

[29]

[42]

[35]

[37]

[44]

[40]

[39]

[46]

[36]

Year

2003

2004

2007

2009

2009

2010

2010

2011

2012

2012

2013

2013

2013

2013

2013

Fully

differential

No

No

No

No

Yes

Yes

Yes

No

Yes

Yes

No

No

No

No

Yes


05

15018

035

013

035

018

018

013

013

035

018

018

018

018

Area(

mm

2 )016

0107

005

NA

NA

002

NA

0063

0054

0072

0065

0065

NA

076

016

Supp

lyvoltage

(V)

53

181

13

1618

121

318

118

112

Supp

lycurrent(120583A)

163827

467

126

125

28

4312

44

16121

261

1213

036

Gain(dB)

395

393

4952

457

383

33191375

394

475

40375

4860

548609

445559

26Ba

ndwidth

(Hz)

25mndash72k

0ndash91


23mndash115

k10ndash5

k100ndash

8k10ndash72k

167ndash69k

50mndash105k

1ndash10k

03ndash9k

038ndash51k

1ndash10k

80ndash15k

Inpu

t-referredno

ise(120583V

rms)

22

7856

443

195

608

236

35

38

22

106

54

44lowast

81

Noise

band

width

(Hz)

NA

01ndash10k

1ndash91

k1ndash12k

01ndash256k

10ndash5

k1ndash8k

10ndash100

k1ndash100k

01ndash105k

1ndash10k

1ndash8k

1ndash8k

03ndash10k

NA

CMRR

(dB)

ge83

NA

5268

58gt63

6079

701

8380

7448

gt60

NA

gt60

PSRR

(dB)

ge85

NA

5193

40gt63

NA

62638

70ge80

5555

gt70

NA

gt80

THD

Inpu

trange

(mV

pp)

1 167

11 5

1 24

053

52

1 1NA

NA

1 57

1 31

1 11 24

12 11 163

103

lowastlowast

005

10NEF

4194

49

216

248

555

668

335

216

29

578

46

19545

152

NEF2

timesV

DD

801129

4322

453

615

9241

7139

2020

559

841

10022

3808

361

297

277

lowast

Referred

totheinp

utno

deof

thee

lectrode

lowastlowast

Thea

mplitu

derangeo

fthe

inpu

tcurrent

is20

nApp











Table2Com

paris

onof

wire

lessmultichann


ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










MOS pseudoresistor

Vout+

minusVin

Vref

C2

C2C2

C2

C1

C1

Ma Mb

CL

MdMc

VSS

VSS

VDD

VDDD2

D4D3

D1

N times C2

OTA



119879is the




1)





119887 The midband




MOSpseudoresistor

Vout+

+

minus

minus

Vin

Vref

C1

Ma

Mb

CL

OTA1

OTA2


BPF

Vout

+

minusVin

Vref

Vref

C2

C1

VSS

VDD

M1 M2M3 M4 M5

M6

M7

M8

M9R1

R2

Q1 Q2

Q3

Q4

(12)Ib1 Ib1

Ib2

Ib3




1 1198762 1198721


1 followed by a




1198726and 119872




1198728and 119872




(1198723ndash1198725and 119876


1



1and 119876

2is



Vout

+

minusVin

Vref

C2

VSS

VDD

M3 M4M5 M6

R1 R2

I1 I2 I3 I4

A B

Mi1Mi2 Mo1

Mo2




1198941and119872

1198942



1and hence 119872

1198941and 119872



1199001

and 1198721199002





2in




Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filterPGA

Mul

tiple

xer

ADC

Dig

ital

proc

essin

g

(a)

Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filter PGA

ADC Dig

ital

proc

essin

g

(b)






Table1Com

paris

onof

integrated

neuralam

plifiers

Parameter

[34]

[109]

[45]

[110]

[111]

[112]

[29]

[42]

[35]

[37]

[44]

[40]

[39]

[46]

[36]

Year

2003

2004

2007

2009

2009

2010

2010

2011

2012

2012

2013

2013

2013

2013

2013

Fully

differential

No

No

No

No

Yes

Yes

Yes

No

Yes

Yes

No

No

No

No

Yes


05

15018

035

013

035

018

018

013

013

035

018

018

018

018

Area(

mm

2 )016

0107

005

NA

NA

002

NA

0063

0054

0072

0065

0065

NA

076

016

Supp

lyvoltage

(V)

53

181

13

1618

121

318

118

112

Supp

lycurrent(120583A)

163827

467

126

125

28

4312

44

16121

261

1213

036

Gain(dB)

395

393

4952

457

383

33191375

394

475

40375

4860

548609

445559

26Ba

ndwidth

(Hz)

25mndash72k

0ndash91


23mndash115

k10ndash5

k100ndash

8k10ndash72k

167ndash69k

50mndash105k

1ndash10k

03ndash9k

038ndash51k

1ndash10k

80ndash15k

Inpu

t-referredno

ise(120583V

rms)

22

7856

443

195

608

236

35

38

22

106

54

44lowast

81

Noise

band

width

(Hz)

NA

01ndash10k

1ndash91

k1ndash12k

01ndash256k

10ndash5

k1ndash8k

10ndash100

k1ndash100k

01ndash105k

1ndash10k

1ndash8k

1ndash8k

03ndash10k

NA

CMRR

(dB)

ge83

NA

5268

58gt63

6079

701

8380

7448

gt60

NA

gt60

PSRR

(dB)

ge85

NA

5193

40gt63

NA

62638

70ge80

5555

gt70

NA

gt80

THD

Inpu

trange

(mV

pp)

1 167

11 5

1 24

053

52

1 1NA

NA

1 57

1 31

1 11 24

12 11 163

103

lowastlowast

005

10NEF

4194

49

216

248

555

668

335

216

29

578

46

19545

152

NEF2

timesV

DD

801129

4322

453

615

9241

7139

2020

559

841

10022

3808

361

297

277

lowast

Referred

totheinp

utno

deof

thee

lectrode

lowastlowast

Thea

mplitu

derangeo

fthe

inpu

tcurrent

is20

nApp











Table2Com

paris

onof

wire

lessmultichann


ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Vout

+

minusVin

Vref

C2

VSS

VDD

M3 M4M5 M6

R1 R2

I1 I2 I3 I4

A B

Mi1Mi2 Mo1

Mo2




1198941and119872

1198942



1and hence 119872

1198941and 119872



1199001

and 1198721199002





2in




Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filterPGA

Mul

tiple

xer

ADC

Dig

ital

proc

essin

g

(a)

Channel nChannel 2

Channel 1

Elec

trode

s

LNA-filter PGA

ADC Dig

ital

proc

essin

g

(b)






Table1Com

paris

onof

integrated

neuralam

plifiers

Parameter

[34]

[109]

[45]

[110]

[111]

[112]

[29]

[42]

[35]

[37]

[44]

[40]

[39]

[46]

[36]

Year

2003

2004

2007

2009

2009

2010

2010

2011

2012

2012

2013

2013

2013

2013

2013

Fully

differential

No

No

No

No

Yes

Yes

Yes

No

Yes

Yes

No

No

No

No

Yes


05

15018

035

013

035

018

018

013

013

035

018

018

018

018

Area(

mm

2 )016

0107

005

NA

NA

002

NA

0063

0054

0072

0065

0065

NA

076

016

Supp

lyvoltage

(V)

53

181

13

1618

121

318

118

112

Supp

lycurrent(120583A)

163827

467

126

125

28

4312

44

16121

261

1213

036

Gain(dB)

395

393

4952

457

383

33191375

394

475

40375

4860

548609

445559

26Ba

ndwidth

(Hz)

25mndash72k

0ndash91


23mndash115

k10ndash5

k100ndash

8k10ndash72k

167ndash69k

50mndash105k

1ndash10k

03ndash9k

038ndash51k

1ndash10k

80ndash15k

Inpu

t-referredno

ise(120583V

rms)

22

7856

443

195

608

236

35

38

22

106

54

44lowast

81

Noise

band

width

(Hz)

NA

01ndash10k

1ndash91

k1ndash12k

01ndash256k

10ndash5

k1ndash8k

10ndash100

k1ndash100k

01ndash105k

1ndash10k

1ndash8k

1ndash8k

03ndash10k

NA

CMRR

(dB)

ge83

NA

5268

58gt63

6079

701

8380

7448

gt60

NA

gt60

PSRR

(dB)

ge85

NA

5193

40gt63

NA

62638

70ge80

5555

gt70

NA

gt80

THD

Inpu

trange

(mV

pp)

1 167

11 5

1 24

053

52

1 1NA

NA

1 57

1 31

1 11 24

12 11 163

103

lowastlowast

005

10NEF

4194

49

216

248

555

668

335

216

29

578

46

19545

152

NEF2

timesV

DD

801129

4322

453

615

9241

7139

2020

559

841

10022

3808

361

297

277

lowast

Referred

totheinp

utno

deof

thee

lectrode

lowastlowast

Thea

mplitu

derangeo

fthe

inpu

tcurrent

is20

nApp











Table2Com

paris

onof

wire

lessmultichann


ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Table1Com

paris

onof

integrated

neuralam

plifiers

Parameter

[34]

[109]

[45]

[110]

[111]

[112]

[29]

[42]

[35]

[37]

[44]

[40]

[39]

[46]

[36]

Year

2003

2004

2007

2009

2009

2010

2010

2011

2012

2012

2013

2013

2013

2013

2013

Fully

differential

No

No

No

No

Yes

Yes

Yes

No

Yes

Yes

No

No

No

No

Yes


05

15018

035

013

035

018

018

013

013

035

018

018

018

018

Area(

mm

2 )016

0107

005

NA

NA

002

NA

0063

0054

0072

0065

0065

NA

076

016

Supp

lyvoltage

(V)

53

181

13

1618

121

318

118

112

Supp

lycurrent(120583A)

163827

467

126

125

28

4312

44

16121

261

1213

036

Gain(dB)

395

393

4952

457

383

33191375

394

475

40375

4860

548609

445559

26Ba

ndwidth

(Hz)

25mndash72k

0ndash91


23mndash115

k10ndash5

k100ndash

8k10ndash72k

167ndash69k

50mndash105k

1ndash10k

03ndash9k

038ndash51k

1ndash10k

80ndash15k

Inpu

t-referredno

ise(120583V

rms)

22

7856

443

195

608

236

35

38

22

106

54

44lowast

81

Noise

band

width

(Hz)

NA

01ndash10k

1ndash91

k1ndash12k

01ndash256k

10ndash5

k1ndash8k

10ndash100

k1ndash100k

01ndash105k

1ndash10k

1ndash8k

1ndash8k

03ndash10k

NA

CMRR

(dB)

ge83

NA

5268

58gt63

6079

701

8380

7448

gt60

NA

gt60

PSRR

(dB)

ge85

NA

5193

40gt63

NA

62638

70ge80

5555

gt70

NA

gt80

THD

Inpu

trange

(mV

pp)

1 167

11 5

1 24

053

52

1 1NA

NA

1 57

1 31

1 11 24

12 11 163

103

lowastlowast

005

10NEF

4194

49

216

248

555

668

335

216

29

578

46

19545

152

NEF2

timesV

DD

801129

4322

453

615

9241

7139

2020

559

841

10022

3808

361

297

277

lowast

Referred

totheinp

utno

deof

thee

lectrode

lowastlowast

Thea

mplitu

derangeo

fthe

inpu

tcurrent

is20

nApp











Table2Com

paris

onof

wire

lessmultichann


ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation



















Table2Com

paris

onof

wire

lessmultichann


ms

Parameter

[113]

[59]

[55]

[114]

[115]

[56]

[67]

[54]

[116]

[15]

Year

2007

2009

2009

2010

2010

2012

2012

2013

2013

2013

Num

bero

fchann

els100

64128

6432

9664

100

6464


05

05

035

035

05

013

013

05

013

013

Area(

mm

2 )2773

NA

6336

837

1627

25184

2548

1212

Supp

lyvoltage

(V)

33

1833

33

1212

312

123

Totalp

ower

(mW)

135

144

6172

585

65

038

6906

503

14Po

wer

perc

hann

el(120583W)

135

225

4687

269

1828

677

593

906

785

218

Amplifier

gain

(dB)

4060

4065ndash83

678ndash78

54475ndash6

55

4654ndash6

054ndash6

0Lo

wfre

quency

corner

(Hz)

300

1001

101

280

200

110

1Highfre

quency

corner

(kHz)

591

2010

810

69

785

5Inpu

t-referredno

ise(120583V

rms)

51

849

305

462

22

38

283

65

51

ADCresolutio

n(bits)

Samplingfre

quency

(kHz)

10 158 625

9 640

72 2081

NA

10 3125

765

2790

12 2078 57

76le100

Dow

nlinkmod

ulation

Carrierfrequ

ency

(MHz)

ASK 264

FSK

48

NA

NA

NA

NA

OOK

4068

NA

OOK

915

NA

Uplinkmod

ulation

Carrierfrequ

ency

(GHz)

FSK

0433

OOK

0070ndash

02

UWB

4FSK

04

FSK

0915

UWB

NA

LSK

000

4FSK

3238

FSK

0915

UWB

0ndash13

1ndash106

Datar

ate(Mbp

s)033

290

125

0709

3019

248

1510

On-chip

signalprocessing

Yes

Yes

Yes

Yes

Yes

No

Yes

No

Yes

Yes

Power

source

Indu

ctive

Indu

ctive

Batte

ryBa

ttery

Indu

ctive

Batte

ryIndu

ctive

Batte

ryBa

ttery

Batte

ryStim

ulationcapability

No

No

No

No

No

No

No

No

No

Yes


VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










VSS

VDD

Isink

Isource

Load current

Tissue

Electrode

(a)

C1 C2 C3 C4 C5

Chargingcircuit

(b)


Amplitude

Time

(a)

Anodicphase

phaseCathodic

(b)

(c)












Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Blockingcapacitor

Load

VSS

VDD

S1

S2 S3

IstimA

IstimC

(a)

VDD

S1 S2 S3

Istim

(b)

VDD

Istim

S1

S1

S2

(c)





1) to gen-








1 1198682 119868

119873act in par-




VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










VSS

VDD

Ssamp

Ssamp

Sanodic

Scathodic

Feedback

SampHVbias

M1

(a)

VSS

VDD

Sanodic

Scathodic

Voltagemonitor

(b)

S1

S1S2

S2

I1 I2 IN

VDD

(c)

Cathodicphase phase

Anodic phase

T

T

Ac

CompensationPassive

discharge phase

(AcN)(MN)

N middot T

(120572N)

120572

(d)







1and





1


1198681198781



2is open and 119863

3 1198622


2to one-diode-



1


1198781and 119868





3and 119862

4 On the following



VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










VDD VDD

S1

S2

S3

(a)

(b)

(c)

(d)

Cblock

A

C

A

C

Φstim left M1M2

M3

C1 C2

M4

IS1 IS2

Φstim right

D1 D2 D3D4

Φdischarge

D5

D6

M5 M6M7

R1C4

C3


Φcathode

D7C5

D8C6

M8

R2

Dischargephase

Dischargephasephase

Stimulation


Φstim left

Φstim right

Φdischarge

Φcathode

Istim Istim





1)

























1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation



















1) from a





1 1198711 1198621) is


0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










0 1 0 0 1 0

0 1 0 0 1 0

VSS

VDD

Downlinkdata in

Uplinkdata out

Vs

Downlinkmodulator

Poweramplifier

Matchingnetwork

PA

Power

ML1 L2

Data

Downlinkdemodulator

Rectifier


Uplink

CR CD

Neuralamplifiers

andstimulators

Implant

Voltageregulator


Vs

R1

C1

L1

M

C2L2 R2 V2










2




2and the load


10038161003816100381610038161003816100381610038161003816

1198812

119881119904

10038161003816100381610038161003816100381610038161003816

=

radic(11987721198771)


11986211198771

11986221198772

(3)


1and secondary



1

Gai

n fa

ctor

kcrit

Coupling (k)



119888119876)



1=

1Ω 1198711= 1 120583H) and (119877

2= 1 kΩ 119871


by 1198621and 119862




1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










1kcrit

Coupling (k)

0

100

50

Effici

ency

(120578)

()


001

0203

04

08

1

12

140

5

10

15


times106


Gai

n fa

ctor

(V2V

s)




Vs

R1

C1

L1

M

C2L2 R2

Data
















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation





















References






























































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation


































































































































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









review article advances in microelectronics for implantable medical...

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