revision: wafer acceptance criteria sq03-0038 20 skyworks

Title: WAFER ACCEPTANCE CRITERIA

Document #: SQ03-0038

Revision: 20

Skyworks Solutions, Inc. Page #: 1 of 41

WHEN PRINTED THIS DOCUMENT IS NOT CONTROLLED. THE USER MUST VERIFY THIS IS THE CORRECT REVISION BEFORE USE.

Skyworks General Information

REVISION HISTORY

Rev Description of Change Author Approval Submit Date

1 Initial Release Carole Rosenberger 7/15/04

2 Modifications to the following: Section 5.3, allowing increased inspections at fabrication Section 5.5.2, tightened foundry outgoing inspection AQL. Also clarification of the following criteria through additional detail or pictures: Sections 4A & 4B, clarifying miss-scribe versus chipouts Section 11, ink dot issues Section 12, incomplete die Section 24, pad contamination Section 30, wafer identification Section 32, edge chips

Carole Rosenberger 1/17/05

3 Modifications to the following:

Section 7, reject crazing.

Section 28, 29, Allow probe damage to only pad seal ring for silicon probed wafers.

Richard Burton 4/20/05

4 Modifications to the following: Section 7, added examples of mechanical damage of GaAs die Section 22, added additional examples of ink residue Section28A, added photo of GaAs die example

Richard Burton 5/22/05

5 Modifications to the following: 1. Updated the AQL table in Sec 5.5.3 2. Added defect code summary in Sec 5.9.1 3. Updated the visual aids with appropriate defect codes in Sec 5.9.2

Arif Zaman 09/27/05

6 Added visual aids for ink contamination: 1. Added ink bridging examples in Sec. 5.9.2.5 2. Added visual aids for improper inking in Sec. 5.9.2.11 3. Added criteria of rejection in Sec 5.9.2.22 4. Added reject criteria in Sec 5.9.2.4B

Arif Zaman 7/25/06



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7 Modifications to the following: 1. Updated acceptance criteria in Sec. 5.9.2.3. for bubbles for all product. 2. Updated and added acceptance criteria in Sec. 5.9.2.4 for chipout and mis-scribe for GaAs wafers, and added visual aids 3. Added visual aids to Sec. 5.9.2.6 for die crack 4. Updated metal void spec in sec 5.9.2.16, and applies applicable for all product 5. Updated mottled plaing defects in Sec. 5.9.2.18 for all products 6. Updated Sec. 5.9.2.21 discolored pad criteria applicable for all products

Arif Zaman 2/13/07

8 Modifications to the following sections: 5.9.2.5, 5.9.2.7, 5.9.2.8, 5.9.2.14, 5.9.2.15, 5.9.2.16 and 5.9.2.20. These sections were modified with new inspection criteria for Woburn GaAs die. Die will be inspected at a minimum sensitivity of 10 microns in the gate area, capacitors, and die perimeter; all other areas of the die are excluded from inspection.

Rich Wynkoop 05/22/07

9 Modifications to the following sections: 1.0, 5.3 and 6.3. These sections were modified to include specific actions to be taken for die crack both for internal and external fabs. Added more die crack sample pictures.

Lawrence Manzano 03/07/2008

10 Add SQ03-0278 under associated documents. Add section 5.5.3.5 and 5.5.3.6. Lawrence Manzano 12/01/2008

11 Add MXVA-0926, MXVA-0390 under associated documents. Add section 5.5.3.5 and 5.5.3.6. Delete sampling plan associated with Skyworks Fab and Skyworks MXL Assembly which is covered by individual site specs.

Lawrence Manzano 01/08/2009

12 Section 3 added Newbury Park documentation NP-W3001, NP-T3001 and NP-W4050 Updated table of content Added visual aid picture to chipouts accept and reject criteria Pg 12 Added visual aid picture to scratch in PBO layer accept and reject criteria Pg28

Ruthie Boyd 4/29/09

13 1) Updated section 3 to include WB-W0226 Silicon Diodes Wafer Acceptance Criteria 2) 5.5.3.7 Added Woburn document for Silicon Diodes Wafer Acceptance Criteria refer to WB-W0226

Ruthie Boyd 6/3/09

14 1) Section 3 Updated to point to Corporate level document SQ03-0314 Silicon Diodes Wafer Acceptance Criteria for Sub-Cons this replaced WB-W0226 Silicon Diodes Wafer Acceptance Criteria

2) 5.5.3.7 Removed Woburn document for Silicon Diodes Wafer Acceptance Criteria refer to WB-W0226 Replaced with SQ03-0314 Silicon Diodes Wafer Acceptance Criteria for Sub-Cons reference

Ruthie Boyd 6/15/09



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15 1. Added link to SQ02-0020 Supplier Quality Manual 2. Section 3 Pg4 added SQ02-0020 Supplier Quality

Manual

Ruthie Boyd 7/8/09

16

1. Added Spanish version 2. Section 3. Was removed reference to MXVA-0926

and changed to MXWI-5U43. 3. In section 11 include ink dot size spec for silicon

wafers no bigger than 15 microns For Silicon Wafers to be processed trough Mexicali Backgrinding and Sawing

Ruthie Boyd

Melissa Antúnez

9/28/2009

17 1. Section 5.8.2 Changed from Wafers mounted on tape must not be stored in a nitrogen atmosphere or exposed to sunlight to "Wafers on tape must not be exposed to light."

2. Were added defect 35)Crackling PBO

Ruthie Boyd

Melissa Antúnez

11/09/09

18 Updates made to the Spanish translation in section 5.9.2 Visual Aids for the following defects within table

a) Defect 5 pg 14 Contamination or Stain b) Defect ,7 Pg 18 Crazing and mechanical damage c) Defect ,8 Pg 19 Delamination / passivation lifting, cracks, holes or peeling d) Defect 16 Pg 24 Metal

e) Defect 20 Pg 27 Scratch (No change made to the English Version)

Ruthie Boyd

Melissa Antúnez

2/2/2010

19 1) English version only correct missing reference in 5.5.3.6 MXWI-5U34

2) Pg 31 Defect 21 updated to include reject pictures of Pad discoloration or Staining in Pad area.

Ruthie Boyd

Melissa Antúnez

3/30/10

20 Pg.40 Defect 36 Acceptance criteria for PBO ghost image added. Ruthie Boyd

Alberto Mendoza

7/23/10

TABLE OF CONTENTS

Section Section Name Page Number (from)

Page Number (to)

1.0 Purpose 3 3

2.0 Scope 3 3

3.0 Internal Applicable / External Reference Documents (Process Inputs)

3 4

4.0 Acronyms / Terminology and Description / Definition 4 4

5.0 Procedure 5 37

6.0 Quality Records (Process Outputs) 37 37



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7.0 Document Responsibilities 37 37

1 Purpose

The purpose of this specification is to define minimum visual inspection criteria for:

• Wafers fabricated internally and externally;

• wafers probed or assembled internally and externally;

• Wafers transferred internally between facilities.

2 Scope

This specification applies to all integrated circuit wafer technologies used by Skyworks.

3 Internal Applicable / External Reference Documents (Process Inputs)

INTERNAL APPLICABLE DOCUMENTS

Document Number Document Title

SQ02-0005 Inspection and Test Procedure

SQ03-0062 ESD Control Policy

SQ03-0278 Wafer Backgrind Requirements for External Suppliers

MXVA-0370 SkyBAW Visual Inspection Criteria

MXWI-5U43 Incoming Inspection for GaAs and Silicon Wafers

NP-W3001 Final Outgoing Wafer Inspection after Scribe and Break

NP-T3001 Final Outgoing Inspection Aid

NP-W4059 Final Process Outgoing Wafer Lot Acceptance

SQ03-0314 Silicon Diode Wafer Acceptance for Sub-Cons

SQ02-0020 Supplier Quality Manual

EXTERNAL REFERENCE DOCUMENTS

Document Number Document Title

ANSI Z1.4 Sampling Procedures and Tables for Inspection by Attributes

MIL-STD-883 Microcircuits Test Method Standard

4 Acronyms/ Terminology and Description / Definition



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Acronyms / Terminology Description / Definition

Active area Any metal feature, diffusion, or polysilicon, such as bond pads, traces, ground ring, power ring, etc.

AQL Acceptable Quality Level per ANSI Z1.5. All affected sites must agree upon AQL levels prior to implementation.

Die on a wafer, die conversion Die on a wafer vary by size. The die conversion rate is the maximum number of die available.

Passivation/scratch coat/glassivation

The top layer of transparent insulating material that covers the active circuit area, including metallization, except bonding pads and beam leads.

Functional circuit elements Diodes, transistors, crossunders, capacitors, and resistors.

Crazing The presence of numerous minute cracks in the referenced material, (e.g., glassivation crazing.)

Active circuit area All areas enclosed by the perimeter of functional circuit elements, operating metallization or any connected combinations thereof excluding beam leads.

Foreign material Any material that is foreign to the microcircuit or package, or any non-foreign material that is displaced from its original or intended position within the microcircuit package.

NCMR Nonconforming Material Report, used for documenting rejected lots.

Substrate The supporting structural material into or upon which or both the passivation, metallization and circuit elements are placed.

5 Procedure

5.1 General information Inspectors shall use proper ESD and cleanroom protocols when handling to prevent damage to the wafers during inspection and handling. Refer to specifications as defined above.

5.2 Sample Size per batch 5.2.1 A batch is defined as that received on one Notice to Ship and may or may not be a

complete wafer lot. A batch may also be a wafer parent lot as received in one shipping cassette.

5.2.2 Wafer lot sampling for outgoing inspection at the fabrication site will not necessarily conform to this plan as inspection is based on single wafer lots.

5.2.3 Additional inspection may be implemented as a secondary inspection, such as that required for containment of a particular failure mode.



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5.2.4 Each batch must be sampled depending on the number of total die included, as described as follows:

Table 1, Sample Sizes, Single Sampling

Number of die in lot Number of wafers to inspect: Total number of die to inspect:

501 to 1200 1 80

1201 to 3200 1 125

3201 to 10000 1 200

10001 to 35000 1 - 2 315

35001 to 150000 2 - 3 500

150001 to 500000 3 - 4 800

5.3 Magnification levels: Acceptance criteria are defined at 50X-70X magnification. Higher magnifications may be used to verify defects. 100X minimum is required for hairline cracks.

5.4 Inspection methods: Methods used to inspect the correct number of die can vary. As long as the correct number of die is inspected, any technique can be used. Once a sampling plan is selected, the inspection must not stray outside of the pre-selected area. For example, if a 5 point, 200 piece sample is chosen, this would imply 5 areas, 40 each (either 2 rows of 20 or 4 rows of 10 die in each area.) If, during the inspection, defects are noted outside of the selected area, they are not to be included in the “AQL” defect count. Specifically, defects extending outside of the area inspection should not be counted. (For example, a scratch that continues beyond the selected sample area.) For details on handling wafers with defects outside of the sample area refer to Section 5.7, Nonconforming Material.

Examples of various techniques are outlined below. These techniques are used for specific area applications as defined in local site work instructions.

5.4.1 X-pattern, or double X technique.

5.4.2 Z or N-pattern technique.

5.4.3 Individual 9-point or area technique.

5.4.4 5-point area technique

5.4.5 21-point area technique

5.5 AQL Details: 5.5.1 Skyworks sampling is based on AQL sampling levels as defined by ANSI, but certain

differences are inherent to wafer level inspection (i.e., non-random sampling :)



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5.5.2 Both the Wafer fabrication and assembly groups must agree to inspection levels used for a specific device. Reduced inspections are permitted for products that meet the performance levels as specified by ANSI.

5.5.3 Inspection is performed to normal criteria as follows:

5.5.3.1 For GaAs wafers, All areas: Level II, Single sampling, AQL = 1.5

Min. Die per Wafer Max. Die per Wafer Sample Size Accept on: Reject On:

501 1200 80 3 4

1201 3200 125 5 6

3201 10000 200 7 8

10001 35000 315 10 11

35001 150000 500 14 15

5.5.3.2 For Silicon wafers, Foundry, Outgoing: Level II, Single sampling AQL=0.4

Min. Die per Wafer Max. Die per Wafer Sample Size Accept on: Reject On:

501 1200 80 0 1

1201 3200 125 1 2

3201 10000 200 2 3

10001 35000 315 3 4

35001 150000 500 5 6

5.5.3.3 For Silicon wafers, Assembly, Incoming: Level I, Double sampling AQL=0.65

Min. Die per

Wafer Max. Die per

Wafer

Sample

Sample Size Accept on: Reject On:

501 1200

First 20 0 2

Second 20 1 2

1201 3200

First 32 0 2

Second 32 1 2

3201 10000

First 50 0 2

Second 50 1 2

10001 35000

First 80 0 3

Second 80 3 4

35001 150000

First 125 1 4

Second 125 4 5



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5.5.3.4 For RF CMOS Silicon Backgrind Wafers from external source, refer to SQ03-0278.

5.5.3.5 For Sky BAW, refer to MXVA-0370.

5.5.3.6 For Mexicali Incoming inspection, refer to MXWI-5U43

5.5.3.7 For Silicon Diode Wafer Acceptance Criteria for Sub-Cons refer to SQ03-0314.

5.6 Rejection Criteria

5.6.1 a lot is rejected only when the total defect count exceeds the AQL criteria table above. Note the total number of defects across all wafers in a sample must be exceeded to fail.

5.6.2 A defect should not be counted in the AQL rejection criteria unless it falls into the category of a rejectable defect as defined in Section 5.9, below. Many anomalies exist on wafers that are cosmetic in nature, and as they do not present a yield or reliability problem they are not rejectable.

5.6.3 Defects are counted as follows: total number of die on a wafer with various defects; it is incorrect to count multiple defects on one die as separate defects.

5.6.4 If the AQL rejection criteria is exceeded, the whole lot fails the AQL. This is not applicable in the case where every wafer in the lot is inspected. In that case, each wafer must follow Table 1 sample size and Table 2 acceptance levels.

5.7 Nonconforming wafers: 5.7.1 Nonconforming material should be reported to the External Foundry Quality or Internal Wafer

Fab Quality, as appropriate, via a Nonconforming Material Report. NCMR’s are issued in QSI, where available.

5.7.2 Nonconforming material shall be reported within 24 hours of discovery of a problem or potential problem.

5.7.3 Disposition will be made by the fabrication site or External Manufacturing with the input of relevant engineering and the end user.

5.7.4 The process for handling wafers with defects is outlined in the flowchart, below:



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5.8 Wafer handling:

5.8.1 Follow all area ESD Safety protocol work instructions when handling wafers, including the use of appropriate grounding equipment and static-safe containers. Additionally, observe all required cleanroom protocols, including handling wafers inside a class 100,000 (ISO 14644 Class 8) cleanroom environment or better.

5.8.2 Wafers on tape must not be exposed to light.

5.8.3 While handling wafers do not touch the surface of the wafer at any time, except with marking pen while inking out a die, if this is necessary.

5.8.4 Fully automated wafer handling systems are to be used (if possible) for loading and unloading wafers at inspection stations.

5.8.5 Vacuum wands should be used in cases where no autoloader is available, and careful attention must be placed to ensure that the wafer is not damaged during removal and replacement into the cassette. Wafers on hoops are handled by the edge of the hoop.





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5.9 GENERAL DIE DEFECTS: 5.9.1 Defect Codes:

Defect Codes Description 8A CHIP OUT 8B BACKSIDE DEFECTS 8C CRACKED DIE 8D OTHER SCRIBE BREAK 8E PROBE DEFECT 8F FAB RELATED DEFECT 8G EQUIP GRINDER 8H POOR INK DOTS 8I INK CONTAMINATION 8J J-HOOK DEFECT 8K MISC DIE DEFECTS 8L PULLED FOR EVAL 8M MECHANICAL DAMAGE 8N SURFACE PARTICLES 8O INCORRECT DATA 8P OPEN/VOID POLY 8Q DELAMINATION 8R RESIDUE ON PADS 8S SCRATCHES 8T MISC DEFECTS 8U UNSEPARATED DIE 8V MIS-ALIGNED VIA 8W CRACKED WAFER 8X EMBEDDED FOREIGN MAT 8Y CONTAMINATION 8Z OTHER FINAL PROCESS



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5.9.1 Visual Aids:

Defect Rejection criteria Description / Graphic

1) Backside ink

Defect Code: 8I

Reject any ink on the back of the substrate. Ink on the tape is acceptable.

Ink residues on the backside of wafer

Action: Ink affected die

2) Bridging

Defect Code: 8F

Visible line of separation between metal pathways must be present. Scratches may result in bridging; see criteria outlined in item 17 below.

Metal bridging, or nearly bridging, two active areas. Generally more than 50% loss of the pathway is deemed unacceptable but may not be verifiable at inspection magnifications.

Action: Ink die exceeding 50% loss

3) Bubbles

Defect Code: 8F

Reject if affects 2 or more active areas

Bubbles in polyimide

Haze, fine particles, or small bubbles in the passivation






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4A) Chipout:

For all GaAs wafers

Defect Code: 8A

Rejectable: Reject if chipout touches any circuit element

Action: Ink affected die with chipouts or mis-scribes into nitride passivation. Use die with passivation visible.





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4A) Chipout:

For all GaAs wafers

Defect Code: 8A

Acceptable: Accept if chipout does not touch any circuit element

Action: Ink affected die with chipouts or mis-scribes into nitride passivation. Use die with passivation visible.

Reject: since the corner crack touches the circuit element (bond pad)

Accept: since the corner chip out doesn’t touch the circuit element (bond pad)



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4B) Mis-scribed die:

Defect Code: 8D

The criteria for mis-scribed die are similar to chipouts. Reject these if they contact an active area or if no nitride is visible next to the active area, or if active area from an adjacent chip is attached. The following mis-scribe is rejectable:

The following both dies are rejectable because the active circuit area of the adjacent die is attached

The following are acceptable dice because nitride is still visible on the right, and there is no circuit form the adjacent chip attached on the left:



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5) Contamination or Stain

Defect Code: 8Y

For Woburn GaAs die only: Reject if contamination or stain exceeds 10 microns (in length or width) on gate or capacitor areas, or exceeds 30 microns (in length or width) on a bond pad. All other areas of the die are excluded from inspection.

For all other die: Reject any that appears to bridge two active areas

Foreign material embedded in critical areas. Reject if contamination is greater than 20% of the die surface (GaAs) or 10% (Silicon)

Foreign materialcovering more than 20% of the bond pad

Reject if the contamination is breaking the passivation surface (under the passivation) and is near any metal lines.

Any particulate or liquid foreign material (including ink) that is not part of the die by design. This defect typically exhibits a distinct edge and may have height.

Particulate bridging:

Particulate contamination in the form of small specs which is less than 20% of the die surface is considered acceptable.

No attempts to remove contamination outside of regular fabrication processes (wafer scrubbers or ashing) should be made.



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6) Crack

Defect Code: 8C

Star Crack – Reject

The presence of minute cracks or any damage to the surface of the passivation (typically due to mechanical damage) is rejectable.


Straight and Edge Cracks (After die singulation):

Action: When required by Skyworks’s Quality or Engineering; apply pressure to the front side of the cracked die using the Ultra Fine Sharpie marker. If the die cracks, apply pressure to the next die in the direction of the crack. Repeat until applying pressure does not crack the die. Ink 5 dies past the last cracked die. Continue to inspect the whole row at 100X to verify no additional cracking.

Straight and Edge Cracks (Whole wafers):

Action: Do not apply pressure. Ink the full row. If the crack is along the scribe line, ink the row of die on each side of the crack. If the wafer breaks into 2 pieces, ink the row of die along the crack on each half of the wafer.

Scribe and Break Cracks:

Actions: Same as Straight and Edge Cracks (after die singulation)

Star Cracks:

Actions: Ink 5 die away from the star crack in all directions.

Crack - Reject



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6) Crack

Defect Code: 8C

Cracks - Reject

Scribe & Break Cracks - Reject

50X magnification

100X

200X




Action: When required by Skyworks’s Quality or Engineering; apply pressure to the front side of the cracked die using the Ultra Fine Sharpie marker. If the die cracks, apply pressure to the next die in the direction of the crack. Repeat until applying pressure does not crack the die. Ink 5 die past the last cracked die. Continue to inspect the whole row at 100X to verify no additional cracking.





Star Cracks:




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6) Crack

Defect Code: 8C

Hairline Crack – Reject

200X

1000X




Action: When required by Skyworks’s Quality or Engineering; apply pressure to the front side of the cracked die using the Ultra Fine Sharpie marker. If the die cracks, apply pressure to the next die in the direction of the crack. Repeat until applying pressure does not crack the die. Ink 5 die past the last cracked die. Continue to inspect the whole row at 100X to verify no additional cracking.





Star Cracks:




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WHEN PRINTED THIS DOCUMENT IS NOT THIS IS THE CORRECT REVISION BEFORE

CONTROLLED. THE USER MUST VERIFY USE.



7) Crazing and

Mechanical damage

Defect Code: 8M

For Woburn GaAs die only: Reject if mechanical damage exceeds 10 microns (in length or width) on gate or capacitor areas. All other areas of the die are excluded from inspection.

For all other die:

Reject.





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8) Delamination / passivation lifting, cracks, holes or peeling

Defect Code: 8M

For Woburn GaAs die only: Reject if cracked passivation exceeds 10 microns (in length or width) on gate or capacitor areas. All other areas of the die are excluded from inspection.

For all other die:

Reject any.

De-lamination on the top nitride layer

De-lamination on the top nitride layer

Passivation is peeling or lifting from the surface of the die, or die is otherwise exposed.




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9) Discoloration

Defect Code: N/A

Reject only if any is extreme discoloration across the entire wafer is visible. Some color variation from plated metal texturing or grainy nitride on the scratch coat is acceptable.

Non-uniform passivation color across a wafer or a die, or unusual color vs. “normal”.

Action: Use-as-is. For extreme cases, put wafer on HOLD for Engineering.

10) Double-Die

Defect : 8U

Unlinked double die are rejectable. Note, excess GaAs from a mis-scribe (section 4B) is not considered a double die.

Any die which have not separated during the scribe and break tape expansion process




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11) Improper Inking

Defect Code: 8I

11) Improper Inking (con’t)

Defect Code: 8I

Ink dot diameter: For smaller die, ink should be roughly 50% of the die. For larger die, ink dot should be roughly 20 – 25% of the die. Ink Dot “centering” If any part of the ink dot is not touching the “dead center” of the die, then it is considered reject. Ink cannot run over the edge of the die onto nearby die. Accept:

Reject:

Ink dot opacity: Reject if ink dots are transparent (i.e., no underlying material, shiny metal, or passivation is visible through the ink dot)

Incorrectly sized ink dots, no ink dots, smeared ink, ink dots not located in center of die.

Action: Ink or re-ink affected die



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No ink dot: Verify build instruction:

For blind build wafers, pizza masks, or product qualification runs: Accept wafers without dots.

If not a blind build, Reject.

Multiple ink dots on one die:

Multiple ink dots, such as in the case of re-inking, must be contiguous with sufficient overlap so that the pick and place systems recognize a single dot.

Ink dot size (For Silicon Wafers to be processed trough Mexicali Backgrinding and Sawing)

Ink dot height must be equal or less than 15 microns to avoid any risk ok breakage at backgrinding.

Reject: If ink dot height is bigger than 15 microns and put on hold waiting for engineering.

12) Incomplete die

Defect Code: N/A

Wafers must utilize an edge exclusion zone of minimum 3 mm to prevent partial die from being used. If edge exclusion is present, no additional inking is required.

Under special circumstances, the full 3 mm edge exclusion is not used. These circumstances include pizza (engineering design) masks, special STR’s requesting no edge ink, or by waiver from the Quality Engineering groups.

Inking is applied to all complete die within the zone as well as any die that have sufficient surface area to be inked.

Partial die, typically on the edge of the wafer, which is not the proper shape or may have thin or missing metallization or passivation due to its edge location.

Action: Ink affected die. No deduction is required because these die are not counted to begin with.



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13) Incorrect metal line width or neckdown

Defect Code: 8F

Metal lines less than half of the normal line width

Line actual width less than per design or metal lines at steps that are diminished in width

Action: Ink affected die.



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14) Loose particles

Defect Code: N/A

For Woburn GaAs die only: Reject if attached or embedded particle exceeds 10 microns (in length or width) on gate or capacitor areas. All other areas of the die are excluded from inspection.

For all other die: Accept particles above the passivation. Particles are removable via a filtered N2 gun or tacky tipped tools (where allowed by area work instructions.)

If air nozzles or tacky tools fail to remove particles at assembly operations, no attempt should be made to remove suspected contamination.

Additional methods of removing particles such as wafer scrubbers are available during fabrication processing only.

Action: Use-as-is



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15) Metal lifting, Peeling, Blistering

Front and Backside

Defect Code: 8F for front, 8B for backside

For Woburn GaAs die only: Reject if any metal lifting exceeds 10 microns (in length or width) on gate or capacitor areas. All other areas of the die are excluded from inspection.

For all other die:

Reject any.

Lifted metal

Backside peeling. Reject.

Surface metallization which separates from layer(s) below

Lifting Peeling Blistering

Or, backside metal peeling as seen in photo on the left.




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16) Metal

Defect Code: 8F

For Woburn GaAs die only: Reject if metal defect exceeds 10 microns (in length or width) on gate or capacitor areas, or exceeds 30 microns (in length or width) on a bond pad. All other areas of the die are excluded from inspection.

Reject void greater than 50% of normal metal width

Missing material in an active area which exposes underlying material.

Action: Ink die with less than 50% metal

17) Misalignment

Defect Code: 8F

Reject if metallization coverage between contact and via is less than 50% of via area or perimeter

Any misalignment of circuitry between different mask layers.




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18) Mottled Plating

Defect Code: N/A

Found only on electroplated metal processes, this condition is acceptable. Do not confuse with voids, above.

Mottled areas

Action: Use-as-is



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19) Protrusion (stacking fault, hillock, crystal defect)

Defect Code: 8F

Reject if any protrusion is seen with measured height greater than half of a bond pad.

EPI defects

A protrusion can be an embedded Si or particulate contamination under the passivation giving the appearance of a bump on the surface of the wafer

Stacking fault is a dislocation in the crystal lattice, which appears as a bump on the surface.

This may cause problems during backgrinding (wafer will crack).


20) Scratch

Defect Code: 8S

For Woburn GaAs die only: Reject if scratch exceeds 10 microns (in length or width) on gate or capacitor areas. All other areas of the die are excluded from inspection.

Reject if the scratch exposes underlying material, causes bridging, or cracks the passivation.

Reject:

Accept:

Missing or disturbed material caused by damage.




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Scratch in the PBO Layer

Accept: if scratch in PBO layer does not expose underlying material.

Reject: if the scratch in PBO layer exposes underlying metal material


Accept: scratch in PBO layer does not expose the underlying material.

Reject the scratch in PBO layer exposes underlying metal material




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21) Discolored Pads:

Newbury Park/ AWSC GaAs die

Defect Code: 8F

Assembly operation: Perform engineering assessment of discolored pads; fail if lot fails wire bonding requirements.

Any pad discoloration from yellow to black in color. Normal pads are off-white and may have small black dots.


Action: Reject: Bond pad discoloration or Staining in Pad area is seen.



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22) Ink Residue

Defect Code: 8I

Ink splatter on pads are rejectable if they exceed 20% of the pad area. Ink splatter or residue on areas other than the bond pad, or which does not cover 20% or more of any bond pad is acceptable.

Ink spatter marks, drops of ink or ink residue on the wafer which contact the bond pad are considered rejectable, if exceed 20% of the pad.


23) Missing metal

(Woburn GaAs only)

Defect Code: 8F

Reject die that are missing more than 25% of the metal at bond pad.




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24) Pad Contamination.

Defect Code: 8Y

Reject all other contamination on bond pad if:

1) The contamination covers more than 20% of the bond pad opening (GaAs) or 10% (Silicon.)

OR

2) The contamination bridges two bond pads or bridges any bond pad to the scribe line

Example of Good clean pads. Acceptable.

Do not confuse with mottled plating, item 18 above. Bond pad issues are related to foreign materials only.

Gross particulate contamination, wax, residual photo resist, passivation (“glass on pad”), etc on top of or embedded into circuitry

Contamination on pads > 10%, reject

Unetched passivation. Reject.




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25) Pad Corrosion

(Silicon only)

Defect Code: 8F

Reject any die with bond pad corrosion.

Etching of bond pad surface which results in a pitted, rough surface appearance.

Corrosion can also be caused by Fluorine residue which can etch away at the pads as can be seen in the photos at the left.

This can lead to failures in wire bonding.

Action: Put lot on hold for Engineering

26) Pad Misalignment

Defect Code: 8F

Reject if pad passivation opening exposes the edge of the pad metallization

Bond pad opening in passivation is shifted




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27) Passivation opening or overetched overcoat

Defect Code: 8F

Reject if pad passivation opening exposes the edge of the pad metallization, or if the overcoat is etched into circuitry.

Bond pad opening is enlarged beyond designed boundaries

Overcoat etched beyond bond pad into metal edges or circuitry


28A) Probe mark

ly

efect Code: 8E

Reject if:

robe mark breaks the passivation window.

Reject

damage

GaAs on

D

1) The p

. Probe mark Brok window

2) The probe marks displace more than 25% of the bond pad or

llization caused by the

in

these photos, the probe mark broke the

this photo, the die was probed 3-4 er

e

exposes underlying substrate.

Disturbed metaprobe process, which does not expose underlying material, but leaves a mark the wire bonding area showing the path of the prober.

Inwindow. This is considered rejectable.

Intimes. The damage to the pad is greatthan 25%, which is out of spec.

This is considered a reject.




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28B) Probe mark damage, Silicon

Defect Code: 8E

Reject if: 1) Probe mark damage (including cracks propagating from probe mark) extends beyond pad seal ring (~5um)

Accept if: Probe mark breaks passivation around perimeter of pad (~5um) but does not disturb any adjacent metal lines, active area, expose substrate, or extend beyond pad seal ring.

Action: Place wafers on HOLD for Engineering disposition



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9) Bond Pad Scratches

Defect Code: 8E

Reject if:

1) The Scratch exposes underlying material

OR 2) Probe marks disturb more than 25% of the pad area. If the pad is elongated, the area referenced is the largest square which fits within the pad.

Disturbed metallization on the bond pad surface due to mechanical damage or abrasion

Action: Place wafers on HOLD for Engineering disposition

30) Wafer Identification and Labeling and counts

Defect Code: 8O

Reject if:

1) Wafer ID does not match invoice

2) Wafer Count on label does not match invoice

3) Die Count difference between electronic tracking systems to label and/or invoice.

4) Invoice does not reference lot identification, or individual wafer identification (for cases where wafer identification is not identical to lot identification.)

5) Where electronic traceability is used, lot and wafer identification must match invoice

Action: Correct issue or place on HOLD for Engineering/Supervisor

31) Wafer tape edge spacing and centering

Defect Code: 8Z

Reject if less than ½” of tape surrounds wafer as pick and place system cannot pick die.

If found at assembly, an attempt should be made to process the wafer. If problems with this centering or edge spacing, contact Supplier Quality department.

Action: Place on HOLD for Engineering



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32) Chips at edge (unsingulated Si or unthinned GaAs wafers only)

Defect Code: 8W

Reject if:

1) Chips larger than the size of the wafer placement notch (approximately 3 mm long) are noted on wafer edge:

OR

2) If chips result in cracks propagating into the wafer:

If either condition is met, place wafer(s) on hold for Supplier Quality evaluation.


33) Die spacing (edge picking collets only)

Defect Code: 8Z

Reject if die spacing after scribe and break expansion cannot be picked with a collet (i.e., less than 4 mils.)

Space between two adjacent die is insufficient to pick die with a collet.




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34) Unprobed die

Defect Code: 8E

If one or several die on an otherwise probed wafer, first verify if wafer is sample probed, then:

• If yes, accept.

• If no, accept and inform Skyworks Supplier Quality.

If entire wafer is unprobed, first verify if wafer is blind build or wafer is cracked, then:

• If yes, accept.

• If no, accept and inform Skyworks Supplier Quality.

Bond pad has no probe mark.


35) Crackling PBO Reject if

Wafer presents cracks in the PBO layer

Action: Put on hold for engineering review



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36) PBO Ghost Image

Defect Code: N/A

Acceptance:

PBO Ghost Image is latent image of reticle ID or barcode on top of PBO layer visible during visual/AOI inspection this condition is acceptable.

Action: Accept.

PBO Ghost image is a cosmetic defect caused by exposure light reflection in the stepper,

6 Quality Records (Process Outputs)

This section is not applicable to this document. Records of nonconformance’s are identified in site specific documentation.

7 Document Responsibilities

Who What

Manufacturing Quality Managers

Approves Changes to this document

External Foundry Managers Approves Changes to this document



Revision: 20




Process Engineering Managers Approves Changes to this document