rf design and review guidelines

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RF DESIGN AND REVIEW GUIDE LINES

Monday, FEBRUARY 15, 2016 Contact Name: T Y JOSE Telephone:+91 9952967626/949276116 Email:[email protected],[email protected]

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Contents

1. Scope of the Document ..................................................................... 4 2. Documents for Design reviews ............................................................ 4 3. RF GUIDELINES ............................................................................. 5 3.1 Power Supply Regulation and specifications ........................................ 5 3.2 Decoupling especially for Tx Power supply.......................................... 5 3.3 Power Supply and ground pad distribution ......................................... 6 3.4 Split ground topology Digital /Analogue/ RF ..................................... 6 3.5 Supply crosstalk ............................................................................ 6 3.6 Supply switches ............................................................................. 6 3.7 Antenna Placement, Enclosure, and Ground Plane ............................... 6 3.8 Matching Network for Antenna ......................................................... 7 3.9 Cross talk and tracks with λ/4 length ................................................ 7 3.10 Un terminated copper shapes lengths ............................................. 8 3.11 All long traces should be with Controlled Impedance traces ................ 8 3.12 Minimize Vias in High frequency paths ............................................ 8 3.13 Xtal Osc spec. stability harmonics . ................................................ 8 3.14 SPI/I2C communication track lengths ............................................. 9 3.15 Verify general fulfilment of all regional regulations GSM/GPRS/LTE ...... 9 3.16 RF traces bending radius .............................................................. 9 3.17 TDD/FDD switching circuits ....................................................... 9 3.18 Presence of shield, mounting and general profile ............................. 10 4. DFM/DFT GUIDE LINES ................................................................. 10 4.1 Component to component spacing ................................................... 10 4.2 Component to board out line and fasteners spacing .......................... 10 4.3 Test points availability size and spacing ............................................ 11 4.4 Spacing of Vias and general features ................................................ 11 4.5 Trace to trace spacing in all routing layers ........................................ 11 4.6 Fiducial and tooling holes ............................................................... 11 4.7 Solder mask ................................................................................. 12 4.8 Assembly and fabrication drawings .................................................. 12 4.9 Stencils, any other tooling .............................................................. 13 4.10 BOM to NM verification ................................................................ 13 4.11 PCB Size and Mechanical Fit ......................................................... 14 4.12 Panel /single - drawing, V Grove /routing ..................................... 14 4.13 Thru hole component lead diameter .............................................. 15 4.14 Tooling holes four corners non plated ............................................ 15 4.15 Reduce number of thru hole components as possible ....................... 15 4.16 No Component legend falling on component pad ............................. 16 4.17 Component orientation, Solder thief .............................................. 16

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5. EMI/EMC GUIDE LINES ................................................................. 16 5.1 Ground System ............................................................................ 16 5.2 Power supply Considerations .......................................................... 16 5.3 Isolated DC-DC Converters ............................................................. 16 5.4 Segregation of components ............................................................ 17 5.5 PCB Considerations ....................................................................... 17 5.6 Board Layers ................................................................................ 17 5.7 Signal Line considerations .............................................................. 17 5.8 Terminate lines with HF and RF signals ............................................. 18 5.9 Digital Circuits .............................................................................. 18 5.10 Clock Termination ...................................................................... 18 5.11 Analogue Circuits ....................................................................... 18 5.12 Decoupling Capacitor .................................................................. 18 5.13 Cables ...................................................................................... 18 5.14 Crosstalk .................................................................................. 19 5.15 Shielding .................................................................................. 19 5.16 Component Considerations .......................................................... 19 5.17 Component Placement ................................................................ 20 6. REFERENCES .................................................................................. 20

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1. Scope of the Document

This document gives guidelines for RF, DFM/DFT and EMI/EMC Design, Review and Verification of designs based on most of the wireless control integrated circuits. It covers all application segments such as automotive, telecom, industrial, IoT and consumer electronics and provides best-practice aspects and checklists for exhaustive system verification in the customer application. Even if some of the hints may sound like common sense or just a good engineering practice, they are still included as reminder.

This document has applications of Wireless Control Wireless IC products in its focus: receivers (RX), transmitters (TX) and transceivers (TRX) – some of them with integrated temperature, acceleration and pressure sensors and microcontrollers – however, current guideline version is narrowed to general and RF, DFM/DFT, EMI/EMC aspects .

This document can help us in following design phases:

Verification plan definition Schematics design and review

PCB layout design and review Firmware/Software/Hardware co-verification and Design-For-Test and manufacturing (DFT

and DFM) System verification, validation and sign-off

Design issue/problem detection, localization, debugging and fixing Definition of production test

Disclaimer & Limitations: This document is provided on an “as-is/best-effort” basis and contains detailed, but still generic and design-independent guidelines, thus it can only extend and by no means replace an obligatory design-specific customer-defined verification plan. Thus there is no liability resulting from following these guidelines whatsoever.

2. Documents for Design reviews

[1]. Schematics with revision details

[2]. PCB LAYOUT with revision details

[3]. Bill of Materials

[4]. Data sheets for the components used

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3. RF GUIDELINES

3.1 Power Supply Regulation and specifications

Clean and stable power supply is essential for good RF applications. Following characteristics must be specified, designed and verified in the application over the full specified range of environmental and operating conditions. Sufficient margin should be provided while designing the power circuits.

Supply voltage: Check all supply & regulated voltages in all functional modes (variation vs. temperature and application supply voltage). Supply voltage must remain within the specified (min-max) range for all devices under all circumstances. Lower operating voltage than “min” may cause performance loss (blocking, linearity, phase noise, output power) or even overall malfunction (due to analog operating point or logic threshold shift). Higher operating voltage than “max” may cause an overall malfunction (due to analog operating point or logic threshold shift), electrical breakdown or product lifetime impact due to higher currents (electro migration), higher dissipation (thermal stress) or overvoltage stress (VT drift over lifetime) – the list of effects being not exhaustive.

Supply voltage stability: Consider and check load and line regulation of all regulators (external

and internal). Do not load on-chip regulators with external loads, except explicitly allowed.

3.2 Decoupling especially for Tx Power supply

Bypassing is essential to high speed and RF circuit performance. It provides low impedance source and return paths to high frequency changes in load current. Capacitors as close as possible to the supply pins of each IC provide localized bypassing.

Regulator stability: Take care about capacitive (decoupling caps!) and inductive (wiring!) loads when designing supply circuitry. Use only recommended capacitor values and types for regulator decoupling and place capacitors as close as possible to input/output pins. Violation of these rules may cause regulator instability (=oscillations with arbitrary load-dependent amplitude and frequency) causing in turn probably sensitivity loss and blocking performance loss (LO spurious mixing) for RX circuits and unwanted TX spurious emissions.

• Supply RF and noise decoupling: DC power supply must be ripple-free. Take care and verify that no external RF and noise sources (EMC) can penetrate into the DC supply network i.e. use feed-through capacitors and ferrite beads. Specifically for TX circuits generating on-board RF currents, voltages and fields make sure there is no “backscatter” from RF output matching or antenna circuits to supply distribution network. Design for low-ohmic and Wideband-low-impedance supply network and test that. To achieve wideband low-impedance behavior use different capacitor values in parallel (high-C || low-L= 100nF || 1 nF || 100 pF). All circuitry generating large current surges (CMOS digital, line drivers) must be locally decoupled to reduce switching noise on supply. Avoid switching regulators – if required in the application, try to implement types with constant switching frequency or apply linear regulators at the output. In that case check explicitly in the application behavior of RX and TX at RF + around the designed switching frequency and its harmonics.

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3.3 Power Supply and ground pad distribution

Power supply and ground lines must be low-ohmic and have low-impedance (low L), i.e. corresponding PCB track width. Use large ground planes and - if possible – inner layers. Avoid ground loops, i.e. contamination of sensitive (input) ground nodes with shared return path for high-current (RF or switching) outputs. Use star topology (common ground) for ground and supply line connection. Use split ground (digital + analog + RF) topology in general. Provide galvanic isolation where feasible. Avoid using PCB Vias in supply and ground distribution – if you must have them, use several multiple Vias in parallel to reduce the parasitic R an L.

3.4 Split ground topology Digital /Analogue/ RF

Grounding and routing are also critical steps in Radio board layout and fabrication. These steps will directly impact board parasitic parameters that sometimes result in undesirable system performance. There are no unique solutions to ground distribution in RF board design; several approaches can achieve satisfactory system performance. Split ground planes or split traces can be utilized to separate analog and digital signals or to isolate high-current or high-heat-generating sections. Based on previous experience with RF board design, however, a single solid ground plane in a four-layer stack-up board works well. The general rule is to avoid cross-interference by using a ground plane to shield the RF section from other circuitry in the board.

3.5 Supply crosstalk

Take care that any wire or PCB trace approaching λ/4 length, independently of its original “purpose” (i.e. even GND or supply), starts to behave like antenna and either emit or receive the RF signal over large distances with high efficiency. Also pure capacitive or inductive crosstalk may contaminate either supply, if routed in parallel with large signal tracks, or sensitive input (RX antenna) or reference (XOSC) signals may become contaminated from a noisy supply line.

3.6 Supply switches

In many applications, it is required to cut-off the supply lines to sub circuits using discrete supply switches. Take care to design for low-ohmic and low-impedance solution (Rds_on) over all supply, temperature and load conditions and verify that.

3.7 Antenna Placement, Enclosure, and Ground Plane

Always place the antenna in a corner of the PCB with sufficient clearance from the rest of the circuit.( For patch antenna give minimum 10 mm clearance from the main PCB)

Always follow the antenna designer’s/manufacturer’s recommended ground pattern for the antenna.

PCB antennas are variants of a monopole antenna. Monopole antennas need solid ground for proper operation.

Never place any component, planes, mounting screws, or traces in the antenna keep-out area across all layers.

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The actual keep-out area depends on the antenna used. Do not place the antenna close to the plastic in the industrial design. Plastic has a higher

dielectric constant than air. Proximity of the plastic to the antenna results in the antenna’s seeing a higher effective dielectric constant. This increases the electrical length of the antenna trace and reduces the resonant frequency.

The battery cable or mic cable must not cross the antenna trace on the PCB on the same side of the antenna.

The antenna must not be covered by a metallic enclosure completely. If the product has a metallic casing or a shield, the casing must not cover the antenna. No metal is allowed in the antenna near-field.

The orientation of the antenna should be in line with the final product orientation so that the radiation is maximized in the desired direction.

There must not be any ground directly below the antenna. There must be enough ground at a distance (ground clearance) from the antenna and this ground plane must have a minimum width.

3.8 Matching Network for Antenna

Antenna is resonant circuit, the most important parameters for the antenna resonance is the length, capacitance and inductor. The capacitance and inductance will be affected by external components, ground plane, enclosures etc. For a perfect matching of the antenna need to tune for these external effects.

Plan to have a provision for an antenna matching network because a lot of parameters in the antenna’s proximity (plastic, ground variation, substrate differences, and other components) can vary its impedance, and therefore, the antenna may need retuning. If the impedance of the antenna is unknown, it is preferable to have a provision for a PI or T network of three components, with 0 ohms populated in series components and no load for shunt components. This helps you to populate any topology needed for a matching network later.

When using the matching network values provided by the antenna manufacturer, ensure that you use the trace length from the antenna to the matching network specified in the manufacturer datasheet or reference design.

Always verify the antenna matching network with the final plastic enclosure in place and the product placed in typical use case scenarios. For example, verify a wireless mouse with its plastic held on the hand and placed on a mouse pad, plastic, wood, metal, or floor

3.9 Cross talk and tracks with λ/4 length

Capacitive and inductive crosstalk occurs between traces that run parallel for even a short distance. In capacitive coupling, a rising edge on the source causes a rising edge on the victim. In inductive coupling, the voltage change on the victim is in the opposite direction as the changing edge on the source. Most instances of crosstalk are capacitive. The amount of noise on the victim is proportional to the parallel distance, the frequency, the amplitude of the voltage swing on the source, and the impedance of the victim, and inversely proportional to the separation distance. Measures that reduce crosstalk are:

Keeping RF-noise-carrying traces that are connected to the microcomputer away from other signals so they do not pick up noise.

Signals that may become victims of noise should have their return ground run underneath them, which serves to reduce their impedance, thus reducing the noise voltage and any radiating area.

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Never run noisy traces on the outside edge of the board.

If possible, group a number of noisy traces together surrounded by ground traces.

Keep non-noisy traces away from areas on the board were they could pick up noise, such as connectors, oscillator circuits, relays, and relay drivers.

Antenna Factor Length Rules: Normally, trace length becomes important when it is greater than 1/10 of the wavelength. For professional applications, that number becomes 1/20 to 1/30 of the wavelength. For automotive and consumer two-layer boards, 1/50 of the wavelength begins to be critical, particularly in unshielded applications. Traces longer than 4 inches can be a problem with noise. In these cases, some form of termination is recommended to prevent ringing.

3.10 Un terminated copper shapes lengths

Open copper shapes form un terminated transmission line. This will results in capacitance and or Inductance, which will degrade the signal integrity. So keep all un terminated copper shapes as short as possible and design pads as small as possible.

3.11 All long traces should be with Controlled Impedance traces

Telecommunications and computing equipment are operating at high frequencies have to be given serious consideration. At high frequency PCB traces act as transmission lines and the energy can reflect back and forth similar to a wave on a lake when it meets an obstruction. Controlled impedance traces are designed to minimize electrical reflections and ensure an error free transition between the PCB track and interconnections. Do not use right-angle bends on traces with controlled impedance.

3.12 Minimize Vias in High frequency paths

Vias will introduce capacitance in high frequency traces, Short RF Traces should be on Component Side of Board, Routed to Eliminate Vias. Minimizing Vias in RF Path Minimizes Breaks in Ground Planes- Minimizes Inductance. Helps Contain Stray Electric & Magnetic Fields. Use as few Vias as possible to avoid adding extra capacitance loading to the trace.

3.13 Xtal Osc spec. stability harmonics in RF board and closely nearby boards.

Crystal oscillators (XOSC) are used in applications as:

RF reference sources for RX (for local oscillator) and TX (for modulator) PLLs and clock sources for digital circuits.

It is thus essential for a XOSC to provide:

fast startup behavior

clean signal: no spurious discrete single-line spectrum & low phase noise

frequency accuracy and stability As every oscillator, it consists of resonator circuitry and an on-chip amplifier for energy loss compensation to fulfill and sustain the oscillation criteria. However, the resonator circuitry includes not only the quartz crystal itself, but also possible external and on-chip pulling (tuning) capacitors and unavoidable LC parasitic (L and C of PCB tracks, pins, IC, XTAL, caps etc). It is thus essential to verify all XOSC parameters in the final design, since there is large influence of all components on the final performance. Additionally, crosstalk via supply, ground or surrounding signal lines, as well

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as intercepted RF fields from outside will contaminate the XOSC output signal, which might cause no troubles for digital circuits, but become critical for output PLL signals.

Verify crystal oscillator startup time and oscillation margin in the final design. Take care that oscillation margin depends on complete circuit incl. PCB. Too low oscillation margin can cause XOSC malfunction with marginal crystals (higher R), leading to no oscillation or parasitic oscillation at some arbitrary frequency.

3.14 SPI/I2C communication track lengths

The integrity of the chip configuration and thus your design’s functionality and performance depends on error-free SPI or I2C communication between the host μC and IC.

Keep the bus length as short as possible: long bus lines will induce substantial capacitive load (high current spikes in the drivers high digital noise, higher current consumption and lower max. data rate) and increase the crosstalk probability.

Bus communication routines (SPI, I2C) and data transfer (Tx Host) are verified during this phase, as well as timing.

Use SPI tracking or checksum registers (not available in all products) in your application and in the verification test to validate the bus implementation (FW and electrical) in an endurance (loop) test. You may want to apply EMC stress during this test.

Implement bus communication timing compliant with datasheet requirements and verify that.

3.15 Verify general fulfilment of all regional regulations

GSM/GPRS/LTE

GSM/GPRS/and LTE operating bands and frequency varies from country to country. While designing and validating country specific parameters should be considered.

3.16 RF traces bending radius

When transmission lines are required to bend (change direction) due to routing constraints, use a bend radius that is at least 3 or 4 times the center conductor width. In other words:

This will minimize any characteristic impedance changes moving through the bend. In cases where a gradually curved bend is not possible, the transmission line can undergo a right-angle bend (non curved). However, this must be compensated to reduce the impedance discontinuity caused by the local increase in effective line width going through the bend. A standard compensation method is the angled miter

Similar methods can be employed for other transmission lines. If there is any uncertainty as to the correct compensation, the bend should be modeled using an electromagnetic simulator if the design requires high-performance transmission lines.

3.17 TDD/FDD switching circuits

Guard time is required between Tx and Rx and vice versa. The guard time is equal to a unit A’s turnaround time plus the round trip delay. A unit A’s turnaround time is in the order of 50 us. The round trip delay is in the order of 66 us. Thus the round trip delay can absorb the transmitter A’s

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turnaround time whenever the direction of traffic switches. The loss in throughput due to guard time for a 5 ms frame is about 2%.

3.18 Presence of shield, mounting and general profile

Proper shielding is required using ground Vias/ planes to reduce EMI.

Decouple the RF parts of the circuit from the DC parts of the circuit.

Inputs and outputs should be far apart, so that RF energy does not reflect back from output to input.

Isolation and return losses should be at least greater than -10dbm.

Shield IF components from RF components.

Decoupling capacitors should be used between an IC and a high speed RF track to avoid signal transference to IC.

4. DFM/DFT GUIDE LINES

4.1 Component to component spacing

The land pattern design and component spacing affect the reliability, manufacturability, testability and repairability of surface mount assemblies. A minimum inter-package spacing is required to satisfy all these manufacturing requirements. Maximum inter-package spacing is limited by several factors, such as available board space, equipment, weight considerations, and circuit operating speed requirements. Some designs require that surface mount components be positioned as close to one another as possible. Recommended minimum spacing is 25Mil.

4.2 Component to board out line and fasteners spacing

Keep the clearance of any copper to the edge of the board as large as possible. Routed edges should have at least 50 Mils clearance. If the copper is too close to the edge, the circuit may be

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manufactured with an exposed copper track, which could lead to corrosion. Also Component to board out line and Fasteners spacing suggested is minimum 100 mils.

4.3 Test points availability size and spacing

Clear access to test point is vital. Ideally, test pads should be provided on each node. If possible, always place test pads on one side of the board to minimize the likelihood of more expensive double-sided test fixtures. Test pads should be round and nominally 35 mils in diameter with pad-to-pad accuracy of ±0.003". Test pads should also be located at least 125 mils from the board edge because; pick and place systems and handlers require access to the board edges. Test pad spacing should be 100 mils whenever possible, 50 mils at a minimum. Test Electronics can probe centers as close as 15 mils , but these small probes are expensive and do not have the durability of the larger probes. Test pads on the component side of the board should have at least 40 mils clearance from components to avoid damage to either the probe or the part.

4.4 Spacing of Vias and general features

Increased component density on SMT designs has mandated the use of thinner copper, narrower conductor width and spacing. Higher component density may increase PCB layer counts as well, requiring the use of more Vias to make the necessary connections between layers.

The minimum spacing is 0.1524 mm or 6 mils. For four-layer inner trace/Vias/pads spacing, the minimum spacing is 0.254mm or 10 mils. Traces and Vias should be a minimum of 50 mils away from routed/scored edge. The traces that connect Vias to BGA pads need to be masked off as a minimum to prevent solder from scavenging into the Vias. The BGA pads are non-solder masked defined (i.e. solder mask opening is larger than the metal pad). For RF boards the space for ground Vias at 1/8 of a wavelength or less your ground plane will look like a solid ground. For a 1-GHz RF circuits that have via spacing of 250 mils

4.5 Trace to trace spacing in all routing layers

Copper spacing is the minimum air gap between any two adjacent copper features. Trace width is the minimum width of a copper feature, usually traces. To minimize crosstalk in high-speed interface implementations, the spacing between the signal pairs must be a minimum of 5 times the width of the trace. This spacing is referred to as the 5W rule. A PCB design with a calculated trace width of 6 mils requires a minimum of 30 mils spacing between high-speed differential pairs. Also, maintain a minimum keep-out area of 30 mils to any other signal throughout the length of the trace. Where the high-speed differential pairs abut a clock or a periodic signal, increase this keep-out to a minimum of 50 mils to ensure proper isolation.

4.6 Fiducial and tooling holes

A fiducial mark is a printed artwork feature created in the same process as the circuit artwork for optical recognition systems. The fiducial and a circuit pattern artwork must be etched in the same step. The fiducial marks provide common datum points for all steps in the assembly process. This allows each piece of equipment used for assembly to accurately locate the circuit pattern. There are two types of fiducial marks. Global fiducial marks are used to locate the position of all circuit features on an individual board. When a multi-image circuit is processed in panel form, the global fiducials are referred to as panel

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fiducials. A minimum of two global fiducial marks is required for correction of offsets (x and y position) and rotational offsets (theta position). These should be located diagonally opposite and as far apart as possible on the circuit or panel. A minimum of three fiducial marks is required for correction of nonlinear distortions (scaling, stretch and twist). These should be located in a triangular position as far apart as possible on the circuit or panel. Local fiducial marks are used to Locate the position of an individual component requiring more precise placement. A minimum of two local fiducial marks are required for correction of translational offsets (x and y position) and rotational offsets (theta position). This can be two marks located diagonally opposed within or outside the perimeter of the land pattern. The optimum fiducial mark is a solid filled circle. The preferred diameter of the fiducial mark is 1.0 mm. The maximum diameter of the mark is 3.0 mm. Fiducial marks should not vary in size on the same PCB more than 25 μm. A clear area devoid of any other circuit features or Markings shall exist around the fiducial mark. The minimum size of the clear area shall be equal to twice the radius of the mark.

4.7 Solder mask

Solder Mask Finishes: Solder mask coatings are used to protect the circuitry on the printed board. Solder mask coatings are available in two forms, liquid and dry film. The polymer mask material is applied using several process methods and is furnished in varying thicknesses. As an example, liquid materials will have a finished thickness of 0.02 mm [0.0079 in] to 0.025 mm [0.00984 in] while the dry film products are supplied in thicknesses of 0.04 mm [0.016 in], 0.08 mm [0.0315 in], and 0.10 mm [0.0394 in]. Although screen type printing for solder mask is available, photo-imaged solder mask is recommended for surface mount applications. The photo process provides a precise pattern image and when properly developed eliminates mask residue from land pattern surfaces. The mask thickness may not be a factor on most surface mount assemblies but, when fine pitch (0.63 mm [0.0248 in] or less) IC devices are mounted on the printed boards, the lower profile solder mask will provide better solder printing control. Solder Mask Clearances: A solder mask may be used to isolate the land pattern from other conductive features on the board such as Vias, lands or conductors. Where no conductors run between lands, a simple gang mask opening can be used .For land pattern designs with routed conductors between lands, the solder mask pattern must completely cover the conductor. A more precise registration is necessary because of the tight tolerance needed to cover the conductors without encroaching on the land area. PCB manufacturers are required to keep the solder mask material off the land. Clearance conditions can vary from 0.0 mm [0.0 in] to 0.1 mm [0.0040 in].

4.8 Assembly and fabrication drawings

Gerber files are created to enable plotting of the individual design file elements. Depending on their function, each Gerber file is compiled as an individual electrical layer, process or design reference. Gerber File Structure:

Electrical Design Layers - These Gerber files are processed to create each electrical layer (internal and external) that will ultimately be finished in copper on the PCB.

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Silkscreen - This file will create the stencil that will be used to apply the silkscreen (ink) to the PCB. The Silkscreen is for component reference, identification and labeling. The Silkscreen exists on the outer layers.

Solder Mask - The solder mask will expose solderable areas and protect the PCB by covering all copper elements. The Solder Mask minimizes solder bridges. In this Example, the Gerber file was created as a negative. Areas in red will not be covered with mask. The solder mask exists on the outer layers.

Solder Paste - This file will be used to create a solder paste stencil. Prior to the board assembly, the stencil will be used to apply solder paste directly to the pads on the PCB (Areas in yellow). Once the solder paste is applied, surface mount components can be placed and soldered.

Fabrication Drawings - This file will be created to display all mechanical and fabrication design parameters of the PCB. Parameters include layer stack up, board thickness, tolerance, drill file, copper weight, dimensioning, and applicable design standards. PCB manufacturing details include drill size, plating, and drill location information, electrical layer stack up, board thickness, slots, cutouts and tolerance.

Assembly Drawings – Identifies location and orientation of the electronic components to be placed.

Aperture Files - This listing defines the shape of individual elements on the PCB.

Drill Files - CNC drill parameters used on the PCB fabricators system to drill and route the PCB.

Net list - The net list is typically an ASCII format generated from the schematic. It contains all components (*part*) and connections (*net*) required for the PCB design.

X-Y Placement Data - Components are placed within the PCB board outline. Keep outs, cutouts and holes must be avoided.

4.9 Stencils, any other tooling

Solder paste plays an important role in reflow soldering. The paste tacks the component before reflow. It contains flux, solvent, suspending agent, and alloy of the desired composition. Solder Paste is applied on the lands before component placement either by screening, stenciling, or syringe. Screens are made from stainless steel or polyester wire mesh, and stencils are etched stainless steel, brass, and other stable alloys. Stencils are preferred for high-volume applications. They are more durable than screens, easier to align, and can be used to apply a thicker layer of solder paste, and, where narrow, point apertures are required for example, for fine pitch lands. Electroformed stencils may be required for very small components such as 0201 capacitors and resistors. The goal of the technology that’s employed to make the stencil is to ensure that this transfer is as efficient and complete as possible. There are several post processes that enhance the stencil’s performance, including electro polishing and trapezoidal section apertures that are created with laser cut technology.

4.10 BOM to NM verification

Verify manufacturing part number for each and every item on the BOM. Review end of life, lead-times and availability of components selected. Select the best component that is not near its end-of-life, the component whose lead-time is within your delivery window and the component that is widely available in distribution. All too often it is only after the design is

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completed and implemented do you realize a difficult or long lead-time item has been unnecessarily designed in the product. Select components with machine placeable features and packaging options. This will avoid driving additional cost at manufacturing phase by incurring additional manual handling of components. When possible, list alternate components to allow manufacturing process to find the best price/lead time part. For specialized components (e.g. ICs) or high dollar items, register the parts with the manufacturer and negotiate special pricing upfront. Select components where the required Minimum Purchase Quantity best matches your annual demand. Expected demand of 1000 units of a component that is only offered in 2500 unit reels multiples creates obsolescence and waste. On SMT assemblies use headers that can be placed with automatic pick & place equipment. Many manufacturers do not offer pick caps for their SMT headers. Avoid selecting components that need to be hand placed as this increases costs and the opportunity for errors. Select parts that can withstand the temperatures of the reflow ovens and wave solder equipment. Restrictions on Hazardous Substances (RoHS) parts need to withstand 260 Celsius as a maximum temperature. It is unadvisable for Ball Grid Arrays (BGA) RoHS components to undergo the traditional Tin-Lead process; however, they can be processed but with higher reflow oven temperature profile. The key is temperature; the temperature must be high enough to allow the balls to fully melt. Verify Non mount parts in final BOM and confirm for smooth assembly for the board. Wires need to be specified for Gauge, Length, Color, and UL rating. Remember to include manufacturer’s part number.

4.11 PCB Size and Mechanical Fit

PCB Size should match for the equipments in assembly house, used for production. The key is that size does matter and bigger is not always better. The larger the panel, typically the more difficult it will be to process. PCB Shape must have two parallel sides (longest sides) to process through automation. 0.125” keep out area along board edges or rails/break off tabs is required. 0.250” rail/break off tab minimum size.

4.12 Panel /single - drawing, V Grove /routing

With the assembly house and PCB fabricator need to optimize for lowest cost by having flexibility on panelization. Panels become less stable as the array size increases. Include information about overhanging parts (outline & keep out areas) V-Groove scoring is applied to both sides of the board. It is a “V” shaped groove leaving a 0.015” web of material to support the board. Components or other features should not be too close to the edge or damage may occur. Typically 0.035” – 0.050” should be allowed. - 45 deg .015" V-Groove scoring guidelines. Routing & Perforated Tabs refer to IPC-700. Perforated tabs are made up of 3 holes 0.040” in diameter. Indent holes by 0.025” to avoid a manual operation after depanelization PCB edge .025" Routing \ Perforated Tab guidelines The location of the cut tab shall be specified, if critical as it may cause interference upon assembly into the application box or hardware.

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4.13 Thru hole component lead diameter

Firstly we should find out the maximum lead diameter. It is present in the datasheet or package drawing of the component. The maximum lead diameters for all shape types of holes, Round hole shape is used for Round PTH Lead. Rectangle holes shape is used for Rectangle PTH Lead. Square holes shape is used for Square PTH Lead. Minimum Hole Size is calculated as Minimum Hole Size = Maximum Lead Diameter + 0.25mm to 0.15mm, depending on the component classification. If it’s a standard component from data base (ERP) the diameter and pad size will be taken care by the system.

4.14 Tooling holes four corners non plated

Tooling holes are added to boards for a variety of reasons. PCB fabricators use them for aligning the board during drilling and routing. Assemblers use them for alignment with stencils during solder paste printing, and for location on pick-and-place machines. They are used for alignment on electrical test fixtures. They may also be used as alignment holes in the final enclosure, often mating with small molded plastic posts. For some of these purposes tooling holes can be placed in the overall panel, but for activities that occur after de-paneling, or for boards that are not panelized, tooling holes are required within the board outline. Tooling holes are often standard sizes, for compatibility with commonly used locating pins. Common imperial sizes are 0.062", 0.093" and 0.125". Common metric sizes are 1.0mm, 1.5mm, 2.0mm, 2.5mm and 3.0mm. Tooling holes are always un-plated. This gives better accuracy since plating thickness is not well controlled. Putting the holes near the outer edges of the board helps ensure that the board will be stable when it is supported on the locating probes before the fixture closes. The centre of gravity of the board should be inside the polygon described by the support locations.

4.15 Reduce number of thru hole components as possible

Even though THM provides stronger mechanical bonds than SMT, making through-hole ideal for components that might undergo mechanical stress, such as connectors or transformers. Good for test and prototyping. But THM has many drawbacks on the bare PCB side; THM requires the drilling holes, which is expensive and time consuming. THM also limits the available routing area on any multilayer boards, because the drilled holes must pass through all the PCB’s layers. On the assembly side, component placement rates for THM are a fraction of surface mount placement rates, making THM prohibitively expensive. Further, THM requires the use of wave, selective, or hand-soldering techniques, which are much less reliable and repeatable than reflow ovens used for surface mount. Most of all, through-hole technology requires soldering on both sides of the board, as opposed to surface-mounts, which only -- for the most part -- require attention to one side of the board. SMT allows for smaller PCB size, higher component density, and more real estate to work with. Because fewer drilling holes are required, SMT allows for lower cost and faster production time. During assembly, SMT components can be placed at rates of thousands—even tens of thousands—of placements per hour, versus less than a thousand for THM. Solder joint formation is much more reliable and repeatable using programmed reflow ovens versus through techniques. SMT has proven to be more stable and better performing in shake and vibration conditions.

http://blog.optimumdesign.com/what-is-selective-soldering

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4.16 No Component legend falling on component pad

A legend is often printed on one or both sides of the PCB. It contains the component designators, switch settings, test points and other indications helpful in assembling, testing and servicing the circuit board. All legends should be visible, should not fall on components or pad.

4.17 Component orientation, Solder thief

On any printed board assembly where surface mount devices are to be wave soldered, the orientation of devices in respect to the solder wave can contribute to excessive solder process defects. The preferred orientation compared optimizes the solder process, minimizing solder bridging on the trailing or shadowed contacts as the assembly exits the solder wave. All polarized surface mount components should be placed in the same orientation when possible. The following additional conditions apply:

1 All passive components should be parallel to each other. 2 The longer axis of SOICs and the longer axis of passive components shall be perpendicular to

each other. 3 The long axis of passive components shall be perpendicular to the direction of travel of the

board along the conveyer of the wave solder machine.

5. EMI/EMC GUIDE LINES

5.1 Ground System

Low inductance ground System, Maximizing ground plane reduces inductance and capacitance reduces EM emission and Cross talk. Distributed ground system reduces return currents.

5.2 Power supply Considerations

Eliminate Loops in power supply Lines. Decouple Power supply in local boundaries. Place High Speed lines close to power supply section and low speed away from power supply

5.3 Isolated DC-DC Converters

An isolated DC-DC converter can provide a significant benefit to reducing susceptibility and conducted emission due to isolating both power rail and ground from the system supply Isolated DC-DC converters are switching devices and as such have a characteristic switching frequency which may need some additional filtering.

https://en.wikipedia.org/wiki/Circuit_diagram#European_and_Australian_codes

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5.4 Segregation of components

Components need to be segregated with functionality – Analog Digital. High speed digital, RF and so on. The tracks for each group should stay in their designated area. For a signal to flow from one subsystem to another, a filter should be used at subsystem boundaries

5.5 PCB Considerations

Avoid slit apertures in PCB layout, particularly in ground planes or near current paths. Areas of high impedance give rise to high EMI, use wide tracks for power lines on the trace side. Make signal tracks strip line and include a ground plane and power plane whenever possible. Keep HF and RF tracks as short as possible, lay out the HF tracks first Avoid track stubs, these cause reflection and harmonics On sensitive components and terminations use surrounding guard ring and ground fill where possible A guard ring around trace layers reduces emission out of the board, only connect to ground at single point and make no other use of the guard ring (i.e. do not use to carry ground return from a circuit). Avoid overlapping power planes, keep separate over common ground (reduces system noise and power coupling. Power plane conductivity should be high, therefore avoid localized concentrations of via and through hole pads (surface mount is the preferred assembly technology) Track smoothening at the edges (non perpendicular edges at corners) reduces field concentration If possible make tracks run orthogonally between adjacent layers Do not loop tracks, even between layers; this forms a receiving or radiating antenna. Do not leave any floating conductor areas, these act as EMI radiators, if possible connect to ground plane (often these sections are placed for thermal dissipation, hence polarity should be unimportant but check component data sheet.

5.6 Board Layers

Care must be taken that the ground layer should always be between high-frequency signal traces and the power plane. If a two-layer board is used and a complete layer of ground is not possible, then ground grids should be used. If a separate power plane is not used, then ground traces should run in parallel with power traces to keep the supply clean.

5.7 Signal Line considerations

Use low pass High pass and band pass filters wherever applicable to limit the band width to optimum.

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Keep Feed and return paths as close as possible in wide band signal lines

5.8 Terminate lines with HF and RF signals

Terminate lines carrying signals external to the board at the board edge. Avoid cables and tracks close to quarter wave length of signal frequency. Track all signals on the board to avoid flying leads. Minimize rise and fall time on signals and clock edges, slew rate limiting also reduces cross talk

5.9 Digital Circuits

When dealing with digital circuits, extra attention must be given to clocks and other high-speed signals. Traces connecting such signals should be kept as short as possible and be adjacent to the ground plane to keep radiation and crosstalk under control. With such signals, engineers should avoid using Vias or routing traces on the PCB edge or near connectors. These signals must also be kept away from the power plane since they are capable of inducing noise on the power plane as well. While routing traces for an oscillator, apart from ground no other trace should run in parallel or below the oscillator or its traces. The crystal should also be kept close to the appropriate chips.

5.10 Clock Termination

Traces carrying clock signals from a source to a device must have matching terminations because whenever there is an impedance mismatch, a part of the signal gets reflected. If proper care is not provided to handle this reflected signal, large amount of energy will be radiated. There are multiple forms of effective termination, including source termination, end termination, AC termination, etc.

5.11 Analogue Circuits

Traces carrying analog signals should be kept away from high-speed or switching signals and must always be guarded with a ground signal. A low pass filter should always be used to get rid of high-frequency noise coupled from surrounding analog traces. In addition, it is important that the ground plane of analog and digital subsystems not be shared.

5.12 Decoupling Capacitor

Any noise on the power supply tends to alter the functionality of a device under operation. Generally, noise coupled on the power supply is of a high frequency, thus a bypass capacitor or decoupling capacitor is required to filter out this noise.

5.13 Cables

Most EMC-related problems are caused by cables carrying digital signals that effectively act as an efficient antenna. Ideally, the current entering a cable leaves it at the other end. In reality, parasitic capacitance and inductance emit radiation. Using a twisted pair cable helps keep coupling to a low level by cancelling any induced magnetic fields. When a ribbon cable is used, multiple ground return paths must be provided. For high-frequency signals, shielded cable must be used where the shielding is connected to ground both at the beginning and at the end of the cable.

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5.14 Crosstalk

Crosstalk can exist between any two traces on a PCB and is a function of mutual inductance and mutual capacitance proportional to the distance between the two traces, the edge rate, and the impedance of the traces. In digital systems, crosstalk caused by mutual inductance is typically larger than the crosstalk caused by mutual capacitance. Mutual inductance can be reduced by increasing the spacing between the two traces or by reducing the distance from the ground plane.

5.15 Shielding

Shielding is not an electrical solution but a mechanical approach to reducing EMC. Metallic packages (conductive and/or magnetic materials) are used to prevent EMI from escaping the system. A shield may be used either to cover the whole system or a part of it, depending upon the requirements. A shield is like a closed conductive container connected to ground which effectively reduces the size of loop antennas by absorbing and reflecting a part of their radiation. In this way, a shield also acts as a partition between two regions of space by attenuating the radiated EM energy from one region to another. A shield reduces the EMI by attenuating both the E-Field and H-field component of radiating wave.

5.16 Component Considerations

Locate biasing and pull up/down components close to driver/bias points. Minimize output drive from clock circuits. Use common mode chokes between current carrying and signal lines to increase coupling and cancel stray fields. Decouple close to chip supply lines, reduces component noise and power line transients. Use low impedance capacitors for decoupling and bypassing (ceramic multilayer types are preferred due to high resonant frequency and stability).

Use discrete components for filters where possible (surface mount is preferable due to lower parasitic and aerial effects of terminations on through hole parts). Ensure filtering of cables and over voltage protection at the terminations (this is especially true of cabling that is external to the system, if possible all external cabling should be isolated at the equipment boundary). Minimize capacitive loading on digital output by minimizing fan-out, especially on CMOS ICs (this reduces current loading and surge per IC). If available, use shielding on fast switching circuits, mains power supply components and low power circuitry (shielding is expensive and should be a ’last resort’ option). In general, keeping the bandwidth of all parts of the system to minimum and isolating circuits where possible reduces susceptibility and emissions. Considerations which are applicable to reducing noise levels are equally applicable to EMC compliance, EMC compliant circuits should obviously exhibit low noise levels.

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5.17 Component Placement

Connectors should be placed on side or corner of the board-Locating the connectors on one edge of the board makes it much easier to hold them all to the same reference potential. This is extremely important for boards with high-frequency components that will not be housed in a shielded enclosure. Some designs require that connectors be located on different sides of the board. In these cases, every effort should be made to avoid placing high-frequency circuits between any two connectors. When placing high-frequency circuits between connectors is unavoidable, a metal enclosure and filtering to chassis ground is generally necessary to keep the board from being able to drive common-mode currents on to the attached cables.

A device on the board that communicates with a device off the board through a connector should be located as close as possible (e.g. within 2 cm) to that connector.

All off-board communication from a single device should be routed through the same connector.

Components not connected to an I/O net should be located at least 2 cm away from I/O nets and connectors.

6. REFERENCES

[1]. Standards document: IPC-7351 February 2005 [2]. Application Notes on RF design and EMI EMC guidelines from major Chip vendors like

TI, Infineon and more.

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END OF THE DOCUMENT

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