rf device technologies - ieee web hosting

2002 IEDM Short Course RF Device Technologies

San Francisco David Harame

RF Device Technologies

David HarameMgr. RF/Analog and Mixed Signal Technologies

Semiconductor Research and Development Center, IBM

Essex Junction, Vermont

1



Outline - IntroductionIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate Parasitics (T-lines)RF MEMSSummary

2



The Evolution of the Broadband Network

Enterprise / Campus

Core

CustomerPremise

WAN

High-SpeedBackbone

CentralOffice

CentralOffice

LAN

Base Station

AccessSOHO / Consumer

SAN

ISP

Edge

Data Services

SAN

SONET 155M, 622M, 2.5G, 10G=> 40G==> 160G

LAN

Storage Farm

Fibre Channel 1, 2G => 10G

Ethernet 10/100M/1G => 10G==> 100G

Wireless LAN 1M,10M => 56 MbpsCellular 1G, 2G => 2.5G, 3G, 4G

3



Large Scale FPGA Networking Platform

ClockRecovery

Control Plane Processing

O/E

E/O

PHYSerDes

SARMAC

Framer

Network Processing

PowerPC

SwitchPHY

SerDes

Clock Management

FIFO

AdaptiveEQ

ClockRecovery

Backplane

CrosspointSwitch

Line Card

= FPGA

A combination of high speed digital processing and analog blocks. Large scale integration requires integrating both together in a SOC.Very high speed serial links are used to reduce the number of parallel lines making the design requirments RF/analog like (devices, models and design features)

4



Cellular Roadmap

1st GenerationVoice Only

2nd GenerationVoice / Messaging

wideband digitalvariable data rate

64 kbps vehicular384 kbps pedestrian2 Mbps stationary

phone with keypad

phone with screen

information appliance

200820072006

IBM

0

1

10

100

1000

10000

analog<9600 baud

digital9600-14000 baud

AMPS

TDMAGSMPDCCDMA

UWC-136W-CDMA

cdma2000 (3xRTT)

EDGEGPRS

cdma2000 (1xRTT)

2.5 GenerationVoice / Data

Digital -variable56-115 kbps 115-384 kbps

3rd GenerationVoice / Data / Media

phone with larger screen/enhanced services

US

EuropeJapanUS/Asia US

3G Evolution

3G + integration of WLAN

data

rate

(kbp

s)

5



Key RF Figures of MeritfT: current-gain vs. freq 0-dB intercept

speed metric (esp. switching circuits such as MUX/DMUX, dividers, etc)fmax: power-gain vs. freq 0-dB intercept

speed metric (esp. circuits such as amps, mixers, VCOs, etc)Fmin: minimum noise figure, tuned over source impedence

determines how signal-to-noise ratio is degraded by deviceGA: associated gain, or gain when device tuned for Fmin

IIP3 / OIP3: input / output 3rd-order harmonic intercept pointbasic measure of linearity

BVCEO, BVCES, BVCER, BVCBO: Bipolar breakdown voltagesmaximum operating voltage limits (circuit dependent)

gm: Transconductance gds: Drain to source Admittance ( gcfor Bipolar)

σth: Threshold Matching (σic for Bipolar)

6



Outline - RF CMOSIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate parasitics (T-lines)RF MEMSSummary

7



RF CMOS FocusLow Cost

Density, yield, and processes derived from digital CMOSCompatible with digital designs

Fast time to market for SOC Scaling for digital is enabling RFCMOS

Lithography scaling and new materials provide improvement in fT , fMAX , FMIN ,and gM

Rs and σth appear significant limits at L < 20 nm Limitations often overcome by innovative design

"Design Issues in CMOS Differential LC Oscillators", A. Hajimiri and T. H. Lee, 1999.

Layout optimization keyOur focus will be the process and device design to optimize for RF/Analog

8



RF-CMOS = Digital CMOS + Adders

0.25 µm foundry CMOS2.5 V FETs3.3 V dual ox option0 Vt FETsResistorsMOS capacitor

0.25 µm foundry RF CMOS technology

2.5 V FETs3.3 V dual ox options0 Vt FETsResistorsMOS varactorMOS and stacked MIM capsThick last metal (inductors)P- substrate

Device Level Design Kit RF Models & Layouts

Add MOS varactorAdd MIM capacitorAdd thick dielectric/metalAdd RF Layouts, Models & Device Level Design Kit

Digital CMOS

RF/Analog Adders

RF CMOS

Parameterized PCELL with call backs to model

9



Figures of Merit gM, ft, gDS, fmax, Fmin, σth

Transconductancegm = µ (W/L) Cox(VGS - VT)

Cutoff Frequency fT = gm / 2πCgate

Drain Conductance gDS = gm dVTH/dVDS

Maximum Oscillation Frequencyfmax = (fT / 2)(gDS (RG+RS) + 2π fTRGCGD)-1/2

Minimum Noise FigureFmin = 1 + K*(f/fT)(gm(RG+RS))1/2

Threshold Matching, σth

σth= Α / (W L)1/2

10



Transconductance, gM

Strained SOI

gm / W scales with1/ tINV (effective gate dielectric thickness) ~ vSAT W (ε / tinv) for short L at high Vds

vSAT is the saturation velocityVdd scaling slow relative to L, thus tINV and gm unable to scale

Gate reliability improvement with Vds/tINV unable to compensateGate leakage due to direct tunneling significant for Lpoly < 130 nmHigh K gate insulators required to continue trend Device structure (double gate or strained silicion) offer alternatives

Limited by intrinsic source and drain resistance for L < 45 nm

101001000Lpoly (nm)

100

1000

10000

Gm

(mS/

mm

)

0200400600800100012001400

(ohm

um

)Se

ries

Res

ista

nce

101001000Lpoly (nm)

0.1

1

10

Vdd

(v) a

nd T

inv

(nm

)

Tinv~25%

Vdd~20% ?

11



gm/gds Trend 65 nm and beyond

Vdd not scaling with LpolyTINV limited by VddL / TINV decreasing

gDS limited by DIBLVdd modulating Idsgm / gDS not scaling long channel gDS degraded by halo implantsMetal gate, high K, asymmetric channel doping, or double gate FINFET structure may improve trend

101001000L (nm)

0

5

10

15

20

Gm

/ G

ds

10

20

30

40

50

L / T

inv

TINV LS D

G

12



Asymmetric Halo Improves gDSHook, Trans ED, 9/2002

Halo implant at drain "shadowed" by adjacent resistno added masksgDS improved - less drain barrier modulation by VDS

Shortest device DIBL (dVT/dVDS) degraded

13



Cutoff Frequency, ft

Scales with 1 / L fT = gm / 2πCGATE

CGATE = W ( L (ε / tINV)+COL) for wide devices

COL is the gate overlap capacitance per unit width Ignoring COL

fT ~ vsat / 2π L scales with 1 / L but

ultimately limited by RsDigital performance scaling driving L and CGATE

New structure or materials required L < 45 nm to suppress DIBL (drain induced barrier lowering)

101001000Lpoly (nm)

10

100

1000

Ft (G

Hz)

Projected Effectof Source Resistance

Double GateStrained SiHigh Krequired

SOI

14



Maximum Oscillation Frequency, fmax

fmax = (fT / 2)(gds (RG+RS) + 2π fTRGCGD)-1/2

For wide / short devices ~ fT (L / W) (COL ρG)-1/2 where ρG is the gate sheet resistance

Scales ideally with fT for fixed L / W~ (COL ρG)-1/2

Improves with metal gate or reduced

overlap capacitanceLimited by parasitic loss for narrow devices

0.1 1 10 100Finger Width (um)

0

50

100

150

200

250

300

Fmax

(GH

z)

E. Morifuji simulation VLSI 1999 L (nm)

3570100120

ScalingParasitic Loss

~ 1/W

15



Constant for fixed (f/fT) with scaled (W / L)Improves at fixed f as fT scales with 1 / L(Fmin - 1) ~ (f/fT) (gm(RG+RS))1/2 ~ (f/fT)(W/L)(ρG/tinv)1/2

Minimum Noise Figure, Fmin

E. Morifuji simulation VLSI 1999 ~ ρG

1/2

1 10 100Finger Width (um)

0

0.1

0.2

0.3

0.4

0.5

Fmin

@ 2

Ghz

(dB

)

ρG (Ohms/sq)

102.00.5

L = 100 nm

0.1 1 10 100Finger Width (um)

0

0.1

0.2

0.3

0.4

0.5

Fmin

@ 2

Ghz

(dB

)

E. Morifuji simulation VLSI 1999

~ W

Parasitic Loss Scaling

L (nm)3570100120

16



SOI offers a path to Performance ImprovementRF CMOS performance improvement from digital performance scaling

Lower S/D capacitance and improved short channel effect -> higher fT and fMAX For lowest noise need body contacted devices -> adds gate capacitance

Substrate crosstalk suppression dependent on frequency and structurehandle wafer grounded = SOI almost equivalent to junction isolationhandle wafer floating = SOI no better than p+ guard rings, worse at high frequency (K.Joardar, BCTM, 1995, pp. 178-181)

Innovative structures and new materials key to continued improvementBulk -> SOI -> strained SOI -> double gate or high K with metal gate -> ???

N.Zamdmer, 2002 ESSDERC

0 10 20 300

1

2

3

Frequency (GHz)

NF m

in (d

B)

0 10 20 305

10

15

20

Ass

ocia

ted

Gai

n (d

B)NFET, this work

PHEMT, [5]

40 50 60 70 80100

120

140

160

180

200

220

Lpoly (nm)

f T (G

Hz)

Vds = 1.2 VVgs = 0.7 V

data best-fit line (for comparison) Agilent PHEMT

17



Threshold Matching, σth

σth ~ q tinv / εox(2 N tdepl / W L)1/2

= A / (W L)1/2

Extrapolating to ~ 3.5 mV umσth ~ 0.2 / L VoltsScaling issue - process and circuit innovation required

101001000Lpoly (nm)

0.001

0.01

0.1

1

10

for m

inim

um d

evic

eVd

d an

d Vt

h M

atch

ing

(V)

Vdd~-20%

σth

∼+33%

DegradedMatching

0 5 10 15 20Tinv (nm)

0

5

10

15

Mat

chin

g C

oeffi

cien

t, A

(mV

um)

3.5 mV um

Pelgrom, IEDM 98 Mizuno, TED 94IBM

18



RF CMOS Scaling TrendScaling Feature Factor gm ft fmax NF gm/gds σTH Innovation

L and W 0.70 HALO, Ldd, SOI, FINFETAsymmetric

Device

Tinv 0.75 FINFET, High KMetal Gate

Gate R 1.0 SilicideMetal gate

Diffusion R 1.0 SilicideRaised S/D

Mobility ? strainedsilicon

Vdd 0.80 Multiple oxides

19



RF CMOS Layout Limitations

Layout Feature gm ft fmax NF Ids Model Accuracy

Reduced GateWiring Resistance

Reduced Drain/Source Diffusion Area

Decreased Drain/SourceWiring Resistance

Wrap Around Substrate Contact Scheme

Layout impacts RF performance but requires tradeoffsWider S/D wires handle more current but add diffusion capacitance Wrap around (ring) substrate contact degrades RF performance(< 5%) and adds area but increases accuracy of the RF compact modelContacting the gate on both ends decreases RG and improves Fmin and fmax but adds area

20



Optimization of Gate Wiring

Gate contacted on 1 sideRG (extrinsic) = 1/3 RSH Poly

M1 Wire to Gates

Polysilicon Gate

Source & DrainDiffusions

Typical Improved

Gate contacted on 2 sidesRG (extrinsic) = 1/12 RSH Poly

Gate ResistanceOften overlooked during layoutCritical to Fmin and fmaxSilicide or metal gate improves performance G ate R es is tan ce

Min

. Noi

se F

igur

e

G a

fm ax

Max

. Osc

. Fre

quen

cyAs

soci

ated

Gai

n

E ffec t o f G ate R es is tan ce

F m in

J.Burghartz, VLSI Technology Symposium 2001, p. 150-153

21



A Optimized RF MOSFET LayoutDesired Features

Controlled substrate and reduced gate resistanceScales in a "controlled" fashion (L,W, fingers, multiplicity)Can be accurately represented by a compact model

One Approach:Start with a typical layoutAdd a 2-sided gate contactAdd a wrap around SX ringAdd the S/D wiringAdd the Gate TabsAdd the "No Extract" ID Shape

The "No Extract" ShapeEverything within the shape is modeled by the compact modelNo parasitic extraction required

Drain

Source

GateRing

SX Ring

"No Extract"

22



Design Specific Custom Layouts?A single device layout may not meet the needs of all designers:

Minimize Gate ResistanceMinimize S/D Capacitance

High Speed

Larger S/D DiffusionsWider Metal, More Contacts

High Current

Low resistance vertical drain connection

A designer balancing speed and current issue might choose a custom approach:

Source (M1)

Drain (M2)

High Speed & Current

Minimum Length Drain (low parasitic capacitance) Large Source Parasitic Cap

(O.K. if not critical node)

Wider Source Metal(low resistance)

23



The PAE vs. Linearity TradeoffAs Power Added Efficiency (PAE) goes , Linearity (IM3) goes !

0

10

20

30

40

50

60

70

80

-20 -10 0 10

Pout [dBm]G

ain

[dB]

, PAE

[%]

-80

-70

-60

-50

-40

-30

-20

-10

0

IM3 [

dBc]

PAE/Gain/IM3 vs. Pout (Class B Operation)

IBM RF CMOS 0.25um NFETW= 300 um(# fingers = 40)Vds= 2.5VIds= 6mA

Note: Peak PAE of 71.2% !!

PAE % = (POUT - PIN)/PDC * 100PDC approximately constant for fixed biasAs PIN increases, PAE increases

Linearity (IM3) is limited by compressionGain roll-off prior to critical frequencySignal swings into weak inversionDevice limitation at high voltage

Source/Drain BreakdownImpact Ionization Substrate Current Body Effect (SCBE)

Class "B" Operation

Non-Linear"Distortion"

Ideal Behavior

24



The Smith ChartA representation of Z in the Reflection Coefficent Plane (Γ)

Z + Z0Γ =

Z - Z0 where: Z0 = reference impedance

50 100250

If the Z0 impedance is 50 Ω

-j50

-j25

j25j50

-j100

j100

Circles of ConstantResistance

0-1 +1

+j1

-j1

Γ Plane

a1

b1

a2

b2

2 - PortSystem

Γ1 = b1/a1 Γ2= b2/a2

Mapping Z to Γ we get:

Circles of ConstantReactance

25



Noise Figure

An ideal input impedance exists that gives a minimum noise figure (FMIN)

( ) 22

2

min11

4)(optS

optSnS rFF

Γ+Γ−

Γ−Γ+=Γ ,

Noise Parameter Equation - Describes the noise parabola

s is the source reflection coefficientopt is the optimum source reflection

coefficient for minimum noise figurern is the normalized noise resistanceFmin is the minimum noise figureRef.: ATN Microwave NP5 System Manual

26



Design Trade-Offs

Constant Gain Circles Constant Noise Circles

The FMIN and Maximum Gain Do not Occur at the same Source Impedance

FMIN = 2.28 dB

Gmax = 11.75 dB

NFET: Total width=600 , length=0.24 , NF=30Vg=1.5 V, Vd=2.5 V, Frequency=5 GHz

Gain Decreasing @ 1.0 dB / circle NF Increasing @ 0.5 dB / circle

27



MOSFET 1/f Noise

1/f Noise Increases ..When gate oxide nitridization is usedWith hot carrier stressAs Ids (gm) increases

10 100 1000 10000 100000Frequency (Hz)

1E-20

1E-19

1E-18

1E-17

1E-16

1E-15

S (V

/Sqr

t(Hz)

) N2O OxideO2 Oxide

Gate Oxide Comparison10x0.5um NFET (L = 35 nm)

CMOS technology scaling impact on 1/f Noise Thinner gate oxides require nitridization to prevent boron penetration. Tunneling in thinner oxides is driving CMOS to High K Dielectrics.

Vgs=1V Vds=1V

10 100 1000 10000 100000Frequency (Hz)

1E-22

1E-21

1E-20

1E-19

1E-18

1E-17

1E-16

1E-15

S (V

/Sqr

t(Hz)

)

DC Bias Dependency10x0.24um NFET(L = 100 nm)

Saturation

Weak Inversion

28



Outline - SiGe BiCMOSIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate Parasitics (T-lines)RF MEMSSummary

29



Graded Base SiGe HBT

Emitter

Ger

man

ium

C

onte

nt

Base Collector

Ener

gy(e

v)

N P N

SiSiGe

EF

EV

EC

e-e-

e-

Strained layer

Graded base bandgapspeeds electrons across basereduces gC (improves Early voltage VA) for improved gain

Base bandgap < emitter bandgaphigher IC, β and gm for given VBE ORtrade for higher base doping for improved resistance, noise, fmax

30



Vertical ScalingSAT

CSCL

n

BCBEC

CEB

C vW

DWCRR

qIkTC

qIkT

2

2

++

+++=

γ

Reduce transit time, increase fT

Kirk-effect extended to higher current densityVertical scaling with lateral scaling maintains constant current / device length for self-heating and current deliveryTradeoff between fT and breakdown voltage

conc

entra

tion

IncreaseGe slope

Narrow Base

Increase Coll

depth

fT

Reducetransit time

Kirkeffectto highercurrent

current density

1E-4 1E-3 1E-2Ic (A)

0

50

100

150

200

250

Cut

off F

requ

ency

(GH

z)

IBM 8HP

IBM 7HP0.18 µm generation

IBM 5HP0.5 µm generation

10X current

1.75X performance

Emitter shrink with increasing current density

CSCLBCEECTf

τττττπ

+++==2

1

31



HBT Lateral ScalingChallenge is to minimize parasitics

RB and CCB have most performance impact (e.g. fmax, gain, noise)Parasitic R’s & C’s are principally near the emitter

extrinsic and intrinsic devices can interactaway from intrinsic device, RB & CCB is already low

New structures provide large leverage in parasitic reduction

Polysilicon diffused-in emitterImplanted

extrinsic base

Dielectric isolation

Patterned collector"pedestal" implant

Low resistance metal salicideE

B

C

Emitt

erEm

itter

Emitt

erEm

itter

Shrinking emitter width reduces unit area RB and increases unit area CCB

CBB

TMAX CR

ffπ8

≈

32



Different Structures for SiGe HBTMetal or salicidePolysilicon

Insulator

Boron-doped polysilicon

SiGe epitaxy

EmitterBase

Collector

Standard CMOSSalicide

Standard CMOS contact

Epitaxy facet

Double poly, selective epibase resistance from link-up, faceting limits geometryself-aligned collector reduces collector capacitance

Implanted extrinsic baseImplanted base eliminates base resistance link-up issuespartially self-aligned collector has higher collector capacitance

33



Integration with CMOSMaintains CMOS structure and electrical characteristicsMajor thermal cycles prior to base depositionLow thermal-cycle HBT module

Ref: S. St Onge, BCTM 99

CMOS / Common Bipolar/Analog

Shallow Trench Isolation

FET Well ImplantsDual Gate Oxide & Gate FormationLDD Implants & AnnealsSpacer Formation

Silicide & ContactsStandard 2 to 6 Metal Layers

– Includes MIM Capacitor

Subcollector & n-EPI Deep Trench Isolation

Collector Plug Implant

Thick Metal Add-On Module

pFET S/D/G Implants nFET S/D/G Implants

HBT Module: Bipolar Window Open SiGe Epi Base Growth Extrinsic Base, Collector & Emitter Formation

Source/Drain and Emitter Anneal

Base EmitterCollector

34



U vs. MAG for fmax

rb

rπ

B C

E

ccbi

cbe

ccbx

gmvbe

vbe

There are multiple definitions of fmax

Unilateral gain, U:well-behaved ~20 dB/dec falloffhigher than "real world" power gain

insensitive to matchable B-C feedback ... elements that appear in both y21 and y12 (e.g. Ccbx)

Max. Available Gain, MAG:closer to "real world" power gainreveals parasitics such as Ccbx

defined only where device is stabledisplays a "bow" rather than 20 dB/dec falloff - difficult to extrapolate

( ) ( ) ( ) ( )[ ]21122211

21221

4 yeyeyeyeyy

Uℜℜ+ℜℜ

−=

U & MAG:Sensitivities to Ccbx

35



Example: fMAX Extraction

10 300Frequency (GHz)

0

10

20

30

U, M

AG

(dB

)

MAGU

40-70 GHz slope: -22.6 dB/dec

fmaxmethod

-20 dB/decextrapolation

40-70 GHzextrapolation

U 285 GHz 233 GHz

MAG 266 GHz 194 GHz

200 300100

Different gain definitions and extrapolation methods yield different fMAX (0-dB intercept) values:

36



Impact of Global Layout on fmax

Gain of device impacted by layout beyond device itselfe.g. RF signal on collector can flow into substrate via CCS

fmax depends on substrate contact placementfmax lowest when:

80 90 100 2001

2

3

4

5SiGe 5AMEmitter = 0.5µ x 2.5µmVCE = 3VVBE = 0.92V

fT = 200 GHzccs = 7 fFccb = 4.5 fFrb = 50 Ω

rsub = 0 Ω 100 200 400 800

Mod

eled

U

Frequency (GHz)

gmvbe

rb

rπ

B C

E

ccb

cbe

vbe

ccs

rsub

( ) 12 −= CSsubMAX CRf π

37



Broadband Noise in SiGe HBT

0 2 4 6 8 10 12 14 16 18 20 22 24 26 280.00.20.40.60.81.01.21.41.61.82.02.22.42.62.83.0

AE = 0.2 x 128 µm2

VCE = 1.5 V

20

103 GHz

F min (d

B)

IC (mA)

0

2

4

6

8

10

12

14

16

18

20

20

10

3 GHz

GA (dB)

Low noise figure is linked to device parameters:low RB and high fT

low β (f << fT)As IC increases, Fmin decreases then increases: balance of competing trends

increasing fT → decreasing Fmin

increasing gm → increasing Fmin

( )

+++≈ 2

2

min1121

TBm f

fRgFβ

4 6 8 10 12 14 16 18 20 22 24 26 28 300

20

40

60

80

0.0

0.5

1.0

1.5

2.0

2.5

3.0

AE = 0.2 x 128 µm2

VCE = 1.5 V

fT

RB

f T (G

Hz)

IC (mA)

RB (Ω

)

38



Broadband Noise & ScalingBoth lateral and vertical scaling contribute to overall noise performance improvement with next-gen HBT

lateral: improves RB

vertical: improves fT

Both Fmin and fMAX influenced by same key device parametersactivities to improve one also improve the other

0 1 2 3 4 5 6 7 8 9 10 110.00.20.40.60.81.01.21.41.61.82.02.22.42.62.8

0.5µm (34 µm2, 3 mA, 3 V) 0.18µm (56 µm2, 10.7 mA, 2 V)

F min (d

B)

Frequency (GHz)

0

2

4

6

8

10

12

14

16

18

20

solid lines = model

GA (dB)

0 1 2 3 4 5 6 7 8 9 10 110.00.20.40.60.81.01.21.41.61.82.02.22.42.62.8

0.5µm

Lateral:3. scale τt + β + Rb 3

21

0.18µm

Vertical:1. scale τt2. scale τt + β

F min (d

B)

Frequency (GHz)

( )

+++≈ 2

2

min1121

TBm f

fRgFβ

39



Noise Measure in SiGe HBTLow noise figure less attractive if gain also lowFeedback can reduce noise figure as well as gain

Capture tradeoff using combined figure of merit:

0 1 2 3 4 5 6 7 8 9 10 110.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0.5µm (34 µm2, 3 mA, 3 V) 0.18µm (56 µm2, 2.7 mA, 2 V) 0.18µm (56 µm2, 5.5 mA, 2 V) 0.18µm (56 µm2, 10.7 mA, 2 V)

Noi

se M

easu

re

Frequency (GHz)

Low bipolar noise measure indicates both:

low Fmin

low RB

high fT

GA >> 1 (0 dB)high fmax

low gC

low CCB

AG

FM 11

1min

−

−=

40



1/f Noise in SiGe HBT

10 100 1k 10k10-17

10-16

10-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

NPN

NFETNPN: WE = 0.2 µmNFET: LG = 0.18µmAreas normalized to 1 µm2

Inpu

t Ref

erre

d N

oise

(V2 /H

z)

Frequency (Hz)

1/f noise due to carriers entering / leaving trapscauses fluctuation in number of carriers and in mobility

1/f noise increase with:trap densitycarrier exposure to traps(e.g. oxide interfaces)

Bipolar:low 1/f noiseaction takes place in bulk, little interface exposurekey exposures: emitter-base spacers and oxide beneath poly emitter

NFET:higher 1/f noisechannel is adjacent to oxide interface

fANS

E

tVB

1⋅∝NPN:

41



Linearity Scaling

-25 -20 -15 -10 -5 0 5 10 15

-70

-60

-50

-40

-30

-20

-10

0

10

20

30

40

OIP3 = 22 dBm

AE = 62.5 µm2

PDC

= 15 mWf = 1.9 GHz

IIP3 = 10 dBm

POUT

(Fundamental)

IM3 (3rd Harmonic)P OU

T, IM

3 (d

Bm)

PIN

(dBm)

Non-linearity leads to generation of harmonicsIP3: extrapolate input (IIP3) or output (OPI3) power at which power in 3rd harmonic becomes equal to that in fundamental

Good linearity hinges on specific device parameter behavior:CCB: linear over large collector voltage swingslow RE and RC: large signal headroom from low knee voltageBVCEO or BVCBO (circuit dep.): large signal headroom from high supply voltage (potential scaling challenge due to fT vs. BV tradeoff)

42



HBT Breakdown Voltage

( )( ) ( ) ( )1-M

rrr1

11-M

1-M

π

bs β+−→eff

+-

VCE

+-

VCE

+-

VCE

R+-

rs

vs

rL

vce

BVCEO BVCES ≈ BVCBO > BVCEO Real-world scenario (small signal)

Small-signalmodel analysis

BVCEO < BVCER < BVCES

( ) ( )1-Mrrr π

bs β<<+

Highest breakdown voltage available when:

Even when rs = 0, non-zero rb can limit breakdown at higher IE, when rπ is small

+-

rs rb

rπ

vbe

gmvbe

(M-1)gmvbe

B

C

Etransistor

vs

+-

vce

avalanche current

Breakdown Voltage Definitions (Off State)

43



HBT Breakdown Optimization

Refs:

0 5 10 15 20 25 30 35BVcbo (V)

0

50

100

150

200

250

Peak

ft (G

Hz)

SiSiGeGaAs

3 4 5 6 7 8 9BVceo (V)

16

18

20

22

24

26

28

30

Peak

ft (G

Hz)

uniform collector non-uniform collector

BV depends on collector-base interaction:both intrinsic and extrinsic components

Fundamental tradeoff between fT and BVCBO

designer has control via material system and collector doping concentration / profileJohnson limit too conservative - based on simplistic assumptions that are not valid in modern devices

0

5

10

15

20

0 50 100 150 200 250 300fT [GHz]

BVc

es [V

]

Johnson Lim it

increasingcollectordoping

2001 BCTM; R. Jos, IEEE JSSC, 36:9, p. 1382, 2001;J.-S. Rieh, under review SSE

44



Outline - III-V DevicesIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate parasitics (T-lines)RF MEMSSummary

45



III-V Material SystemsDevices employ one or multiple materials:

single material: MESFETheterostructure: HEMT, HBT

Devices leverage materials with various bandgaps but having lattice compatibilityStrain puts limit on given layer thicknessExamples:

AlxGa1-xAs/GaAs (any x)Alx Ga1-x As/Iny Ga1-y As/GaAs(any x, larger y = more strain)Inx Al1-x As/Iny Ga1-y As/InP(x = 0.52, y = 0.53 for no strain)Inx Ga1-x P/GaAs (no Al-induced traps)(x = 0.48 for no strain)

lattice-matched lattice-mismatched

strain

46



The HEMT / PHEMT

Key merit: separation of donorsand mobile electrons

very high channel mobilityhigh ID, gm, fT, fmax

very low noise if Rg kept lowhigh power-added efficiency

Key applications:wireless front end (e.g. satellite dish)PA

n+ capn-type barrier/donorundoped channel

barrier / bufferS.I. substrate

gateohmic

GaAs

Al.38Ga.62AsGaAs

Al.38Ga.62As

GaAs

GaAsHEMT

GaAs

Al.38Ga.62AsIn.3Ga.7As

Al.38Ga.62As

GaAs

GaAsPHEMT

InP

In.52Al.48AsIn.53Ga.47AsIn.52Al.48As

In.53Ga.47As

InPHEMT

Design tradeoffs & challenges:push to higher InAs % in channel

increases ID, gm, fT, fmax

reduces breakdown voltageuse of InP substrate or relaxed buffers (MHEMT) to reduce strain

move toward Al-free barriers (e.g. InGaP) to reduce trapsuse of T-gates to maintain low Rg despite Lg scalingrecessed cap process (for reduced Rs, Rd)

47



GaAs and InP HBTs

Double heterojunction CB bandstructuresFrom C.R.Bolognesi IPRMS 2001 p27

Base

Collector

Mesa structureFormed by wet etchesUniform CCB over the base mesa

Critical differences between GaAs & InP HBTs

VBE = 1.3V (GaAs) vs. 0.8V (InP)Wafer size 6" (GaAs) vs. 4" (InP)

Double compared to single heterostructure

Reduced VCE offsetIncreased breakdownImproved thermal properties (InP)Better saturation charge storage, worse active charge storageMore difficult to achieve uniformity

From Hafizi TED ED-18, 358 (1997)

From M.Sokolich JSSC Vol 36 No. 9, p. 1328, 2000

Reduce base dimension -> CBC reduced 60%

fT

fMAX

48



Outline - Active Device ComparisonsIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate parasitics (T-lines)RF MEMSSummary

49



Network and Wireless Product Circuits Requirements

Network CircuitsProduct Critical Issues Technology

Requirements

Transimpedance Amp (TIA)

Low NoiseHigh Transimpedance

Low NoiseHigh GainDecoupling/IsolationPassives (R, C)

Postamplifier (PA) High Dynamic RangeLow NoiseLow Jitter

High GainLow JitterDecoupling/IsolationPassives (R, C)

Laser Driver / Electroabsorption Modulator Driver

High Voltage Swings (high breakdown) Low Output Jitter

High BreakdownHigh-Q InductorsDecoupling/IsolationPassives (R, C)

Stand-alone Ser/Des Jitter ToleranceJitter Generation

High-Q InductorsDecoupling/IsolationPassives (R, C)Logic

Integrated Ser/Des + Framer

Jitter ToleranceJitter GenerationIsolation

High-Q InductorsDecoupling/IsolationPassives (R, C)CMOS standard-cell logic

Backplane parallel bus, Switch chips, NPs

PowerJitterEase of IntegrationIsolation

Low PowerSmall AreaCMOS compatibleDominated by big D

Product Critical Issues Technology Requirements

Low Noise Amplifier

Low NoiseGain per stageHigh Linearity

Low nFMIN, Low HBT rB

Maximum Availablle GainHigh Early VoltageHigh fT,fMAX

Mixer High Linearity for low IDCHigh Port IsolationCarrier Leakage

High Early Voltage, (linearity)High fT/fMAX Isolation (DT)Small HBT & Passives mismatch

VCO Low Phase NoiseFarther from CarrierCloser to CarrierLinear Freq Change with Voltage

Highest Q PassivesLow 1/f noise HBTVaractor with C2 or 1/Vtune

Synthesizer

Low Phase NoiseLow Reference Spurs

Power and Area

Same as VCOSmall nFET/pFET asymmetry Small passives mismatchSmall gate length CMOS for low supply operation and reduced area

Power Amplifier(PA)

Power Added EfficiencyGain per StageRobustness

Low loss matching & interconnect circuits (High Q Ind., Thick Metal)Maximum Available Gain HBTHigh Breakdown Voltage HBT

Wireless Circuits

50



Active Device Comparison MatrixDesigners have a broad range of choicesNo single technology meets all market requirements

CMOS LDMOS SiGe HBT*

GaAs MESFET*

GaAs HEMT*

GaAs/InP HBT*

fT + - ++ - + ++fMAX + - + + ++ +NFMIN ++ + + + ++ -1/f noise - - ++ + - ++Linearity/PDC + + ++ ++ + ++Gain gm/g0 - + ++ - + ++Breakdown - + + ++ ++ ++Matching - + ++ ++ + ++Collector efficiency + + ++ + ++ ++Logic CMOS Integration

+++ ++ ++ - - -

High device count +++ + ++ + + -Thermal ++ ++ + - - - to +Cycle time + ++ - + + +Cost ++ +++ + - - -

* From Jiann Yuan, SiGe, GaAs and InP Heterojunction Bipolar Transistors, Wiley 1999 pg 3

51



Bipolar advantages over MOSNoiseEarlier fT availabilityHigher voltage capabilityMore effective fT

gM ability to drive loads fT tolerancemismatchempirically fT,Bipolar = 2-3XfT,CMOS

0 50 100 150 200 250

Measured fT

0

5

10

15

20

Max

vo

ltag

e

SOI 8SF8RF6RF

SiGe 8HPSiGe 7HP

SiGe 5/6HP

SiGe 5HP

Bias-dependent limit range

Junction-limited

Gate-oxide limited

Year

6SF

7SF

8SF

9SF

1997 1998 1999 2000 2001 2002 2003 20040

50

100

150

200

250

CMOS fTBipolar fT

10Gbps

40Gbps

0.25 µm

0.18 µm 0.13 µm

0.10 µm

Dev

ice

f T(G

Hz)

0.13 µm SiGe BICMOS

0.18 µm SiGe BICMOS

0.5 µm SiGe BICMOS

25 50 75 100 1258

101214161820222426

Bipolar CML

nFET SCL

Prop

agat

ion

Del

ay (p

s)

Load (fF)

ITAIL= 3mA

0.18 µm CMOSfT =70GHz NFET

0.5 µm SiGefT=47GHz HBT

Delay ~ gM/(CIN+CLOAD)

52



III-V compared to Si FETs

MESFETs : similar fT, gM/gDS, but higher voltage capability relative to Si NFETHEMTs : higher fT, VDS(MAX), gM/gDS relative to Si NFETSilicon wins in cost & integration capability

05

101520253035404550

0.01 0.1 1

Lgate (um)

Gm

/Gds

GaAs MESFETInGaAs HEMTSi NFET

0

2

4

6

8

10

12

14

0.01 0.1 1

Lgate (um)

Vds

(max

) (V)


Voltage gM/gDS

050

100150200250300350400450

0.01 0.1 1

Lgate (um)

fT (G

Hz)


fT

53



Technology Selection Case Study: VCOFigures of merit => Low Phase Noise, broad tuning, low gain variationBiCMOS is choice for demanding applicationsCMOS adequate for less demanding applications or with novel circuit topologies At low frequencies, passive devices dominate performance

Foundry CMOS RF CMOS SiGe BiCMOS

low 1/f noise

low noise figure

high breakdown

high fmax

high Q inductors/MIMslinear varactor with wide tuning

BestPoor OK

54



Outline - On-chip PassivesIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate parasitics (T-lines)RF MEMSSummary

55



Menu of Passives in 0.18µm SiGe BiCMOSLarge suite of passives required for RF/Analog Applications

Diffusion, poly, and metal resistors available for designersCapacitors reliable for 5.0V operationVaractors for high tuning range and linear operation

Resistors Rs (O/Sq) TCR (ppm/C)Subcollector 8.1 1430N+ Diffusion 72 1910P+ Diffusion 105 1430P+ Polysilcon 270 50P Polysilicon 1600 -1178TaN 142 -750Capacitors Cp (fF/um2) VCC (+5/-5 ppm/V)MIM 1 <45MOS 2.6 -7500 / -1500Inductor L (nH) Max Q at 5 GHzAl - Spiral Inductor >=0.7 18Varactor Tuning Range Q @0.5 GHzCB Junction 1.64:1 90MOS Accumulation 3.1:1 300

56



Varactor Options

N+NOX

P+ Single Crystal Silicon

NOX

Custom Implant Varactor (1 mask adder)

C-B junction varactor

N-WELL

Accumulation Varactor

P+ Single Crystal Silicon

N+

N+N+N+ Polysilicon

P+ Polysilicon

P+ Polysilicon

Custom ImplantN+ Subcollector

N+ Subcollector P-

P-

N

-3 -2.5 -2 -1.5 -1 -0.5 0Delta Voltage (V)

1

1.5

2

2.5

3

3.5

C /

Cm

in

MOS

Collector-Base

Custom Implant

Figures of Merit Tunability - Cmax/CminLinearityQ

MOS has the largest Tunability but has very poor linearity

57



ResistorsP+ Polysilcion Resistors

Low Temperature / Voltage CoefficientsGood ParasiticsNew Methods for low tolerance

BEOL ResistorsLow Rs (~50 Ω/Sq)Low Tolerance 8-10% (Target +/- Tolerance)Low Parasitic Capacitance to Substrate

TaN Resistor

ViaMetal

220 270 58 140 Sheet Resistance (Ohm/Sq.)

0

5

10

15

Tole

ranc

e %

TaN

Res

isto

r

TaN

Res

isto

r

P+ P

oly

Res

isto

r

P+ P

oly

Res

isto

r

58



CapacitorsFigures of MeritCA=Capacitance per unit areaCbot=parasitic capacitance to the substrate Q (FEOL a concern, process and layout innovation)

Main concernTradeoff between Capacitance and Reliabilty

FEOL CapacitorsHigher thermal cycles allow higher CA achieved than MIM Challenge is to Minimize Resistances (BiCMOS vs FET)Substrate and polysilicon layers, free vs dedicated steps

BEOL (Metal-Insulator-Metal MIM) CapacitorsDielectrics improving Oxide->Nitride->High KAluminum simple integration, Copper Damascene Integration issues

StrategyStackable Configurations

Reliabilty targets100K Power On Hours - 5V1-2 Million Square Microns Per Chip

Metal Mx+1

Top Plate

Base Plate Metal Layer Mx

Metal Mx+1

Top Plate

Middle Plate

Base Plate Metal Layer Mx

Nitride Ta2O50.01

0.1

1

10

100

ILEA

K@

3.6

V (u

A/s

q. c

m)

Dual nitride MIMTa2O5 data from Phillips Semiconductor website

ILEAK, Nitride ~< 140 x ILEAK, Ta2O5

59



Inductors

SPICE modelSPICE model

Silicon

Inductor Spiral

Via

Underpass

Si02

dielectricheight

(P-)

Figures of MeritQ = Power Stored/Power DissipatedL per unit area (intertwined)

Reduce parasitic spiral-to-substrate (C1,C2) and intra-spiral capacitance C3Reduce power consumption through substrate resistance, R3 ->0 or R3 ->infinityReduce parasitic resistance, R1, in the spiralE&M modeling results demonstrate the need for Thick Metal

60



Relevance of metal thickness for Inductors

Additional metal thicknessallows more "sidewall" for current flow, reducing effective resistance

Spiral line with current crowding

Edge Current

More even distribution

Edge current

Expected areaof sidewallcurrent flow

4µm

2GHz Method of Moments E-M Simulation (SONNETTM) of multi-turn spiral current flow

61



Inductors in Deep-Submicron CMOSQ reduction due to scaling-driven interconnect thinning offset by increased number of available levels

thinner levels have increased R (>0.1 ohm/sq.)multiple parallel levels can achieve reasonable sheet resistances (~0.02 ohm/sq.) at the expense of increased capacitance to substrate (decreasing self-resonant frequency)

Tight wiring pitch enables extremely high inductance density by stacking multiple series layers

10's of pH per sq. um achievable (10nH in 25umX25um, Feng, MTTS 2002)

Faraday shields effective at reducing electric field related substrate lossesPlanarization driven metal pattern density requirements require careful consideration

62



Parallel Stacking Reduces Series LossQ reduction due to scaling-driven interconnect thinning partially offset by increased number of available levels

thinner levels have increased R (>0.1 ohm/sq.)multiple parallel levels can achieve reasonable sheet resistances (~0.02 ohm/sq.) at the expense of increased capacitance to substrate (decreasing self-resonant frequency)

Si Si Si

Decreasing R, Decreasing self resonant freq.

R/4 R/2 R

CC C

63



Series Stacking Allows High Ind. Density

Tight wiring pitch enables extremely high inductance density by stacking multiple series layers

10's of pH per sq. um achievable (10nH in 25umX25um for 6 layer spiral with [email protected], Feng, MTTS 2002)trade-off is decreased self resonant frequency due to increased shunt capacitance

Si Si Si

L4xL16xL

Increasing L, Decreasing self resonant freq.

4 spiral layers connected in series2 spiral layers connected in series single layer spiral

64



Faraday Shields Enable Higher QThin CMOS dielectric stack enhances coupling to substrate, increasing substrate losses.Patterned conductive shield (Faraday shield) minimizes electric field induced power loss in the substrate

Q enhancement of 50% possibledrawback is decreased self resonant frequency and enhanced frequency dependence of inductanceuseful for medium resistivity substrates (1-20 ohm-cm)

does nothing to block magnetically induced eddy currents in highly conductive substrates

Faraday shield

P- substrate 1-20Ω-cm

EE

no shieldP- substrate 1-20Ω-cm

EE

electric field penetratessubstrate causing loss(reduced Q)

electric field shieldedfrom penetration into substrate (increased Q)

Faraday shield

65



High Q Inductors

Cross-section parallel Dual Metal Inductors

10-1 100 101 1020

5

10

15

20

25

301.1nH Spiral Inductor (Parallel Stack MA||E1)

Peak Qof 28

Last metal add on modules "Dual Metal Inductors"Option 1: Thick single last metal Option 2: dual thick last metal levelsIncreased dielectric layers

Excellent Q values over very large frequency rangeExample: 1.1nH inductor Q >15 from 600 MHz - 9 GHz

Al

Cu

Al

Al

Al

W

Silicon

D.Coolbaugh MTT 2001

1.1 nH Parallel Stack Inductor (MA - 4µm Al || E1 - 3µm Cu)25 um wire, 1.5 turns

MA 4µm

E1 3µm

66



Inductors - Single, Parallel, Series Stackup

parallel: largest areasmallest L, highest Q(MA - 4µm Al || E1 - 3µm Cu)single: large areamedium L, Medium Q(MA - 4µm Al )series: smallest arealargest L, lowest Q(MA - 4µm Al + E1 - 3µm Cu)

Inductor Wire Size Spacing Turns App. Area

Ind. Q at 2.5 GHz

Parallel Stack

25 um 5 um 1.5 400 um^2 1.5 nH 24

Single 25 um 5 um 2.0 400 um^2 2.5 nH 21

Series Stack

10 um 5 um 6 .0(3/ level)

220 um^2 8 nH 15

10-1 100 1010

5

10

15

20

25

Freq. (GHz)

Ind.

(nH

), Q

series

single

parallel

L

Q

Design optimization for 2.5GHz peak Q drives different geometry choices depending on spiral metal stackup

67



Outline - Interconnect and Substrate ParasiticsIntroduction

RF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate parasitics (T-lines)RF MEMSSummary

68



Motivation for Interconnect Modeling

Due to increasing signal frequencies, the transmission line effects of interconnects are more prominent in modern RF and mixed-signal integrated circuit (IC) designsIn multi-GHz design regimes, on-chip interconnects have a substantial impact on an IC performanceThe main issues are impedance matching, loss control, phase delay, coupling to other circuit elements and silicon substrateEven around 1 GHz inductance starts to impact longer lines. Therefore simple RC interconnect model is not accurate anymore and inductance has to be included into the modelIn order to account for transmission line effects during design process, critical interconnects should be accurately modeled over a wide frequency rangeInteraction between interconnects and lossy silicon substrate should be well understood

69



Interconnect Over Lossy Silicon SubstrateInterconnect over lossy substrate without bottom ground shield:

Bad isolation of an interconnect from a silicon substrateIncreased losses due to interconnect coupling to a lossy silicon substrateNot a well-defined waveguide structureField is not effectively contained around an interconnectAbsence of a well-defined current return pathDifficulties with accurate modeling over a wide frequency range

Supports three fundamental propagation modes:"slow-wave": low ω, low/moderate ρSi

electric field is confined in the SiO2 layer while the magnetic field feels free to penetrate the silicon substratethe separation of electric and magnetic fields slows down energy propagation

"skin-effect": high ω, low ρSi

electric field is confined in the SiO2 layer, while magnetic field penetrates the silicon substrate to a certain depth

"dielectric quasi-TEM": high ω, moderate/large ρSi

electric and magnetic fields feel free to penetrate the silicon substrate, which behaves as a lossy dielectric

For the SiGe silicon substrate:slow-wave mode (up to ~0.1GHz)transition from slow-wave to quasi-TEM mode (from ~0.1GHz up to ~10GHz)quasi-TEM mode (starting from ~10GHz)

Electromagnetic field distribution around interconnect

electric field, magnetic field

2SiO

Silicon Substrate

slow-wavemode

Silicon Substrate

2SiO

quasi-TEMmode

70



Simple Quasi-TEM Model

≤

−+−+

≥

+

π=

+−ε++ε=εε

εεσ

=εεε

=εεε

=

+++

+=

σ=

−

1hw ,

wh1

wh44.042.2

hw

1hw ,

h4w

wh8ln

21

)w,h(F

w/h10121

21)h,(

CG ,

)w,h(F)h,(

C ,)w,h(F)h,(

C

3tw50049.0

tw2ln002.0L ,

wtR

16

eff

Si0Si

SiSi

Si

0SiSieffSi

ox

0oxoxeffox

DCmetal

DCl

ll

l

Effective capacitance Cand conductance G are frequency dependentCapacitance (C) reduces faster than inductance (L) raising line characteristic impedance (Z) which affects impedance matchningCapacitance reduction frequency marks the transition from "slow-wave" mode to "dielectric Quasi-TEM" mode

Capacitance Inductance

SiC

oxC

SiG

2SiO

SiliconSubstrate

)(L ω)(R ω)(C ω

)(G ω

71



Microstrip Lines and Coplanar Waveguides

Microstrip lines:Microstrip single and coupledwire devices with optional side shielding Shielded effectively from below with possible side shielding to eliminate the silicon substrate losses and coupling to other interconnectsUsed for most critical lines such as signal lines in VCO's for MUX/DEMUX, multiple clock lines over a common ground plane

Coplanar waveguidesTapered finite-ground coplanar waveguidesUsed in RF-CMOS where on-chip circuit density is high

A suitable methodology is to characterize critical interconnects through the development of SPICE-compatible lumped element models, preferably passive by constructionUser form in layout view should allow rapid evaluation of electrical RLCZ parameters by designer which are important for impedance matching and loss control

microstrip lines

coplanar waveguides

Signal

Single lineshielded from

below

Coupled linesshielded from

belowand on both sides

Single lineshielded from

belowand on both sides

Coupled linesshielded from

below

Stacked Vias

Groundwsig

htsig

tgnd wgnd

Finite-groundcoplanar

waveguide(FG-CPW)

Finite-groundcoplanar

differential pair

Signal Ground

wsig wgnd

dwp

t

72



Substrate Noise Isolation

High speeddigital circuits

Low speeddigital circuits

High amplitudeanalog circuits

Sensitive analogcircuitry

Digital outputbuffers

P+ Guard Rings

n+ n+ n+ p+ p+n+

analog digital

Current noise flow

Substrate coupling occurs between "noisy" analog and digital circuitry and "sensitive" analog and RF circuitryRequirement for designers to predict/model the effects of substrate noise between blocks:

1. Test-site structures can be used to derive simple analytical models for the inter-block impedance

2. TCAD simulation can be used to accurately predict the effects of different isolation structures between the circuit blocks.

73



Technology Options for Substrate Isolation Conventional "free" technology Options

Shallow TrenchDeep Trench (single and in mazes)MOAT - typically a high resistance area separating circuit blocks P+ Guard rings

Technology ChoicesHigh resistivity substratesSOI (DC great isolation, AC poor)

PRML Read Channel1200 SiGe HBT, (>1,000,000 FETs

DigitalMoatAnalog

P- Wafer

P+STI STI

P- Wafer

STI STI

P+

STI STI

SOIP- Wafer

STI STISOI

STI

74



Predicting Substrate Isolation using TCAD Modeling

D

300 um

15 um

25 um

p+p+

5 um5 umisolation

deviceisolation device

TCAD Modeling can be used to predict effect substrate isolation/attentuationAccuracy should be calibrated with test site resultsThis approach allows IC designers to:

Understand the relative benefits of each different substrate isolation schemePredict accurately the isolation expected

Results show that substrate isolation drops rapidly above approx. 10GHz

Substrate impedance turns from resistive to capacitive, ...Leading to low impedance at higher frequencies.

1.0E+2 1.0E+4 1.0E+6 1.0E+8 1.0E+10 1.0E+12Signal Frequency (GHz)

-70

-60

-50

|S21

| (dB

)

(SX GR)-(SX GR) D=50um(SX GR)-(SX GR) D=75um(SX GR)-(SX GR) D=100um(SX GR)-(SX GR) D=150um(SX GR-DT)-(DT-SX GR)D=150um(SX GR-DT-SX GR)-(SX GR-DT-SX GR) D=100um

Without accurate substrate isolation modeling, high fequency capacitive effects may lead to design failures!!! Due to unexpected high levels of substrate coupling.

substrate AC impedance changing

75



Outline - RF MEMsIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate parasitics (T-lines)RF MEMSSummary

76



Microelectromechanical Systems (MEMS) rf Passive Components

Possible applications of MEMS passive components in a cell phone handset. Many potential advantages:

Better performance, smaller size, lower power dissipation, lower cost

Antenna1 Antenna2

AntennaSwitch

Bandpass Filter

(Ceramic)

VCO

Xstal Tank

Xstal Tank

VCOTransmitter

Receiver

Transmit PLL

Off-Chip Passive

Elements

IF Filter (SAW)

MixerRF LNA

C. Nguyen, L. Katehi, and G. Rebeiz, Proc. IEEE, vol. 86, pp. 1756-1768, Aug. 1998.

I

ADC

ADC

Q

I

Q

DAC

DACModulator

IF MixerIF LNA

AGC

Power Amplifier

Channel Select PLL IF PLL

Image Reject Filter

(Ceramic)

µmech. switch

µmech. switch

µmech. resonator

µmech. resonator

µmech. resonator

90o

90o

µmech. resonator

on-chip inductor

+µmech. tunable

capacitoror

TFRor

µmech./µmachin. resonator

µmech./µmachin. resonatorTFR or

µmech. tunable

capacitor+on-chip

inductor

77



Types of rf MEMS Passive ComponentsMEMS switches

Lower insertion loss and better linearity than PIN diodes or FET switchesPrototypes under active development at many companiesDo not yet meet all requirements (e.g. activation voltage too high, unknown reliability, difficult packaging)

MEMS resonators and filters using vibrating beams

High Q; small sizeMay be difficult to scale to GHz frequencies

High-Q inductorsSomewhat higher inductance and Q compared to conventional inductors may be possible

Voltage-tunable capacitorsMuch more complex than varactors

G.M.Rebeiz et al., IEEE Microwave Magazine, Dec 2001, p. 59

MEMSCAP, www.memscap.com

J.L. Lund, Solid State Sensor and Actuator Microsystems Workshop, p. 38-41, June 2001 Hilton Head

Parc Solutions, www.parc.com

MEMSCAP, www.memscap.com

78



MEMS rf Switches

Figure of Merit Typical ValuesInsertion loss (attenuation with switch closed) 0.1 - 1 dBIsolation (attenuation with switch open) 20 - 50 dBActuation voltage 5 - 60 VSwitching time 3 - 20 µsec for electrostatic; magnetic and

thermal slowerContact lifetime 106 - 109 cycles (conditions??)

Electrostatically Actuated MEMS Switch

Pull-down electrodes Switch contactsAnchor

Different beam shapes and numbers of anchors may be usedSwitches may also be actuated magnetically or thermallySwitch contacts may be resistive or capacitive

AnchorContacts

Pulldown electrode

Beam

B.McCarthy, J. Microelectomechanical Systems, Vol. 11, June 2002.

S.Duffy, IEEE Microwave and Wireless Components Letters, Vol. 11, Mar. 2001

79



MEMS Resonators

Resonant frequencies from simple, analytical formula f i = (ζ i / 4π 31/2) (E/ρ)1/2 (t / l2)

where ζ 1 = 1.875 and ζ i2 = 4.494 for cantilever, 4.730 for fixed beam E = Young's modulus ρ = Beam density t = Beam thickness l = Beam length

E = 160 GPa ρ= 3.1 g/cm3

PredictedFirst Mode

(MHz)

MeasuredFirst Mode

(MHz)

PredictedSecond Mode

(MHz)

PredictedSecond Mode

(MHz)Cantilever 7x15 µm 3.35 3.05 21.01 21.35Cantilever 4x10 µm 7.54 7.32 47.27 45.15Fixed beam 7x15 µm 21.33 21.83 - -Fixed beam 4x10 µm 48.00 42.35 - -

J. Lund et al., Tech. Dig. Solid State Sensor and Actuator Microsystems Workshop, pp. 38-41 (2002).

J. Lund et al., Tech. Dig. Solid State Sensor and Actuator Microsystems

Workshop, pp. 38-41 (2002).

J.R.Clark, IEDM 2000 p. 493

V. Rao, Intel Developer Forum, Feb. 2002

Fixed Beam MEMS Resonator

ElectrodesAnchor Anchor

80



Outline - SummaryIntroductionRF CMOSSiGe BiCMOSIII-V DevicesActive Device ComparisonsOn-chip Passives (Resistor/Varactor/Capacitor/Inductor)Interconnect and Substrate parasitics (T-lines)RF MEMSSummary

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SummaryWireless and Networking Frequencies and data rates continue to increaseExtensively reviewed active and passive devices focusing in particular on RF CMOS, SiGe HBTs, Inductors and Transmission LinesIn general RF CMOS analog parameters improve with scaling concerns remain - gm/gds, 1/f, inductor Q, etc.

Performance critically tied layoutSiGe HBT BiCMOS ideal but additional cost over CMOSInductor optimization will require extensive parallelingTransmission lines required to control losses in critical circuits Design System is key for first pass design success

82



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backup slides

83



TDDB Stress procedure for Capacitor qualification

1 2 3 4 5 6 7 8 9 10 11

ln[t(s)]

-5-4-3-2-10123

ln[-l

n(1-

F(t))

] 33 V 35 V 37 V

Weibull Cumulative DistributionCapacitors subjected to constant voltage and temperature time dependent dielectric breakdown (TDDB) stress

Time to fail statistics based on Weibull cumulative distribution function,F(t) = 1 - exp[-(t/c)β], where β is the scale parameter and c is the characteristics lifetime (or time to 63.2% failure)

Develop characteristic lifetime model based on voltage (a), area (b) and temperature (c).c ~ Vα g(A) exp[∆H/kBT]

Voltage acceleration found to obey power-law behavior. g(A) is a generalized function of area which is process dependent 10 12 14 16 18 20 22

Stress Voltage (V)

1E+01E+11E+21E+31E+41E+51E+61E+71E+81E+9

Tim

e to

63.

2% F

ailu

re (s

ec)

expModel PowerModel E-model Measured Data

TDDB Results - Nitride MIM10 ppm failure rate @ 5V/100 KPOH

Time to 15% Failure

Estimated Range for 63.2% Failure

84



TDDB Stress procedure for Capacitor qualification

100 1000 10000 100000 1000000Capacitor Area (um2)

0

5

10

Thou

sand

sTi

me

(s) t

o 63

.2%

Fai

lure

30 35 401/kT (ev-1)

4

5

6

7

8

9

10

11

12

ln[T

63.2

%]

Develop characteristic lifetime model based on voltage (a), area (b) and temperature (c).c ~ Vα g(A) exp[∆H/kBT]

Voltage acceleration found to obey power-law behavior. g(A) is a generalized function of area which is process dependentArrenhius plot for temperature

Given a specific application condition (temperature, lifetime and design area), the maximum voltage limitation can be estimated.

20 40 60 80 100 120 140Temperature (C)

11.4

11.6

11.8

12

12.2

12.4

12.6

12.8

Max

imum

App

lied

Volta

ge (V

)

85



Microstrip Transmission Line

Silicon Substrate

ground shield

signal 2SiO


Electromagnetic field distribution around microstrip line

Microstrip line:Has well-defined current return pathProvides good isolation of an interconnect from a lossy substrateField is effectively contained around transmission line, reducing lossCan be easily used for impedance matching

Example applications:Clock routing in wireline communication designsInter-stage lines in wireless power amplifier designs

Microstrip line structures have to be accurately modeled and introduced into design flow

Models should be accurate enough over a wide frequency rangeFrequency dependent skin and proximity effects should be includedDeveloped models should be parametric. It enables for a designer to design effectively critical interconnects to resolve all impedance matching, energy losses and signal integrity issues

Simple equations to estimate some electrical parameters

CLZ ,

CjLjRZ

c

,C

L ,h8

w11

wh321

4L

ht

8.2h

w15.1C ,

twtwR

HFHF

ox2

HF

2sig

2

sig

0DC

222.0sigsig

0oxgndgndgndsigsigsigl

DC

=ω

ω+=

ε=ττ=

π++

+

πµ=

+εε=

σ+

σ=

l

ll

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Coplanar Waveguide

Coplanar waveguide (CPW):Has well-defined current return pathField is effectively contained around waveguide, reducing lossCan be easily used for impedance matching

Example applications:interconnects and clock-lines in CMOS and RF-CMOS flows

Coplanar waveguide interconnects have to be accurately modeled and introduced into design flow

Models should be accurate enough over a wide frequency rangeFrequency dependent skin and proximity effects should be includedModel has to take into account coupling of the CPW interconnect to the lossy silicon substrateDeveloped models should be parametric, which enables for a designer to design effectively critical interconnects to resolve all impedance matching, energy losses and signal integrity issues

Simple equations to estimate some electrical parameters

Silicon Substrate

2SiOsignalground ground


Electromagnetic field distribution around coplanar waveguide

d

w ,)1ln(

tww

ln

)tw)(1(w

ln5.0

11ln5.0tw

dln5.0tw

dln2

L

tw2twR

p

gnd

p

gnd

p

gndsigDC

gndgndgndsigsigDC

=α

−α

+π

+−απ

+

α−+

+π+

+π

πµ=

σ+

σ= ll

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Example: Microstrip Line (~50 Ohm)

Each RLC block has a ladder network to incorporate frequency-dependent skin-effectA few RLC blocks (at least 10 per smallest on-chip wavelength) have to be connected in series to accurately represent real transmission line

Model vs. EM solver correlation up to 100GHz~50 Ohm characteristic impedancew = 8um, wg = 34.5um, h = 9.25um, th = 4.0um, th_g = 0.36um, l = 1000um, no side shielding

Good agrement between EM solver and ModelInterconnect has low losses (parameter S21)Phase delay can be easily predicted

0 20 40 60 80 100-80

-60

-40

-20

0

0 20 40 60 80 100-100

-50

0

50

100

0 20 40 60 80 100-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0 20 40 60 80 100-250

-200

-150

-100

-50

0

S11 - Magnitude (dB) S11 - Phase (degrees)

S21 - Magnitude (dB) S21 - Phase (degrees)

----- EM solver----- Model

Frequency (GHz) Frequency (GHz)

w

wg

h

th

th_g

1L 2L 3LDCL

DCR 1R 2R 3R

2C

2C

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HBT Breakdown Voltage

DC breakdown varies with RS:depends on rS + rB compared with

off-state breakdown > on-stateBreakdown example - Power amps:

experience collector voltage up to 4x supply voltage under high VSWRdisplay tolerance to voltages >> BVCEO

VSWR tolerance correlated with BVCBO

Em qIkT

g== 1rπ

β

16 17 18 19 20 21 220

1

2

3

4

5

6

7

8

9

10AE = 2880 µm2

VC = 3.5 VPout = 35 dBmf = 900 MHz

Tole

rate

d VS

WR

BVCBO

Off-state: high rπBVCER → BVCES

RS < 1 MΩ

RS = 0

RS-dependentvoltagelimits

RS=0ΩRS=100ΩRS=1kΩRS=10kΩ

On-state

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The GaAs MESFET

Key advantage: no heterostructuresimplest / least costly III-V devicegood yield and reliability

Key disadvantages:channel mobility limited by impurity scatteringchannel charge limited by gate diode leakage (low forward VGS)requires difficult-to-control gate recess for best RS and RD

Key applications:wireless transceivers, including PAsMMICs

Design challenges:obtaining reliable surface passivation, esp. around gateimproving gate Schottky barrier height for greater gate swinguse of T-gates to maintain low Rg despite Lg scalingrecessed cap process (for reduced Rs, Rd) without increased cost of using heterostructure

S.I. GaAs substrate / channel

gateohmiccontact

gate recess n-type GaAs channel

90



Substrate Resistance Model

w d

l

w d

l

0

100

200

300

400

500

600

1 10 100

Res

ista

nce

(ohm

)

Distance (µm)

10x1.5

20x5

10x510x10

p+p+Shallow trench

p- substrate

p - well

p+p+Shallow trench

p- substrate

p - well

wlR

R contactunitcontact

)(2 ×=

)4.0log()_( wdAR spreadinglateralsub ×+×=

lwdR

R NWellsheetverticalsub

)4.0(_)(

×+×=

)()_()()_(

)( verticalRspreadinglateralRverticalRspreadinglateralRRR

subsub

subsubcontacttotalsubs +

×+=

MeasuredModel

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